SR3.3 [SEMTECH]
RailClamp Low Capacitance TVS Diode Array; RailClamp低电容TVS二极管阵列
| 型号： | SR3.3 |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | RailClamp Low Capacitance TVS Diode Array |
| 文件： | 总7页 (文件大小：91K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SR3.3
RailClamp
Low Capacitance TVS Diode Array
PRELIMINARY
PROTECTION PRODUCTS
Features
Description
RailClamps are surge rated diode arrays designed to
protect high speed data interfaces. The SR series has
been specifically designed to protect sensitive compo-
nents which are connected to data and transmission
lines from overvoltage caused by ESD (electrostatic
discharge), EFT (electrical fast transients), and tertiary
lightning.
! ESD protection to IEC 61000-4-2, Level 4
! Array of surge rated diodes with internal
EPD TVS diode
! Protects two I/O lines
! Low capacitance (<10pF) for high-speed interfaces
! Low leakage current (< 1µA)
! Low operating voltage: 3.3V
! Solid-state technology
The unique design of the SR series devices incorpo-
rates four surge rated, low capacitance steering diodes
and a TVS diode in a single package. The TVS diode is
constructed using Semtech’s proprietary low voltage
EPD technology for superior electrical characteristics at
3.3 volts.
Mechanical Characteristics
! JEDEC SOT-143 package
! Molding compound flammability rating: UL 94V-0
! Marking : R3.3
During transient conditions, the steering diodes direct
the transient to either the positive side of the power
supply line or to ground. The internal TVS diode pre-
vents over-voltage on the power line, protecting any
downstream components.
! Packaging : Tape and Reel per EIA 481
Applications
! Data and I/O lines
! Sensitive Analog Inputs
! Video Line Protection
! Portable Electronics
! Microcontroller Input Protection
! WAN/LAN Equipment
The low capacitance array configuration allows the user
to protect two high-speed data or transmission lines.
The low inductance construction minimizes voltage
overshoot during high current surges.
Circuit Diagram
Schematic & PIN Configuration
Pin 4
4
1
Pin 2
Pin 3
2
3
Pin 1
SOT-143 (Top View)
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Revision 9/2000
1
SR3.3
PROTECTION PRODUCTS
PRELIMINARY
Absolute Maximum Rating
Rating
Peak Pulse Power (tp = 8/20µs)
Peak Pulse Current (tp = 8/20µs)
Peak Forward Voltage (IF = 1A, tp=8/20µs)
Lead Soldering Temperature
Operating Temperature
Symbol
Ppk
Value
150
Units
Watts
A
IPP
10
VFP
1.5
V
TL
260 (10 sec.)
-55 to +125
-55 to +150
°C
TJ
°C
Storage Temperature
TSTG
°C
Electrical Characteristics
SR3.3
Parameter
Reverse Stand-Off Voltage
Punch-Through Voltage
Snap-Back Voltage
Symbol
Conditions
Minimum
Typical
Maximum
Units
VRWM
VPT
VSB
IR
3.3
V
V
IPT = 2µA
3.5
2.8
ISB = 50mA
V
Reverse Leakage Current
Clamping Voltage
VRWM = 3.3V, T=25°C
IPP = 1A, tp = 8/20µs
IPP = 10A, tp = 8/20µs
tp = 8/20µs
1
µA
V
VC
7
Clamping Voltage
VC
15
10
10
V
Maximum Peak Pulse Current
Junction Capacitance
IPP
A
Cj
Between I/O pins and
Gnd
VR = 0V, f = 1MHz
6
3
pF
Between I/O pins
VR = 0V, f = 1MHz
pF
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2000 Semtech Corp.
2
SR3.3
PROTECTION PRODUCTS
PRELIMINARY
Typical Characteristics
Non-Repetitive Peak Pulse Power vs. Pulse Time
Power Derating Curve
10
110
100
90
80
70
60
50
40
30
20
10
0
1
0.1
0.01
0
25
50
75
100
125
150
0.1
1
10
100
1000
Ambient Temperature - TA (oC)
Pulse Duration - tp (µs)
Pulse Waveform
Clamping Voltage vs. Peak Pulse Current
110
100
90
80
70
60
50
40
30
20
10
0
16
14
12
10
8
Waveform
Parameters:
Line-To-Line
µ
tr = 8 s
µ
td = 20 s
e-t
Line-To-Ground
td = IPP/2
6
4
2
0
5
10
15
20
25
30
0
Time (µs)
0
2
4
6
8
10
12
Peak Pulse Current (A)
Forward Voltage vs. Forward Current
10
9
8
7
6
5
4
3
2
1
0
Waveform
Parameters:
tr = 8 s
µ
td = 20 s
µ
0
5
10
15
20
25
30
35
40
45
50
Forward Current - IF (A)
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2000 Semtech Corp.
3
SR3.3
PROTECTION PRODUCTS
PRELIMINARY
Applications Information
Device Connection Options for Protection of
Two High-Speed Data Lines
Data Line and Power Supply Protection Using
Vcc as reference
The SR3.3 TVS is designed to protect two data lines
from transient over-voltages by clamping them to a
fixed reference. When the voltage on the protected
line exceeds the reference voltage (plus diode VF) the
steering diodes are forward biased, conducting the
transient current away from the sensitive circuitry.
Data lines are connected at pins 2 and 3. The nega-
tive reference (REF1) is connected at pin 1. This pin
should be connected directly to a ground plane on the
board for best results. The path length is kept as short
as possible to minimize parasitic inductance.
The positive reference (REF2) is connected at pin 4.
The options for connecting the positive reference are
as follows:
Data Line Protection with Bias and Power Sup-
ply Isolation Resistor
1. To protect data lines and the power line, connect
pin 4 directly to the positive supply rail (VCC). In this
configuration the data lines are referenced to the
supply voltage. The internal TVS diode prevents
over-voltage on the supply rail.
2. The SR3.3 can be isolated from the power supply
by adding a series resistor between pin 4 and VCC.
A value of 10kΩ is recommended. The internal
TVS and steering diodes remain biased, providing
the advantage of lower capacitance.
3. In applications where no positive supply reference
is available, or complete supply isolation is desired,
the internal TVS may be used as the reference. In
this case, pin 4 is not connected. The steering
diodes will begin to conduct when the voltage on
the protected line exceeds the working voltage of
the TVS (plus one diode drop).
Data Line Protection Using Internal TVS Diode
as Reference
Board Layout Considerations for ESD Protection
Board layout plays an important role in the suppression
of extremely fast rise-time ESD transients. Recall that
the voltage developed across an inductive load is
proportional to the time rate of change of current
through the load (V = L di/dt). The total clamping
voltage seen by the protected load will be the sum of
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2000 Semtech Corp.
4
SR3.3
PROTECTION PRODUCTS
PRELIMINARY
Applications Information (continued)
the TVS clamping voltage and the voltage due to the
parasitic inductance (VC(TOT) = VC + L di/dt) . Parasitic
inductance in the protection path can result in signifi-
cant voltage overshoot, reducing the effectiveness of
the suppression circuit. An ESD induced transient for
I
PP
ISB
example reaches a peak in approximately 1ns. For a
PIN Descriptions
30A pulse (per IEC 61000-4-2 Level 4), 1nH of series
inductance will increase the effective clamping voltage
by 30V
IPT
I R
VBRR
(V = 1x10-9 (30/1x10-9)). For maximum effectiveness,
the following board layout guidelines are recom-
mended:
V
V
V
VC
RWM
SB
PT
I BRR
"
"
"
Minimize the path length between the SR3.3 and
the protected line.
Place the SR3.3 near the RJ45 connector to
restrict transient coupling in nearby traces.
Minimize the path length (inductance) between the
RJ45 connector and the SR3.3.
Figure 1 - EPD TVS IV Characteristic Curve
EPD TVS Characteristics
The internal TVS of the SR3.3 is constructed using
Semtech’s proprietary EPD technology. The structure
of the EPD TVS is vastly different from the traditional
pn-junction devices. At voltages below 5V, high leak-
age current and junction capacitance render conven-
tional avalanche technology impractical for most
applications. However, by utilizing the EPD technology,
the SR3.3 can effectively operate at 3.3V while main-
taining excellent electrical characteristics.
The IV characteristic curve of the EPD device is shown
in Figure 1. The device represents a high impedance
to the circuit up to the working voltage (VRWM). During a
transient event, the device will begin to conduct as it is
biased in the reverse direction. When the punch-
through voltage (VPT) is exceeded, the device enters a
low impedance state, diverting the transient current
away from the protected circuit. When the device is
conducting current, it will exhibit a slight “snap-back” or
negative resistance characteristic due to its structure.
This must be considered when connecting the device
to a power supply rail. To return to a non-conducting
state, the current through the device must fall below
the snap-back current (approximately < 50mA).
The EPD TVS employs a complex nppn structure in
contrast to the pn structure normally found in tradi-
tional silicon-avalanche TVS diodes. The EPD mecha-
nism is achieved by engineering the center region of
the device such that the reverse biased junction does
not avalanche, but will “punch-through” to a conduct-
ing state. This structure results in a device with supe-
rior dc electrical parameters at low voltages while
maintaining the capability to absorb high transient
currents.
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2000 Semtech Corp.
5
SR3.3
PROTECTION PRODUCTS
PRELIMINARY
Outline Drawing - SOT-143
Notes:
(1) Controlling dimension: Inch (unless otherwise specified).
(2) Dimension A and B do not include mold protrusions. Mold protrusions are .006” max.
Land Pattern - SOT-143
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2000 Semtech Corp.
6
SR3.3
PROTECTION PRODUCTS
PRELIMINARY
Marking Codes
Marking
Part Number
Code
SR3.3
R3.3
Ordering Information
Part
Number
Working
Voltage
Qty per
Reel
Reel Size
SR3.3.TC
SR3.3.TG
3.3V
3.3V
3,000
7 Inch
10,000
13 Inch
Contact Information
Semtech Corporation
Protection Products Division
652 Mitchell Rd., Newbury Park, CA 91320
Phone: (805)498-2111 FAX (805)498-3804
www.semtech.com
2000 Semtech Corp.
7
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