SR3.3.TC [SEMTECH]
RailClamp® Low Capacitance TVS Diode Array; RailClamp ？低电容TVS二极管阵列
| 型号： | SR3.3.TC |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | RailClamp® Low Capacitance TVS Diode Array |
| 文件： | 总7页 (文件大小：173K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SR3.3
RailClamp
Low Capacitance TVS Diode Array
PROTECTION PRODUCTS
Features
Description
RailClamps are surge rated diode arrays designed to
protect high speed data interfaces. The SR series has
been specifically designed to protect sensitive compo-
nents which are connected to data and transmission
lines from overvoltage caused by electrostatic dis-
charge (ESD), electrical fast transients (EFT), and
tertiary lightning.
ESD protection to
IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact)
IEC 61000-4-4 (EFT) 40A (5/50ns)
Array of surge rated diodes with internal
EPD TVS diode
Protects two I/O lines
Low capacitance (<10pF) for high-speed interfaces
Low leakage current (< 1µA)
Low operating voltage: 3.3V
Solid-state technology
The unique design of the SR series devices incorpo-
rates four surge rated, low capacitance steering diodes
and a TVS diode in a single package. The TVS diode is
constructed using Semtech’s proprietary low voltage
EPD technology for superior electrical characteristics at
3.3 volts.
Mechanical Characteristics
JEDEC SOT-143 package
During transient conditions, the steering diodes direct
the transient to either the positive side of the power
supply line or to ground. The internal TVS diode pre-
vents over-voltage on the power line, protecting any
downstream components.
Molding compound flammability rating: UL 94V-0
Marking : R3.3
Packaging : Tape and Reel
Applications
The low capacitance array configuration allows the user
to protect two high-speed data or transmission lines.
The low inductance construction minimizes voltage
overshoot during high current surges.
Data and I/O lines
Sensitive Analog Inputs
Video Line Protection
Portable Electronics
Microcontroller Input Protection
WAN/LAN Equipment
Circuit Diagram
Schematic & PIN Configuration
Pin 4
4
1
Pin 2
Pin 3
2
3
Pin 1
SOT-143 (Top View)
www.semtech.com
Revision 01/16/08
1
SR3.3
PROTECTION PRODUCTS
Absolute Maximum Rating
Rating
Peak Pulse Power (tp = 8/20µs)
Peak Pulse Current (tp = 8/20µs)
Peak Forward Voltage (IF = 1A, tp=8/20µs)
Lead Soldering Temperature
Operating Temperature
Symbol
Ppk
Value
150
Units
Watts
A
IPP
10
VFP
1.5
V
TL
260 (10 sec.)
-55 to +125
-55 to +150
°C
TJ
°C
Storage Temperature
TSTG
°C
Electrical Characteristics
SR3.3
Parameter
Reverse Stand-Off Voltage
Punch-Through Voltage
Snap-Back Voltage
Symbol
Conditions
Minimum
Typical
Maximum
Units
V
VRWM
VPT
VSB
IR
3.3
IPT = 2µA
3.5
2.8
V
ISB = 50mA
V
Reverse Leakage Current
Clamping Voltage
VRWM = 3.3V, T=25°C
IPP = 1A, tp = 8/20µs
IPP = 10A, tp = 8/20µs
1
7
µA
V
VC
Clamping Voltage
VC
15
10
V
Junction Capacitance
Cj
Between I/O pins and
Ground
VR = 0V, f = 1MHz
6
3
pF
Between I/O pins
VR = 0V, f = 1MHz
pF
www.semtech.com
2008 Semtech Corp.
2
SR3.3
PROTECTION PRODUCTS
Typical Characteristics
Non-Repetitive Peak Pulse Power vs. Pulse Time
10
Power Derating Curve
110
100
90
80
70
60
50
40
30
20
10
0
1
0.1
0.01
0
25
50
75
100
125
150
0.1
1
10
100
1000
Ambient Temperature - TA (oC)
Pulse Duration - tp (µs)
Pulse Waveform
Clamping Voltage vs. Peak Pulse Current
110
100
90
80
70
60
50
40
30
20
10
0
16
14
12
10
8
Waveform
Line-To-Line
Parameters:
µ
tr = 8 s
µ
td = 20 s
e-t
Line-To-Ground
td = IPP/2
6
4
Waveform
Parameters:
tr = 8µs
2
td = 20µs
0
5
10
15
Time (µs)
20
25
30
0
0
2
4
6
8
10
12
Peak Pulse Current - IPP (A)
Forward Voltage vs. Forward Current
10
9
8
7
6
5
4
3
2
1
0
Waveform
Parameters:
tr = 8µs
td = 20µs
0
5
10
15
20
25
30
35
40
45
50
Forward Current - IF (A)
www.semtech.com
2008 Semtech Corp.
3
SR3.3
PROTECTION PRODUCTS
Applications Information
Device Connection Options for Protection of
Two High-Speed Data Lines
Data Line Protection Using Internal TVS Diode
as Reference
The SR3.3 TVS is designed to protect two data lines
from transient over-voltages by clamping them to a
fixed reference. When the voltage on the protected
line exceeds the reference voltage (plus diode VF) the
steering diodes are forward biased, conducting the
transient current away from the sensitive circuitry.
Data lines are connected at pins 2 and 3. The nega-
tive reference (REF1) is connected at pin 1. This pin
should be connected directly to a ground plane on the
board for best results. The path length is kept as short
as possible to minimize parasitic inductance.
The positive reference (REF2) is connected at pin 4.
The options for connecting the positive reference are
as follows:
Note that pins 4 is connected internally to the cathode
of the low voltage TVS. It is not recommended that this
pin be directly connected to a DC source greater than
the snap-back votlage (VSB) as the device can latch on
as described below.
IPP
ISB
EPD TVS Characteristics
These devices are constructed using Semtech’s
proprietary EPD technology. By utilizing the EPD tech-
nology, the SR3.3 can effectively operate at 3.3V while
maintaining excellent electrical characteristics.
IPT
IR
VBRR
V
RWM
V
SB
V
PT
VC
IBRR
The EPD TVS employs a complex nppn structure in
contrast to the pn structure normally found in tradi-
tional silicon-avalanche TVS diodes. Since the EPD
TVS devices use a 4-layer structure, they exhibit a
slightly different IV characteristic curve when compared
to conventional devices. During normal operation, the
device represents a high-impedance to the circuit up to
the device working voltage (VRWM). During an ESD
event, the device will begin to conduct and will enter a
low impedance state when the punch through voltage
(VPT) is exceeded. Unlike a conventional device, the low
voltage TVS will exhibit a slight negative resistance
characteristic as it conducts current. This characteris-
tic aids in lowering the clamping voltage of the device,
but must be considered in applications where DC
voltages are present.
Figure 1 - EPD TVS IV Characteristic Curve
characteristics due to its structure. This point is
defined on the curve by the snap-back voltage (VSB)
and snap-back current (ISB). To return to a non-
conducting state, the current through the device must
fall below the ISB (approximately <50mA) and the
voltage must fall below the VSB (normally 2.8 volts for a
3.3V device). If a 3.3V TVS is connected to 3.3V DC
source, it will never fall below the snap-back voltage of
When the TVS is conducting current, it will exhibit a
slight “snap-back” or negative resistance
2.8V and will therefore stay in a conducting state.
www.semtech.com
2008 Semtech Corp.
4
SR3.3
PROTECTION PRODUCTS
Applications Information (continued)
Board Layout Considerations for ESD Protection
Board layout plays an important role in the suppression
of extremely fast rise-time ESD transients. Recall that
the voltage developed across an inductive load is
proportional to the time rate of change of current
PIN Descriptions
through the load (V = L di/dt). The total clamping
voltage seen by the protected load will be the sum of
the TVS clamping voltage and the voltage due to the
parasitic inductance (VC(TOT) = VC + L di/dt) . Parasitic
inductance in the protection path can result in signifi-
cant voltage overshoot, reducing the effectiveness of
the suppression circuit. An ESD induced transient for
example reaches a peak in approximately 1ns. For a
30A pulse (per IEC 61000-4-2 Level 4), 1nH of series
inductance will increase the effective clamping voltage
by 30V
(V = 1x10-9 (30/1x10-9)). For maximum effectiveness,
the following board layout guidelines are recom-
mended:
z
z
z
Minimize the path length between the SR3.3 and
the protected line.
Place the SR3.3 near the RJ45 connector to
restrict transient coupling in nearby traces.
Minimize the path length (inductance) between the
RJ45 connector and the SR3.3.
Matte Tin Lead Finish
Matte tin has become the industry standard lead-free
replacement for SnPb lead finishes. A matte tin finish
is composed of 100% tin solder with large grains.
Since the solder volume on the leads is small com-
pared to the solder paste volume that is placed on the
land pattern of the PCB, the reflow profile will be
determined by the requirements of the solder paste.
Therefore, these devices are compatible with both
lead-free and SnPb assembly techniques. In addition,
unlike other lead-free compositions, matte tin does not
have any added alloys that can cause degradation of
the solder joint.
www.semtech.com
2008 Semtech Corp.
5
SR3.3
PROTECTION PRODUCTS
Outline Drawing - SOT-143
D
e
A
H
DIMENSIONS
INCHES MILLIMETERS
e/2
DIM
MIN NOM MAX MIN NOM MAX
c
GAUGE
PLANE
-
-
-
.031
.000
4
3
0
A
.048 0.80
.006 0.013
1.22
0.15
-
SEATING
PLANE
A1
B
A2 .029 .035 .042 0.75 0.90 1.07
-
-
-
-
-
-
b
.011
.020 0.30
.037 0.76
.008 0.08
0.51
0.94
0.20
0.25
C
b1 .029
L
L1
c
D
E
.003
.110 .114 .120 2.80 2.90 3.04
.082 .093 .104 2.10 2.37 2.64
E
E1
DETAIL A
E1 .047 .051 .055 1.20 1.30 1.40
e
.075
.008
1.92 BSC
0.20 BSC
e1
L
.015 .020 .024 0.40 0.50 0.60
(.021)
(0.54)
L1
N
4
4
1
2
-
-
0
0°
8°
0°
8°
aaa
.006
.008
.004
0.15
0.20
0.10
bbb
ccc
bxN
e1
SEE DETAIL A
bbb
C A B
SIDE VIEW
A2
A
ccc
C
4X
SEATING PLANE
A1
b1
C
aaa
C A B
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
-A- -B- -H-
2. DATUMS
AND
TO BE DETERMINED AT DATUM PLANE
DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
3.
4. REFERENCE JEDEC STD TO-253, VARIATION D.
Land Pattern - SOT-143
X1
X1
Y
Y
DIMENSIONS
DIM
INCHES
MILLIMETERS
(.087)
(2.20)
C
E1
E2
G
E1
Z
.076
.068
.031
.039
.047
.055
.141
1.92
1.72
0.80
1.00
1.20
1.40
3.60
G
C
E2
X1
X2
Y
Z
X2
X1
NOTES:
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY
1.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
2. REFERENCE IPC-SM-782A.
www.semtech.com
2008 Semtech Corp.
6
SR3.3
PROTECTION PRODUCTS
Marking Codes
Marking
Part Number
Code
SR3.3
R3.3
Ordering Information
Part
Qty per
Reel
Lead Finish
Number
Reel Size
SR3.3.TC
SnPb
3,000
3,000
7 Inch
7 Inch
SR3.3.TCT
Pb Free
Contact Information
Semtech Corporation
Protection Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
www.semtech.com
2008 Semtech Corp.
7
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