SC656ULTRT [SEMTECH]
Backlight Driver for 7 LEDs with Charge Pump and PWM Control; 背光驱动器7 LED的电荷泵和PWM控制
| 型号： | SC656ULTRT |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | Backlight Driver for 7 LEDs with Charge Pump and PWM Control |
| 文件： | 总17页 (文件大小：487K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SC656
Backlight Driver for 7 LEDs with
Charge Pump and PWM Control
POWER MANAGEMENT
Features
Description
Input supply voltage range — 2.9V to 5.5V
Charge pump modes — ꢀx, ꢀ.5x and 2x
PWM dimming control with low pass filter provides
DC backlight current (not pulsed)
The SC656 is a high efficiency charge pump LED driver
using Semtech’s proprietary charge pump technology.
Performance is optimized for use in single-cell Li-ion
battery applications.
Two independently configurable backlight banks
PWM frequency range — 200Hz to 50kHz
Seven adjustable current sinks — 500µA to 25mA
Backlight current accuracy ꢀ.5% typical
Backlight current matching 0.5% typical
LED float detection
The device provides backlight current using up to seven
matched current sinks. The load and supply conditions
determine whether the charge pump operates in ꢀx, ꢀ.5x,
or 2x mode. The seven backlights can be configured as a
single group or split into two independent banks by
setting the state of the BANK2 and BANKꢀ pins. If only one
bank is needed, the BANK2, BANKꢀ, ENS and ISETS pins
must be grounded.
Charge pump frequency — 250kHz
Low shutdown current — 0.ꢀµA typical
Ultra-thin package — 3 x 3 x 0.6(mm)
Fully WEEE and RoHS compliant, and halogen free.
The maximum current per LED in each bank is set by a
resistor connected to ISETM or ISETS. LED current can be
set between 500µA and 25mA. Backlight current is varied
by applying a pulse-width modulated (PWM) signal to the
ENM pin for the main LED bank and the ENS pin for the
sub LED bank. The resulting DC current in each LED (IBL) is
equal to the maximum current setting multiplied by the
duty cycle of the PWM signal. During PWM operation, a
low-pass filter is used to develop a DC current through the
LED. The resulting power conversion is more efficient than
comparable pulsed current solutions. Backlight fading is
initiated when the duty cycle is changed.
Applications
Cellular phones, smart phones, and PDAs
LCD display modules
Portable media players
Digital cameras
Personal navigation devices
Display/keypad backlighting and LED indicators
The 3 x 3 (mm) package and minimal number of small
external components make the SC656 an ideal backlight
driver solution for space-limited designs.
Typical Application Circuit
SC656
VBAT = 2.9V to 5.5V
IN
OUT
CIN
2.2µF
COUT
2.2µF
GND
RISETM
RISETS
ISETM
ISETS
BL1
BL2
BL3
BL4
BL5
BL6
BL7
BANK2
BANK1
PWM Signal
PWM Signal
ENM
ENS
C1+ C1- C2+ C2-
C1
C2
2.2µF
2.2µF
US Patents: 6,504,422; 6,794,926
September 24, 2009
ꢀ
© 2009 Semtech Corporation
SC656
Pin Configuration
Ordering Information
Device
Package
SC656ULTRT(ꢀ)(2)
MLPQ-UT-20 3×3
Evaluation Board
SC656EVB
Notes:
20
19
18
17
16
(ꢀ) Available in tape and reel only. A reel contains 3,000 devices.
(2) Lead-free package only. Device is WEEE and RoHS compliant, and
halogen free.
ENS
IN
1
2
3
15
14
13
12
11
C2-
TOP VIEW
GND
BANK2
ISETM
ISETS
BL1
4
5
BANK1
BL7
T
8
6
7
9
10
MLPQ-UT-20; 3x3, 20 LEAD
θJA = 35°C/W
Marking Information
656
yyww
xxxx
yyww = Date Code
xxxx = Semtech Lot Number
2
SC656
Absolute Maximum Ratings
Recommended Operating Conditions
IN, OUT (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0
Cꢀ+, C2+ (V) . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VOUT + 0.3)
Pin Voltage — All Other Pins (V) . . . . . . . . . -0.3 to (VIN + 0.3)
OUT Short Circuit Duration . . . . . . . . . . . . . . . . . Continuous
ESD Protection Level(ꢀ) (kV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ambient Temperature Range (°C). . . . . . . . . . -40 ≤TA ≤ +85
Input Voltage (V) . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9 to 5.5
Output Voltage (V) . . . . . . . . . . . . . . . . . . . . . . . . 2.5 to 5.25
VoltageDifferencebetweenanytwoLEDs(V)...∆VF ≤ꢀ.0(2)
Thermal Information
Thermal Resistance, Junction to Ambient(3) (°C/W) . . . 40
Maximum Junction Temperature (°C) . . . . . . . . . . . . . . +ꢀ50
Storage Temperature Range (°C) . . . . . . . . . . . -65 to +ꢀ50
Peak IR Reflow Temperature (ꢀ0s to 30s) (°C) . . . . . . +260
Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters
specified in the Electrical Characteristics section is not recommended.
NOTES:
(ꢀ) Tested according to JEDEC standard JESD22-Aꢀꢀ4-B.
(2) ∆VF(max) = ꢀ.0V when VIN = 2.9V, higher VIN supports higher ∆VF(max)
(3) Calculated from package in still air, mounted to 3 x 4.5(in), 4 layer FR4 PCB per JESD5ꢀ standards.
Electrical Characteristics
Unless otherwise noted, TA = +25°C for Typ, -40°C to +85°C for Min and Max, TJ(MAX) = ꢀ25°C, VIN = 3.7V, CIN= COUT = Cꢀ= C2= 2.2µF, (ESR = 0.03Ω),
500µA < IFS_BL < 25mA, Duty Cycle of PWM = ꢀ00%, All 7 LEDs connected and enabled as a single bank.
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Shutdown Current
IQ(OFF)
TA = 25°C
0.ꢀ
2
µA
ꢀx mode, VIN = 3.7V, 7 LEDs at ꢀmA on main bank,
PWM duty cycle = 5%, RISETM = 4.99kΩ
2.5
2.8
3.0
ꢀ.5x mode, VIN = 3.2V, 7 LEDs at ꢀmA on main bank,
PWM duty cycle = 5%, RISETM = 4.99kΩ
Quiescent Current
IQ
mA
2x mode, VIN = 2.9V, 7 LEDs at ꢀmA on main bank,
PWM duty cycle = 5%, RISETM = 4.99kΩ
VIN > 3.0V, sum of all active LED currents,
VOUT(MAX) = 4.2V
Maximum Total Output Current
IOUT(MAX)
ꢀ75
0.5
mA
Backlight Current Setting
Current Gain(ꢀ)
IFS_BL
IGAIN
VIN - ISET
IBL-BL
PWM duty cycle = ꢀ00%, 200kΩ ≥ RISETX ≥ 4kΩ
Gain from IISETX to IFS_BL
25
mA
A/A
V
ꢀ00
ꢀ
Current Set Voltage
Voltage across RISETX
Backlight Current Matching(2)
Backlight Current Accuracy
EN/PWM Input Frequency
ENM, ENS Minimum High
IFS_BL = ꢀ2mA, Duty = ꢀ00%
-3.5
0.2
0.5
ꢀ.5
+3.5
50
%
IBL_ACC
fEN/PWM
tHIGH_MIN
IFS_BL = ꢀ2mA, Duty = ꢀ00%
%
Duty-cycle percentage changes linearly with IFS_BL
kHz
µs
ꢀ
3
SC656
Electrical Characteristics (continued)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Current Transition Settling Time
ts
Duty cycle change from ꢀ00% to 50%(ꢀ)(4)
0.5
s
Time that voltage on ENM or ENS can be low with-
out disabling the device
ENM/ENS Low Time
tLT
5
ms
V
ꢀx Mode to ꢀ.5x Mode
Falling Transition Voltage
VTRANSꢀx
IOUT = 70mA, IBLn = ꢀ0mA, VOUT = 3.2V
IOUT = 70mA, IBLn = ꢀ0mA, VOUT = 4.0V(3)
VIN = VBLn = 4.2V
3.26
2.90
0.ꢀ
ꢀ.5x Mode to 2x Mode
Falling Transition Voltage
VTRANSꢀ.5x
V
Current Sink Off-State
Leakage Current
IBLn(off)
fPUMP
ꢀ
µA
Charge Pump Frequency
VIN = 3.2V
OUT pin shorted to GND
VOUT > 2.5V
250
50
kHz
Output Short Circuit Current Limit
IOUT(SC)
mA
400
2.4
500
5.7
ꢀ65
25
Under Voltage Lockout Threshold
UVLO Hysteresis
VUVLO
VUVLO-HYS
VOVP
Increasing VIN — lockout released
V
mV
V
Over-Voltage Protection
Over-Temperature
OUT pin open circuit, VOUT = VOVP, VIN rising threshold
Rising Temperature
6.0
TOT
°C
°C
OT Hysteresis
TOT-HYS
Digital Logic Pins — ENM, ENS, BANK2, AND BANK1
Input High Threshold
Input Low Threshold
Input High Current
Input Low Current
VIH
VIL
IIH
VIN = 5.5V
VIN = 2.9V
VIN = 5.5V
VIN = 5.5V
ꢀ.4
V
V
0.4
ꢀ
µA
µA
IIL
ꢀ
Notes:
(ꢀ) Guaranteed by design
(2) Current matching equals ꢁIBL(MAX) - IBL(MIN] / ꢁIBL(MAX) + IBL(MIN)].
(3) Test voltage is VOUT = 4.0V — a relatively extreme LED voltage used to force a transition during test. Typically VOUT = 3.2V for white LEDs.
(4) The settling time is affected by the magnitude of change in the PWM duty cycle.
4
SC656
Typical Characteristics
CIN = COUT= Cꢀ = C2 = 2.2µF — 0603 size (ꢀ608 metric)
Backlight Accuracy (7 LEDs) — 25mA Each
Backlight Matching (7 LEDs) — 25mA Each
VOUT = 3.56V, IOUT = 175mA, 25°C
VOUT = 3.56V, IOUT = 175mA, 25°C
8
6
8
6
4
2
4
2
MAX LED
0
0
MIN LED
-2
-2
-4
-6
-8
-4
-6
-8
4.2
3.9
3.6
3.3
3
2.7
4.2
3.9
3.6
3.3
3
2.7
VIN (V�
VIN (V�
Backlight Accuracy (7 LEDs) — 12mA Each
Backlight Matching (7 LEDs) — 12mA Each
VOUT = 3.42V, IOUT = 84mA, 25°C
VOUT = 3.42V, IOUT = 84mA, 25°C
8
6
8
6
4
4
MAX LED
MIN LED
2
2
0
0
-2
-4
-2
-4
-6
-8
-6
-8
2.7
4.2
3.9
3.6
3
2.7
4.2
3.9
3.6
3
3.3
3.3
VIN (V�
VIN (V�
Backlight Accuracy (7 LEDs) — 5mA Each
Backlight Matching (7 LEDs) — 5mA Each
VOUT = 3.28V, IOUT = 35mA, 25°C
VOUT = 3.28V, IOUT = 35mA, 25°C
8
6
4
2
8
6
4
2
MAX LED
0
-2
-4
-6
-8
0
MIN LED
-2
-4
-6
-8
4.2
3.9
3.6
3.3
3
2.7
3
2.7
4.2
3.9
3.6
3.3
VIN (V�
VIN (V�
5
SC656
Typical Characteristics (continued)
Backlight Current (7 LEDs) — 25mA Each
Charge Pump Efficiency (7 LEDs) — 25mA Each
VOUT = 3.56V, IOUT = 175mA, 25°C
VOUT = 3.56V, IOUT = 175mA, 25°C
100
400
350
300
250
200
150
100
90
80
70
60
50
2.7
4.2
3.9
3.6
3.3
3
2.7
4.2
3.9
3.6
3.3
3
VIN (V�
VIN (V�
Backlight Current (7 LEDs) — 12mA Each
Charge Pump Efficiency (7 LEDs) — 12mA Each
VOUT = 3.42V, IOUT = 84mA, 25°C
VOUT = 3.42V, IOUT = 84mA, 25°C
135
125
115
105
95
100
90
80
70
60
50
85
75
3
2.7
4.2
3.9
3.6
3.3
4.2
3.9
3.6
3.3
3
2.7
VIN (V�
VIN (V�
Charge Pump Efficiency (7 LEDs) — 5mA Each
Backlight Current (7 LEDs) — 5mA Each
VOUT = 3.28V, IOUT = 35mA, 25°C
VOUT = 3.28V, IOUT = 35mA, 25°C
100
80
70
90
80
70
60
50
40
30
20
60
50
4.2
3.9
3.6
3.3
3
2.7
4.2
3
3.9
3.6
3.3
2.7
VIN (V�
VIN (V�
6
SC656
Typical Characteristics (continued)
PWM Accuracy — 4.2V
Percentage of Maximum IBL — 4.2V
VIN = 4.2V, RISET = 4.99kΩ, Calculated IBL = (100/RISET) x Duty Cycle
VIN = 4.2V, RISET = 4.99kΩ
20
100
80
16
12
60
40
20
0
50kHz
8
50kHz
200Hz
32kHz
4
32kHz
200Hz
0
4
8
16
0
12
20
40
60
100
0
20
80
Meaꢁureꢀ IBL (mA�
PWM Duty Cycle (%�
PWM Accuracy — 3.7V
Percentage of Maximum IBL — 3.7V
VIN = 3.7V, RISET = 4.99kΩ
VIN = 3.7V, RISET = 4.99kΩ, Calculated IBL = (100/RISET) x Duty Cycle
100
80
20
16
60
12
8
50kHz
200Hz
50kHz
40
20
0
32kHz
32kHz
200Hz
4
0
0
4
8
0
40
PWM Duty Cycle (%�
100
12
16
20
20
60
80
Meaꢁureꢀ IBL (mA�
Percentage of Maximum IBL — 2.9V
PWM Accuracy — 2.9V
VIN = 2.9V, RISET = 4.99kΩ, Calculated IBL = (100/RISET) x Duty Cycle
VIN = 2.9V, RISET = 4.99kΩ
20
16
100
80
12
8
50kHz
60
40
32kHz
50kHz
200Hz
32kHz
4
20
0
200Hz
0
0
4
8
0
20
80
100
12
Meaꢁureꢀ IBL (mA�
16
20
40
60
PWM Duty Cycle (%�
7
SC656
Typical Characteristics (continued)
Ripple — 1X Mode
Ripple — 1X Mode
VIN=4.2V, RISET = 4kΩ, 7 Backlights — 25 mA each, 25°C
VIN=4.2V, RISET = 5.56kΩ, 7 Backlights — ꢀ8 mA each, 25°C
VIN (ꢀ00mV/div)
VIN (ꢀ00mV/div)
VOUT (ꢀ00mV/div)
VOUT (ꢀ00mV/div)
Time (10µꢁꢂꢀiꢃ�
Time (10µꢁꢂꢀiꢃ�
Ripple — 1.5X Mode
Ripple — 1.5X Mode
VIN=3.2V, RISET = 4kΩ, 7 Backlights — 25 mA each, 25°C
VIN=3.2V, RISET = 5.56kΩ, 7 Backlights — ꢀ8 mA each, 25°C
VIN (ꢀ00mV/div)
VIN (ꢀ00mV/div)
VOUT (ꢀ00mV/div)
VOUT (ꢀ00mV/div)
Time (10µꢁꢂꢀiꢃ�
Time (10µꢁꢂꢀiꢃ�
Ripple — 2X Mode
Ripple — 2X Mode
VIN=2.9V, RISET = 4kΩ, 7 Backlights — 25 mA each, 25°C
VIN=2.9V, RISET = 5.56kΩ, 7 Backlights — ꢀ8 mA each, 25°C
VIN (ꢀ00mV/div)
VIN (ꢀ00mV/div)
VOUT (ꢀ00mV/div)
VOUT (ꢀ00mV/div)
Time (10µꢁꢂꢀiꢃ�
Time (10µꢁꢂꢀiꢃ�
8
SC656
Typical Characteristics (continued)
Start-up — 0% to 100%
Start-up — 0% to 50%
VIN = 3.7V, 0 to ꢀ00% duty cycle, RISET = 4.99kΩ, no PWM
VIN = 3.7V, 0 to 50% duty cycle, RISET = 4.99kΩ, fPWM = 32kHz
20mA
ꢀ0mA
IBL (ꢀ0.0mA/div)
0mA—
IBL (ꢀ0.0mA/div)
0mA—
VPWM (2V/div)
0V—
VPWM (2V/div)
0V—
ꢀ00%
50%
Time (200mꢁꢂꢀiꢃ�
Time (200mꢁꢂꢀiꢃ�
IBL Settling Time — 100% to 50%
IBL Settling Time — 50% to 100%
VIN = 3.7V, RISET = 4.99kΩ, fPWM = 32kHz
VIN = 3.7V, RISET = 4.99kΩ, fPWM = 32kHz
20mA
20mA
ꢀ0mA
ꢀ0mA
IBL (ꢀ0.0mA/div)
0mA—
IBL (ꢀ0.0mA/div)
0mA—
VPWM (2V/div)
0V—
VPWM (2V/div)
0V—
50%
ꢀ00%
50%
ꢀ00%
Time (200mꢁꢂꢀiꢃ�
Time (200mꢁꢂꢀiꢃ�
DC Backlight Current — 32kHz PWM
DC Backlight Current — 200Hz PWM
VIN = 3.7V, 50% duty cycle, RISET = 4.99kΩ, IBL = ꢀ0mA
VIN = 3.7V, 50% duty cycle, RISET = 4.99kΩ, IBL = ꢀ0mA
IBL (ꢀ0.0mA/div)
0mA—
IBL (ꢀ0.0mA/div)
0mA—
VPWM (2V/div)
0V—
VPWM (2V/div)
0V—
Time (1mꢁꢂꢀiꢃ�
Time (20μ�ꢁꢀꢂꢁꢀiꢂꢃꢃ�
9
SC656
Pin Descriptions
Pin #
Pin Name
Pin Function
ꢀ
2
ENS
IN
Enable pin for sub display LED bank — also used as the PWM dimming control input for this bank
Battery voltage input
Current setting pin — connect a resistor between ISETM and IN to set the main bank LED
current.
3
4
ISETM
ISETS
Current setting pin — connect a resistor between ISETS and IN to set the sub bank LED
current.
5
6
BLꢀ
BL2
BL3
BL4
BL5
BL6
BL7
Current sink output for backlight LED ꢀ — leave this pin open if unused
Current sink output for backlight LED 2 — leave this pin open if unused
Current sink output for main backlight LED 3 — leave this pin open if unused
Current sink output for main backlight LED 4 — leave this pin open if unused
Current sink output for main backlight LED 5 — leave this pin open if unused
Current sink output for main backlight LED 6 — leave this pin open if unused
Current sink output for main backlight LED 7 — leave this pin open if unused
7
8
9
ꢀ0
ꢀꢀ
Logic input that, along with BANK 2, controls the configuration of the main and sub bank functions. See
application information section for details.
ꢀ2
ꢀ3
BANK ꢀ
BANK 2
Logic input that, along with BANK ꢀ, controls the configuration of the main and sub bank functions. See
application information section for details.
ꢀ4
ꢀ5
ꢀ6
ꢀ7
ꢀ8
ꢀ9
20
GND
C2-
Ground pin
Negative connection to bucket capacitor 2
Cꢀ-
Negative connection to bucket capacitor ꢀ
Cꢀ+
C2+
OUT
ENM
Positive connection to bucket capacitor ꢀ
Positive connection to bucket capacitor 2
Charge pump output — all LED anode pins are connected to this pin.
Enable pin for the main display LED bank — also used as the PWM dimming control input for this bank
ꢀ0
SC656
Block Diagram
C1+ C1- C2+ C2-
17
16
18
15
VIN
VOUT
Fractional Charge Pump
(1x, 1.5x, 2x)
2
19
IN
OUT
14
GND
Oscillator
Control
Interface,
Level
Converter,
Digital LPF
20
ENM
5
6
BL1
BL2
BL3
BL4
BL5
BL6
Current
Setting
Block
3
4
ISETM
ISETS
7
Current
Setting
Block
8
Control
Interface,
Level
Converter,
Digital LPF
9
1
ENS
10
11
BL7
13
12
BANK2
BANK1
LED Bank
Configuration
Logic
ꢀꢀ
SC656
Applications Information
IOUT up to 90mA. For output currents higher than 90mA, a
nominal value of 2.2µF is recommended for COUT and CIN.
General Description
This design is optimized for handheld applications sup-
plied from a single Li-Ion cell and includes the following
key features:
Capacitors with X7R or X5R ceramic dielectric are strongly
recommended for their low ESR and superior tempera-
ture and voltage characteristics. Y5V capacitors should
not be used as their temperature coefficients make them
unsuitable for this application.
• A high efficiency fractional charge pump that
supplies power to all LEDs
• Seven matched current sinks that control LED
backlighting current, providing 500µA to 25mA
per LED
Capacitor Recommendations
The full rated output of ꢀ75mA is achieved using 2.2µF
0603 size capacitors for input, output, and bucket
capacitors.
• Two LED bank options with independent current
settings and enable pins with PWM control of
LED brightness.
For applications which do not require the full ꢀ75mA
output capability of the SC656 , a lower cost and smaller
size capacitor option may be used. The ꢀµF capacitor in
Table ꢀ may be used with no loss in accuracy, for up to
90mA of output current.
High Current Fractional Charge Pump
The backlight outputs are supported by a high efficiency,
high current fractional charge pump output at the OUT
pin. The charge pump multiplies the input voltage by ꢀ,
ꢀ.5, or 2 times. The charge pump switches at a fixed fre-
quency of 250kHz in ꢀ.5x and 2x modes and is disabled in
ꢀx mode to save power and improve efficiency.
Table 1 — Capacitor Recommendations
Capacitance
The mode selection circuit automatically selects the ꢀx,
ꢀ.5x, or 2x mode based on circuit conditions such as LED
voltage, input voltage, and load current. The ꢀx mode is
the most efficient mode, followed by ꢀ.5x and 2x modes.
Circuit conditions such as low input voltage, high output
current, or high LED voltage place a higher demand on
the charge pump output. A higher numerical mode (ꢀ.5x
or 2x) may be needed momentarily to maintain regulation
at the OUT pin during intervals of high demand. The
charge pump responds to momentary high demands,
setting the charge pump to the optimum mode to deliver
the output voltage and load current while optimizing effi-
ciency. Hysteresis is provided to prevent mode toggling.
Value of
CIN = COUT
= C1 = C2
Size Code
EIA (JIS)
Application IOUT Limit
2.2µF
ꢀ.0µF
0603 (ꢀ608)
0402 (ꢀ005)
up to IOUT = ꢀ75mA(ꢀ)
up to IOUT = 90mA(2)(3)
Notes:
(ꢀ) Note that 2.2µF in the 0402 size is not equivalent to 2.2µF in the
0603 size, so 0402 may not be substituted for this application.
(2) Larger size capacitors may be substituted.
(3) Exceeding 90mA, or using less than ꢀ.0µF, may cause excessive
peak-to-peak output ripple, (>ꢀ20mV), and some loss of accuracy
in ꢀ.5x mode.
Bank Control Options
The charge pump requires two bucket capacitors for
proper operation. One capacitor must be connected
between the Cꢀ+ and Cꢀ- pins and the other must be con-
nected between the C2+ and C2- pins as shown in the
Typical Application Circuit diagram. These capacitors
should be equal in value, with a minimum capacitance of
ꢀµF to support the charge pump current requirements.
The device also requires at least ꢀµF capacitance on the IN
pin and at least ꢀµF capacitance on the OUT pin to mini-
mize noise and support the output drive requirements of
The backlight drivers can be configured as a single bank
or as two independently controlled banks. The configu-
ration of the banks is determined by the BANK2 and
BANKꢀ pins as described in Table 2. The ENM and ISETM
pins control the brightness of LEDs assigned to the main
bank, and the ENS and ISETS pins allow the sub bank
current to be set independently as described in the fol-
lowing section. Note that when both BANK2 and BANKꢀ
are set to 0, the sub bank feature is disabled. In this case,
both ENS and ISETS should be tied to GND.
ꢀ2
SC656
Applications Information (continued)
Table 2 — Backlight Bank Configuration Settings
PWM Sampling
The sampling system that translates the PWM signal to
a DC current requires the ENM and ENS pins to have a
minimum high time tHIGH_MIN to set the DC level. High
time less than tHIGH_MIN impacts the accuracy of the target
IBL. The minimum duty cycle needed to support the
minimum high time specification varies with the applied
PWM frequency (see figure ꢀ). Note that use of a lower
PWM frequency, from 200Hz to ꢀ0kHz, will support
lower minimum duty cycle and an extended backlight
dimming range.
Bank 2
Bank 1
Main Bank
Sub Bank
0
0
ꢀ
ꢀ
0
ꢀ
0
ꢀ
BLꢀ — BL7
BL2 — BL7
BL3 — BL7
BL4 — BL7
none
BLꢀ
BLꢀ — BL2
BLꢀ — BL3
LED Backlight Current Sinks
The full scale backlight current (IFS_BL) is set via the current
through the ISET pin controlling the corresponding LED
bank (ISETM or ISETS) . The IFS_BL is regulated to the value
of the ISETM or ISETS pin current multiplied by an internal
gain of ꢀ00A/A. RISETM and RISETS are used to control the
current into the ISETM and ISETS pins. The relationship
between each resistance RISETx and the full scale backlight
current is:
tHIGH_MIN = 1µs
5
4
3
2
1
0
RISETx = ꢀ00/IFS_BL
All backlight current sinks have matched currents, even
when there is a variation in the forward voltages (∆VF ) of
the LEDs. A ∆VF of ꢀ.0V is supported when the input
voltage is at 2.9V. Higher ∆VF LED mis-match is supported
when VIN is higher than 2.9V. All current sink outputs are
compared and the lowest output is used for setting the
voltage regulation at the OUT pin. This is done to ensure
that sufficient bias exists for all LEDs.
0.2
10
20
PWM Frequency (kHz�
40
50
30
Figure 1 — Minimum Duty Cycle
Shutdown Mode
Shutdown occurs after ENM and ENS are both held low
for an interval of ꢀ5ms or more. When the ENM and ENS
pins are both held low for 5ms or less, the device will not
shutdown.
Any unused LED driver outputs must be left open for
normal operation.
PWM Operation
A PWM signal on the ENM or ENS pin can be used to
adjust the DC current through the LEDs. When the duty
cycle is ꢀ00%, the backlight current through each LED (IBL)
equals the full scale current set by the corresponding ISET
pin. As the duty cycle decreases, the ENM or ENS input
samples the control signal and converts the duty cycle to
a DC current level. In conventional PWM controlled
systems, the output current pulses on and off with the
PWM input to achieve an average output current.
Providing a DC current through the LEDs instead of a
pulsed current provides an efficiency advantage over
other PWM controlled systems by allowing the charge
pump to remain in ꢀx mode longer since the maximum
current is equal to the average current.
Protection Features
The SC656 provides several protection features to safe-
guard the device from catastrophic failures. These features
include:
• Output Open Circuit Protection
• Over-Temperature Protection
• Charge Pump Output Current Limit
• LED Float Detection
ꢀ3
SC656
Applications Information (continued)
Output Open Circuit Protection
Charge Pump Output Current Limit
Over-Voltage Protection (OVP) at the OUT pin prevents
the charge pump from producing an excessively high
output voltage. In the event of an open circuit between
the OUT pin and all current sinks (no loads connected),
the charge pump runs in open loop and the voltage rises
up to the OVP limit. OVP operation is hysteretic, meaning
the charge pump will momentarily turn off until VOUT is
sufficiently reduced. The maximum OVP threshold is 6.0V,
allowing the use of a ceramic output capacitor rated
at 6.3V.
The device limits the charge pump current at the OUT pin.
If the OUT pin is shorted to ground, or VOUT is lower than
2.5V, the typical output current limit is 70mA. The output
current is limited to 225mA when over loaded resistively
with VOUT greater than 2.5.
LED Float Detection
Float detect is a fault detection feature of the LED back-
light outputs. If an output is programmed to be enabled
and an open circuit fault occurs at any backlight output,
that output will be disabled to prevent a sustained output
OVP condition from occurring due to the resulting open
loop. Float detect ensures device protection but does not
ensure optimum performance.
Over-Temperature Protection
The Over-Temperature (OT) protection circuit prevents the
device from overheating and experiencing a catastrophic
failure. When the junction temperature exceeds ꢀ65°C, the
device goes into thermal shutdown with all outputs dis-
abled until the junction temperature is reduced. All regis-
ter information is retained during thermal shutdown.
Hysteresis of 20°C is provided to ensure that the device
cools sufficiently before re-enabling.
PCB Layout Considerations
The layout diagram in Figure 2 illustrates a proper two
layer PCB layout for the SC656 and supporting compo-
nents. Following fundamental layout rules is critical for
achieving the performance specified in the Electrical
Characteristics table. The following guidelines are rec-
ommended when developing a PCB layout:
OUT
Ground Plane
GND
COUT
C1
C2
CIN
ENS
C2-
GND
IN
IN
GND
GND
ISETM
ISETS
BL1
BANK2
RSETM
RSETS
SC656
BANK1
BL7
Figure 2 — Recommended Layout
ꢀ4
SC656
Applications Information (continued)
• Place all bucket and decoupling capacitors —
Cꢀ, C2, CIN, and COUT — as close to the device as
possible.
• All charge pump current passes through pins
IN, OUT, Cꢀ+, C2+, Cꢀ-, and C2-. Therefore,
ensure that all connections to these pins make
use of wide traces so that the voltage drop on
each connection is minimized.
• The GND pin should be connected to a ground
plane using multiple vias to ensure proper
thermal connection for optimal heat transfer.
• Make solid ground connections between the
grounds of the COUT, CIN, and the GND pin on the
device.
• Resistors RSETM and RSETS should be connected as
shown in Figure 2, close to pins IN and ISET.
The placement and routing shown minimizes
parasitic capacitance at the ISET pin.
• Figure 3 shows the pads on layer ꢀ that should
be connected with vias to layer 2. CIN, COUT and
the GND pin all use vias to connect to the
ground plane.
• Figure 4 shows layer 2, which functions as the
ground plane. Layer 2 is also used for routing
signals to pins ENM, ENS, BANKꢀ, and BANK2. A
void in the copper beneath the ISETM and ISETS
pins serves to reduce capacitance coupled from
these pins to ground.
• Avoid coupling noise to the ENM and ENS pins.
This will help prevent unintended clocking of
the PWM. The layout should be routed to
achieve the least possible trace to trace capaci-
tance between ENM and ENS. Also, minimize
trace capacitance between ENM or ENS and any
high speed signals.
Figure 4 — Layer 2
Figure 3 — Layer 1
ꢀ5
SC656
Outline Drawing — MLPQ-UT-20 3x3
B
E
DIMENSIONS
INCHES MILLIMETERS
MIN NOM MAX MIN NOM MAX
A
D
DIM
A
-
-
-
.020
A1 .000
A2
.024 0.50
.002 0.00
0.60
0.05
-
(.006)
(0.152)
PIN 1
INDICATOR
(LASER MARK)
b
D
.006 .008 .010 0.15 0.20 0.25
.114 .118 .122 2.90 3.00 3.10
D1 .061 .067 .071 1.55 1.70 1.80
.114 .118 .122 2.90 3.00 3.10
E1 .061 .067 .071 1.55 1.70 1.80
E
e
L
N
aaa
bbb
.016 BSC
.012 .016 .020 0.30 0.40 0.50
0.40 BSC
A2
C
20
.003
.004
20
0.08
0.10
A
SEATING
PLANE
aaa C
A1
D1
e
LxN
E/2
E1
2
1
N
D/2
bxN
bbb
C A B
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2.
3.
COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
DAP IS 1.90 x 1.90mm.
ꢀ6
SC656
Land Pattern — MLPQ-UT-20 3x3
K
DIMENSIONS
INCHES MILLIMETERS
R
DIM
(.114)
.083
.067
.067
.016
.004
.008
.031
.146
(2.90)
2.10
1.70
1.70
0.40
0.10
0.20
0.80
3.70
C
G
H
K
P
R
X
Y
Z
Z
(C)
H
G
Y
X
P
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
3. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD
SHALL BE CONNECTED TO A SYSTEM GROUND PLANE.
FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR
FUNCTIONAL PERFORMANCE OF THE DEVICE.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 930ꢀ2
Phone: (805) 498-2ꢀꢀꢀ Fax: (805) 498-3804
www.semtech.com
ꢀ7
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