ACS8942A [SEMTECH]
Support Circuit, 1-Func, 5 X 5 MM, QFN-32;
| 型号： | ACS8942A |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | Support Circuit, 1-Func, 5 X 5 MM, QFN-32 ATM 异步传输模式 电信 电信集成电路 |
| 文件： | 总30页 (文件大小：520K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ACS8942A JAM PLL
Jitter Attenuating, Multiplying Phase Locked Loop
for SONET/SDH Applications to OC-48/STM-16
ADVANCED COMMUNICATIONS
Introduction
PRELIMINARY
Features
APPLICATION DATASHEET
The ACS8942A JAM PLL is a jitter attenuating and
multiplying (JAM) Phase-Locked Loop (PLL) for generating
ultra-low jitter output clocks compliant to SONET OC-48
and STM 16 2.5 GHz specifications. Its primary function is
to clean up clock jitter, but it can also perform frequency
translation for optimum interfacing to an OC-12 or OC-48
SONET serializer or framer.
Meets jitter requirements of:
Telcordia GR-253 for OC-3, OC-12 and OC-48 rates
ITU-T G.813 & 812 for STM-1, STM-4 and STM-16
rates
ETSI EN300-462-5 & EN302-084 to STM-16 rates
PLL bandwidth fully adjustable - supports PLL
loop bandwidths from 1.5 kHz for superior input
jitter filtering
Ideal dejittering solution for use with Semtech
Clock & line card parts: ACS8510, 20, 22, 30 &
ACS8525, 26, 27
The headline jitter generation figures quoted for the
ACS8942A depend on the frequency band over which the
jitter is measured. For example, typical output jitter is
0.93 ps rms for GR-253-CORE (OC-48, 12 kHz to 20 MHz)
against specification of 4.02 ps, and as low as 0.10 ps
rms for G.813 Option 1 (STM-16, 1 MHz to 20 MHz). The
device's operating bandwidth (and consequently the jitter
attenuation point relating to this bandwidth) is fully
configurable, and is set by external passive components
in a differential arrangement.
Typical jitter generation down to
0.13 ps rms for 250 kHz to 5 MHz band for G.813,
or EN300 462, at STM-4 (OC-12) rates
0.93 ps rms for 12 kHz to 20 MHz band (against
4.02 ps rms for GR-253-CORE at OC-48 rate)
For a “Real World” application where the input clock
source is driven from a relatively high jitter OC-3 standard,
line card clock selector and conditioner (e.g.
ITU, ETSI and Telcordia frequency band results
shows exceptional performance in a “Real World”
environment (low PLL bandwidth of 2 KHz and a
typical input from an ACS8525 partner IC):
ACS8525/26/27), the output jitter is typically 1.55 ps
rms GR-253-CORE (OC-48, 12 kHz to 20 MHz), and as low
as 0.10 ps rms for G.813 Option 1 (STM-16, 1 MHz to
20 MHz). The overall combined bandwidth will take that of
the SETS device, typically 35 Hz, to ensure excellent jitter
filtering of noisy input sources, very low final output jitter,
and excellent stability during source switchovers and
failures.
0.10 ps rms in the STM-16 1 MHz to 20 MHz band
1.55 ps rms in the STM-4 12 kHz to 5 MHz band
1.55 ps rms in the OC-48 12 kHz to 20 MHz band
(GR-253-CORE spec is 4 ps rms)
External Feedback option for alternative input
frequencies e.g. 19.44, 38.88, 77.76 MHz.
The differential LVPECL input clock is typically
155.52 MHz and the differential CML output clock can be
configured as 622.08 MHz or 77.76 MHz.
3.3 V operation. - 40 to 85°C temperature range
Frequency translation e.g. 155.52 MHz to
622.08 MHz
Block Diagram
Leadless 5 mm x 5 mm QFN32 package
Figure 1 Simplified Block Diagram of the ACS8942A JAM PLL
Loop
Filter
RESETB
VC
PFD
Charge
Pump
2.5 GHz
VCO
REFCLK
LVPECL
CML
OUT
Frequency
Dividers
Differential Input
LVPECL
Differential Output Clock
CML
622.08 MHz or
77.76 MHz
Typically
155.52 MHz
Lock
Detector
LOCK_EN
LOCKB
XF_VDDP3 XF_CK
OUT77M Frequency Select
Differential Input for
External Feedback Option
F8942AD_004Blockdiag_01
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ACS8942A JAM PLL
Table of Contents
ADVANCED COMMUNICATIONS PRELIMINARY
APPLICATION DATASHEET
Table of Contents
Section
Page
Introduction................................................................................................................................................................................................ 1
Block Diagram............................................................................................................................................................................................ 1
Features ..................................................................................................................................................................................................... 1
Table of Contents ...................................................................................................................................................................................... 2
Pin Diagram ............................................................................................................................................................................................... 3
Pin Description........................................................................................................................................................................................... 3
Description................................................................................................................................................................................................. 5
Input....................................................................................................................................................................................................5
Outputs ...............................................................................................................................................................................................5
Voltage-Controlled Oscillator.............................................................................................................................................................5
Clock Multiplication ...........................................................................................................................................................................5
Jitter Filtering (ACS8942A Standalone)............................................................................................................................................6
Total Solution for Jitter Filtering-Partnered with Semtech LC/P Parts ...........................................................................................6
Input Jitter Tolerance.........................................................................................................................................................................6
Jitter Transfer .....................................................................................................................................................................................7
Phase Noise Performance.................................................................................................................................................................7
External Feedback Option .................................................................................................................................................................9
PLL Bandwidth Setting ................................................................................................................................................................... 10
Lock Detector.................................................................................................................................................................................. 11
Output Jitter..................................................................................................................................................................................... 11
System Reset .................................................................................................................................................................................. 11
PCB Layout ...................................................................................................................................................................................... 11
Applications..................................................................................................................................................................................... 12
Application Schematic of Combined ACS8525 and ACS8942A.................................................................................................. 12
Electrical Specifications......................................................................................................................................................................... 14
ESD Protection ................................................................................................................................................................................ 14
Latch-up Protection......................................................................................................................................................................... 14
Maximum Ratings ........................................................................................................................................................................... 14
Operating Conditions ...................................................................................................................................................................... 14
Thermal Characteristics ................................................................................................................................................................. 15
DC Characteristics .......................................................................................................................................................................... 15
Input and Output Interface Terminations...................................................................................................................................... 17
AC Characteristics (Jitter Performance) ........................................................................................................................................ 18
Input/Output Timing ....................................................................................................................................................................... 24
Package Information .............................................................................................................................................................................. 25
Thermal Conditions......................................................................................................................................................................... 25
Abbreviations .......................................................................................................................................................................................... 27
References and Related Standards...................................................................................................................................................... 27
Trademark Acknowledgements ............................................................................................................................................................. 28
Revision Status/History ......................................................................................................................................................................... 28
Notes ....................................................................................................................................................................................................... 29
Ordering Information .............................................................................................................................................................................. 30
Disclaimers...................................................................................................................................................................................... 30
Contacts........................................................................................................................................................................................... 30
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ACS8942A JAM PLL
ADVANCED COMMUNICATIONS
PRELIMINARY
APPLICATION DATASHEET
Pin Diagram
Figure 2 ACS8942A Pin Diagram
F
R
A
A
A
C
N
P
V
7
3
1
0
9
2
6
2
1
2
3
4
5
6
7
8
NC1
24 VDDP1
23 CLKP
22 CLKN
21 VSSP1
20 VSSP2
19 OUTN
18 OUTP
17 VDDP2
VSSOSC
NC2
RESETB
IC1
OUT77M
NC3
ACS8942A
IC2
Dimensions: 5 mm x 5 mm
Lead Pitch: 0.5 mm
(Leads centered on package)
F8942A_D_002PINDIAG_01
Pin Description
Table 1 Power Pins
Pin No.
17
Symbol
VDDP2
I/O
Type
Description
P
P
P
P
P
P
P
P
P
-
-
-
-
-
-
-
-
-
-
-
Supply Voltage: Supply to clock output pin, +3.3 Volts ± 10%.
Supply Voltage: Supply to input clock pads, +3.3 Volts ± 10%.
Supply Voltage: Supply for internal Dividers in VCO loop, +3.3 Volts ± 10%.
Supply Voltage: Supply for internal VCO, +3.3 Volts ± 10%.
Supply Ground: 0 Volts for peripheral pads.
24
VDDP1
27
VDDADIV
VDDARF
32
10, 16 VSSP3, VSSP3A
20, 21 VSSP2, VSSP1
Supply Ground: 0 Volts for output clock pads.
26
31
2
VSSADIV
VSSARF
Supply Ground: 0 Volts for internal dividers in VCO loop.
Supply Ground: 0 Volts for internal VCO.
VSSOSC
Centre Pad
Supply Ground: 0 Volts for the internal VCO.
Not
shown
Centre Pad: Pad is not used but should be connected to ground for improved heat
dissipation.
Note...I = Input, O = Output, P = Power, TTL/CMOSU = TTL/CMOS input with pull-up resistor, TTL/CMOSD = TTL/CMOS input with pull-down
resistor.
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ACS8942A JAM PLL
ADVANCED COMMUNICATIONS
PRELIMINARY
APPLICATION DATASHEET
Table 2 Internally Connected (IC)/ Not Connected (NC) Pins
Pin No.
Symbol
I/O
Type
Description
Internally Connected: Must connect to ground.
5 ,8,
28,
IC1, IC2, IC3
-
-
1,3, 7, NC1, NC2, NC3,
11, 12 NC4, NC5
-
-
Not Connected: Leave to float.
Table 3 Functional Pins
Pin No.
Symbol
RESETB
I/O
Type
Description
4
I
TTL/CMOSU Active low reset signal with pull up and Schmitt type input. Used to apply a Power On
(Schmitt)
Reset (POR) signal during system initialization. Should be connected via a capacitor to
ground.
6
9
OUT77M
LOCKB
I
TTL/CMOSU When connected to 3.3 V the option to output 77.76 MHz from the OUTP and OUTN
(Schmitt)
differential output, pins 18 and 19, is enabled. When this pin is connected to ground pins
the output is at 622.08 MHz.
O
LVTTL/CMOS Lock detector output. This is a digital output pad that is an XOR of the two phase detector
(tristate)
outputs. By filtering this with an external RC circuit an indication of PLL lock is provided.
After RC filtering, when this pin is high it indicates that a large phase error is being
detected and hence indicates not locked. When the filtered signal is low it indicates PLL
lock. The value of the RC components determines the time and level of consistency
required for lock indication.
13
14
XF_VDDP3
XF_CKN
P/I
Power and
select
When connected to 3.3 V the option to route the feedback clock from an external source
into the internal Phase and Frequency Detector (PFD) is enabled. The feedback clock
should be input to differential input pins 14 and 15. This pin is then the 3.3 V power
supply to pins 14 and 15.
CAUTION! If pin 13 is to be powered down or grounded, pins 14 and 15 must also be
grounded to prevent damage to the device.
I
LVPECL (LVDS Optional differential input for the feedback clock to the internal PFD. It must be at the
or CML inputs same frequency as the main clock input on pins 22 and 23. This input is particularly
also possible) useful when wanting to use external dividers to, for example, divide the 622 MHz main
output down to 155, 77 or 38 MHz and wanting to also maintain the same phase of the
divided down signal across multiple boards.
CAUTION! If pin 13 is to be powered down or grounded, pins 14 and 15 must also be
grounded to prevent damage to the device.
15
XF_CKP
I
LVPECL (LVDS Optional differential input for the feedback clock to the internal PFD. See description
or CML inputs above for pin 14.
also possible) CAUTION! If pin 13 is to be powered down or grounded, pins 14 and 15 must also be
grounded to prevent damage to the device.
18
19
OUTP
OUTN
O
O
CML
CML
CML differential output at 622.08 MHz or 77.76 MHz. The output frequency being
controlled by pin 6. Partnered with pin 19. Can also drive LVPECL or LVDS loads as well
as CML given suitable external interface components.
CML differential output at 622.08 MHz or 77.76 MHz. The output frequency being
controlled by pin 6. Partnered with pin 18. See pin 18.
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ACS8942A JAM PLL
ADVANCED COMMUNICATIONS
Table 3 Functional Pins (cont...)
PRELIMINARY
APPLICATION DATASHEET
Pin No.
Symbol
CLKN
I/O
Type
Description
22
I
LVPECL (LVDS Input reference clock that the PLL will phase and frequency lock to. Accepts 155.52 MHz
or CML inputs and can accept other input frequencies in external feedback mode (see pins 13, 14, 15)
also possible) providing the frequency is matched to that of the external feedback signal on pins
14/15. Partnered with pin 23. Can accept LVPECL or LVDS or CML inputs given suitable
external interface components.
23
CLKP
I
LVPECL (LVDS Input reference clock that the PLL will phase and frequency lock to. Accepts 155.52 MHz.
or CML inputs Can accept other input frequencies in external feedback mode (see pins 13, 14, 15)
also possible) providing the frequency is matched to that of the external feedback signal on pins
14/15. Partnered with pin 22. Can accept LVPECL or LVDS or CML inputs given suitable
external interface components.
25
LOCK_EN
I
TTL/CMOSD Active high enable input to enable the lock detector output. Disabling the output allows
for a quieter operating environment.
29
30
VCP
VCN
I
I
Analog
Analog
Differential charge pump output at 10 uA plus VCO control voltage input.
Differential charge pump output at 10 uA plus VCO control voltage input.
Note...I = Input, O = Output, P = Power, TTL/CMOSU = TTL/CMOS input with pull-up resistor, TTL/CMOSD = TTL/CMOS input with pull-down
resistor.
Outputs
Description
The ACS8942A JAM PLL (Jitter Attenuating and
Multiplying Phase Locked Loop) is an ultra-low jitter
integrated PLL for dejittering and clock rate translation. It
uses a two-pole differential loop filter that meets the
output jitter requirements for SONET up to and including
OC-48 (2.5 GHz) systems. It is compliant to the relevant
ITU, Telcordia and ETSI standards for at least OC-3
(155.52 MHz), OC-12 (622.08 MHz) and OC-48
(2488.32 MHz) equivalent to the corresponding STM1, 4
and 16 rates.
The ACS8942A has a single, CML, differential output.
Output clock rates at either 622.08 MHz or 77.76 MHz
are selectable and are produced in a CML output format.
This can be arranged to drive all common interface
standards (CML, LVDS and LVPECL) using suitable
interface components as detailed in a later in “Input and
Output Interface Terminations” on page 17.
Voltage-Controlled Oscillator
It requires a minimal number of external components
(capacitors and resistors for loop filter) and is available in
a small form factor QFN32 package at 5 mm x 5 mm x
0.9 mm outer dimensions.
The internal VCO operates at 2.48832 GHz and is
internally divided down to 622.08 MHz or 77.76 MHz
giving a precise 50/50 balanced mark/space ratio for the
output.
Input
Clock Multiplication
The ACS8942A has a single, LVPECL, differential input.
The input is nominally fixed at 155.52 MHz, unless in
external feedback mode, and can be accepted in all
common electrical interface formats (CML, LVDS and
LVPECL) when suitable passive resistive and capacitive
interface components are used. Phase comparisons are
performed directly at this rate in the internal Phase and
Frequency Detector (PFD).
Clock multiplication from any common SONET, SDH or
PDH spot frequency (e.g. 19.44, 25.92, 38.88, 51.84,
77.76 and 155.52 MHz) up to SONET OC-12 622.08 MHz
(or 77.76 MHz) can be achieved by configuring The
ACS8942A into external feedback mode and using the
appropriate external divider ratio.
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ACS8942A JAM PLL
ADVANCED COMMUNICATIONS
Jitter Filtering (ACS8942A Standalone)
PRELIMINARY
APPLICATION DATASHEET
z Low final output jitter e.g. 1.55 ps rms (measured over
the integration range 12 kHz to 20 MHz)
Jitter filtering of the input reference clock is dependent on
the PLL loop filter, which is configured using external
components. The recommended loop filter topology is a
passive 2 pole low pass filter arrangement as shown in
Figure 12, with associated component value
z High frequency stability when all input clocks fail
holdover frequency control to Stratum 3.
z High flexibility for device setup, control and monitoring
(via the ACS8525 uP interface)
recommendations for particular bandwidths and damping
factor given in Tables 4 and 5 on page 10. This allows the
PLL bandwidth and damping factor to be specifically
optimized to match system requirements. Input jitter
which is at a higher frequency than the loop filter cut off
frequency (Fc) will be attenuated. Below Fc, (defined by
the -3 dB point on the jitter transfer curve, i.e. the position
of the first pole of the PLL loop filter), the jitter will be
tracked.
z Clock multiplication from any common SONET, SDH or
PDH spot frequency (e.g. 2 kHz, n x 8 kHz, and 1.544,
2.048, 6.48, 19.44, 25.92, 38.88, 51.84, 77.76 and
155.52 MHz) up to SONET OC-12 622.08 MHz (or
77.76 MHz).
Input Jitter Tolerance
Jitter tolerance is defined as the max amplitude of
sinusoidal jitter that can exist on the input reference clock
above which the device fails to maintain lock.
Using a typical reference clock of 155.52 MHz, and a
closed loop filter bandwidth of 2 kHz and damping factor
1.2 gives:
z High input jitter attenuation and roll off:
• - 20 dB/decade from first loop filter pole (Fc)
• - 40 dB/decade from 2nd pole (typically 10 x Fc)
z Jitter peaking is less than 1 dB
For the device in standalone mode the jitter tolerance is
shown in Figure 3. For frequencies below the PLL
bandwidth, jitter tolerance is seen to decrease at a rate of
-20dB per decade. For jitter frequencies above the PLL
bandwidth, jitter tolerance is limited to 1.2 UI p-p.
z Low final output jitter. e.g. 0.93 ps rms measured over
the integration range of 12 kHz to 20 MHz offset from
carrier.
Figure 3 Jitter Tolerance; ACS8942A Standalone using
a 155.52 MHz Input Reference Clock
Total Solution for Jitter Filtering-Partnered
with Semtech LC/P Parts
The recommended PLL bandwidth setting of 2 kHz and
damping factor 1.2 is suitable for providing a low jitter
total solution when partnered with the Semtech
ACS8525, ACS8526 or ACS8527 series of line card
protection devices.
The test results detailed in the electrical specifications
section show the “Real World” performance of the total
line card solution using the combination of an ACS8525
and an ACS8942A. This combination of parts is a superior
solution to those traditionally using simple discrete PLLs,
and has the following advantages:
z Low overall bandwidth, 18 Hz for example
z High input jitter attenuation and roll-off
z First, second and third order roll-off points:
• - 20 dB/decade 18 Hz to 2 kHz
When the ACS8942A follows an ACS8525, the input jitter
tolerance is wholly defined by the ACS8525. The system
jitter tolerance is dramatically increased due to the
extended phase capture range of the digital phase locked
loop within the ACS8525 device.
• - 40 dB/decade 2 kHz to 200 kHz
• - 60 dB/decade for >200 kHz
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ACS8942A JAM PLL
ADVANCED COMMUNICATIONS
Jitter Transfer
PRELIMINARY
APPLICATION DATASHEET
Jitter peaking is directly influenced by the damping factor
used in the loop filter. Increasing the damping factor
decreases jitter peaking at the expense of a slower roll off
as can be seen in Figure 5.
Jitter transfer is a ratio of input jitter present on the ref
clock to the filtered jitter present on the output clock. In
standalone mode the jitter transfer characteristic is
defined by the loop filter bandwidth and associated
damping factor. These parameters may be configured to
optimize the PLL jitter transfer characteristic for individual
system requirements. Figures 4 and 5 show typical jitter
transfer characteristics, with Figure 4 showing the effect
of varying bandwidth while damping factor remains fixed
at 1.2, and Figure 5 showing the effect of varying damping
factor while the bandwidth remains fixed at 2 kHz.
In the total solution, the ACS8942A follows an ACS8525.
In this case the additional low frequency jitter filtering of
the ACS8525 tends to mask any jitter peaking introduced
by the ACS8942A. Therefore in the total solution the jitter
transfer response is predominantly defined by the
ACS8525 device as can be seen in Figure 6.
Figure 6 Jitter Transfer Characteristic, ACS8525 and
ACS8942A combined.
Figure 4 Jitter Transfer Characteristic, ACS8942A
Standalone. Damping Factor Fixed at 1.2
(ACS8525 bandwidth settings)
Figure 5 Jitter Transfer Characteristic, ACS8942A
Standalone. Bandwidth Fixed at 2 kHz
Phase Noise Performance
The inherent jitter generation by the ACS8942A is shown
in the phase noise plot in Figure 7 for a clean input of
155.52 MHz. The phase noise plot for the combined
ACS8525 and ACS8942A is shown for comparison in
Figure 8. It can be seen that when the recommended loop
filter values are used, the phase noise response of the
total line card solution is very close to the inherent phase
noise performance of the standalone ACS8942A.
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ACS8942A JAM PLL
ADVANCED COMMUNICATIONS
Figure 7 Phase Offset from Carrier, ACS8942A
Standalone
PRELIMINARY
APPLICATION DATASHEET
Figure 9 Combined Phase Noise
Frequency (Hz)
1.0E+07 1.0E+08
Frequency (Hz)
1.0E+02
1.0E+03
1.0E+04
1.0E+05
1.0E+06
1.0E+02
-10
1.0E+03
1.0E+04
1.0E+05
1.0E+06
1.0E+07 1.0E+08
-10
-30
-30
-50
)
)
H
-50
z
H
-70
/
c
d
B
-70
d
(
-90
s
s
N
i
-90
o
-110
-130
-150
-170
N
-110
a
h
P
-130
-150
-170
Red =Open loop phase noise of ACS8942A alone
Blue = Phase noise of combined ACS85xx and ACS8942A
Magenta = Phase noise of ACS85xx alone
Figure 8 Phase Offset from Carrier, ACS8525 with
ACS8942A
Frequency (Hz)
1.0E+07 1.0E+08
In combined solution, increasing ACS8942A bandwidth
above the optimum 2 kHz would reduce the phase noise
close to carrier, but would increase the phase noise after
crossover point as indicated by black line in Figure 10.
1.0E+02
-10
1.0E+03
1.0E+04
1.0E+05
1.0E+06
-30
-50
Figure 10 Effects of Adjusting Bandwidth on Phase noise,
for the Combined Solution
-70
-90
-110
-130
-150
-170
In the total line card solution, the inherent jitter generated
by the ACS8525 is attenuated by the ACS8942A. Figure 9
shows the phase noise of the ACS8525 alone, alongside
the open loop phase noise of the ACS8942A, then shows
the mutual benefits of the combined solution with the
combined phase noise response obtained with the
ACS8942A using a loop bandwidth of 2 kHz and damping
factor 1.2.
There is a dramatic improvement in the jitter attenuation
after the frequency crossover point (where the blue line
closely follows the open loop characteristic of the
ACS8942A), when compared against the performance of
the ACS8525 alone, at the expense of a modest decrease
in jitter attenuation close to carrier.
Decreasing the ACS8942A bandwidth however, raises the
phase noise close to carrier as indicated by the green
hatched line, but with no improvement after the crossover
point as, thereafter, the phase noise cannot fall below the
open loop phase noise plot of ACS8942A standalone.
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ACS8942A JAM PLL
ADVANCED COMMUNICATIONS
External Feedback Option
PRELIMINARY
APPLICATION DATASHEET
using an external divide by 15 on the output to provide the
feedback clock and an external divide by 16 on the input
side for the input clock, then the device will lock to a
16/15 FEC rate and produce a standard SONET
622.08 MHz or 77.76 MHz clock.
As an additional feature to the normal ‘clock in to clock
out’ PLL configuration, the device also supports a mode
where the PLL feedback clock can be supplied externally
instead of being provided from the VCO output internally.
This feature allows for different frequencies to be locked
to at the input, given that a suitable external divider on the
output is used to provide the feedback clock.
The external feedback option also allows the final output
signal from external buffers or dividers to be in exact
phase alignment with the clock input, meaning that
externally divided clocks could be in phase across
multiple line cards and removing the delay contribution
from the output stage and any external buffers.
It also allows the system to lock to FEC (forward error
correction) clock rates on the input side and generate
standard SONET rates on the output side. For example
Figure 11 External Feedback Configuration Example to Support More Frequency Options: 19.44 MHz Input, Dejittered
19.44 MHz, 38.88 MHz and 77.76 MHz Outputs
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ACS8942A JAM PLL
ADVANCED COMMUNICATIONS
PRELIMINARY
APPLICATION DATASHEET
The external feedback option is activated by connecting
pin 13 to 3.3 V. The feedback input is supplied to the
XF_CKP and XF_CKN pins. A circuit diagram showing an
example of how the external feedback arrangement might
be used in conjunction with an external buffer/divider is
shown in Figure 11.
The components required to achieve a range of different
bandwidths and damping factors are shown in Table 4 for
155 MHz input reference, and in Table 5 for 19.44 MHz
input reference. The components highlighted yellow in
these tables give the approximate 2 kHz PLL bandwidth
(damping factor 1.2) recommended for use with
Semtech’s ACS8525/8526/8527 line card protection
parts. Contact Semtech for component values to suit
other specific bandwidth/damping factor/frequency
settings.
In the example in Figure 11, the external feedback
configuration is used to allow different input frequencies
to be locked to, in this case 19.44 MHz. A typical
100EL34W clock divider circuit provides the necessary
19.44 MHz PFD feedback signal back to the ACS8942A.
Even though the 19.44 MHz output is divided down from
the 2.5 GHz VCO inside the ACS8942A, the phase of the
19.44 MHz output is precisely aligned to the 19.44 MHz
input using this technique.
Table 4 Typical Bandwidths and Components Values
155.52 MHz Reference Clock
Closed Loop
Bandwidth, Fc/
kHz
R1 & R2/
C2 & C4/
F
C1 & C3/
F
Ω
Other input frequencies could be similarly supported
using this technique, for example the common
arrangement of 77.76 MHz input and 77.76 MHz output
could be supported without the need for any additional
external divider. This would be done by using the
77.76 MHz output option in the ACS8942A and feeding
this output back to the external feedback input. The
device would then lock to a 77.76 MHz input and give a
low jitter 77.76 MHz output.
Damping Factor = 0.7
1.5
2
91
6u8
4u7
330n
220n
33n
120
300
620
5
680n
150n
10
6n8
Damping Factor = 1.2
1.5
2
110
150
360
750
10u
6u8
1u
68n
47n
6n8
2.2n
PLL Bandwidth Setting
The bandwidth is set by two identical sets of passive RC
components that connect to the differential charge pump
outputs and internal VCO control inputs. Pins VCN and
VCP are the combined differential charge pump outputs
and VCO control voltage inputs. Figure 12 shows the
arrangement.
5
10
330n
Damping Factor = 2.0
1.5
2
120
160
390
820
33u
15u
33n
15n
Figure 12 Loop Filter Components
5
2u2
2n2
LOCK_EN
VSSADIV
VDDADIV
IC3
10
680n
680p
VCP
VCN
VSSARF
VDDARF
Table 5 Typical Bandwidths and Components Values
19.44 MHz Reference Clock
R1
R2
Closed Loop
Bandwidth, Fc/
kHz
R1 & R2/
C2 & C4/
F
C1 & C3
F
C1
C2
C3
C4
Ω
Damping Factor = 0.7
GND
F8942A_010Loopfilter_02
1.5
750
1u
47n
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ACS8942A JAM PLL
ADVANCED COMMUNICATIONS
Table 5 Typical Bandwidths and Components Values
19.44 MHz Reference Clock (cont...)
PRELIMINARY
APPLICATION DATASHEET
The filtering components are external so that the time to
indicate the lock state (locked or not locked) can be
optimized for the application. The output indicates both
phase and frequency lock. During off-frequency
conditions the LOCKB output will be predominately high in
its PWM pulse generation with the filtered version,
LOCK_B, giving a constant high state.
Closed Loop
Bandwidth, Fc/
kHz
R1 & R2/
C2 & C4/
F
C1 & C3
F
Ω
2
5
1k
470n
68n
22n
4n7
2k4
5k1
Output Jitter
10
22n
680p
The output jitter meets all requirements of ITU, Telcordia
and ETSI standards for SONET rates up to OC-48/STM-16
2.5 GHz. See the Electrical Specifications Section for
details on the jitter figures across the different output
jitter frequency bands relevant to each specification.
Damping Factor = 1.2
1.5
2
910
1k1
3k
1u5
680n
150n
33n
10n
6n8
1n
5
The recommended bandwidth of around 2 kHz is suitable
for both meeting the specification on output jitter
generation requirements and for filtering out the input
jitter from the input clock.
10
6k2
220p
Damping Factor = 2.0
1.5
2
1k
3u3
2u2
3n3
1n5
1k3
3k3
6k8
System Reset
5
330n
68n
330p
68p
After power-up or a system reset via the RESETB (pin 4),
the internal control logic waits for the presence of an input
signal of approximately the correct frequency (at least
40 % of the nominal frequency) and then allows a further
settling time of 10 ms before allowing internal frequency
tuning and frequency and phase locking on to the input
clock. Consequently reset should be removed only when
the input frequency is within ±100 ppm of the nominal
frequency.
10
Lock Detector
A simple lock detector is incorporated which combines the
plus and minus phase errors from a phase detector, such
that if any phase error signal is present the LOCK output
goes high, otherwise it is low. Consequently this output is
a pulse width modulated (PWM) pulse stream whose
mark/space ratio indicates the current input phase error.
Filtering this signal with a simple external RC filter, as
shown in Figure 13, will give a signal whose output level
indicates PLL phase and frequency lock.
PCB Layout
A separate filtered power and ground plane is
recommended with supply decoupling capacitors of 10 nF
and 100 pF. The use of good high frequency chip
capacitors (0402 or 0603 format surface-mount
package) on each VCC is recommended. Good differential
signal layout on the input and output lines should be used
to ensure matched track impedance and phase. Gerber
plots of demonstration PCBs are available on request
from Semtech.
Figure 13 LOCK Filtering over 10 ms Period
XF_CKN
XF_VDDP3
NC5
NC4
VSSP3
LOCKB
RL
47K
LOCK_B
CL
220nF
GND
F8942A_011Lockfilter_02
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ACS8942A JAM PLL
ADVANCED COMMUNICATIONS
Applications
PRELIMINARY
APPLICATION DATASHEET
Application Schematic of Combined
ACS8525 and ACS8942A
The ACS8942A is targeted at applications requiring clock
cleaning at SONET rates from 77.76 MHz to 622.08 MHz.
Input jitter is filtered out or attenuated at frequencies
The following circuit of Figure 15 shows the circuit
above the ACS8942A PLL bandwidth of typically 2 kHz. It diagram of the clock solution part of a line card. The full
also performs the function of a clock multiplying unit
(CMU) translating from 155.52 MHz (or other frequencies
if in external feedback mode) up to 622.08 MHz
design uses a simple 8-bit, 8-pin microcontroller for
advanced control and ACS8525 device setup; an
ACS8525 line card protection device containing
DPLLs/APLLs, synthesizers and monitors; the ACS8942A
for jitter reduction, and a 100EL34W clock dividing and
buffering part. Just the parts relevant to the clock
production are shown here, i.e. the ACS8525 and
ACS8942A. Clocks at 622.08 MHz, 155.52 MHz and
77.76 MHz are available in this example. The jitter results
in the electrical specification section show performance
based on a design like this as it is intended to represent a
simplified “Real-World” application.
In the example application of Figure 14, the ACS8942A is
shown symbolically in place on the Line Card, providing a
dejittering function for a Semtech ACS8525/8526/8527
Line Card Protection device, and frequency multiplication
for onward distribution as required in the line card.
Figure 14 Typical Application
Multiple Line cards
Line Card (0C-12, OC-48)
Recovered Clock
Master Clock
Frame Sync
ACS8515
ACS8525
ACS8526
ACS8527
Master Sync
Slave Clock
FRAMER
SERDES
Multi Frame Sync
Slave Sync
E1/DS1
To/from
SONET/SDH/PDH
Network
LINE
CARD
Stand-by Clock
Stand-by Sync
Clock
Distribution
PROTECTION
ACS8942A
JAM PLL
Low Jitter/Low Skew
Low Jitter up to 622 MHz
Backplane
Slave Sync Card
Master Sync Card
Input CLK Sources
Config.
ACS8510
ACS8520
ACS8522
ACS8530
SETS
Priorities
mP/Serial Bus
SSM
Priorities
Output
CLKs
TCLK
CLK
Primary Ref.
Input/
output
SSM Handling
Function
Line
I/F
Unit
DATA
Clock
Distribution
DATA
SEC
SetsLinecardGenApp_07
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ACS8942A JAM PLL
ADVANCED COMMUNICATIONS
PRELIMINARY
APPLICATION DATASHEET
Figure 15 Line Card Clock Source Example Schematic ACS8525 and ACS8942A
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ACS8942A JAM PLL
ADVANCED COMMUNICATIONS
PRELIMINARY
APPLICATION DATASHEET
Electrical Specifications
ESD Protection
Maximum Ratings
Suitable precautions should be taken to protect against
Important Note: The Absolute Maximum Ratings, Table 6,
electrostatic damage during handling and assembly. This are stress ratings only, and functional operation of the
device incorporates ESD protection structures that
protect the device against ESD damage at ESD input
device at conditions other than those indicated in the
Operating Conditions sections of this specification are not
levels up to at least ±2 kV using the JEDEC Human Body implied. Exposure to the absolute maximum ratings for an
Model (HBD).
extended period may reduce the reliability or useful
lifetime of the product.
Latch-up Protection
This device is protected against latch-up for input currents
pulses of magnitude up to at least ± 100 mA according to
JEDEC Standard No.78 August 1997.
Table 6 Absolute Maximum Ratings
Parameter
Symbol
Minimum
Maximum
Units
Supply Voltage (D.C.):
VDD
-0.5
3.6
V
VDDP2, VDDP1, VDDADIV, VDDARF,
Input Voltage (D.C):
XF_CKP, XF_CKN, CLKP, CLKN
VIN
VIN
-0.5
-0.5
-0.5
3.6
5.5
3.6
V
V
V
Input Voltage:
RESETB, OUT77M, LOCK_EN
Output Voltage:
VOUT
LOCKB, OUTP, OUTN, VCP, VCN
Ambient Operating Temperature Range
Storage Temperature
TA
-40
-50
+85
°C
°C
TSTOR
+150
Operating Conditions
Table 7 Operating Conditions
Parameter
Symbol
Minimum
Typical
Maximum
Units
Supply Voltage (D.C.):
VDD
3.0
3.3
3.6
V
VDDP1, VDDP2, XF_VDDP3, VDDADIV, VDDARF,
Ambient Temperature Range
Supply Current (Note (i))
TA
IDD
-40
-
-
-
-
+85
90
°C
mA
mA
mW
-
-
-
Supply Current (Note (ii))
IDD
140
440
Total Power Dissipation (Note (iii))
PTOT
Notes: (i) Specified at VDD = 3.6 V, Normal mode (internal feedback). OUTP and OUTN terminated to 50 Ω.
(ii) Specified at VDD = 3.6 V, External feedback mode. OUTP and OUTN terminated to 50 Ω.
(iii) Specified at VDD = 3.6 V, External feedback mode. Power dissipation in external loads excluded.
Revision 1.06/March 2005 © Semtech Corp.
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ACS8942A JAM PLL
ADVANCED COMMUNICATIONS
Thermal Characteristics
PRELIMINARY
APPLICATION DATASHEET
Table 8 Thermal Conditions
Parameter
Symbol
θJA
Minimum
Typical
Maximum
Units
°C/W
°C
Thermal Resistance Junction to Ambient (Note (i))
Operating Junction Temperature (Note (ii))
-
-
-
-
37
54
TJCT
Notes: (i) Worst case value assumes center pad not connected to PCB ground.
(ii) Specified relative to ambient temperature of 25°C, using worst case θJA
DC Characteristics
Across all operating conditions, unless otherwise stated.
Table 9 DC Characteristics: TTL/CMOS Schmitt Input Port with Internal Pull-up
Parameter
Schmitt Trigger Low to High Threshold
Schmitt Trigger High to Low Threshold
Pull-up Resistor
Symbol
VT+
Minimum
Typical
1.5
0.94
70
Maximum
1.5
Units
V
1.47
0.90
53
VT-
0.96
V
RPU
IIN
113
kΩ
µA
Input Current
-
-
±10
Table 10 DC Characteristics: TTL/CMOS Input Port with Internal Pull-down
Parameter
Symbol
VIH
Minimum
Typical
Maximum
Units
V
VIN High
IN Low
2
-
-
-
-
V
VIL
0.8
108
±10
V
Pull-down Resistor
Input Current
RPD
IIN
43
-
58
-
kΩ
µA
Table 11 DC Characteristics: LVPECL Input Port
Parameter
Symbol
Minimum
Typical
Maximum
Units
LVPECL Input Offset Voltage
Differential Inputs (Note (ii))
VIO_LVPECL
VDD-2.0
-
VDD-0.5
V
Input Differential Voltage
VID_LVPECL
0.1
VSS
-
-
1.4
V
V
LVPECL Input Low Voltage
Single-ended Input (Note (i))
VIL_LVPECL_S
VDD-1.5
LVPECL Input High Voltage
Single-ended Input (Note (i))
VIL_LVPECL_S
VDD-1.3
-
VDD
V
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ACS8942A JAM PLL
ADVANCED COMMUNICATIONS
PRELIMINARY
APPLICATION DATASHEET
Table 11 DC Characteristics: LVPECL Input Port (cont...)
Parameter
Symbol
Minimum
Typical
Maximum
Units
Input High Current
IIH_LVPECL
-10
-
+10
µA
Input Differential Voltage VID = 1.4 V
Input Low Current
IIL_LVPECL
-10
-
+10
µA
Input Differential Voltage VID = 1.4 V
Notes: (i) Unused differential input terminated to VDD-1.4 V.
(ii) Both pins must remain within the supply voltage, i.e. >VSS and <VDD
.
Table 12 DC Characteristics: LVTTL/CMOS Output Port
Parameter
Output Low Voltage @ IOL (MAX)
Symbol
VOL
Minimum
Typical
Maximum
Units
V
-
-
-
0.4
-
Output High Voltage @ IOH (MIN)
Low Level Output Current @ VOL = 0.4 V
High Level Output Current @ VOH = 2.4 V
VOH
2.4
4.5
6.1
V
IOL
6.6
12.4
8.3
20.2
mA
mA
IOH
Table 13 DC Characteristics: CML Output Port
Parameter
Symbol
IOUT
Minimum
Typical
Maximum
0.4
Units
mA
Ω
I
OUT current source
8
1
-
50
-
Required external load to GND (Note (i))
RLD
1M
Output voltage amplitude single ended at nominal
VOS
400
800
mV
50 Ω load to GND
Output voltage amplitude differential at nominal dual
VOD
800
-
1600
mV
50 Ω load to GND
Note: (i) Recommended external load is 50 Ω. Output is protected against open circuit and grounded output conditions.
Revision 1.06/March 2005 © Semtech Corp.
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ACS8942A JAM PLL
ADVANCED COMMUNICATIONS
Input and Output Interface Terminations
PRELIMINARY
APPLICATION DATASHEET
Figure 17 CML Output Termination (50 to GND) plus
Optional AC Coupling to LVPECL Inputs
Interfacing at both the input and output side to either the
same type or electrically different interface types is
illustrated by the following circuit diagrams, covering
translation to and from CML, LVDS and LVPECL.
Because the output clocks are always running, they may
be AC coupled, allowing the receive end to be at any
common mode voltage. Of course, the lines must always
be terminated at their characteristic impedance.
The preferred termination circuitry for the LVPECL signals
between the ACS8525/26/27 and the ACS8942A is 50 Ω
to VDD -2 Volts (or Thevenin equivalent) as in Figure 16.
The preferred termination for the CML type output is 50 Ω
to GND, as also shown in Figure 16. A.C. coupling may be
used subsequently to translate the levels to other
interface types.
A similar arrangement to that of Figure 17 would be used
when using the CML output to drive an LVDS receiver. The
exact input bias required should be checked against the
LVDS receiver used.
The example of Figure 17 shows the normal external CML
load of, in this case 50 Ω, followed by A.C. coupling and
level translation to LVPECL levels, necessary for the clock
buffer and divider integrated circuit (100EL34W in this
example).
A similar A.C. coupling interface would also be used when
driving the ACS8942A LVPECL inputs with either CML, or
LVDS outputs, with suitable modification of the D.C. load
R1 and R2. For instance an LVDS drive from an ACS8527
is translated to LVPECL for the ACS8942A by the following
circuit of Figure 18.
Note...The bias for the LVPECL input is set for A.C. inputs at a
mid point of approximately 2 V (with a 3.3 V VDD), as opposed
to a normal D.C. coupled bias of VDD - 2 V. This is due to the
push-pull nature of an A.C. coupled signal.
Figure 18 LVDS to LVPECL Input Translation
Figure 16 LVPECL Input Termination and CML Output
Termination
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ACS8942A JAM PLL
ADVANCED COMMUNICATIONS
PRELIMINARY
APPLICATION DATASHEET
AC Characteristics (Jitter Performance)
Table 14 Output Jitter Generation ACS8942A Standalone - 155.52 MHz Input, 622.08 MHz Output
Test Definition
Measured Results (Across all Operating Conditions)
Specification Interface Frequency
Filter Spec
Spec Limit
Typical
Max
Effective Filter
Used(iv)
Units
1.0
1.4
0.1 UI p-p = 40 ps
ps p-p
1 MHz - 20 MHz
5 kHz - 20 MHz
250 kHz - 5 MHz
1 kHz - 5 MHz
1 MHz - 20 MHz
5 kHz - 10 MHz
250 kHz - 5 MHz
1 kHz - 5 MHz
0.10
20.2
2.02
1.3
0.14
35.3
3.53
1.8
-
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
STM-16 = 2.5 GHz
0.5 UI p-p = 201 ps
-
G.813
Option 1
0.1 UI p-p = 161 ps
0.13
71.1
7.11
9.3
0.18
117.4
11.74
17.9
1.79
17.8
1.78
1.4
-
STM-4 = 622 MHz
0.5 UI p-p = 804 ps
-
0.1 UI p-p = 40 ps
STM-16 = 2.5 GHz 12 kHz - 20 MHz
1 MHz - 20 MHz
12 kHz - 5 MHz
1 MHz - 20 MHz
5 kHz - 10 MHz
250 kHz - 5 MHz
1 kHz - 5 MHz
0.93
9.3
-
G.813
Option 2
0.1 UI p-p = 161 ps
STM-4 = 622 MHz
STM-16 = 2.5 GHz
12 kHz - 5 MHz
1 MHz - 20 MHz
5 kHz - 20 MHz
250 kHz - 5 MHz
1 kHz - 5 MHz
0.93
1.0
-
0.1 UI p-p = 40 ps
0.10
20.2
2.02
1.3
0.14
35.3
3.53
1.8
-
0.5 UI p-p = 201 ps
-
ETSI
EN 300 462
0.1 UI p-p = 161 ps
0.13
71.1
7.11
20.2
2.02
1.0
0.18
117.4
11.74
35.3
3.53
1.4
-
0.5 UI p-p = 804 ps
-
STM-4 = 622 MHz
0.15 UI p-p = 600 ps
-
5 kHz - 20 MHz
1 MHz - 20 MHz
12 kHz - 20 MHz
12 kHz - 5 MHz
5 kHz - 10 MHz
1 MHz - 20 MHz
12 kHz - 20 MHz
12 kHz - 5 MHz
0.15 UI p-p = 60 ps
-
OC-48 / STS-48
= 2.5 GHz
0.10
9.3
0.14
17.9
1.79
17.8
1.78
GR-253-
CORE
0.1 UI p-p = 40 ps
0.01 UI rms = 4 ps
0.1 UI p-p = 161 ps
0.01 UI rms = 16 ps
0.93
9.3
OC-12/ STS-12
= 622 MHz
0.93
Notes: (i) Typical case based on actual performance measurements made on the ACS8942A evaluation board with the reference input clock
being supplied from an Agilent ESG series signal generator.
(ii) The loop filter components used are R1 = R2 = 150 Ω, C2 = C4 = 6.8 uF, C1 = C3 = 47nF.
(iii) All measurement results are derived from the phase noise plots using integration ranges defined by the telecommunication
standards' specifications. The p-p value is derived from the measured rms values taking the normal Gaussian crest value (ratio
between p-p and rms) of 10, The Max case values based on worst case estimate.
Revision 1.06/March 2005 © Semtech Corp.
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ACS8942A JAM PLL
ADVANCED COMMUNICATIONS
PRELIMINARY
APPLICATION DATASHEET
Table 15 Output Jitter Generation ACS8525 and ACS8942A Combined - 155.52 MHz Input, 622.08 MHz Output
Test Definition
Measured Results
Specification Interface Frequency
Filter Spec
Spec Limit
Typical
Max Effective Filter
Units
Used(iv)
1.0
1.1
0.1 UI p-p = 40 ps
ps p-p
1 MHz - 20 MHz
5 kHz - 20 MHz
250 kHz - 5 MHz
1 kHz - 5 MHz
1 MHz - 20 MHz
0.10
30.3
3.03
1.5
0.11
38.2
3.82
1.6
-
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
STM-16 = 2.5 GHz
0.5 UI p-p = 201 ps
5 kHz - 10 MHz
250 kHz - 5 MHz
1 kHz - 5 MHz
-
G.813
Option 1
0.1 UI p-p = 161 ps
0.15
111.6
11.16
15.5
1.55
15.5
1.55
1.0
0.16
130.1
13.01
19.1
1.91
19.1
1.91
1.1
-
STM-4 = 622 MHz
0.5 UI p-p = 804 ps
-
0.1 UI p-p = 40 ps
STM-16 = 2.5 GHz 12 kHz - 20 MHz
1 MHz - 20 MHz
12 kHz - 5 MHz
1 MHz - 20 MHz
5 kHz - 10 MHz
250 kHz - 5 MHz
1 kHz - 5 MHz
-
G.813
Option 2
0.1 UI p-p = 161 ps
STM-4 = 622 MHz
STM-16 = 2.5 GHz
12 kHz - 5 MHz
1 MHz - 20 MHz
5 kHz - 20 MHz
250 kHz - 5 MHz
1 kHz - 5 MHz
-
0.1 UI p-p = 40 ps
0.10
30.3
3.03
1.5
0.11
38.2
3.82
1.6
-
0.5 UI p-p = 201 ps
-
ETSI
EN 300 462
0.1 UI p-p = 161 ps
0.15
111.6
11.16
30.3
3.03
1.0
0.16
130.1
13.01
38.2
3.82
1.1
-
0.5 UI p-p = 804 ps
-
STM-4 = 622 MHz
0.15 UI p-p = 600 ps
-
5 kHz - 20 MHz
1 MHz - 20 MHz
12 kHz - 20 MHz
12 kHz - 5 MHz
5 kHz - 10 MHz
1 MHz - 20 MHz
12 kHz - 20 MHz
12 kHz - 5 MHz
0.15 UI p-p = 60ps
-
OC-48 / STS-48
= 2.5 GHz
0.10
15.5
1.55
15.5
1.55
0.10
19.1
1.91
19.1
1.91
GR-253-
CORE
0.1 UI p-p = 40 ps
0.01 UI rms = 4 ps
0.1 UI p-p = 161 ps
0.01 UI rms = 16 ps
OC-12/ STS-12
= 622 MHz
Notes: (i) Typical case based on actual performance measurements made on the ACS8942A evaluation board with the reference input clock
being supplied from an ACS8525. Hence ACS8942A input jitter at approx. 45 ps rms broadband, 500 ps p-p
(ii) The loop filter components used are (R1 = R2 = 150 Ω, C2 = C4 = 6.8 uF, C1 = C3 = 47nF
(iii) All measurement results are derived from the phase noise plots using integration ranges defined by the telecommunication
standards' specifications. The p-p value is derived from the measured rms values taking the normal Gaussian crest value (ratio
between p-p and rms) of 10. Max case values based on worst case estimate.
Revision 1.06/March 2005 © Semtech Corp.
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ACS8942A JAM PLL
ADVANCED COMMUNICATIONS
PRELIMINARY
APPLICATION DATASHEET
Table 16 Output Jitter Generation ACS8942A Standalone - 155.52 MHz Input, 77.76 MHz Output
Test Definition
Measured Results
Specification Interface Frequency
Filter Spec
Spec Limit
Typical
Max Effective Filter
Units
Used(iv)
6.9
9.8
0.1 UI p-p = 40 ps
ps p-p
1 MHz - 20 MHz
5 kHz - 20 MHz
250 kHz - 5 MHz
1 kHz - 5 MHz
1 MHz - 20 MHz
0.69
25.6
2.56
3.7
0.98
36.1
3.61
5.2
-
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
STM-16 = 2.5 GHz
0.5 UI p-p = 201 ps
5 kHz - 10 MHz
250 kHz - 5 MHz
1 kHz - 5 MHz
-
G.813
Option 1
0.1 UI p-p = 161 ps
0.37
96.8
9.68
12.7
1.27
11.2
1.12
6.9
0.52
136.7
13.67
18.0
1.80
15.8
1.58
9.8
-
STM-4 = 622 MHz
0.5 UI p-p = 804 ps
-
0.1 UI p-p = 40 ps
STM-16 = 2.5 GHz 12 kHz - 20 MHz
1 MHz - 20 MHz
12 kHz - 5 MHz
1 MHz - 20 MHz
5 kHz - 10 MHz
250 kHz - 5 MHz
1 kHz - 5 MHz
-
G.813
Option 2
0.1 UI p-p = 161 ps
STM-4 = 622 MHz
STM-16 = 2.5 GHz
12 kHz - 5 MHz
1 MHz - 20 MHz
5 kHz - 20 MHz
250 kHz - 5 MHz
1 kHz - 5 MHz
-
0.1 UI p-p = 40 ps
0.69
25.6
2.56
3.7
0.98
36.1
3.61
5.2
-
0.5 UI p-p = 201 ps
-
ETSI
EN 300 462
0.1 UI p-p = 161 ps
0.37
96.8
9.68
25.6
2.56
6.9
0.52
136.7
13.67
36.1
3.61
9.8
-
0.5 UI p-p = 804 ps
-
STM-4 = 622 MHz
0.15 UI p-p = 600 ps
-
5 kHz - 20 MHz
1 MHz - 20 MHz
12 kHz - 20 MHz
12 kHz - 5 MHz
5 kHz - 10 MHz
1 MHz - 20 MHz
12 kHz - 20 MHz
12 kHz - 5 MHz
0.15 UI p-p = 60ps
-
OC-48 / STS-48
= 2.5 GHz
0.69
12.7
1.27
11.2
1.12
0.98
18.0
1.80
15.8
1.58
GR-253-
CORE
0.1 UI p-p = 40 ps
0.01 UI rms = 4 ps
0.1 UI p-p = 161 ps
0.01 UI rms = 16 ps
OC-12/ STS-12
= 622 MHz
Notes: (i) Typical case based on actual performance measurements made on the ACS8942A evaluation board with the reference input clock
being supplied from an Agilent ESG series signal generator.
(ii) The loop filter components used are R1 = R2 = 150 Ω, C2 = C4 = 6.8 uF, C1 = C3 = 47 nF.
(iii) All measurement results are derived from the phase noise plots using integration ranges defined by the telecommunication
standards' specifications. The p-p value is derived from the measured rms values taking the normal Gaussian crest value (ratio
between p-p and rms) of 10, The Max case values based on worst case estimate.
Revision 1.06/March 2005 © Semtech Corp.
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ACS8942A JAM PLL
ADVANCED COMMUNICATIONS
PRELIMINARY
APPLICATION DATASHEET
Table 17 Output Jitter Generation ACS8525 and ACS8942A Combined - 155.52 MHz Input, 77.76 MHz Output
Test Definition
Measured Results
Specification Interface Frequency
Filter Spec
Spec Limit
Typical
Max Effective Filter
Units
Used(iv)
7.8
11.0
0.1 UI p-p = 40 ps
ps p-p
1 MHz - 20 MHz
5 kHz - 20 MHz
250 kHz - 5 MHz
1 kHz - 5 MHz
1 MHz - 20 MHz
0.78
33.0
3.30
4.2
1.10
46.6
4.66
5.9
-
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
STM-16 = 2.5 GHz
0.5 UI p-p = 201 ps
5 kHz - 10 MHz
250 kHz - 5 MHz
1 kHz - 5 MHz
-
G.813
Option 1
0.1 UI p-p = 161 ps
0.42
135.8
13.58
17.6
1.76
16.2
1.62
7.8
0.59
191.9
19.19
24.8
2.48
22.8
2.28
11.0
1.10
46.6
4.66
5.9
-
STM-4 = 622 MHz
0.5 UI p-p = 804 ps
-
0.1 UI p-p = 40 ps
STM-16 = 2.5 GHz 12 kHz - 20 MHz
1 MHz - 20 MHz
12 kHz - 5 MHz
1 MHz - 20 MHz
5 kHz - 10 MHz
250 kHz - 5 MHz
1 kHz - 5 MHz
-
G.813
Option 2
0.1 UI p-p = 161 ps
STM-4 = 622 MHz
STM-16 = 2.5 GHz
12 kHz - 5 MHz
1 MHz - 20 MHz
5 kHz - 20 MHz
250 kHz - 5 MHz
1 kHz - 5 MHz
-
0.1 UI p-p = 40 ps
0.78
33.0
3.30
4.2
-
0.5 UI p-p = 201 ps
-
ETSI
EN 300 462
0.1 UI p-p = 161 ps
0.42
135.8
13.58
33.0
3.30
7.8
0.59
191.9
19.19
46.6
4.66
11.0
1.10
24.8
2.48
22.8
2.28
-
0.5 UI p-p = 804 ps
-
STM-4 = 622 MHz
0.15 UI p-p = 600 ps
-
5 kHz - 20 MHz
1 MHz - 20 MHz
12 kHz - 20 MHz
12 kHz - 5 MHz
5 kHz - 10 MHz
1 MHz - 20 MHz
12 kHz - 20 MHz
12 kHz - 5 MHz
0.15 UI p-p = 60ps
-
OC-48 / STS-48
= 2.5 GHz
0.78
17.6
1.76
16.2
1.62
GR-253-
CORE
0.1 UI p-p = 40 ps
0.01 UI rms = 4 ps
0.1 UI p-p = 161 ps
0.01 UI rms = 16 ps
OC-12/ STS-12
= 622 MHz
Notes: (i) Typical case based on actual performance measurements made on the ACS8942A evaluation board with the reference input clock
being supplied from an ACS8525. Hence ACS8942A input jitter at approx. 45 ps rms broadband, 500 ps p-p.
(ii) The loop filter components used are R1 = R2 = 150 Ω, C2 = C4 = 6.8 uF, C1 = C3 = 47 nF.
(iii) All measurement results are derived from the phase noise plots using integration ranges defined by the telecommunication
standards' specifications. The p-p value is derived from the measured rms values taking the normal Gaussian crest value (ratio
between p-p and rms) of 10, The Max case values based on worst case estimate.
Revision 1.06/March 2005 © Semtech Corp.
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ACS8942A JAM PLL
ADVANCED COMMUNICATIONS
PRELIMINARY
APPLICATION DATASHEET
Table 18 Output Jitter Generation ACS8942A Standalone - in External Feedback Mode - 19.44 MHz Input,
77.76 MHz Output
Test Definition
Measured Results
Specification Interface Frequency
Filter Spec
Spec Limit
Typical
Max Effective Filter
Units
Used(iv)
7.3
10.3
1.03
38.3
3.83
5.9
0.1 UI p-p = 40 ps
ps p-p
1 MHz - 20 MHz
5 kHz - 20 MHz
250 kHz - 5 MHz
1 kHz - 5 MHz
1 MHz - 20 MHz
0.73
27.1
2.71
4.2
-
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
STM-16 = 2.5 GHz
0.5 UI p-p = 201 ps
5 kHz - 10 MHz
250 kHz - 5 MHz
1 kHz - 5 MHz
-
G.813
Option 1
0.1 UI p-p = 161 ps
0.42
175.4
17.54
13.6
1.36
12.1
1.21
7.3
0.59
247.7
24.77
19.2
1.92
17.0
-
STM-4 = 622 MHz
0.5 UI p-p = 804 ps
-
0.1 UI p-p = 40 ps
STM-16 = 2.5 GHz 12 kHz - 20 MHz
1 MHz - 20 MHz
12 kHz - 5 MHz
1 MHz - 20 MHz
5 kHz - 10 MHz
250 kHz - 5 MHz
1 kHz - 5 MHz
-
G.813
Option 2
0.1 UI p-p = 161 ps
STM-4 = 622 MHz
STM-16 = 2.5 GHz
12 kHz - 5 MHz
1 MHz - 20 MHz
5 kHz - 20 MHz
250 kHz - 5 MHz
1 kHz - 5 MHz
1.70
10.3
1.03
38.3
3.83
5.9
-
0.1 UI p-p = 40 ps
0.73
27.1
2.71
4.2
-
0.5 UI p-p = 201 ps
-
ETSI
EN 300 462
0.1 UI p-p = 161 ps
0.42
175.4
17.54
27.1
2.71
7.3
0.59
247.7
24.77
38.3
3.83
10.3
1.03
19.2
1.92
17.0
-
0.5 UI p-p = 804 ps
-
STM-4 = 622 MHz
0.15 UI p-p = 600 ps
-
5 kHz - 20 MHz
1 MHz - 20 MHz
12 kHz - 20 MHz
12 kHz - 5 MHz
5 kHz - 10 MHz
1 MHz - 20 MHz
12 kHz - 20 MHz
12 kHz - 5 MHz
0.15 UI p-p = 60ps
-
OC-48 / STS-48
= 2.5 GHz
0.73
13.6
1.36
12.1
1.21
GR-253-
CORE
0.1 UI p-p = 40 ps
0.01 UI rms = 4 ps
0.1 UI p-p = 161 ps
0.01 UI rms = 16 ps
OC-12/ STS-12
= 622 MHz
1.70
Notes: (i) Typical case based on actual performance measurements made on the ACS8942A evaluation board with the reference input clock
being supplied from an Agilent ESG series signal generator.
(ii) The loop filter components used are R1 = R2 = 1.1 kΩ, C2 = C4 = 680 nF, C1 = C3 = 6.8 nF.
(iii) All measurement results are derived from the phase noise plots using integration ranges defined by the telecommunication
standards' specifications. The p-p value is derived from the measured rms values taking the normal Gaussian crest value (ratio
between p-p and rms) of 10, The Max case values based on worst case estimate.
Revision 1.06/March 2005 © Semtech Corp.
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ACS8942A JAM PLL
ADVANCED COMMUNICATIONS
PRELIMINARY
APPLICATION DATASHEET
Table 19 Output Jitter Generation ACS8525 and ACS8942A Combined - with ACS8942A in External Feedback Mode
- 19.44 MHz Input, 77.76 MHz Output
Test Definition
Measured Results
Specification Interface Frequency
Filter Spec
Spec Limit
Typical
Max Effective Filter
Units
Used(iv)
7.3
10.3
1.03
37.7
3.77
5.9
0.1 UI p-p = 40 ps
ps p-p
1 MHz - 20 MHz
5 kHz - 20 MHz
250 kHz - 5 MHz
1 kHz - 5 MHz
1 MHz - 20 MHz
0.73
26.7
2.67
4.2
-
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
STM-16 = 2.5 GHz
0.5 UI p-p = 201 ps
5 kHz - 10 MHz
250 kHz - 5 MHz
1 kHz - 5 MHz
-
G.813
Option 1
0.1 UI p-p = 161 ps
0.42
193.9
19.39
13.8
1.38
12.2
1.22
7.3
0.59
273.9
27.39
19.4
1.94
17.3
1.73
10.3
1.03
37.7
3.77
5.9
-
STM-4 = 622 MHz
0.5 UI p-p = 804 ps
-
0.1 UI p-p = 40 ps
STM-16 = 2.5 GHz 12 kHz - 20 MHz
1 MHz - 20 MHz
12 kHz - 5 MHz
1 MHz - 20 MHz
5 kHz - 10 MHz
250 kHz - 5 MHz
1 kHz - 5 MHz
-
G.813
Option 2
0.1 UI p-p = 161 ps
STM-4 = 622 MHz
STM-16 = 2.5 GHz
12 kHz - 5 MHz
1 MHz - 20 MHz
5 kHz - 20 MHz
250 kHz - 5 MHz
1 kHz - 5 MHz
-
0.1 UI p-p = 40 ps
0.73
26.7
2.67
4.2
-
0.5 UI p-p = 201 ps
-
ETSI
EN 300 462
0.1 UI p-p = 161 ps
0.42
193.9
19.39
26.7
2.67
7.3
0.59
273.9
27.39
37.7
3.77
10.3
1.03
19.4
1.94
17.3
1.73
-
0.5 UI p-p = 804 ps
-
STM-4 = 622 MHz
0.15 UI p-p = 600 ps
-
5 kHz - 20 MHz
1 MHz - 20 MHz
12 kHz - 20 MHz
12 kHz - 5 MHz
5 kHz - 10 MHz
1 MHz - 20 MHz
12 kHz - 20 MHz
12 kHz - 5 MHz
0.15 UI p-p = 60ps
-
OC-48 / STS-48
= 2.5 GHz
0.73
13.8
1.38
12.2
1.22
GR-253-
CORE
0.1 UI p-p = 40 ps
0.01 UI rms = 4 ps
0.1 UI p-p = 161 ps
0.01 UI rms = 16 ps
OC-12/ STS-12
= 622 MHz
Notes: (i) Typical case based on actual performance measurements made on the ACS8942A evaluation board with the reference input clock
being supplied from an ACS8525. Hence ACS8942A input jitter at approx. 45 ps rms broadband, 500 ps p-p.
(ii) The loop filter components used are R1 = R2 = 1.1 kΩ, C2 = C4 = 680 nF, C1 = C3 = 6.8 nF.
(iii) All measurement results are derived from the phase noise plots using integration ranges defined by the telecommunication
standards' specifications. The p-p value is derived from the measured rms values taking the normal Gaussian crest value (ratio
between p-p and rms) of 10, The Max case values based on worst case estimate.
Revision 1.06/March 2005 © Semtech Corp.
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ACS8942A JAM PLL
ADVANCED COMMUNICATIONS
Input/Output Timing
PRELIMINARY
APPLICATION DATASHEET
Figure 19 Input Output Typical Delays
Input/Output
Delay (Typ)
0.5 ns
CLKP/N to OUTP/OUTN
155.52 MHz Input
622.08 MHz Output
Delay (Typ)
0.9 ns
CLKP/N to OUTP/OUTN
155.52 MHz Input
77.76 MHz Output
External Feedback (19.44 MHz)
Alignment of Input Clocks
XF_CLKP/N to CLKP/N
Delay (Typ)
0.3 ns
19.44 MHz Input
19.44 MHz Input
F8942AD_021IP_OPTiming_02
Revision 1.06/March 2005 © Semtech Corp.
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ACS8942A JAM PLL
ADVANCED COMMUNICATIONS
PRELIMINARY
APPLICATION DATASHEET
Package Information
Figure 20 QFN32 Package.
Thermal Conditions
The device is rated for full temperature range when this
package is used with a 4-layer or more PCB. Copper
coverage must exceed 50%. All pins must be soldered to
the PCB. Maximum operating temperature must be
reduced when the device is used with a PCB with less than
these requirements.
As the device includes a large thermal die paddle which
should ideally be soldered to the PCB (ground plane) in
addition to the pins for improved pull-off strength and
thermal dissipation characteristics.
Revision 1.06/March 2005 © Semtech Corp.
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ACS8942A JAM PLL
ADVANCED COMMUNICATIONS
Figure 21 Typical 32 Pin QFN PCB Footprint
PRELIMINARY
APPLICATION DATASHEET
Not Drawn to Scale
X
Pitch
Y
F1
F1
Gmin
Zmax
F8542AD_004QFNFootprt32_03
Table 20 Footprint Measurements
Parameter
Pitch
Zmax
5.0
Gmin
4.0
F1
3.5
140
Y
X
Dimension/mm
Dimension/thou
0.5
20
0.5
20
0.25
10
200
160
Revision 1.06/March 2005 © Semtech Corp.
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ACS8942A JAM PLL
ADVANCED COMMUNICATIONS
PRELIMINARY
APPLICATION DATASHEET
Abbreviations
CMU
I/O
LVDS
LVPECL
Clock Multiplier Unit
Input - Output
Low Voltage Differential Signal
Low Voltage (3.3 V) PECL
[6] ITU-T G.703 (10/1998)
Physical/electrical characteristics of hierarchical digital
interfaces
[7] ITU-T G.736 (03/1993)
Characteristics of a synchronous digital multiplex
equipment operating at 2048 kbit/s
OC-3/12/48 Optical Carrier Signal Level 3/12
155.52 Mbps/ 622.08 Mbps/
2.488.32 Gbps
PECL
PFD
PLL
p-p
rms
SDH
SEC
SETS
SONET
[8] TU-T G.742 (1988)
Second order digital multiplex equipment operating at
8448 kbit/s, and using positive justification
Positive Emitter Coupled Logic
Phase and Frequency Detector
Phase Locked Loop
peak-to-peak
root-mean-square
Synchronous Digital Hierarchy
SDH/SONET Equipment Clock
Synchronous Equipment Timing source
Synchronous Optical Network
[9] ITU-T G.783 (10/2000)
Characteristics of synchronous digital hierarchy (SDH)
equipment functional blocks
[10] ITU-T G.812 (06/1998)
Timing requirements of slave clocks suitable for use as
node clocks in synchronization networks
STM-1/4/16 Synchronous Transport Module Levels
1/4/16: 155.52 Mbps/ 622.08 Mbps
(SDH)/ 2.488.32 Gbps
[11] ITU-T G.813 (08/1996)
Timing characteristics of SDH equipment slave clocks
(SEC)
STS-12
Synchronous Transport Signal Level: 12,
[12] ITU-T G.822 (11/1988)
622.08 Mbps (SONET)
Controlled slip rate objectives on an international digital
connection
UI
uP (µP)
VCO
Unit Interval
Microprocessor
Voltage Controlled Oscillator
[13] ITU-T G.823 (03/2000)
The control of jitter and wander within digital networks
which are based on the 2048 kbit/s hierarchy
[14] ITU-T G.824 (03/2000)
References and Related Standards
The control of jitter and wander within digital networks
which are based on the 1544 kbit/s hierarchy
[1] ANSI T1 1.101-1999 (1999)
Synchronization Interface Standard
[15] ITU-T G.825 (03/2000)
The control of jitter and wander within digital networks
which are based on the Synchronous Digital Hierarchy
(SDH)
[2] AT & T 62411 (12/1990)
ACCUNET ® T1.5 Service description and Interface
Specification
[16] ITU-T K.41 (05/1998)
[3] ETSI ETS 300 462-3, (01/1997)
Transmission and Multiplexing (TM); Generic
requirements for synchronization networks; Part 3: The
control of jitter and wander within synchronization
networks
Resistability of internal interfaces of telecommunication
centres to surge overvoltages
[17] Telcordia GR-253-CORE, Issue 3 (09/ 2000)
Synchronous Optical Network (SONET) Transport
Systems: Common Generic Criteria
[4] ETSI ETS 300 462-5 (09/1996)
Transmission and Multiplexing (TM); Generic
requirements for synchronization networks; Part 5: Timing
characteristics of slave clocks suitable for operation in
Synchronous Digital Hierarchy (SDH) equipment
[18] Telcordia GR-499-CORE, Issue 2 (12/1998)
Transport Systems Generic Requirements (TSGR)
Common requirements
[5] IEEE 1149.1 (1990)
Standard Test Access Port and Boundary-Scan
Architecture
[19] Telcordia GR-1244-CORE, Issue 2 (12/2000)
Clocks for the Synchronized Network: Common Generic
Criteria
Revision 1.06/March 2005 © Semtech Corp.
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ACS8942A JAM PLL
ADVANCED COMMUNICATIONS
PRELIMINARY
APPLICATION DATASHEET
Trademark Acknowledgements
Semtech and the Semtech S logo are registered
trademarks of Semtech Corporation.
Application Datasheet content reflects the intention of the
design. The Application Datasheet is raised to
PRELIMINARY status when initial prototype devices are
physically available, and the Application Datasheet
content more accurately represents the realization of the
design. The Application Datasheet is only raised to FINAL
status after the device has been fully characterized, and
the datasheet content updated with measured, rather
than simulated parameter values.
Telcordia is a registered trademark of Telcordia
Technologies.
Revision Status/History
The Revision Status, as shown in top center of the
Application Datasheet header bar, may be TARGET,
PRELIMINARY, or FINAL, and refers to the status of the
Device (not the Application Datasheet), within the design
cycle. TARGET status is used when the design is being
realized but is not yet physically available, and the
This is a PRELIMINARY release of the ACS8942A
Application Datasheet. Changes made for this document
revision are given below.
Table 21 Revision History
Revision
Reference
Description of Changes
1.00/May 2003 to 1.04/August
2004
All Pages
All pages
Internal releases
1.05/March 2005
Datasheet completely revised using measured data from first
production batch.
1.06/March 2005
Page 5
Output type changed from PECL to CML.
All Pages
Minortypographical corrections and revision level updated.
Revision 1.06/March 2005 © Semtech Corp.
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ACS8942A JAM PLL
ADVANCED COMMUNICATIONS
PRELIMINARY
APPLICATION DATASHEET
Notes
Revision 1.06/March 2005 © Semtech Corp.
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ACS8942A JAM PLL
ADVANCED COMMUNICATIONS
PRELIMINARY
APPLICATION DATASHEET
Ordering Information
Table 22 Parts List
Part Number
Description
JAM PLL Jitter Attenuating, Multiplying Phase Locked Loop for SONET/SDH Applications to OC-48/STM-16
ACS8942A
Disclaimers
Life support- This product is not designed or intended for use in life support equipment, devices or systems, or other critical
applications. This product is not authorized or warranted by Semtech for such use.
Right to change- Semtech Corporation reserves the right to make changes, without notice, to this product. Customers are advised
to obtain the latest version of the relevant information before placing orders.
Compliance to relevant standards- Operation of this device is subject to the User’s implementation and design practices. It is the
responsibility of the User to ensure equipment using this device is compliant to any relevant standards.
Contacts
For Additional Information, contact the following:
Semtech Corporation Advanced Communications Products
E-mail:
Internet:
USA:
sales@semtech.com
acsupport@semtech.com
http://www.semtech.com
Mailing Address:
Street Address:
Tel: +1 805 498 2111,
P.O. Box 6097, Camarillo, CA 93011-6097
200 Flynn Road, Camarillo, CA 93012-8790
Fax: +1 805 498 3804
FAR EAST: 11F, No. 46, Lane 11, Kuang Fu North Road, Taipei, R.O.C.
Tel: +886 2 2748 3380 Fax: +886 2 2748 3390
EUROPE: Semtech Ltd., Units 2 and 3, Park Court, Premier Way,
Abbey Park Industrial Estate, Romsey, Hampshire, SO51 9DN
Tel: +44 (0)1794 527 600
Fax: +44 (0)1794 527 601
ISO9001
CERTIFIED
Revision 1.06/March 2005 © Semtech Corp.
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