ACS8944 [SEMTECH]
Jitter Attenuating, Multiplying Phase Locked Loop for OC-12/STM-4; 抖动衰减，乘法锁相环的OC- 12 / STM- 4
| 型号： | ACS8944 |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | Jitter Attenuating, Multiplying Phase Locked Loop for OC-12/STM-4 |
| 文件： | 总24页 (文件大小：468K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ACS8944 JAM PLL
Jitter Attenuating, Multiplying Phase Locked Loop
for OC-12/STM-4
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Introduction
Features
The ACS8944 JAM PLL is a Jitter- Attenuating, Multiplying
Phase-Locked Loop, for generating low jitter output clocks
compliant up to SONET OC-12 and STM-4 622.08 MHz
specifications. Its primary function is to clean up clock
jitter for high performance optical line cards which have
OC-3 or OC-12 SONET serializers or framers, and is the
entry level device in Semtech’s range of JAM PLLs.
Meets rms jitter requirements of:
Telcordia GR-253-CORE[8] for OC-3 and OC-12
ITU-T G.813[4]/G.812[3] for STM-1 and STM-4 rates
ETSI EN300-462-7[1]/EN302-084[2] up to STM-16
rates
Typical jitter generation down to:
The ACS8944 JAM PLL has a single differential LVPECL
input and a single differential LVPECL output. Both input
and output clock frequencies are individually
programmable and can be hardware configured to be any
of 19.44 MHz, 38.88 MHz, 77.76 MHz or 155.52 MHz.
• 0.3 ps rms for 250 kHz to 5 MHz band for G.813,
or EN300-462, at STM-4 (OC-12) rates
• 2.8 ps rms for 12 kHz to 20 MHz band (against
4.02 ps rms for GR-253-CORE at OC-48 rate)
The headline jitter figures quoted for the ACS8944
depend on the frequency band over which the jitter is
measured. For example, typical stand-alone output jitter
is typically 2.8 ps rms (well within GR-253-CORE[8]
specification requirements of 16.1 ps rms for OC-12 and
64.3 ps rms for OC-3).
Pull-in range ±400 ppm about center input frequency
Frequency translation e.g. 19.44 MHz to 155.52 MHz
3.3 V operation, - 40 to +85°C temperature range
Small outline leadless 7 mm x 7 mm QFN48 package
Demonstration Board available on request
PLL bandwidth and jitter peaking are fully adjustable.
The device's operating bandwidth (and consequently the
jitter attenuation point relating to this bandwidth) is set by
external passive components in a differential
Supports bandwidths from 2 kHz for superior input
jitter filtering
arrangement which offers good noise immunity.
Lead (Pb)-free version available (ACS8944T), RoHS[9]
and WEEE[10] compliant
[1],[2], etc.
Note...For items marked
references are given in full
Block Diagram
in the Reference Section on page 21.
Figure 1 Simplified Block Diagram of the ACS8944 JAM PLL
Loop
Filter
RESETB
VC
Differential
Input Reference
LVPECL
Differential
Clock Output
LVPECL
PFD
Charge
Pump
155.52 MHz
77.76 MHz
38.88 MHz
19.44 MHz
155.52 MHz
77.76 MHz
38.88 MHz
19.44 MHz
Frequency
Divider
2.5 GHz
VCO
Frequency
Divider
LVPECL
LVPECL
Control and Monitor
F8944D_001Blockdiag_02
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ACS8944 JAM PLL
Table of Contents
ADVANCED COMMUNICATIONS FINAL
DATASHEET
Table of Contents
Section
Page
Introduction................................................................................................................................................................................................ 1
Block Diagram............................................................................................................................................................................................ 1
Features ..................................................................................................................................................................................................... 1
Table of Contents ...................................................................................................................................................................................... 2
Pin Diagram ............................................................................................................................................................................................... 3
Pin Description........................................................................................................................................................................................... 3
Description................................................................................................................................................................................................. 5
Input....................................................................................................................................................................................................5
Input Configuration ............................................................................................................................................................................5
Output.................................................................................................................................................................................................5
Voltage Controlled Oscillator.............................................................................................................................................................6
Jitter Filtering......................................................................................................................................................................................6
Jitter Filtering: Partnering with Semtech Line Card Protection Part...............................................................................................6
Input Jitter Tolerance.........................................................................................................................................................................6
Jitter Transfer .....................................................................................................................................................................................6
Phase Noise Performance.................................................................................................................................................................7
Loop Filter Components ....................................................................................................................................................................7
Output Jitter........................................................................................................................................................................................8
System Reset .....................................................................................................................................................................................8
Layout Recommendations ................................................................................................................................................................8
Lock Detector.....................................................................................................................................................................................8
Applications........................................................................................................................................................................................9
Application Schematic of Combined ACS8525 and ACS8944.................................................................................................... 10
Electrical Specifications......................................................................................................................................................................... 11
Maximum Ratings ........................................................................................................................................................................... 11
Operating Conditions ...................................................................................................................................................................... 11
Thermal Characteristics ................................................................................................................................................................. 12
AC Characteristics........................................................................................................................................................................... 12
DC Characteristics .......................................................................................................................................................................... 12
Input and Output Interface Terminations...................................................................................................................................... 14
Input/Output Timing ....................................................................................................................................................................... 14
Jitter Performance .......................................................................................................................................................................... 15
Package Information .............................................................................................................................................................................. 19
Thermal Conditions......................................................................................................................................................................... 20
References and Related Standards...................................................................................................................................................... 21
Abbreviations .......................................................................................................................................................................................... 21
Trademark Acknowledgements............................................................................................................................................................. 22
Revision Status/History ......................................................................................................................................................................... 22
Notes ....................................................................................................................................................................................................... 23
Ordering Information .............................................................................................................................................................................. 24
Disclaimers...................................................................................................................................................................................... 24
Contacts........................................................................................................................................................................................... 24
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ACS8944 JAM PLL
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Pin Diagram
Figure 2 ACS8944 Pin Diagram
8
6
7
4
3
S
4
7
6
4
4
4
4
1
0
9
8
7
1
2
3
4
5
6
7
8
9
VDDO1
OUTN
OUTP
NC1
36 VCN
35 VCP
34 VDDARF
33 NC15
32 NC14
31 NC13
30 NC12
29 VDDP1
28 CLKP
NC2
NC3
NC4
NC5
ACS8944
NC6
10 NC7
11 NC8
12 NC9
27 CLKN
26 VDDADIV
25 VDDADIV
Dimensions: 7 mm x 7 mm
Lead Pitch: 0.5 mm
(Leads centered on package)
Connect large central pad
to GND
F8944_D_002PINDIAG_04
Pin Description
Table 1 Power Pins
Pin No.
Symbol
VDDO1
I/O
P
Type
Description
1
-
-
Supply voltage. Supply to OUTP & OUTN clock output pins, +3.3 Volts ±5%.
25, 26 VDDADIV
P
Supply voltage. Supply for internal dividers in VCO loop, kept as an isolated supply to
allow for low supply noise for the output divider stages. +3.3 Volts ±5%.
29, 43 VDDP1,VDDP2
P
P
-
-
Supply voltage. Supply to input and output pins. +3.3 Volts ±5%.
34
VDDARF
Supply voltage. Supply for phase and frequency detector (PFD), kept as an isolated supply
to allow for low supply noise. +3.3 Volts ±5%.
38
39
49
VDDOSC
VSSOSC
VSS0
P
P
P
-
-
-
Supply voltage. Supply input to the internal VCO. +3.3 Volts +5%/-10%
Supply ground. 0 V for VCO.
Supply ground. Common 0 V.
This is the central leadframe pad on the underneath of the package.
Note...I = Input, O = Output, P = Power, LVTTL/LVCMOSU = LVTTL/LVCMOS input with pull-up resistor, LVTTL/LVCMOSD = LVTTL/LVCMOS input
with pull-down resistor.
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ACS8944 JAM PLL
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Table 2 Internally Connected (IC)/ Not Connected (NC) Pins
Pin No.
Symbol
I/O
Type
Description
Internally connected. Connect to ground.
18,19, IC1, IC2,
37, 41 IC3, IC4,
-
-
42
IC5
-
-
-
-
Internally connected. Connect to VDD.
Not connected. Leave to float.
4, 5,
6, 7,
8, 9,
NC1, NC2,
NC3, NC4,
NC5, NC6,
10, 11, NC7, NC8,
12, 20, NC9, NC10,
21, 30, NC11, NC12
31, 32, NC13, NC14,
33, 44, NC15, NC16,
45, 47, NC17, NC18,
48
NC19
Table 3 Functional Pins
Pin No.
Symbol
OUTN
I/O
Type
Description
2
O
LVPECL
LVPECL differential output at a rate from 19.44 MHz up to 155.52 MHz. Partnered with
pin 3. See pin 3 description for more detail.
3
OUTP
O
LVPECL
LVPECL differential output at a rate from 19.44 MHz up to 155.52 MHz. Partnered with
pin 2. The output frequency selection is preset by externally connecting OP_FSEL pin (pin
46), to one from a set of four output frequency pins CFG_OUT[3:0] (Pins 16, 15, 14 and
13); which, on reset will give a corresponding generated output frequency of 19.44 MHz,
38.88 MHz, 77.76 MHz, or 155.52 MHz.
13
14
15
16
17
CFG_OUT0
CFG_OUT1
CFG_OUT2
CFG_OUT3
LOCKB
O
O
O
O
O
LVTTL/LVCMOS Configuration pin used to set input reference frequency for CLK (N and P) and output clock
frequency for OUT (N and P) used in conjunction with pins 14, 15, 16, and 46 as defined in
Tables 4 and 5.
LVTTL/LVCMOS Configuration pin used to set input reference frequency for CLK (N and P) and output clock
frequency for OUT (N and P) used in conjunction with pins 13, 15, 16 and 46 as defined in
Tables 4 and 5.
LVTTL/LVCMOS Configuration pin used to set input reference frequency for CLK (N and P) and output clock
frequency for OUT (N and P) used in conjunction with pins 13, 14, 16 and 46 as defined in
Tables 4 and 5.
LVTTL/LVCMOS Configuration pin used to set input reference frequency for CLK (N and P) and output clock
frequency for OUT (N and P) used in conjunction with pins 13, 14, 15 and 46 as defined in
Tables 4 and 5.
Analog
Lock detect output. This is a pulse width modulated output current, with each pulse
typically +10 µA. The output produces a pulse with a width in proportion to the phase error
seen at the internal phase detector. This pin should be connected via an external parallel
capacitor and resistor to ground. The pin voltage will then give an indication of phase lock:
When low, the device is phase locked; when high the device has frequent large phase
errors and so is not phase locked. The value of the RC components used determines the
time and level of consistency required for lock indication.
22
23
EXT1
EXT2
I
I
LVTTL/LVCMOSD Input frequency configuration pin. See Table 4.
LVTTL/LVCMOSD Input frequency configuration pin. See Table 4.
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ACS8944 JAM PLL
ADVANCED COMMUNICATIONS
Table 3 Functional Pins (cont...)
FINAL
DATASHEET
Pin No.
24
Symbol
EXT3
I/O
Type
Description
I
I
LVTTL/LVCMOSD Input frequency configuration pin. See Table 4.
27
CLKN
LVPECL
LVPECL
Input reference clock to which the PLL will phase and frequency lock (negative pin of
differential pair, partnered with pin 28). Can accept 19.44 MHz, 38.88 MHz, 77.76 MHz or
155.52 MHz to within ±400 ppm.
28
CLKP
I
Input reference clock to which the PLL will phase and frequency lock (positive pin of
differential pair, partnered with pin 27). Can accept 19.44 MHz, 38.88 MHz, 77.76 MHz or
155.52 MHz to within ±400 ppm.
35
36
40
46
VCP
I/O
Analog
Analog
Connection for external loop filter components. This is the differential control voltage input
to the internal VCO and the internal differential charge pump output.
VCN
I/O
Connection for external loop filter components. This is the differential control voltage input
to the internal VCO and the internal differential charge pump output.
RESETB
OP_FSEL
I
I
LVTTL/LVCMOSU Active low reset signal with pull up and Schmitt type input. Used to apply a Power On Reset
Schmitt Trigger (POR) signal during system initialization. Should be connected via a capacitor to ground.
LVTTL/
LVCMOSD
Output Frequency Select Pin. Used with the Output Frequency Configuration pins (pins 13
to 16) to configure the output frequency (on power-up/reset) of the differential output
OUT(N/P). See Table 5.
Note...I = Input, O = Output, P = Power, LVTTL/LVCMOSU = LVTTL/LVCMOS input with pull-up resistor, LVTTL/LVCMOSD = LVTTL/LVCMOS input
with pull-down resistor
(VSS), in accordance with the configuration scheme in
Description
Table 4, e.g. for an expected input of 155.52 MHz,
The ACS8944 is a low jitter integrated PLL for clock
connect EXT1 to VSS, EXT2 to CFG_OUT1 and EXT3 to
dejittering and clock rate translation, meeting the jitter
requirements for SONET up to and including OC-12
CFG_OUT3.
(622.08 MHz systems). It is compliant to the relevant ITU,
Telcordia/Bellcore and ETSI standards for at least OC-3
Table 4 Input Frequency Selection
(155.52 MHz) and OC-12 (622.08 MHz) - equivalent to
the corresponding STM-1 and STM-4 rates.
For Expected
Input
Frequency
of
Connect
EXT2
EXT1
EXT3
It can be configured for a range of applications using a
minimal number of external components and is available
in a small form factor QFN48 package at 7 mm x 7 mm x
0.9 mm outer dimensions.
to
19.44 MHz
38.88 MHZ
77.76 MHz
155.52 MHz
CFG_OUT3
CFG_OUT0
VDD
VDD
CFG_OUT3
CFG_OUT3
CFG_OUT3
CFG_OUT3
CFG_OUT1
VDD
Input
VSS
CFG_OUT1
The ACS8944 has a single, LVPECL, differential input
(CLKN/P, pins 27 and 28). It is designed to operate with
any of 19.44 MHz, 38.88 MHz, 77.76 MHz or
155.52 MHz input references, and can pull in an input
which is within ±400 ppm of these spot frequencies.
Output
The ACS8944 has a single, LVPECL, differential output
(OUTN/P, pins 2 and 3).
Input Configuration
The frequency of the output is determined by the wiring of
OP_FSEL to the appropriate CFG_OUT pin in accordance
The input must be configured for the expected input
frequency. This is achieved by connecting the EXT[3:1]
pins, to the configuration pins or to power (VDD) or ground with Table 5.
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ACS8944 JAM PLL
ADVANCED COMMUNICATIONS
Table 5 Output Frequency Selection
FINAL
DATASHEET
z High input jitter attenuation and roll-off:
For Output Frequency of
19.44 MHz
Connect OP_FSEL to
z First, second and third order roll-off points:
• - 20 dB/decade 18 Hz to 750 Hz,
• - 40 dB/decade 750 Hz to 200 kHz and
• - 60 dB/decade for >200 kHz.
CFG_OUT3
CFG_OUT2
CFG_OUT1
CFG_OUT0
38.88 MHZ
77.76 MHz
155.52 MHz
z Typical final output jitter, e.g. 2.9 ps rms (measured
over the integration range 12 kHz-20 MHz)—dictated
by the ACS8944.
Voltage Controlled Oscillator
The internal VCO operates at 2.48832 GHz and is
internally divided down to the selected rate giving a
precise 50/50 balanced mark/space ratio for the output.
z High frequency stability when all input clocks fail;
holdover frequency control to Stratum 3—dictated by
the ACS8525.
Jitter Filtering
Input Jitter Tolerance
Input jitter is attenuated by the PLL with the frequency cut-
off point (Fc) at which jitter is either tracked or attenuated
being defined by the -3 dB point, i.e. the position of the
first pole of the PLL loop filter. The bandwidth (frequency
at which the first pole occurs) is defined by the component
value selected for the filter from Table 6.
Jitter tolerance is defined as the maximum amplitude of
sinusoidal jitter that can exist on the input reference clock
above which the device fails to maintain lock. For the
ACS8944 device, the jitter tolerance is shown in Figure 3.
Figure 3 Jitter Tolerance; ACS8944 Standalone
For 19.44 MHz input, using a loop filter bandwidth of
2 kHz gives:
Input Jitter Tolerance With 2kHz PLL Bandwidth
1000
z High input jitter attenuation and roll off:
• - 20 dB/decade from first loop filter pole, (Fc)
• - 40 dB/decade from 2nd pole (typically 10 x Fc)
100
z Jitter peaking is less than 1 dB (dependent on the
ACS8946 Jitter
Tolerance
loop filter components)
10
OC_12
Tolerance Mask
z Typical final output jitter, e.g. 2.8 ps rms measured
over the integration range of 12 kHz-20 MHz offset
from carrier.
OC_48
Tolerance Mask
1
10
100
1000
10000
100000
1000000
Jitter Filtering: Partnering with Semtech
Line Card Protection Part
0.1
One “Real World” application for the ACS8944 is to use it
to dejitter the clock output from a Semtech ACS8525
LC/P device. In this case it is recommended to set the
ACS8944 PLL to a bandwidth of around 2 kHz to provide
a low jitter total solution. The test results detailed in the
electrical specifications section show the “Real World”
performance of this combination of parts to be a superior
solution when compared with those traditionally using
simple discrete PLLs, and has the following advantages:
0.01
Jitter Frequency Offset from Carrier (Hz)
Jitter Transfer
Jitter transfer is a ratio of input jitter present on the
reference clock to the filtered jitter present on the output
clock. Standalone, the Jitter Transfer Characteristic is
defined solely by the loop filter bandwidth and is shown in
Figure 4.
z Low overall bandwidth, 18 Hz for example—dictated
by the ACS8525.
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ACS8944 JAM PLL
ADVANCED COMMUNICATIONS
Figure 4 Jitter Transfer Characteristic, ACS8944
Stand-alone
FINAL
DATASHEET
Figure 6 Phase Offset from Carrier, ACS8944
Typical Phase Noise @ 155.52MHz
Frequency (Hz)
ACS8944 RMS Jitter Transfer Curve
1.0E+02
0
1.0E+03
1.0E+04
1.0E+05
1.0E+06
1.0E+07
3.0
0.0
-3.0
-6.0
-9.0
-20
)
-40
-60
B
/
d
)
-12.0
s
B
H
-15.0
-18.0
-21.0
-24.0
-27.0
-80
-100
-120
-140
-160
a
P
100
1000
10000
100000
Frequency (Hz)
In the combined solution, the ACS8525 device provides
additional low frequency jitter filtering. The jitter transfer
characteristic of the combined ACS8944 and ACS8525 is
shown in Figure 5.
In the combined line card solution, the inherent jitter
generated by the ACS8525 is attenuated by the ACS8944
as shown in the phase noise plot in Figure 7, which uses
a PLL bandwidth of 2 kHz.
Figure 5 Jitter Transfer Characteristic, ACS8525 and
ACS8944 combined
Figure 7 Phase Offset from Carrier, ACS8525
with/without ACS8944
Typical Phase Noise Cleaning of ACS8525
Frequency (Hz)
1.0E+02
-10
1.0E+03
1.0E+04
1.0E+05
1.0E+06
1.0E+07
1.0E+08
-30
-50
-70
-90
-110
-130
-150
-170
ACS8525 alone
ACS8525 + ACS8944
Phase Noise Performance
Loop Filter Components
The inherent jitter generation by the ACS8944 is shown in
the phase noise plot in Figure 6 for a PLL bandwidth of
2 kHz, output frequency of 155.52 MHz and input of
19.44 MHz.
The loop filter comprises two identical sets of passive RC
components that connect to the differential charge pump
outputs and internal VCO control inputs. Pins VCN and
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ACS8944 JAM PLL
ADVANCED COMMUNICATIONS
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VCP are the combined differential charge pump outputs
and VCO control voltage inputs. Figure 5 shows the
arrangement.
Output Jitter
The output jitter meets all requirements of ITU, Telcordia
and ETSI standards for SONET rates up to
Figure 8 Loop Filter Components
OC-12/STM-4/622.08 MHz. See the “Electrical
Specifications” sections for details on the jitter figures
across the different output jitter frequency bands relevant
to each specification.
L
L
P
VCP
VCN
M
AJ
The recommended bandwidth of around 2 kHz is suitable
for both meeting the specification on output jitter
generation requirements and for filtering out the input
jitter from the input clock.
R1
C2
R2
C4
C1
C3
System Reset
GND
F8944_010Loopfilter_01
After power-up or a system reset via the RESETB (pin 40),
the internal control logic waits for the presence of an input
signal of approximately the correct frequency (at least
40% of the nominal) and then allows a further settling
time of 60ms before allowing internal frequency tuning,
frequency-locking and phase-locking on to the input clock.
Consequently reset should be removed only when the
input frequency is within 400 ppm of the nominal
frequency.
All electrolytic capacitors should be low leakage and low
ESR (equivalent series resistance). Ceramic (preferred) or
tantalum are suitable for C1 and C3.
Tables 6 and 7 are based on a damping factor of 1.2
(phase margin 80.2°). Higher damping factors may be
used if lower transfer peaking is required. Contact
Semtech Sales Support for further details.
Table 6 Loop Filter Components when using 19.44 MHz
or 77.76 MHz Input Frequency
Layout Recommendations
Closed Loop
Bandwidth
R1 & R2
C2 & C4
C1 & C3
It is highly recommended to use a stable and filtered 3.3 V
power supply to the device. A separate filtered power and
ground plane is recommended with supply decoupling
capacitors of 10 nF and 100 pF utilizing good high
frequency chip capacitors (0402 or 0603 format surface-
mount package) on each VDD. Good differential signal
layout on the input and output lines should be used to
ensure matched track impedance and phase. Contact
Semtech directly for further layout recommendations.
2 kHz
4 kHz
75 Ω
150 Ω
270 Ω
56 Ω
15 µF
4.7 µF
0.68 µF
33 µF
100 nF
33 nF
8 kHz
7.5 nF
200 nF
1.5 kHz
Lock Detector
Table 7 Loop Filter Components when using 38.88 MHz
or 155.52 MHz Input Frequency
A simple lock detector is incorporated which combines the
plus and minus phase errors from the phase detector,
such that if any phase error signal is present, the LOCKB
output drives out a +10 µA current, otherwise it is off.
Closed Loop
Bandwidth
R1 & R2
C2 & C4
C1 & C3
2 kHz
4 kHz
150 Ω
300 Ω
560 Ω
110 Ω
6.8 µF
2.2 µF
0.47 µF
15 µF
47 nF
22 nF
3.9 nF
91 nF
Consequently this output (LOCKB) is a pulse width
modulated (PWM) pulse stream whose mark/space ratio
indicates the current input phase error. Filtering this
signal with a simple external RC parallel filter as shown in
Figure 9 will give a signal whose output level indicates PLL
phase and frequency lock.
8 kHz
1.5 kHz(i)
Note: (i) Not available at 155.52 MHz input frequency
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ACS8944 JAM PLL
ADVANCED COMMUNICATIONS
FINAL
Applications
DATASHEET
Figure 9 Lock Filter Components
LOCK_B
C5
The ACS8944 is targeted at applications requiring clock
cleaning at 19.44 MHz, 38.88 MHz, 77.76 MHz or
155.52 MHz where input jitter is filtered out or attenuated
at frequencies above the ACS8944 PLL bandwidth. It also
performs the function of a clock multiplying unit (CMU)
translating any one of these input frequencies to any one
of 19.44 MHz, 38.88 MHz, 77.76 MHz or 155.52 MHz
output frequencies.
220nF
L
L
P
LOCKB
M
J
R3
470K
GND
F8944_011Lockfilter_03
The filtering components are external so that the time to
indicate lock or not locked can be optimized for the
application. The output indicates both phase and
frequency lock. During off-frequency conditions the
LOCKB output will be predominately high in its PWM
generation with the filtered version giving a constant high
state.
The ACS8944 can save space when compared with
discrete analog + VCXO solutions or module-based
solutions. In the example in Figure 10 the ACS8944 is
shown symbolically as a low cost line card dejittering
device. The ACS8944 carries out the appropriate
frequency multiplication for onward distribution as
required by the line card.
Figure 10 Typical Application
Multiple Line cards
Line Card (0C-12)
Recovered Clock
Master Clock
Frame Sync
ACS8515
ACS8525
ACS8526
ACS8527
Master Sync
Slave Clock
FRAMER
SERDES
Multi Frame Sync
Slave Sync
E1/DS1
To/from
SONET/SDH/PDH
Network
LINE
CARD
Stand-by Clock
Stand-by Sync
Clock
Distribution
PROTECTION
ACS8944
JAM PLL
Low Jitter/Low Skew
Low Jitter up to 155.52 MHz
Backplane
Slave Sync Card
Master Sync Card
Input CLK Sources
Config.
ACS8510
ACS8520
ACS8522
ACS8530
SETS
Priorities
TCLK
mP/Serial Bus
Priorities
SSM
Output
CLKs
CLK
Primary Ref.
Input/
output
SSM Processing
Line
I/F
Unit
DATA
Clock
Distribution
DATA
SEC
SetsLinecardGenApp_08
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ACS8944 JAM PLL
ADVANCED COMMUNICATIONS
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DATASHEET
Application Schematic of Combined ACS8525 and ACS8944
Figure 11 shows the circuit diagram of the clock solution device containing DPLLs/APLLs, synthesizers and
part of an application combining an ACS8525 line card
part with a dejittering ACS8944. A full design would
require a microcontroller for advanced control and
ACS8525 device setup; an ACS8525 line card protection
monitors and the ACS8944 for jitter reduction. Just the
parts relevant to the clock production are shown here, i.e.
the ACS8525 and ACS8944.
Figure 11 Line Card Clock Source Example Schematic ACS8525 and ACS8944
Input Clocks
uProc interface for
control, monitoring or
setup
AGND
SEC2
SEC1
C15
100nF
VDDA
VDDA
AGND
C6
100nF
R10
1M
AGND
VDDA
C7
100nF
TCK
TDO
TDI
SDO
DGND6
VDD7
IC
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD1
DGND4
SEC2
SEC1
SYNC1
VDD5V
SEC2NEG
SEC2POS
SEC1NEG
SEC1POS
VDD_DIFF
GND_DIFF
O1NEG
O1POS
MFrSync
FrSync
C8
AGND
100nF
VDDA
AGND
VDDA
IC1
ACS8525
O2
C10
100nF
AGND
VA3+
AGND4
IC1
IC2
IC3
VDDA
C9
100nF
IC4
IC5
AGND
SONSDHB
C14
100nF
VDDA
VDDA
R13
AGND
AGND
AGND
VDDA
R11
82
C12
100nF
C13
100nF
R8
10R
R9
10R
VDDA
C11
130
100nF
R12
82
X1
R14
130
AGND
AGND
C1
12.8MHz
IQXO-71
VDDA2
VDDA2
AGND
VDDA2
AGND2
C20
10nF
C18
10nF
C2
C3
C4
R1
LOOP FILTER
COMPONENTS
C16
C17
10nF
100pF
C21
100pF
R2
C19
100pF
AGND2
For Loop Filter
AGND2
Components, see
Table 6 and Table 7.
VDDA2
AGND2
R15 ZERO
OHM LINK
C28 100pF
C27 10nF
C26 100uF
IC3
EXT3
EXT2
EXT1
NC11
NC10
IC2
IC1
LOCKB
CFG_OUT3
CFG_OUT2
CFG_OUT1
RESET
CONTROLLER
VDDOSC
VSSOSC
RESETB
IC4
IC5
VDDP2
NC16
NC17
OP_FSEL
NC18
VDDA2
R3
470K
R16
1M
C29
100nF
C5
AGND2
AGND2
LOCKB
220nF
J1
C24
10nF
C25
100pF
AGND3
AGND2
NC19
CFG_OUT0
VDDA2
AGND2
R4
R5
130
130
DOWNSTREAM
DEVICE,
LVPECL INPUTS
OUT1N
OUT1P
C22
100pF
R6
82
R7
82
VDDA2
C23
AGND2
10nF
F8944D_021ExSchematic_08
AGND3
Note...For optimal performance use a Low Voltage Dropout (LDO) Regulator to supply VDDA2
Revision 3/November 2006 © Semtech Corp.
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ACS8944 JAM PLL
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Electrical Specifications
implied. Exposure to the absolute maximum ratings for an
extended period may reduce the reliability or useful
lifetime of the product.
Maximum Ratings
Important Note: The Absolute Maximum Ratings, Table 8,
are stress ratings only, and functional operation of the
device at conditions other than those indicated in the
Operating Conditions sections of this specification are not
Table 8 Absolute Maximum Ratings
Parameter
Symbol
Minimum
Maximum
Units
Supply Voltage (D.C.): VDDP1, VDDP2, VDDADIV,
VDDARF, VDDOSC, VDDO
VDD
-0.5
3.6
V
Input Voltage (non-supply pins):
Digital Inputs: EXT1, EXT2, RESETB, OP_FSEL
VIN
VIN
-0.5
-0.5
5.5
V
V
Input Voltage (non-supply pins)
LVPECL Inputs: CLKN, CLKP,
ANALOG I/O: VCN, VCP, LOCKB
VDD + 0.5
Output Voltage (non-supply pins):
Digital Outputs:FREQ155, FREQ77, FREQ38,
FREQ19
VOUT
-0.5
VDD + 0.5
V
LVPECL Outputs: OUTN, OUTP
Ambient Operating Temperature Range
Storage Temperature
TA
TSTOR
-40
+85
+150
245
260
-
°C
°C
°C
°C
kV
-50
Reflow Temperature (Pb)
Reflow Temperature (Pb Free)
ESD HBM (Human Body Model)(i), (ii)
Latchup(iii)
TREPB
-
TREPBFREE
ESDHBM
ILU
-
2
±100
-
mA
Notes: (i) All pins pass 2kV HBM except VCN/VCP which are rated at 500 V HBM.
(ii) Tested to JEDEC standard JESD22-A114.
(iii) Tested to JEDEC standard JESD78.
Operating Conditions
Table 9 Operating Conditions
Parameter
Symbol
Minimum
Typical
Maximum
Units
Supply Voltage (D.C.): VDDP1, VDDP2, VDDADIV,
VDDARF, VDDO
VDD
3.135
3.3
3.465
V
VDDOSC
VDDOSC
TA
3.0
3.3
-
3.465
+85
300
25
V
Ambient Temperature Range
Supply Current (including VDDOSC)
VDDOSC Supply Current
-40
°C
mA
mA
IDD
-
-
250
20
IDDOSC
Revision 3/November 2006 © Semtech Corp.
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ACS8944 JAM PLL
ADVANCED COMMUNICATIONS
Table 9 Operating Conditions (cont...)
FINAL
DATASHEET
Parameter
Symbol
Minimum
Typical
Maximum
Units
Total Power Dissipation (excluding power dissipation
in external biasing components
PTOT
-
870
1040
mW
Thermal Characteristics
Table 10 Thermal Conditions
Parameter
Thermal Resistance Junction to Ambient
Operating Junction Temperature
Symbol
θJA
Minimum
Maximum
Units
-
-
25
°C/W
°C
TJCT
125
AC Characteristics
Table 11 AC Characteristics
Parameter
Input to Output Delay
Symbol
tPDIO
tCRF
Minimum
Typical
Maximum
Units
0.5
-
-
3.0
10
ns
ns
ns
%
Input Clock Rise/Fall Time(i) (CLK)
LVPECL Output Rise/Fall Time(i), (ii)
Input Clock Duty Cycle (CLK)
Output Clock Duty Cycle
-
tPECLRF
tCDF
-
40
48
-
0.8
50
50
-
1.2
60
tODC
52
%
RESETB Pulse Width after Power-up
Frequency Tuning after RESETB High
tRPW
tFT
100
60
ms
ms
-
-
Notes: (i) Rise/fall time measured 10-90%.
(ii) Using output load specified in Figure 14.
DC Characteristics
Across all operating conditions, unless otherwise stated.
Table 12 DC Characteristics: LVCMOS Inputs with Internal Pull-down/Schmitt input with Internal Pull-up
Parameter
Symbol
VIH
Minimum
Maximum
-
Units
VIN High
IN Low
Pull-down Resistor
2
-
V
V
VIL
0.8
V
RPD
RPU
IIN
43
53
-
108
113
±10
kΩ
kΩ
µA
Pull-up Resistor (Schmitt input)
Input Current
Revision 3/November 2006 © Semtech Corp.
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ACS8944 JAM PLL
ADVANCED COMMUNICATIONS
Table 13 DC Characteristics: LVPECL Input Port
FINAL
DATASHEET
Parameter
Symbol
Minimum
Maximum
Units
LVPECL Input Offset Voltage
Differential Inputs (Note (ii))
VIO_LVPECL
VDD-2.0
VDD-0.5
V
Input Differential Voltage
VID_LVPECL
0.1
VSS
1.4
V
V
LVPECL Input Low Voltage
Single-ended Input (Note (i))
VIL_LVPECL_S
VDD-1.5
LVPECL Input High Voltage
Single-ended Input (Note (i))
VIL_LVPECL_S
IIH_LVPECL
IIL_LVPECL
VDD-1.3
-10
VDD
+10
+10
V
Input High Current
Input Differential Voltage VID = 1.4 V
µA
µA
Input Low Current
-10
Input Differential Voltage VID = 1.4 V
Notes: (i) Unused differential input terminated to VDD-1.4 V.
(ii) Both pins must remain within the supply voltage, i.e. >VSS and <VDD
.
Table 14 DC Characteristics: LVPECL Output Port
Parameter
Symbol
Minimum
VDD-2.1
VDD-1.45
0.37
Maximum
VDD-1.62
VDD-0.88
1.22
Units
LVPECL Output Low Voltage (Note (i))
LVPECL Output High Voltage (Note (i))
LVPECL Output Differential Voltage (Note (i))
VOL_LVPECL
VOH_LVPECL
VOD_LVPECL
V
V
V
Note: (i) With a 50 ohms load on each pin to VDD -2V.
Table 15 DC Characteristics: LVTTL/CMOS Output Port
Parameter
Output Low Voltage @ IOL (MAX)
Symbol
VOL
Minimum
Typical
Maximum
Units
-
2.4
2
-
-
-
-
0.4
V
Output High Voltage @ IOH (MIN)
Low Level Output Current @ VOL = 0.4 V
High Level Output Current @ VOH = 2.4 V
VOH
-
-
-
V
IOL
mA
mA
IOH
2
Revision 3/November 2006 © Semtech Corp.
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ACS8944 JAM PLL
ADVANCED COMMUNICATIONS
Input and Output Interface Terminations
FINAL
DATASHEET
The preferred termination circuitry for the LVDS signals
between the ACS8525/26/27 and the ACS8944 LVPECL
is shown in Figure 13. The bias for the LVPECL input is set
for A.C. inputs at a mid point of approximately 2 V (with a
3.3 V VDD), as opposed to a normal D.C. coupled bias of
VDD - 2 V. This is due to the push-pull nature of an A.C.
coupled signal.
Interfacing to either the same type or electrically different
interface types is illustrated by the following circuit
diagrams, covering translation from LVDS to LVPECL.
The example of Figure 12 shows LVPECL to LVPECL
terminations with D.C. coupling, so that the ACS8944
sees an equivalent load of around 50 Ω from the R3, R4,
R5, R6 resistor arrangement at the receiver end.
Figure 13 Generic LVDS - AC Coupled to LVPECL Receiver
Figure 12 LVPECL Output - DC Coupled to LVPECL or LVDS
Receiver
VDD
ASC8944 or similar
LVPECL Output
R5
2K7
LVDS
Output
Device
R2
2K7
VDD
JAM PLL
C1
220nF
VDD
LVPECL
INPUT
These resistors may
be integrated on-chip
OUTN
OUTP
CLKN
CLKP
Transmission
Line Impedance
50 Ohms
130R
130R
R1
100
C2
OUTP
220nF
OUTN
ACS8944 or similar
LVPECL/LVDS receiver
Transmission Line
OUTP
VDD -1.0 V
VDD -1.4 V
VDD -1.8 V
R3
82R
4K3
82R
R4
4K3
VSS
F8944D_015LVPECL2LVPECL_03
Time
F8944D_017LVDS2LVPECL_02
GND
Input/Output Timing
Figure 14 Timing Diagrams
1) Input to Output
Delay
tPDIO
CLKX
OUTY
Start of Frequency
Tuning Algorithm
2) Power-up Sequence
tRPW
(90% VDD)
VDD
tFT
RESETB
CLKX
Input frequency must be within 400 ppm of nominal
before releasing reset
Revision 3/November 2006 © Semtech Corp.
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ACS8944 JAM PLL
ADVANCED COMMUNICATIONS
Jitter Performance
FINAL
DATASHEET
Table 16 Output Jitter Generation: ACS8944 Stand-alone @155.52 MHz Input/155.52 MHz Output
Test Definition
Filter Spec (iv)
Measured Results
Max
Specification
Interface
Frequency
Spec Limit
Typical
Units
ps p-p
G.813
STM-1 (optical) 65 kHz to
0.1 UI p-p = 643 ps
*
*
*
*
*
*
*
5.1
0.5
12.5
1.2
Option 1[4]
and ETSI
,
155 MHz
1.3 MHz
-
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
EN 300 462 -
500 Hz to
1.3 MHz
0.5 UI p-p = 3215 ps
110.4
11.0
3.2
302.8
30.3
5.3
7 - 1[1]
-
STM-4 622 MHz 250 kHz to
5 MHz
0.1 UI p-p = 161 ps
-
0.3
0.5
1 kHz to 5 MHz 0.5 UI p-p = 804 ps
-
82.4
8.2
213.0
21.3
6.3
STM-16 2.5 GHz 1 MHz to
20 MHz
0.1 UI p-p = 40 ps
-
3.7
0.4
0.6
5 kHz to 20 MHz 0.5 UI p-p = 201 ps
-
33.7
3.4
90.3
9.0
ETSI
STM-1
65 kHz to
1.3 MHz
0.075 UI p-p = 482 ps
-
5.1
12.5
1.2
EN 300 462 - (electrical)
0.5
7 - 1[1]
155 MHz
G.813
STM-1 155 MHz 12 kHz to
1.3 MHz
0.1 UI p-p = 643 ps
-
*
*
*
*
*
*
*
18.1
1.8
52.4
5.2
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
Option 2[4]
STM-4 622 MHz 12 kHz to 5 MHz 0.1 UI p-p = 161 ps
-
18.2
1.8
47.9
4.8
STM-16 2.5 GHz 12 kHz to
20 MHz
0.1 UI p-p = 40 ps
18.4
1.8
48.4
4.8
GR-253-
CORE[8]
OC-3/STS-3
155 MHz
12 kHz to
1.3 MHz
0.1 UI p-p = 643 ps
18.1
1.8
52.4
5.2
0.01 UI rms = 64.3 ps
OC-12/STS-12 12 kHz to 5 MHz 0.1 UI p-p = 161 ps
622 MHz
18.2
1.8
47.9
4.8
0.01 UI p-p = 16.1 ps
OC-48/STS-48 5 kHz to 20 MHz 1.5 UI p-p = 600 ps
2.5 GHz
33.7
3.4
90.3
9.0
-
1 MHz to
20 MHz
0.15 UI p-p = 60 ps
-
3.7
6.3
0.4
0.6
Notes: (i) Measured on the ACS8944 Evaluation Board using output clock OUT1, with a 0 dBm reference clock from an ESG E4400B signal
generator AC coupled to CLK1. VDD = 3.0 V to 3.465 V, TA -40°C to +85°C.
(ii) “*” Derived values using the normal Gaussian crest value ratio of 10.
(iii) PLL Closed Loop bandwidth set to 2 KHz with a damping factor of 1.2.
(iv) All measurement results are derived from the phase noise plots using integration ranges defined by the telecommunication
standards' specifications
Revision 3/November 2006 © Semtech Corp.
Page15
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ACS8944 JAM PLL
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Table 17 Output Jitter Generation: ACS8944 Stand-alone @77.76 MHz Input/155.52 MHz Output
Test Definition
Filter Spec (iv)
Measured Results
Max
Specification
Interface
Frequency
Spec Limit
Typical
Units
ps p-p
G.813
STM-1 (optical) 65 kHz to
0.1 UI p-p = 643 ps
*
*
*
*
*
*
*
5.1
0.5
12.3
1.2
Option 1[4]
and ETSI
,
155 MHz
1.3 MHz
-
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
EN 300 462 -
500 Hz to
1.3 MHz
0.5 UI p-p = 3215 ps
102.6
10.3
3.2
281.3
28.1
5.4
7 - 1[1]
-
STM-4 622 MHz 250 kHz to
5 MHz
0.1 UI p-p = 161 ps
-
0.3
0.5
1 kHz to 5 MHz 0.5 UI p-p = 804 ps
-
76.6
7.7
197.8
19.8
6.2
STM-16 2.5 GHz 1 MHz to
20 MHz
0.1 UI p-p = 40 ps
-
3.7
0.4
0.6
5 kHz to 20 MHz 0.5 UI p-p = 201 ps
-
32.7
3.3
87.5
8.7
ETSI
STM-1
65 kHz to
1.3 MHz
0.075 UI p-p = 482 ps
-
5.1
12.3
1.2
EN 300 462 - (electrical)
0.5
7 - 1[1]
155 MHz
G.813
STM-1 155 MHz 12 kHz to
1.3 MHz
0.1 UI p-p = 643 ps
-
*
*
*
*
*
*
*
17.5
1.7
50.8
5.1
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
Option 2[4]
STM-4 622 MHz 12 kHz to 5 MHz 0.1 UI p-p = 161 ps
-
17.6
1.8
46.4
4.6
STM-16 2.5 GHz 12 kHz to
20 MHz
0.1 UI p-p = 40 ps
17.8
1.8
46.9
4.7
GR-253-
CORE[8]
OC-3/STS-3
155 MHz
12 kHz to
1.3 MHz
0.1 UI p-p = 643 ps
17.5
1.7
50.8
5.1
0.01 UI rms = 64.3 ps
OC-12/STS-12 12 kHz to 5 MHz 0.1 UI p-p = 161 ps
622 MHz
17.6
1.8
46.4
4.6
0.01 UI p-p = 16.1 ps
OC-48/STS-48 5 kHz to 20 MHz 1.5 UI p-p = 600 ps
2.5 GHz
32.7
3.3
87.5
8.7
-
1 MHz to
20 MHz
0.15 UI p-p = 60 ps
-
3.7
6.2
0.4
0.6
Notes: (i) Measured on the ACS8944 Evaluation Board using output clock OUT1, with a 0 dBm reference clock from an ESG E4400B signal
generator AC coupled to CLK1. VDD = 3.0 V to 3.465 V, TA -40°C to +85°C.
(ii) “*” Derived values using the normal Gaussian crest value ratio of 10.
(iii) PLL Closed Loop bandwidth set to 2 KHz with a damping factor of 1.2.
(iv) All measurement results are derived from the phase noise plots using integration ranges defined by the telecommunication
standards' specifications.
Revision 3/November 2006 © Semtech Corp.
Page16
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ACS8944 JAM PLL
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Table 18 Output Jitter Generation: ACS8944 Stand-alone @38.88 MHz Input/155.52 MHz Output
Test Definition
Filter Spec (iv)
Measured Results
Max
Specification
Interface
Frequency
Spec Limit
Typical
Units
ps p-p
G.813
STM-1 (optical) 65 kHz to
0.1 UI p-p = 643 ps
*
*
*
*
*
*
*
5.3
0.5
12.9
1.3
Option 1[4]
and ETSI
,
155 MHz
1.3 MHz
-
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
EN 300 462 -
500 Hz to
1.3 MHz
0.5 UI p-p = 3215 ps
111.1
11.1
3.3
304.7
30.5
5.4
7 - 1[1]
-
STM-4 622 MHz 250 kHz to
5 MHz
0.1 UI p-p = 161 ps
-
0.3
0.5
1 kHz to 5 MHz 0.5 UI p-p = 804 ps
-
86.9
8.7
224.5
22.4
6.2
STM-16 2.5 GHz 1 MHz to
20 MHz
0.1 UI p-p = 40 ps
-
3.7
0.4
0.6
5 kHz to 20 MHz 0.5 UI p-p = 201 ps
-
33.7
3.7
100.0
10.0
12.9
1.3
ETSI
STM-1
65 kHz to
1.3 MHz
0.075 UI p-p = 482 ps
-
5.3
EN 300 462 - (electrical)
0.5
7 - 1[1]
155 MHz
G.813
STM-1 155 MHz 12 kHz to
1.3 MHz
0.1 UI p-p = 643 ps
-
*
*
*
*
*
*
*
19.3
1.9
56.1
5.6
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
Option 2[4]
STM-4 622 MHz 12 kHz to 5 MHz 0.1 UI p-p = 161 ps
-
19.5
1.9
51.2
5.1
STM-16 2.5 GHz 12 kHz to
20 MHz
0.1 UI p-p = 40 ps
19.6
2.0
51.7
5.2
GR-253-
CORE[8]
OC-3/STS-3
155 MHz
12 kHz to
1.3 MHz
0.1 UI p-p = 643 ps
19.3
1.9
56.1
5.6
0.01 UI rms = 64.3 ps
OC-12/STS-12 12 kHz to 5 MHz 0.1 UI p-p = 161 ps
622 MHz
19.5
1.9
51.2
5.1
0.01 UI p-p = 16.1 ps
OC-48/STS-48 5 kHz to 20 MHz 1.5 UI p-p = 600 ps
2.5 GHz
37.3
3.7
100.0
10.0
6.2
-
1 MHz to
20 MHz
0.15 UI p-p = 60 ps
-
3.7
0.4
0.6
Notes: (i) Measured on the ACS8944 Evaluation Board using output clock OUT1, with a 0 dBm reference clock from an ESG E4400B signal
generator AC coupled to CLK1. VDD = 3.0 V to 3.465 V, TA -40°C to +85°C.
(ii) “*” Derived values using the normal Gaussian crest value ratio of 10.
(iii) PLL Closed Loop bandwidth set to 2 KHz with a damping factor of 1.2.
(iv) All measurement results are derived from the phase noise plots using integration ranges defined by the telecommunication
standards' specifications.
.
Revision 3/November 2006 © Semtech Corp.
Page17
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ACS8944 JAM PLL
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Table 19 Output Jitter Generation: ACS8944 Stand-alone @19.44 MHz Input/155.52 MHz Output
Test Definition
Filter Spec (iv)
Measured Results
Max
Specification
Interface
Frequency
Spec Limit
Typical
Units
ps p-p
G.813
STM-1 (optical) 65 kHz to
0.1 UI p-p = 643 ps
*
*
*
*
*
*
*
6.6
0.7
16.0
1.6
Option 1[4]
and ETSI
,
155 MHz
1.3 MHz
-
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
EN 300 462 -
500 Hz to
1.3 MHz
0.5 UI p-p = 3215 ps
137.1
13.7
3.4
376.0
37.6
5.6
7 - 1[1]
-
STM-4 622 MHz 250 kHz to
5 MHz
0.1 UI p-p = 161 ps
-
0.3
0.6
1 kHz to 5 MHz 0.5 UI p-p = 804 ps
-
117.5
11.7
3.7
303.5
30.3
6.2
STM-16 2.5 GHz 1 MHz to
20 MHz
0.1 UI p-p = 40 ps
-
0.4
0.6
5 kHz to 20 MHz 0.5 UI p-p = 201 ps
-
55.9
5.6
149.6
15.0
16.0
1.6
ETSI
STM-1
65 kHz to
1.3 MHz
0.075 UI p-p = 482 ps
-
6.6
EN 300 462 - (electrical)
0.7
7 - 1[1]
155 MHz
G.813
STM-1 155 MHz 12 kHz to
1.3 MHz
0.1 UI p-p = 643 ps
-
*
*
*
*
*
*
*
27.8
2.8
80.6
8.1
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
ps p-p
ps rms
Option 2[4]
STM-4 622 MHz 12 kHz to 5 MHz 0.1 UI p-p = 161 ps
-
27.9
2.8
73.3
7.3
STM-16 2.5 GHz 12 kHz to
20 MHz
0.1 UI p-p = 40 ps
28.0
2.8
73.6
7.4
GR-253-
CORE[8]
OC-3/STS-3
155 MHz
12 kHz to
1.3 MHz
0.1 UI p-p = 643 ps
27.8
2.8
80.6
8.1
0.01 UI rms = 64.3 ps
OC-12/STS-12 12 kHz to 5 MHz 0.1 UI p-p = 161 ps
622 MHz
27.9
2.8
73.3
7.3
0.01 UI p-p = 16.1 ps
OC-48/STS-48 5 kHz to 20 MHz 1.5 UI p-p = 600 ps
2.5 GHz
55.9
5.6
149.6
15.0
6.2
-
1 MHz to
20 MHz
0.15 UI p-p = 60 ps
-
3.7
0.4
0.6
Notes: (i) Measured on the ACS8944 Evaluation Board using output clock OUT1, with a 0 dBm reference clock from an ESG E4400B signal
generator AC coupled to CLK1. VDD = 3.0 V to 3.465 V, TA -40°C to +85°C.
(ii) “*” Derived values using the normal Gaussian crest value ratio of 10.
(iii) PLL Closed Loop bandwidth set to 2 KHz with a damping factor of 1.2.
(iv) All measurement results are derived from the phase noise plots using integration ranges defined by the telecommunication
standards' specifications.
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ADVANCED COMMUNICATIONS
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DATASHEET
Package Information
Figure 15 QFN48 Package.
Revision 3/November 2006 © Semtech Corp.
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ACS8944 JAM PLL
ADVANCED COMMUNICATIONS
Thermal Conditions
FINAL
DATASHEET
Although not essential for the ACS8944, one technique
that may be used to improve heat dissipation from
through the large centre pad is to include a thermal
landing the same size as the centre pad on the
component side of the board (and one on the opposite
side of the PCB) connected to analog ground using a
number of thermal vias, approximately 0.33mm diameter.
These vias should be completely connected (flooded over)
to the thermal landing(s) as well as to internal ground
planes if using a multilayer PCB. 3 x 3 vias pitched at 1.27
mm between via centres would be more than sufficient for
the ACS8944 if this method were adopted.
The device is rated for full temperature range when this
package is used with a 4-layer or more PCB. Copper
coverage must exceed 50%. All pins must be soldered to
the PCB. Maximum operating temperature must be
reduced when the device is used with a PCB with less than
these requirements.
The device includes a large thermal die paddle which
must be soldered to the PCB in addition to the pins for
improved thermal dissipation characteristics and to
strengthen the mechanical connection to the PCB.
Figure 16 Typical 48 Pin QFN PCB Footprint
Revision 3/November 2006 © Semtech Corp.
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ADVANCED COMMUNICATIONS
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DATASHEET
Abbreviations
References and Related Standards
CMU
ESD
ESR
HBM
I/O
Clock Multiplier Unit
Electrostatic Discharge
Equivalent Series Resistance
Human Body Model
Input/Output
[1] ETSI EN 300 462-7-1 v1.1.2 (06/2001)
Transmission and Multiplexing (TM); Generic
requirements for synchronization networks; Part 7-1:
Timing characteristics of slave clocks suitable for
synchronization supply to equipment in local node
applications
JAM PLL
Jitter Attenuating, Multiplying Phase
Locked Loop
Low Voltage Drop-out
[2] ETSI EN 302 084 V1.1.1 (2000-02)
Transmission and Multiplexing (TM); The control of jitter
and wander in transport networks
LDO
LVCMOS
LVDS
LVPECL
OC-3/12
Low Voltage CMOS
Low Voltage Differential Signal
Low Voltage (3.3 V) PECL
Optical Carrier Signal Level 3/12
155.52 Mbps/ 622.08 Mbps
Positive Emitter Coupled Logic
Phase and Frequency Detector
Phase Locked Loop
Power-On Reset
peak-to-peak
Pulse Width Modulated
root-mean-square
Restrictive Use of Certain Hazardous
Substances (directive)
[3] ITU-T G.812 (06/1998)
Timing requirements of slave clocks suitable for use as
node clocks in synchronization networks
[4] ITU-T G.813 (08/1996)
Timing characteristics of SDH equipment slave clocks
(SEC)
PECL
PFD
PLL
POR
p-p
PWM
rms
RoHS
[5] ITU-T G.823 (03/2000)
The control of jitter and wander within digital networks
which are based on the 2048 kbit/s hierarchy
[6] ITU-T G.824 (03/2000)
The control of jitter and wander within digital networks
which are based on the 1544 kbit/s hierarchy
[7] ITU-T G.825 (03/2000)
The control of jitter and wander within digital networks
which are based on the Synchronous Digital Hierarchy
(SDH)
SDH
SEC
SETS
SONET
Synchronous Digital Hierarchy
SDH/SONET Equipment Clock
Synchronous Equipment Timing source
Synchronous Optical Network
[8] Telcordia GR-253-CORE, Issue 3 (09/ 2000)
Synchronous Optical Network (SONET) Transport
Systems: Common Generic Criteria
STM-1/4/16 Synchronous Transport Module Levels
1/4: 155.52 Mbps/ 622.08 Mbps/
2.488 Gbps (SDH)
[9] RoHS Directive 2002/95/EC: Directive 2002/95/EC
of the European Parliament and of the Council of 27
January 2003 on the restriction of the use of certain
hazardous substances in electrical and electronic
equipment
STS-12
Synchronous Transport Signal Level: 12,
622.08 Mbps (SONET)
UI
Unit Interval
uP (µP)
WEEE
Microprocessor
Waste Electrical and Electronic
Equipment (directive)
[10] Waste Electrical and Electronic Equipment (WEEE)
Directive (2002/96/EC): Directive 2002/96/EC of the
European Parliament and of the Council of 27 January
2003 on waste electrical and electronic equipment
(WEEE)
VCO
Voltage Controlled Oscillator
Revision 3/November 2006 © Semtech Corp.
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ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Trademark Acknowledgements
Semtech and the Semtech S logo are registered
trademarks of Semtech Corporation.
intention of the design. The datasheet is raised to
PRELIMINARY status when initial prototype devices are
physically available, and the datasheet content more
accurately represents the realization of the design. The
datasheet is only raised to FINAL status after the device
has been fully characterized, and the datasheet content
updated with measured, rather than simulated parameter
values.
Telcordia is a registered trademark of Telcordia
Technologies.
Revision Status/History
The Revision Status, as shown in top center of the
datasheet header bar, may be DRAFT, PRELIMINARY, or
FINAL, and refers to the status of the device (not the
datasheet), within the design cycle. DRAFT status is used
when the design is being realized but is not yet physically
available, and the datasheet content reflects the
This is a “FINAL” release of the ACS8944 datasheet.
Changes made for this document revision are given
below.
Table 20 Revision History
Revision
Reference
Description of Changes
Rev. 0.01/October 2004 to
Rev. 0.10/May 2006
See version 0.09, April 2006
Initial drafts, for details see Revision Status/History in version 0.09.
Rev. 1.00/May 2006
All pages
All pages
All pages
Updated to Preliminary status.
Updated to Final status.
Rev. 2.00/October 2006
Rev. 3/November 2006
Revision scheme updated.
Revision 3/November 2006 © Semtech Corp.
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ACS8944 JAM PLL
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Notes
Revision 3/November 2006 © Semtech Corp.
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ACS8944 JAM PLL
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Ordering Information
Table 21 Parts List
Part Number
Description
ACS8944
JAM PLL Jitter Attenuating, Multiplying Phase Locked Loop for OC-12/STM-4.
Lead (Pb)-free packaged version of ACS8944; RoHS and WEEE compliant.
ACS8944 Evaluation Board (Demo Board).
ACS8944T
ACS8944EVB
Disclaimers
Life support- This product is not designed or intended for use in life support equipment, devices or systems, or other critical
applications. This product is not authorized or warranted by Semtech for such use.
Right to change- Semtech Corporation reserves the right to make changes, without notice, to this product. Customers are advised
to obtain the latest version of the relevant information before placing orders.
Compliance to relevant standards- Operation of this device is subject to the User’s implementation and design practices. It is the
responsibility of the User to ensure equipment using this device is compliant to any relevant standards.
Contacts
For Additional Information, contact the following:
Semtech Corporation Advanced Communications Products
E-mail:
Internet:
USA:
sales@semtech.com
acsupport@semtech.com
http://www.semtech.com
200 Flynn Road, Camarillo, CA 93012-8790
Tel: +1 805 498 2111, Fax: +1 805 498 3804
FAR EAST: 12F No. 89 Sec. 5, Nanking E. Road, Taipei, 105, TWN, R.O.C.
Tel: 886-2-2748-3380 Fax: 886-2-2748-3390.
EUROPE: Semtech Ltd., Units 2 and 3, Park Court, Premier Way,
Abbey Park Industrial Estate, Romsey, Hampshire, SO51 9DN
Tel: +44 (0)1794 527 600
Fax: +44 (0)1794 527 601
ISO9001
CERTIFIED
Revision 3/November 2006 © Semtech Corp.
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