SFP95N03L [SEMIWELL]
Logic N-Channel MOSFET; 逻辑N沟道MOSFET
| 型号： | SFP95N03L |
| 厂家： | 
SEMIWELL SEMICONDUCTOR |
| 描述： | Logic N-Channel MOSFET |
| 文件： | 总7页 (文件大小：1219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
SFP95N03L
SemiWell Semiconductor
Logic N-Channel MOSFET
Features
2. Drain
Symbol
{
■ Low RDS(on) (0.0085Ω )@VGS=10V
●
■ Low Gate Charge (Typical 39nC)
■ Low Crss (Typical 185pF)
■ Improved dv/dt Capability
◀
▲
1. Gate
●
●
{
■ 100% Avalanche Tested
■ Maximum Junction Temperature Range (175°C)
{
3. Source
General Description
TO-220
This Power MOSFET is produced using SemiWell’s advanced
planar stripe, DMOS technology. This latest technology has been
especially designed to minimize on-state resistance, have a low
gate charge with superior switching performance, and rugged
avalanche characteristics. This Power MOSFET is well suited
for synchronous DC-DC Converters and Power Management in
portable and battery operated products.
1
2
3
Absolute Maximum Ratings
Symbol
Parameter
Value
Units
VDSS
Drain to Source Voltage
30
V
Continuous Drain Current(@TC = 25°C)
Continuous Drain Current(@TC = 100°C)
Drain Current Pulsed
(Note 6)
(Note 1)
95
A
ID
67.3
380
A
A
V
IDM
VGS
Gate to Source Voltage
±20
450
7.0
EAS
Single Pulsed Avalanche Energy
Peak Diode Recovery dv/dt
(Note 2)
(Note 3)
mJ
V/ns
W
dv/dt
Total Power Dissipation(@TC = 25 °C)
150
1.0
PD
Derating Factor above 25 °C
W/°C
°C
T
STG, TJ
Operating Junction Temperature & Storage Temperature
- 55 ~ 175
Maximum Lead Temperature for soldering purpose,
1/8 from Case for 5 seconds.
TL
300
°C
Thermal Characteristics
Value
Typ.
Symbol
Parameter
Units
Min.
Max.
RθJC
RθCS
RθJA
Thermal Resistance, Junction-to-Case
Thermal Resistance, Case to Sink
-
-
-
-
0.5
-
1.0
°C/W
°C/W
°C/W
-
Thermal Resistance, Junction-to-Ambient
62.5
1/7
September, 2002. Rev. 0.
Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved.
SFP95N03L
Electrical Characteristics ( TC = 25 °C unless otherwise noted )
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BVDSS
VGS = 0V, ID = 250uA
D = 250uA, referenced to 25 °C
Drain-Source Breakdown Voltage
30
-
-
-
-
V
Δ BVDSS
Δ TJ
/
Breakdown Voltage Temperature
coefficient
I
0.023
V/°C
V
V
DS = 30V, VGS = 0V
-
-
-
-
-
-
-
-
1
uA
uA
nA
nA
IDSS
Drain-Source Leakage Current
DS = 24V, TC = 150 °C
10
VGS = 20V, VDS = 0V
GS = -20V, VDS = 0V
Gate-Source Leakage, Forward
Gate-Source Leakage, Reverse
100
-100
IGSS
V
On Characteristics
VGS(th)
VDS = VGS, ID = 250uA
GS =10 V, ID = 47.5A
VGS =5 V, ID = 47.5A
Gate Threshold Voltage
1.0
-
3.0
V
V
Static Drain-Source On-state Resis-
tance
-
-
0.0065 0.0085
0.0085 0.0115
RDS(ON)
Ω
Dynamic Characteristics
Ciss
Input Capacitance
-
-
-
1015
845
1320
1110
240
pF
Coss
Crss
Output Capacitance
V
GS =0 V, VDS =25V, f = 1MHz
Reverse Transfer Capacitance
185
Dynamic Characteristics
td(on)
tr
td(off)
tf
Turn-on Delay Time
-
-
-
-
-
-
45
165
70
100
340
150
290
51
VDD =15V, ID =95A, RG =50Ω
※ see fig. 13.
Rise Time
ns
Turn-off Delay Time
Fall Time
(Note 4, 5)
140
39
Qg
Total Gate Charge
Gate-Source Charge
V
DS =24V, VGS =5V, ID =95A
Qgs
13
-
nC
Qgd
Gate-Drain Charge(Miller Charge)
-
18
-
※ see fig. 12.
(Note 4, 5)
Source-Drain Diode Ratings and Characteristics
Symbol
IS
Parameter
Test Conditions
Integral Reverse p-n Junction
Diode in the MOSFET
Min.
Typ.
Max.
95
Unit.
Continuous Source Current
Pulsed source Current
Diode Forward Voltage
-
-
-
-
-
-
A
ISM
380
1.5
VSD
IS =95A, VGS =0V
V
trr
Reverse Recovery Time
-
-
55
65
-
-
ns
nC
IS=95A,VGS=0V,dIF/dt=100A/us
Qrr
Reverse Recovery Charge
※ NOTES
1. Repeativity rating : pulse width limited by junction temperature
2. L = 50 uH, I =95A, V = 15V, R = 0Ω , Starting T = 25°C
AS
DD
G
J
3. ISD ≤ 95A, di/dt ≤ 300A/us, V
≤ BV
, Starting T = 25°C
DD
DSS J
4. Pulse Test : Pulse Width ≤ 300us, Duty Cycle ≤ 2%
5. Essentially independent of operating temperature.
6. Continuous Drain current calculated by maximum junction temperature ; limited by package
2/7
Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved.
SFP95N03L
Fig 1. On-State Characteristics
Fig 2. Transfer Characteristics
VGS
Top :
10.0 V
8.0 V
102
101
100
10-1
6.0 V
5.0 V
4.5 V
102
4.0 V
3.5 V
175oC
Bottom : 3.0 V
25oC
-55oC
※ Notes :
1. 250µ s Pulse Test
2. TC = 25℃
※ Notes :
101
1. VDS = 15V
2. 250µ s Pulse Test
10-1
100
101
0
2
4
6
8
10
12
VGS, Gate-Source Voltage [V]
VDS, Drain-Source Voltage [V]
Fig 4. On State Current vs.
Allowable Case Temperature
Fig 3. On Resistance Variation vs.
Drain Current and Gate Voltage
20
15
10
5
102
101
100
10-1
VGS = 5V
VGS = 10V
175℃
25℃
※ Notes :
1. VGS = 0V
2. 250µ s Pulse Test
※ Note : T = 25℃
J
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0
100
200
300
400
ID, Drain Current [A]
VSD, Source-Drain voltage[V]
Fig 5. Capacitance Characteristics
Fig 6. Gate Charge Characteristics
12
6000
C
iss=Cgs+Cgd(Cds=shorted)
oss=Cds+Cgd
Crss=Cgd
C
VDS = 15V
10
8
5000
4000
3000
2000
1000
0
VDS = 24V
※ Notes :
1. VGS = 0V
2. f=1MHz
6
C
iss
4
Coss
2
※ Note : ID = 95 A
Crss
0
0
5
10
15
20
25
30
35
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70
Qg, Total Gate Charge [nC]
VDS, Drain-Source Voltage [V]
3/7
Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved.
SFP95N03L
Fig 7. Breakdown Voltage Variation
Fig 8. On-Resistance Variation
1.2
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.1
1.0
※ Notes :
1. VGS = 0 V
2. ID = 250 µ A
0.9
0.8
※ Notes :
1. VGS = 10 V
2. ID = 47.5 A
-100
-50
0
50
100
150
200
-100
-50
0
50
100
150
200
TJ, Junction Temperature [oC]
TJ, Junction Temperature [oC]
Fig 10. Maximum Drain Current
vs. Case Temperature
Fig 9. Maximum Safe Operating Area
100
80
60
40
20
0
103
102
101
100
Limited by Package
Operation in This Area
is Limited by R DS(on)
100 µs
1 ms
10 ms
DC
※ Notes :
1. TC = 25 o
C
C
2. TJ = 175 o
3. Single Pulse
10-1
100
101
25
50
75
100
125
150
175
TC, Case Temperature [℃]
VDS, Drain-Source Voltage [V]
Fig 11. Transient Thermal Response Curve
100
10-1
10-2
D=0.5
0.2
※
N otes :
1. Z (t) = 1.0 ℃ /W M ax.
2. DθuJtCy Factor, D=t1/t2
3. TJM - TC = PDM * Z (t)
0.1
θ
JC
0.05
0.02
0.01
single pulse
10-5
10-4
10-3
10-2
10-1
100
101
t1, Square W ave Pulse Duration [sec]
4/7
Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved.
SFP95N03L
Fig. 12. Gate Charge Test Circuit & Waveforms
VGS
5 V
Same Type
50K
Ω
as DUT
Qg
12V
200nF
300nF
VDS
VGS
Qgs
Qgd
DUT
1mA
Charge
Fig 13. Switching Time Test Circuit & Waveforms
RL
VDS
90%
VDS
VDD
( 0.5 rated VDS
)
10%
5 V
Vin
DUT
RG
Pulse
td(on)
tr
td(off)
tf
Generator
t on
t off
Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms
L
BVDSS
1
2
VDS
----
2
--------------------
BVDSS -- VDD
EAS
=
LL IAS
VDD
BVDSS
IAS
ID
RG
ID (t)
VDD
VDS (t)
DUT
10V
t p
Time
5/7
Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved.
SFP95N03L
Fig. 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms
DUT
+
VDS
_
I S
L
Driver
RG
Same Type
as DUT
VDD
VGS
• dv/dt controlled by RG
• IS controlled by pulse period
Gate Pulse Width
VGS
( Driver )
--------------------------
Gate Pulse Period
D =
10V
IFM , Body Diode Forward Current
I S
di/dt
( DUT )
IRM
Body Diode Reverse Current
Body Diode Recovery dv/dt
Vf
VDS
( DUT )
VDD
Body Diode
Forward Voltage Drop
6/7
Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved.
SFP95N03L
TO-220 Package Dimension
mm
Typ.
Inch
Typ.
Dim.
Min.
Max.
10.1
6.7
9.47
13.3
1.4
Min.
Max.
0.398
0.264
0.373
0.524
0.055
A
B
C
D
E
F
9.7
6.3
9.0
12.8
1.2
0.382
0.248
0.354
0.504
0.047
1.7
2.5
0.067
0.098
G
H
I
3.0
1.25
2.4
3.4
1.4
2.7
5.15
2.6
1.62
0.6
0.118
0.049
0.094
0.197
0.087
0.056
0.018
0.046
0.134
0.055
0.106
0.203
0.102
0.064
0.024
0.054
J
K
L
M
N
O
Ø
5.0
2.2
1.42
0.45
1.17
1.37
3.6
0.142
φ
I
H
E
A
B
C
F
M
L
G
1
2
3
D
1. Gate
2. Drain
3. Source
J
N
O
K
7/7
Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved.
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