S1F75510M0A0 [SEIKO]

SWITCHED CAPACITOR REGULATOR, PDSO24, SSOP3-24;
S1F75510M0A0
型号: S1F75510M0A0
厂家: SEIKO EPSON CORPORATION    SEIKO EPSON CORPORATION
描述:

SWITCHED CAPACITOR REGULATOR, PDSO24, SSOP3-24

光电二极管
文件: 总21页 (文件大小:170K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
PF1233-03  
S1F75510  
Charge-pump DC/DC Converter &  
Voltage Regulator  
DESCRIPTION  
The S1F75510 is a power IC designed for use with medium or small capacity TFT–LCD panel modules.  
A single chip of this IC is capable of generating three different levels of positive and negative output voltages  
simultaneously, which are necessary to drive the LCD, by use of a single input power of +2.7 through +3.6V.  
Since the S1F75510 does not require external transistors nor diodes as its voltage conversion circuit, its built-  
in CMOS transistors constituting a complete charge pump type DC/DC converter, it is most suitable for the  
purpose of reducing the current consumption levels of the LCD modules.  
Moreover, the charge pump type DC/DC converter of the S1F75510 can be operated upon the frequencies,  
which are to be switched over by the mode changing signals, using either of the built-in clock signals or external  
clock signals optimal to respective cases.  
This function can drastically suppress the current consumption of this IC while under light load state, thus  
exhibiting very high power conversion efficiencies.  
FEATURES  
Supply voltage ························································································2.7V to 3.6V single power input  
Self consumption current (normal mode/blank mode) ····························200µA / 17µA (TBD)  
Normal mode: Boosting by use of the internal clock  
Blank mode: Selectable between boosting by use of the internal clock or by use of the external clock.  
Conversion efficiency of the charge pump part simple substance ··········95% or more respectively  
Whole conversion efficiency  
2.7V at the time of an input 91%  
3.0V at the time of an input 82%  
Built-in voltage conversion circuits constituted by charge pump type DC/DC converter,  
2 boosting circuit in the positive direction  
3 boosting circuit in the positive direction  
3 boosting circuit in the negative direction  
Built-in voltage stabilizing circuit  
Capable of outputting the positive supply voltage VOUT2 for the source driver  
2 boosting circuit in the positive direction + voltage stabilizing circuit  
Output voltage: +5.0V  
Output current: 14mA *Refer to “Mode changeover circuit ”  
Capable of outputting the positive supply voltage VOUT3 for the gate driver  
3 boosting circuit in the positive direction  
Output voltage: +15V  
Output impedance: RVOUT3 = 0.7kΩ  
VOUT3 = (VOUT2 3) – (RVOUT3 IOUT3)  
Capable of outputting the negative supply voltage VOUT4 for the gate driver  
3 boosting circuit in the negative direction  
Output voltage: –10V  
Output impedance: RVOUT4 = 1kΩ  
VOUT4 = (VOUT2 –2) – (RVOUT4 IOUT4)  
Rev. 1.1  
S1F75510  
Built-in electric charge discharging circuit  
Built-in shut down function  
Shipping state ·························································································SSOP324pin  
This IC is not of the radiation resistant design nor of the light resistance design.  
BLOCK DIAGRAM  
VDD  
VSS  
C1P  
+
+
(8)  
POFFX  
C1  
C2  
C1N  
Discharging  
circuit  
(4)  
×2 boosting circuit in  
the positive direction  
C2P  
C2N  
OSC1  
OSC2  
(1)  
ROSC  
CR oscillation circuit  
CVOUT1  
+
VOUT1  
CL  
(5)  
(2)  
Voltage stabilizing  
circuit  
CVOUT2  
+
MODE  
Mode changeover  
circuit  
VOUT2  
OSCSEL  
C3P  
C3N  
+
C3  
(3)  
(6)  
C4P  
C4N  
Timing signal forming  
circuit  
+
×3 boosting circuit in  
the positive direction  
C4  
+
VOUT3  
CVOUT3  
C5P  
C5N  
+
C5  
(7)  
×3 boosting circuit in  
the negative direction  
C6P  
C6N  
+
+
C6  
VOUT4  
CVOUT4  
Fig. 1 Block diagram  
2
Rev. 1.1  
S1F75510  
DESCRIPTIONS FOR THE BLOCK DIAGRAM  
(1) CR oscillation circuit  
The oscillation circuit is constituted by connecting a resistor between the OSC1 pin and the OSC2 pin. The  
clock signals being generated by this oscillation circuit will become effective as boosting clock signals while the  
mode changeover signal MODE is on the VDD level (normal mode) or while the mode changeover signal MODE  
is on the VSS level and, at the same time, when the internal/external clock selection signal OSCSEL is on the  
VDD level (blank mode · internal clock). When the MODE is set to the VSS level and, at the same time, when the  
OSCSEL is set to the VSS level (blank mode · external clock), the oscillation will be interrupted.  
(2) Mode changeover circuit  
The operation modes of the boosting circuit and voltage stabilizing circuit are being switched over by the mode  
changeover signal MODE. Also, it selects the clock signals to feed to the timing signal forming circuit from  
either of the external clock signals or internal clock signals.  
(3) Timing signal forming circuit  
This circuit generates the charge pump boosting clock signals. This circuit outputs timing signals of the clock  
type (internal clock or external clock) having been selected by the mode changeover circuit to drive respective  
boosting circuits. When the shut down signal POFFX is set to the VSS level, the timing signal stops to interrupt  
the boosting operation.  
(4) 2 boosting circuit in the positive direction  
This circuit makes 2 boosting in the positive direction by charge pump boosting upon the inputted supply  
voltage VDD VSS using the VSS potential as the reference voltage. The 2 boosted output will enter into the  
voltage stabilizing circuit.  
(5) Voltage stabilizing circuit  
This circuit generates the positive supply voltage VOUT2 for the source driver. ON the basis of the built-in  
reference, this circuit stabilizes the output from the above "(4) 2 boosting circuit in the positive direction" by  
use of the series regulator.  
(6) 3 boosting circuit in the positive direction  
This circuit generates the positive supply voltage VOUT3 for the gate driver. This circuit effects 3 boosting in  
the positive direction by charge pump boosting upon the voltage VOUT2 VSS using the VSS potential as the  
reference voltage.  
(7) 3 boosting circuit in the negative direction  
This circuit generates the negative supply voltage VOUT4 for the gate driver. This circuit effects 3 boosting in  
the negative direction by charge pump boosting upon the voltage VOUT2 VSS using the VOUT2 potential as the  
reference voltage.  
(8) Electric charge discharging circuit  
This circuit discharges the electric charge remaining in the VOUT3 pin and VOUT4 pin to the VSS level. This  
circuit will work when the POFFX pin is set to the VSS level.  
Rev. 1.1  
3
S1F75510  
PIN ASSIGNMENT  
SSOP324pin S1F75510M0A0  
24  
13  
1
12  
Pin No.  
Pin name  
C3N  
Pin No.  
Pin name  
MODE  
CL  
1
2
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
C3P  
3
C4P  
POFFX  
OSC1  
OSC2  
OSCSEL  
VOUT2  
VOUT4  
C6P  
4
C4N  
5
VOUT3  
VDD  
6
7
C1N  
8
C1P  
9
VOUT1  
C2P  
10  
11  
12  
C6N  
C2N  
C5N  
VSS  
C5P  
4
Rev. 1.1  
S1F75510  
PIN DESCRIPTION  
(1) CR oscillation circuit · Mode changeover circuit · Timing signal forming circuit · Electric charge discharging  
circuit  
Pin name  
POFFX  
I/O  
Pin No.  
Function  
I
15  
This is the shut down pin. Set it to the VDD level while the IC is in  
operation. When this signal is set to the VSS level, operations of all  
the circuits will be interrupted bringing the IC into the shut down  
state. The electric charge discharging circuit discharges the electric  
charge remaining in the VOUT3 pin and VOUT4 pin to the VSS level.  
This is the CR oscillation circuit gate input pin. This is the pin to  
connect the oscillation resistor. Fix it to the VSS level in case the  
built-in oscillation circuit will not be used.  
OSC1  
OSC2  
CL  
I
O
I
16  
17  
14  
This is the CR oscillation circuit drain input pin. Connect the osci-  
llation resistor between this pin and the OSC1 pin.  
This should be OFF in use of the built-in oscillation circuit.  
This is the boosting external clock signal input pin. Input the charge  
pump clock signals under the blank mode into this pin from the  
external.  
Fix it to the VSS level in case the external clock will not be used.  
This is the mode changeover pin.  
MODE  
I
I
13  
18  
OSCSEL  
This is the pin for selection between the internal clock and exter-  
nal clock signals.  
MODE  
HIGH(VDD) HIGH(VDD) Normal mode  
LOW(VSS) The boosting clock signals are being  
OSCSEL  
Function  
generated through the internal  
oscillation.  
The built-in oscillation circuit will ope-  
rate and the voltage stabilizing circuit  
will operate.  
LOW(VSS) HIGH(VDD) Blank mode (internal oscillation)  
The boosting clock signals are being  
generated through the internal  
oscillation.  
The built-in oscillation circuit will  
operate.  
LOW(VSS) Blank mode (external oscillation)  
The boosting clock signals are being  
generated by the external clock.  
The built-in oscillation circuit will be  
interrupted.  
Rev. 1.1  
5
S1F75510  
(2) 2 boosting circuit in the positive direction  
Pin name  
I/O  
Pin No.  
Function  
VOUT1  
O
9
This is the output pin of the 2 boosting circuit in the positive  
direction.  
C1P  
C1N  
C2P  
C2N  
(O)  
(O)  
(O)  
(O)  
8
7
This is the pin to connect the positive side of the VOUT1 output  
voltage generating flying capacitor C1.  
This is the pin to connect the negative side of the VOUT1 output  
voltage generating flying capacitor C1.  
10  
11  
This is the pin to connect the positive side of the VOUT1 output  
voltage generating flying capacitor C2.  
This is the pin to connect the negative side of the VOUT1 output  
voltage generating flying capacitor C2.  
(3) Voltage stabilizing circuit  
Pin name  
I/O  
Pin No.  
Function  
VOUT1  
I
9
This is the input power pin (+) for the voltage stabilizing circuit.  
This pin is being connected to the output pin of the 2 boosting  
circuit in the positive direction internally, inside this IC.  
This is the output pin of the voltage stabilizing circuit.  
VOUT2  
O
19  
(4) 3 boosting circuit in the positive direction  
Pin name  
I/O  
Pin No.  
Function  
VOUT3  
O
5
This is the output pin of the 3 boosting circuit in the positive  
direction.  
C3P  
C3N  
C4P  
C4N  
(O)  
(O)  
(O)  
(O)  
2
1
3
4
This is the pin to connect the positive side of the VOUT3 output  
voltage generating flying capacitor C3.  
This is the pin to connect the negative side of the VOUT3 output  
voltage generating flying capacitor C3.  
This is the pin to connect the positive side of the VOUT3 output  
voltage generating flying capacitor C4.  
This is the pin to connect the negative side of the VOUT3 output  
voltage generating flying capacitor C4.  
6
Rev. 1.1  
S1F75510  
(5) 3 boosting circuit in the negative direction  
Pin name  
I/O  
Pin No.  
Function  
VOUT4  
O
20  
This is the output pin of the 3 boosting circuit in the negative  
direction.  
C5P  
C5N  
C6P  
C6N  
(O)  
(O)  
(O)  
(O)  
24  
23  
21  
22  
This is the pin to connect the positive side of the VOUT4 output  
voltage generating flying capacitor C5.  
This is the pin to connect the negative side of the VOUT4 output  
voltage generating flying capacitor C5.  
This is the pin to connect the positive side of the VOUT4 output  
voltage generating flying capacitor C6.  
This is the pin to connect the negative side of the VOUT4 output  
voltage generating flying capacitor C6.  
(6) Power pins  
Pin name  
I/O  
Pin No.  
Function  
This is the input power pin (+).  
This is the input power pin ().  
VDD  
I
I
6
VSS  
12  
Rev. 1.1  
7
S1F75510  
FUNCTIONAL DESCRIPTION  
Operational description  
The S1F75510 is a power supply IC for TFT-LCD panel modules. With this IC chip alone, 3 positive and 3  
negative levels of output voltages required for driving the LCD can be generated simultaneously by a single  
power input.  
The voltage converter circuit for the S1F75510 does not require an external transistor or diode since it is  
equipped with a charge pump type DC/DC converter configured with a built-in CMOS transistor, enabling low  
power consumption of the LCD module.  
Generating voltage levels are:  
· Positive boosting supply voltage necessary for the voltage stabilizing circuit (VOUT1)  
· Positive stabilized supply voltage necessary for the source driver (VOUT2)  
· Positive and negative boosting supply voltages necessary for the gate driver (VOUT3 and VOUT4)  
The VOUT1 supply voltage is being generated by the charge pump type DC/DC converter (2 boosting circuit in  
the positive direction). It makes 2 boosting in the positive direction of the potential difference occurring be-  
tween the VDD VSS using the VSS potential as the reference voltage.  
The VOUT2 supply voltages is being generated by the series regulator stabilizing the potential difference occur-  
ring between the VOUT1 VSS using the VSS potential as the reference voltage.  
The VOUT3 supply voltage is being generated by the charge pump type DC/DC converter (3 boosting circuit in  
the positive direction). It makes 3 boosting in the positive direction of the potential difference occurring be-  
tween the VOUT2 VSS using the VSS potential as the reference voltage.  
The VOUT4 supply voltage is being generated by the charge pump type DC/DC converter (3 boosting circuit in  
the negative direction). It makes 3 boosting in the negative direction of the potential difference occurring  
between the VOUT2 VSS using the VOUT2 potential as the reference voltage.  
Indicated below is the system configuration diagram for the power circuit.  
Gate driver  
LCD panel  
VOUT3, VOUT4  
VDD  
VOUT2  
S1F75510  
Source driver  
VSS  
Fig. 2 System configuration diagram  
8
Rev. 1.1  
S1F75510  
Indicated below is the potential correlation diagram inside the system as is shown in Fig. 2.  
×3 boosting in the  
positive direction  
VOUT3  
×2 boosting in the  
VOUT1  
VOUT2  
positive direction  
Voltage stabilizing  
VDD  
VSS  
Source driver  
Gate driver  
VOUT4  
×3 boosting in the  
negative direction  
Power Supply IC (S1F75510)  
Fig. 3 Potential correlation diagram inside the system  
CR oscillation circuit  
The S1F75510 incorporates a CR oscillation circuit as the oscillation circuit for the boosting clock signals. This  
circuit is to be used connecting the external oscillation resistor ROSC between the OSC1 pin and the OSC2 pin.  
The CR oscillation circuit will stop operation under the blank mode and when using the external clock (MODE =  
VSS level and OSCSEL = VSS level) or under the shut down state (POFFX = VSS level). Also, the oscillation will  
be interrupted by setting the OSC1 pin to the VSS level and, at the same time, setting the OSC2 pin into open  
state.  
In this document, the electrical characteristics are referred to as the external oscillation resistance value,  
ROSC=1M.  
Rev. 1.1  
9
S1F75510  
Mode changeover circuit  
By external settings of the mode changeover signal MODE and the internal/external clock selection signal  
OSCSEL, the charge pump boosting can be driven under optimum frequencies. Since the current consumption  
of the IC can be suppressed drastically under the blank mode, it is possible to achieve high power conversion  
efficiency even under light load operations.  
The closer to 50% the external clock duty in the blank mode gets, the more optimum it becomes.  
OSCSEL  
pin  
Built-in CR  
oscillation circuit  
MODE pin  
Mode name  
Max. output current  
VOUT2: 14mA *1  
VOUT3: 0.7kΩ  
VOUT4: 1kΩ  
HIGH(VDD)  
LOW(VSS)  
HIGH(VDD)  
Normal mode  
In operation  
In operation  
In standstill  
VOUT2: 300µA *2  
VOUT3: 4.0kΩ  
VOUT4: 4.0kΩ  
VOUT2: 300µA *2  
VOUT3: 4.0kΩ  
VOUT4: 4.0kΩ  
Blank mode  
(internal oscillation)  
HIGH(VDD)  
LOW(VSS)  
LOW(VSS)  
Blank mode  
(external oscillation)  
duty=50% when  
CL = 1.25kHz  
*1 When IOUT3 = 300µA, IOUT3 = 300µA:  
IOUT2 (Max.) < 16.0mA (3 IOUT3 + 3 IOUT4) must be satisfied.  
*2 When IOUT3 = 30µA, IOUT3 = 30µA:  
IOUT2 (Max.) < 0.50mA (3 IOUT3 + 3 IOUT4) must be satisfied.  
Timing signal forming circuit  
This circuit generates the clock signals necessary for charge pump boosting using the internal oscillation or  
using external clock signals.  
Two different types of capacitors are being used as the charge pump capacitors, one being the flying capacitor  
which shifts between the charging state and the discharging state and the other being the smoothing capacitor  
which preserves the electric charge. The operating frequency of the flying capacitor should equal to the fre-  
quency of the charge pump clock being generated by this timing signal forming circuit.  
Under the shut down state (POFFX = VSS level), the charge pump clock stops operation and all the boosting  
operations of this IC will be interrupted. The operating frequencies of the flying capacitor are as follows.  
Operating frequencies of the flying capacitor  
OSCSEL  
MODE pin  
Mode name  
2 boosting in  
3 boosting in  
3 boosting in  
pin  
the positive direction the positive direction the negative direction  
HIGH(VDD)  
LOW(VSS)  
HIGH(VDD)  
Normal mode  
Blank mode  
10kHz  
625kHz  
10kHz  
625kHz  
10kHz  
625kHz  
HIGH(VDD)  
LOW(VSS)  
LOW(VSS)  
Blank mode  
1/2 fosc Hz  
1/2 fosc Hz  
1/2 fosc Hz  
CL = fosc (Hz)  
10  
Rev. 1.1  
S1F75510  
2 boosting circuit in the positive direction  
The 2 boosting circuit in the positive direction generates the voltages necessary to input into the voltage  
stabilizing circuit. It makes 2 boosting in the positive direction of the potential difference occurring between the  
VDD VSS using the VSS potential as the reference voltage to output through the VOUT1 pin.  
Under the blank mode, since the boosting operation is being carried out with the flying capacitor C2 stopping its  
operation, the current consumption can be suppressed accordingly.  
The theoretical equation (output voltage value under the idealistic non-load state) for the VOUT1 becomes as  
follows:  
VOUT1 = (VDD VSS) 2  
Actually, when a load is connected to the VOUT1, the output voltage will drop to the value represented by the  
equation indicated below.  
VOUT1 = (VDD VSS) 2 RVOUT1 IVOUT1  
RVOUT1 : Output impedance of the x2 boosting circuit in the positive direction  
IVOUT1 : Load current  
Voltage stabilizing circuit  
The voltage stabilizing circuit stabilizes the voltage being output through the VOUT1 pin by the series regulator  
to output the positive supply voltage for the source driver through the VOUT2 pin.  
The output voltage setting for the VOUT2 pin should be Typ. +5.0V (TBD).  
As for IOUT2, in order to obtain normal output voltage value through the VOUT2 pin, use the IC within the range  
of the max. load current (Refer to Mode changeover circuit ).  
The circuit configuration · connection diagram for the voltage stabilizing circuit is as follows:  
[Internal structure of the S1F75510]  
CVOUT1  
+
V
OUT1  
OUT2  
×2 boosting circuit in the  
positive direction  
VOUT1 = (VDDVSS) × 2  
To the source driver  
V
+
Voltage stabilizing  
circuit  
+
CVOUT2  
Reference voltage circuit  
V
DD  
VSS  
×3 boosting circuit in the positive direction  
×3 boosting circuit in the negative direction  
Fig. 4 Configuration diagram of the voltage stabilizing circuit  
Rev. 1.1  
11  
S1F75510  
3 boosting circuit in the positive direction  
The 3 boosting circuit in the positive direction generates the VOUT3 output voltage, means the positive supply  
voltage for the gate driver. It makes 3 boosting in the positive direction of the potential difference occurring  
between the VOUT2 VSS using the VSS potential as the reference voltage, by charge pump boosting, to output  
through the VOUT3 pin.  
The theoretical equation (output voltage value under the idealistic non-load state) for the VOUT3 becomes as  
follows:  
VOUT3 = (VOUT2 VSS) 3  
Actually, when a load is connected to the VOUT3, the output voltage will drop to the value represented by the  
equation indicated below.  
VOUT3 = (VOUT2 VSS) 3 (RVOUT3 IVOUT3)  
RVOUT3 : Output impedance of the 3 boosting circuit in the positive direction  
IVOUT3 : Load current  
It means that the VOUT3 voltage will drop by the load.  
To acquire desired output voltage, use the IC within the range of the specified load (Refer to Mode changeover  
circuit ).  
3 boosting circuit in the negative direction  
The 3 boosting circuit in the negative direction generates the VOUT3 output voltage, means the negative  
supply voltage for the gate driver. It makes 3 boosting in the negative direction of the potential difference  
occurring between the VOUT2 VSS using the VOUT2 potential as the reference voltage, by charge pump boost-  
ing, to output through the VOUT4 pin.  
The theoretical equation (output voltage value under the idealistic non-load state) for the VOUT4 becomes as  
follows:  
VOUT4 = (VOUT2 VSS) (2) (The voltage value using the VSS potential as the reference voltage)  
Actually, when a load is connected to the VOUT4, the output voltage will drop to the value represented by the  
equation indicated below.  
VOUT4 = (VOUT2 VSS) (2) (RVOUT4 IVOUT4)  
RVOUT4 : Output impedance of the 3 boosting circuit in the negative direction  
IVOUT4 : Load current  
It means that the VOUT4 voltage will drop by the load.  
To acquire desired output voltage, use the IC within the range of the specified load (Refer to Mode changeover  
circuit ).  
12  
Rev. 1.1  
S1F75510  
Start-up sequence  
The ON sequence when the S1F75510 starts up is described as follows.  
INPUT  
VDD  
POFFX  
OUTPUT  
VOUT2  
0V  
0V  
VOUT4  
VOUT3  
0V  
1
2
34  
5
1The S1F75510 is energized.  
2The operation start signal is input and the internal booster (VOUT1) starts up.  
3The positive power supply for source driver (stabilized output) VOUT2 starts up.  
4The negative power supply for gate driver VOUT4 starts up.  
5The positive power supply for gate driver VOUT3 starts up.  
Discharge circuit  
The S1F75510 is equipped with a built-in circuit that discharges the positive power supply for source driver  
(stabilized output) VOUT2, positive power supply for gate driver VOUT3 and negative power supply for gate driver  
VOUT4 to the VSS level. This discharge circuit starts discharging VOUT2, VOUT3 and VOUT4 when the POFFX  
terminal is turned to the VSS level.  
Rev. 1.1  
13  
S1F75510  
ABSOLUTE MAXIMUM RATINGS  
Rating  
Applicable  
pin  
Item  
Symbol  
Unit  
Remarks  
Min.  
Max.  
4.0  
Input supply voltage  
Output voltage 1  
Output voltage 2  
Output voltage 3  
Output voltage 4  
Input pin voltage 1  
Input current  
VDD  
VOUT1  
VOUT2  
VOUT3  
VOUT4  
VIN  
0.3  
0.3  
0.3  
0.3  
15.0  
0.3  
V
V
VDD  
7.5  
VOUT1  
VOUT2  
VOUT3  
VOUT4  
<Note 1>  
VDD  
7.5  
V
22.5  
0.3  
V
V
VDD + 0.3  
50  
V
IVDD  
mA  
mA  
mA  
mA  
mA  
mW  
˚C  
Output current 1  
Output current 2  
Output current 3  
Output current 4  
Allowable dissipation  
Operating temperature  
Storage temperature  
Soldering temperature  
and time  
IVOUT1  
IVOUT2  
IVOUT3  
IVOUT4  
Pd1  
20  
VOUT1  
VOUT2  
VOUT3  
VOUT4  
20  
5
5
520  
85  
Ta 25˚C  
Topr  
30  
55  
Tstg  
150  
260·10  
˚C  
Tsol  
˚C·s  
At leads  
<Note 1> The applicable pins are POFFX, OSC1, CL, MODE and OSCSEL.  
<Note 2> Do not apply external voltage to the output pins and the pin connecting to the capacitor.  
<Note 3> Use of the IC under any conditions exceeding the above absolute maximum ratings may cause malfunc-  
tioning or permanent breakdown. Or, even if the IC may operate normally temporarily, the reliability may  
greatly drop.  
14  
Rev. 1.1  
S1F75510  
ELECTRICAL CHARACTERISTICS  
DC characteristics  
In case particular designations are not made (Note 1): Ta = 25˚C  
Rating  
Item  
Symbol  
Conditions  
Unit Remarks  
Min.  
2.7  
Typ.  
3.0  
Max.  
3.6  
Input supply voltage  
High level input voltage  
Low level input voltage  
Input leak current 1  
VDD  
VIH  
Applicable pin: VDD  
V
V
2
0.8VDD  
0
VDD  
VIL  
0.2VDD  
0.5  
V
2
ILIN1  
VSS VI VDD,  
VDD = 2.7 to 3.6V  
VDD = 3.0V, no load  
Under the normal mode  
VDD = 3.0V, no load  
Under the blank mode  
CL = 1.25kHz, duty = 50%  
Under the normal mode  
VDD = 2.7V  
0.5  
µA  
2
Current consumption 1  
Current consumption 2  
IOP1  
IOP2  
200  
17  
280  
30  
µA  
µA  
Power conversion efficiency 1  
(Overall efficiency including  
the stabilized outputs)  
Power conversion efficiency 2  
(Overall efficiency including  
the stabilized outputs)  
Peff1  
Peff2  
%
%
3
4
91  
82  
VDD = 3.0V  
Blank mode exterior  
CL = 1.25kHz, duty = 50%  
VDD = 2.7V  
89  
80  
VDD = 3.0V  
Resting current  
IQ  
VDD = 3.6V  
1.0  
µA  
POFFX = LOW  
<Note 1> Conditions on the operation mode, external parts constant, pins, etc. in case particular designations are  
not made are as follows.  
Connection and parts constant : Standard connection 1, 10.1  
MODE pin  
CL pin  
: MODE = HIGH (Normal mode)  
: CL = LOW (Fixed voltage)  
<Note 2> The applicable pins are POFFX, OSCI, CL, MODE, OSCSEL  
<Note 3> Load conditions: IVOUT2 = 10mA, IVOUT3 = 100µA, IVOUT4 = 100µA  
Conversion efficiency = [(VOUT2 IVOUT2) + (VOUT3 IVOUT3) + (VOUT4 IVOUT4)] / (VDD IVDD ) 100  
*
*
<Note 4> Load conditions: IVOUT2 = 200µA, IVOUT3 = 10µA, IVOUT4 = 10µA  
Conversion efficiency = [(VOUT2 IVOUT2) + (VOUT3 IVOUT3) + (VOUT4 IVOUT4)] / (VDD IVDD ) 100  
*
*
Rev. 1.1  
15  
S1F75510  
Characteristics of 2 boosting in the positive direction + stabilized output  
In case particular designations are not made: Ta = 25˚C  
Rating  
Typ.  
20  
Item  
Symbol  
Conditions  
Unit Remarks  
Min.  
Max.  
VOUT1 output impedance RVOUT1-1 Applicable pin:  
(Normal mode)  
VOUT1 output impedance RVOUT1-2 Applicable pin:  
25  
V
5
6
7
8
VOUT1  
4.90  
400  
5.00  
5
600  
5.10  
10  
(Blank mode)  
VOUT1  
VOUT2  
VOUT2  
Applicable pin:  
VOUT2  
Stabilized output voltage  
VOUT2 Stabilized output  
saturated resistance  
RVOUT2  
Applicable pin:  
VOUT2  
<Note 5> VDD = 2.7V to 3.6V, Load condition: IVOUT1 = 10mA  
<Note 6> VDD = 2.7V to 3.6V, Load condition: IVOUT1 = 200mA  
<Note 7> VDD = 2.7V to 3.6V, Load condition: IVOUT2 = 1mA  
Ta = 10 to +70˚C  
<Note 8> VDD = 2.7V to 3.6V, Load condition: IVOUT2 = 10mA  
Characteristics of 3 boosting in the positive direction and 3 boosting in he negativet  
direction  
In case particular designations are not made: Ta = 25˚C  
Rating  
Item  
Symbol  
Conditions  
Unit Remarks  
Min.  
Typ.  
Max.  
VOUT3 output impedance RVOUT3-1 Applicable pin:  
(Normal mode)  
VOUT3 output impedance RVOUT3-2 Applicable pin:  
(Blank mode)  
VOUT4 output impedance RVOUT4-1 Applicable pin:  
(Normal mode)  
VOUT4 output impedance RVOUT4-2 Applicable pin:  
(Blank mode)  
0.7  
1.0  
9
VOUT3  
4.0  
1.0  
4.0  
5.0  
1.3  
5.0  
10  
11  
12  
VOUT3  
VOUT4  
VOUT4  
<Note 9> VDD = 2.7V to 3.6V, Load condition: IVOUT3 = 100µA  
<Note 10> VDD = 2.7V to 3.6V, Load condition: IVOUT3 = 10µA  
<Note 11> VDD = 2.7V to 3.6V, Load condition: IVOUT4 = 100µA  
<Note 12> VDD = 2.7V to 3.6V, Load condition: IVOUT4 = 10µA  
16  
Rev. 1.1  
S1F75510  
AC characteristics  
Measurement conditions for the AC characteristics  
· Input signal level  
VIH = 0.8VDD (V)  
VIL = 0.2VDD (V)  
· Input signal rise time Tr = Max. 100ns  
· Input signal fall time Tf = Max. 100ns  
VDD = 2.7 to 3.6V, VSS = 0V  
Ta = 30 to +85˚C  
CL inputting timing  
tWHCK  
VIH  
VIL  
VIH  
VIH  
CL  
VIL  
tWLCK  
tCCK  
Rating  
Typ.  
Applicable  
Item  
Symbol  
Unit  
Remarks  
Min.  
10  
Max.  
pin  
CL cycle  
tCCK  
tWHCK  
tWICK  
1000  
µs  
ns  
ns  
CL High pulse duration  
CL Low pulse duration  
2
2
CL  
Rev. 1.1  
17  
S1F75510  
REFERENCE EXTERNAL CONNECTION (AN EXAMPLE)  
Standard connection (+5V, +15V, 10V Output)  
VDD  
VSS  
VDD  
VSS  
+
C1P  
C1  
POFFX  
POFFX  
C1N  
+
C2P  
C2N  
C2  
OSC1  
OSC2  
ROSC  
CVOUT1  
+
VOUT1  
VOUT2  
(VOUT1)  
VOUT2  
+5V  
CL  
MODE  
CL  
CVOUT2  
+
MODE  
OSCSEL  
+
+
C3P  
C3N  
C3  
C4  
OSCSEL  
C4P  
C4N  
CVOUT3  
+
VOUT3  
VOUT3  
+15V  
+
+
C5P  
C5N  
C5  
C6P  
C6N  
Reference values for the  
external parts  
C6  
ROSC=1MΩ  
C1=C2=CVOUT1=4.7µF  
CVOUT2=4.7µF  
C3=C4=CVOUT3=1.0µF  
C5=C6=CVOUT4=1.0µF  
CVOUT4  
+
VOUT4  
VOUT4  
10V  
18  
Rev. 1.1  
S1F75510  
Extended connection (+5V, +15V, –15V Output)  
VDD  
VSS  
VDD  
VSS  
+
+
C1P  
C1  
POFFX  
POFFX  
C1N  
C2P  
C2N  
C2  
OSC1  
OSC2  
ROSC  
CVOUT1  
+
VOUT1  
VOUT2  
(VOUT1)  
VOUT2  
+5V  
CL  
MODE  
CL  
CVOUT2  
+
MODE  
OSCSEL  
+
+
C3P  
C3N  
C3  
C4  
OSCSEL  
C4P  
C4N  
CVOUT3  
+
VOUT3  
VOUT3  
+15V  
C5P  
C5N  
+
+
C5  
C6  
C6P  
C6N  
Reference values for the  
external parts  
ROSC=1M  
C1=C2=CVOUT1=4.7µF  
CVOUT2=4.7µF  
C3=C4=CVOUT3=1.0µF  
C5=C6=C7=CVOUT4’=1.0µF  
+
+
C7  
CVOUT4’  
VOUT4’  
–15V  
VOUT4  
* Note  
D
*Note : The boosting magnification of 3 times or more can be realizable by adding a diode and one capacitor at a  
time to the example of standard connection.  
Since output impedance becomes larger under the influence of VF of a diode, the diode of low VF is  
recommended.  
Rev. 1.1  
19  
S1F75510  
Recommended capacitance value of external capacitor and theoretical value of  
voltage biased to both pins  
Circuit name  
Kind of  
Capacitor  
name  
C1  
Recommended  
Theoretical value of voltage  
capacitor  
capacitance value [µF] biased to capacitor’s both pins  
2 boosting circuit Flying capacitor  
4.7  
4.7  
4.7  
4.7  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
(VDD – VSS)  
(VDD – VSS)  
in the positive  
direction  
Flying capacitor  
C2  
Accumulation capacitor CVOUT1  
(VOUT1 – VSS)  
(VOUT2 – VSS)  
(VOUT2 – VSS)  
(VOUT2 – VSS) 2  
(VOUT3 – VSS)  
(VOUT2 – VSS)  
(VOUT2 – VSS) 2  
(VOUT2 – VSS) 3  
(VOUT4 – VSS)  
(VOUT4’ – VSS)  
Stabilizing circuit Smoothing capacitor CVOUT2  
3 boosting circuit Flying capacitor  
C3  
C4  
in the positive  
direction  
Flying capacitor  
Accumulation capacitor CVOUT3  
3 (4) boosting Flying capacitor  
circuit in the Flying capacitor  
negative direction Flying capacitor  
C5  
C6  
C7  
Accumulation capacitor CVOUT4  
CVOUT4’  
<Note> “ELECTRICAL CHARACTERISTICS” are available when capacitors’ capacitance values are as shown  
above. Since the characteristics may vary with the maximum load current, the working environment,  
applicable parts, etc., however, evaluate the characteristics for each application and check the capaci-  
tance values.  
20  
Rev. 1.1  
S1F75510  
DIMENSIONAL OUTLINE DRAWING  
SSOP324pin  
0 ~ 10°  
0.375 Typ.  
7.9±0.2  
0.65  
0.5±0.2  
+0.1  
0.05  
0.22  
0.12  
M
0.10  
Unit : mm  
NOTICE:  
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson  
reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any  
inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this  
material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights  
is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free  
from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to  
strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry  
of International Trade and Industry or other approval from another government agency.  
© Seiko Epson Corporation 2002, All rights reserved.  
All other product names mentioned herein are trademarks and/or registered trademarks of their respective companies.  
ELECTRONIC DEVICES MARKETING DIVISION  
IC Marketing & Engineering Group  
EPSON Electronic Devices Website  
http://www.epsondevice.com  
ED International Marketing Department  
Europe & U.S.A  
421-8 Hino, Hino-shi, Tokyo 191-8501, JAPAN  
Phone: 042  
587  
5812 FAX: 042  
587  
5564  
ED International Marketing Department  
Asia  
421-8 Hino, Hino-shi, Tokyo 191-8501, JAPAN  
Phone: 042  
587  
5814 FAX: 042  
587  
5110  
First issue July, 2001  
Printed August, 2002 in Japan  
H
Rev. 1.1  

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