S1F75520D0A0000 [SEIKO]
SWITCHED CAPACITOR REGULATOR, 28kHz SWITCHING FREQ-MAX, UUC72, 4.30 X 4.30 MM, ALUMINUM PAD, DIE-72;
| 型号： | S1F75520D0A0000 |
| 厂家： | 
SEIKO EPSON CORPORATION |
| 描述： | SWITCHED CAPACITOR REGULATOR, 28kHz SWITCHING FREQ-MAX, UUC72, 4.30 X 4.30 MM, ALUMINUM PAD, DIE-72 开关 |
| 文件： | 总52页 (文件大小：489K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PF1267-02
S1F75520 Series
Charge-pump DC/DC Converter &
Voltage Regulator with VCOM
ꢀ DESCRIPTION
The S1F75520 is a TFT liquid crystal panel power supply IC. A single power input generates the bias voltage
necessary for driving the liquid crystal. The voltage conversion circuit does not need any external transistors or
diodes, and since all internal CMOS transistors are configured from a charging pump type DC/DC converter, it
is most appropriate for lowering the power consumption of the LCD module.
Combining the S1D19200 or other source drivers and the S1D17917 or other gate drivers may further lower the
LCD module power consumption.
ꢀ FEATURES
• Power supply voltage··········· 2.7 to 3.6V single power input
• Self current consumption ····· Typ. 160 µA
• Standby current ··················· 5 µA
• Built-in charging pump type DC/DC converter voltage conversion circuit
• Outputs positive power supply voltage VSCE for the source driver
· Outputs from the primary booster circuit and the source driver voltage regulator.
· VSCE output voltage can be set within 3.5V to 5.0V from external resistors.
• Outputs positive power supply voltage VGON for the gate driver.
· Outputs from the gate driver voltage regulator and the secondary booster circuit.
· Output voltage can be set within 6.6V to 20V from an external resistor.
• Outputs negative power supply voltage VGOFF for gate driver.
· Outputs from the gate driver voltage regulator and the tertiary booster circuit.
· Output voltage can be set within –15 to –6.6V from an external resistor.
• Built-in counter-voltage VCOM output voltage
· Outputs to the polarity input pin POL synchronously.
· Central voltage of the output voltage can be set within 0.0 to 2.5V.
· Central voltage of the output voltage can be controlled by the analog input signal (VCENT) or the digital input
signal
· Digital input signal controls are made through a 3-line system (BDATA, BCK, XBCS).
· The output voltage amplitude can be set within 3.0 to 5.5V range.
· The output amplitude is controlled through analog input signal (VSWIN).
· Built-in output off function
• Built-in logic power supply voltage regulator
· The output voltage can be set within 1.5 to 1.8V range.
• Built-in soft start circuit
• Built-in discharge circuit
• Built-in CR oscillator circuit
• Shipping forms ················· TQFP12–48pin (S1F75520F0A0000)
Rev. 1.1
S1F75520 Series
QFN7–48pin (S1F75520F5A0000)
Chip Al pad (S1F75520D0A0000)
Chip Au bump (S1F75520D5A0000)
• The product resist radiation or light. (Connected to an external component to configure a switching regulator.)
Use the following semiconductor chip handling notes.
[
]
IC handling notes against light :
If semiconductor chips are exposed to strong light, their characteristics may change. Therefore, if the ICs are
placed in the light, they may malfunction. To protect them, the following general requirements must be
satisfied for IC mounting boards and products.
(1) Do not expose ICs to the light before mounting during board design and IC mounting.
(2) Also, do not expose the ICs to the light in the inspection phase.
(3) Do not expose the top, bottom and sides of an IC chip to the light.
2
Rev. 1.1
S1F75520 Series
ꢀ BLOCK DIAGRAM
(10)
CZ1N
CZ2P
CZ2N
V
EP2
Tertiary booster circuit
(9)
V
GON
V
GOFF
CY2N
CY2P
CY1N
CY1P
Secondary booster
circuit
(11)
SEVCOM
BDATA
BCK
VRGP
XBCS
POL
(8)
(7)
V
COM control circuit
Gate driver
voltage regulator
RVP
PSAVE1
PSAVE0
V
SWIN
V
CENT
XOFFCM
VSCE
RVS
Source driver
voltage regulator
V
REF2
(12)
(13)
VREF1
Discharge circuit
V
V
V
V
COM2
(6)
V
COM
Soft start circuit
COM output voltage
generator circuit
COMH
COML
V35
(2)
XSLPX
XSLPY
MODE
CNT
VP
Timing signal
formation circuit
VN
PCK
(5)
CX1P
CX1N
CX2P
CX2N
CX3P
CX3N
(1)
Primary booster circuit
OSC2
OSC1
CR oscillator circuit
(3)
XOFF18
SEVTG2
SEVTG1
SEVTG0
(4)
Logic power
Logic power supply
voltage regulator
supply control circuit
V18
VDD1 to 2
VSS
Fig. 1 Block Diagram
Rev. 1.1
3
S1F75520 Series
ꢀ BLOCK DESCRIPTION
(1) CR oscillator circuit
This is used as the primary to tertiary booster circuit clock for the IC. Pin setup (MODE) allows external input
(PCK) of the charging pump clock. The oscillation frequency can be adjusted by an external resistor.
(2) Timing signal formation circuit
This generates the primary to tertiary booster circuit clock from the PCK pin or the oscillation signal from the CR
oscillator circuit.
(3) Logic power supply control circuit
It controls the logic power supply voltage regulator.
(4) Logic power supply voltage regulator
This is the voltage regulator for the logic power supply, which outputs 1.5 to 1.8V as an external power supply
to LCD controllers and other devices other than this IC.
(5) Primary booster circuit
This is the positive and negative output booster circuit configured from a charging pump type DC/DC converter.
Boosting can be set to 1.5 or 2-times via the CNT pin.
(6) VCOM output voltage generator circuit
This generates a counter-voltage VCOM output voltage. It also outputs synchronous square waves to the POL
polarity input pin . The VCOM amplitude and the VCOM central voltage can be controlled by the VCOM control
circuit.
(7) Source driver voltage regulator
This generates a positive power supply voltage for the source driver. The output voltage is VSCE=3.5V(Typ.).
By adding external resistors, the voltage can be set within 3.5 to 5V. The tone voltage VREF1 output voltage and
VREF2 output voltage are also generated.
(8) Gate driver voltage regulator
The gate output positive and negative power supply voltages for the gate driver are generated by this regulator
and the secondary and tertiary booster circuits.
This regulator outputs VRGP=3.3V(Typ.). By adding external resistors, the voltage can be set within 3.3 to 5V.
(9) Secondary booster circuit
This is a positive output booster circuit configured from a charging pump type DC/DC converter. It boosts the
gate driver voltage regulator VRGP voltage by 2, 3 or 4-times based on VSS=0V. Boosting can be set via
external wiring.
(10) Tertiary booster circuit
This is a negative output booster circuit configured from a charging pump type DC/DC converter. It boosts the
gate driver voltage regulator VRGP voltage by –2, –3 or –4-times based on VSS=0V. Boosting can be set via
external wiring.
4
Rev. 1.1
S1F75520 Series
(11) VCOM control circuit
This controls the VCOM output voltage generator circuit. The VCOM amplitude is controlled by the analog input
signal, and the VCOM central voltage is controlled by the analog or digital input signal.
(12) Discharge circuit
This discharges the residual voltages on the VSCE pin, the VGON pin and the VGOFF pin to VSS.
(13) Soft start circuit
This alleviates the current surge to the booster capacitor at the start of boosting.
ꢀ PAD LAYOUT AND PIN LAYOUT
ꢀPad Layout
Alignment mark
54
34
DIE no.
Alignment mark
55
33
SEVCOM
SEVCOM
CNT
VREF2
XOFF18
V
SS
V
REF1
SS
SCE
VSCE
V
V35
V
V
V
V
SWIN
RVS
SS
VSS
COML
RVP
VRGP
VDD2
V
V
V
V
V
V
V
COMH
CENT
COM
DD2
DD1
SS
Ο
V
SS
SS
V
CX2N
CX2P
V
P
CX1P
SS
CX1N
CX3P
CX3N
V18
Alignment mark
Alignment mark
16
72
15
1
4.30mm
Chip size
Pad pitch
: 4.30 × 4.30mm
: Min. 150µm
Chip thickness : 300µm
Circuit potential : VSS
Rev. 1.1
5
S1F75520 Series
ꢀ S1F75520D0A00 (AL pad)
DIE number
: F7552D0A
: 100µm × 100µm
PAD opening
Alignment marks :
Aluminium
50µm
40µm
80µm
Alignment coordinate=(–1974.8, 1974.8)
Alignment coordinate=(1974.8, –1974.8)
ꢀ S1F75520D5A00 (Au bump)
DIE number : F7552D5A
Au bump specifications : Au vertical bumps
Bump size
: 100µm × 100µm
Bump height
Alignment marks:
: 22.5µm(Typ.) Details are given in the delivery specifications.
Bump
50µm
40µm
80µm
Alignment coordinate=(1974.8, 1974.8)
Alignment coordinate=(–1974.8, –1974.8)
6
Rev. 1.1
S1F75520 Series
ꢀPad Center Coordinates
Unit : µm
PAD No.
1
PAD Name
VCOM
VCOM
VGON
VEP2
X
Y
PAD No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
—
PAD Name
XSLPY
XSLPX
MODE
SEVTG0
SEVTG1
SEVTG2
PSAVE0
PSAVE1
VDD2
X
Y
–1468.8
–1318.8
–1048.4
–898.4
–746.8
–504.4
–262.8
–48.8
–1974.8
505.2
1974.8
2
355.2
3
205.2
4
–212.4
–362.4
–512.4
–662.4
–812.4
–962.4
–1112.4
–1262.4
–1412.4
–1562.4
–1712.4
–1974.8
5
VSS
6
VGOFF
CZ2P
CZ2N
CZ1N
CY2N
CY2P
CY1N
CY1P
VN
7
8
9
106.4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
256.4
POL
406.4
XBCS
BCK
556.4
706.4
BDATA
BDATA
SEVCOM
SEVCOM
CNT
1108.0
1258.0
1974.8
VN
1712.8
1562.8
1412.8
1262.8
1112.8
962.8
812.8
662.8
512.8
362.8
–144.8
–294.8
–444.8
–594.8
–744.8
–894.8
–1044.8
–1824.8
—
CX3N
CX3P
CX1N
CX1P
VP
–1824.8
–1568.0
–1340.8
–1023.6
–818.8
–628.0
–420.0
–244.8
–94.8
XOFF18
VSS
VSCE
V35
CX2P
CX2N
VSS
VSWIN
VSS
VSS
VCOML
VCOMH
VCENT
VCOM
VDD2
VDD2
VRGP
RVP
55.2
205.2
355.2
VSS
505.2
RVS
655.2
VDD1
VSCE
VSS
805.2
VSS
955.2
VSS
VREF1
VREF2
VCOM2
TEST
FCLK
1105.2
1824.8
1974.8
V18
—
—
—
—
—
—
—
—
—
1555.2
1405.2
1255.2
1105.2
955.2
—
—
—
—
—
—
—
—
—
OSC2
OSC1
PCK
—
—
—
—
—
—
805.2
—
—
—
XOFFCM
655.2
—
—
—
Rev. 1.1
7
S1F75520 Series
ꢀPin Assignment
36
25
36
25
24
37
24
37
48
48
13
13
1
12
1
12
Fig. 2 TQFP12–48pin
Fig. 3 QFN7–48pin
Pin No.
Pin Name
VGON
VEP2
Pin No.
13
Pin Name
CX3P
CX1N
CX1P
VP
Pin No.
25
Pin Name
Pin No.
37
Pin Name
CNT
1
2
OSC2
OSC1
14
26
38
XOFF18
V35
3
VGOFF
CZ2P
CZ2N
CZ1N
CY2N
CY2P
CY1N
CY1P
VN
15
27
PCK
39
4
16
28
XOFFCM
XSLPY
XSLPX
MODE
SEVTG0
SEVTG1
PSAVE0
PSAVE1
POL
40
VSWIN
VCOML
VCOMH
VCENT
VCOM
VDD2
5
17
CX2P
CX2N
VRGP
RVP
29
41
6
18
30
42
7
19
31
43
8
20
32
44
9
21
RVS
33
45
10
11
12
22
VSCE
34
46
VDD1
23
VREF1
VREF2
35
47
VSS
CX3N
24
36
48
V18
Pin names are common to both TQFP12-48pin and QFN7-48pin.
8
Rev. 1.1
S1F75520 Series
ꢀPin name - Pin Number Correspondence Table
Pin Name
CHIP
TQFP12–48
Pin Name
CHIP
TQFP12–48
QFN7–48
—
—
1
QFN7–48
29
30
31
32
33
—
VCOM
VCOM
VGON
VEP2
1
XSLPY
XSLPX
MODE
SEVTG0
SEVTG1
SEVTG2
PSAVE0
PSAVE1
VDD2
POL
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
—
—
—
—
—
—
—
—
2
3
4
2
VSS
5
—
3
VGOFF
CZ2P
CZ2N
CZ1N
CY2N
CY2P
CY1N
CY1P
VN
6
7
4
34
35
—
8
5
9
6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
7
36
—
8
XBCS
BCK
9
—
10
11
—
12
13
14
15
16
17
18
—
—
—
19
20
—
21
22
—
23
24
—
—
—
25
26
27
28
BDATA
BDATA
SEVCOM
SEVCOM
CNT
—
—
VN
—
CX3N
CX3P
CX1N
CX1P
VP
—
37
38
—
XOFF18
VSS
VSCE
V35
—
CX2P
CX2N
VSS
39
40
—
VSWIN
VSS
VSS
VCOML
VCOMH
VCENT
VCOM
VDD2
VDD1
VSS
41
42
43
44
45
46
—
VDD2
VRGP
RVP
VSS
RVS
VSCE
VSS
VSS
47
48
—
VREF1
VREF2
VCOM2
TEST
FCLK
V18
—
—
—
—
—
—
—
OSC2
OSC1
PCK
—
—
—
—
—
—
XOFFCM
—
—
Rev. 1.1
9
S1F75520 Series
ꢀ PIN DESCRIPTION
(1) CR oscillator circuit
Pin Name
OSC1
I/O
I
PAD No.
Function
38
37
CR oscillator circuit gate input pin. Oscillator resistor connection pin.
CR oscillator circuit drain input pin.
OSC2
O
Connects oscillation resistor between this pin and OSC1.
(2) Timing signal formation circuit
Pin Name
I/O
PAD No.
Function
External clock input pin.
PCK
I
39
Inputs the charging pump clock to this pin.
Booster clock conversion pin (with pull-down).
MODE
I
43
Sets the source oscillation for the booster clock.
MODE Function
VSS
Booster clock generated by the external clock PCK pin. CR
oscillator circuit stops.
VDD
Booster clock generated by the CR oscillator circuit.
CNT
I
57
Primary booster circuit boosting setup pin. (with pull-up).
Sets boosting for the primary booster circuit.
CNT
VSS
Function
1.5-times boosting mode. Outputs the following voltage
based on VSS=0V. VP=(VDD–VSS) × 1.5
2-times boosting mode. Outputs the following voltage based
on VSS=0V. VP=(VDD–VSS) × 2
VDD
XSLPX
XSLPY
I
I
42
41
Source driver positive and negative power supply voltage sleep pin.
Changing the pin to VSS level turns off the VSCE output voltage. The
discharge circuit also operates and discharges the residual voltages in
the VSCE pin to VSS pin.
Gate driver positive and negative power supply voltage sleep pin.
Changing the pin to VSS level turns off the VGON output voltage and the
VGOFF output voltage. The discharge circuit also operates and dis-
charges the residual voltages in the VGON pin and the VGOFF pin to VSS
pin. Secondary and tertiary booster circuits stop.
10
Rev. 1.1
S1F75520 Series
(3) Logic power supply control circuit
Pin Name
I/O
PAD No.
Function
XOFF18
I
58
Logic power supply voltage regulator sleep pin (with pull-up).
Changing the pin to VSS level turns off the logic power supply voltage
regulator. The residual voltages in the V18 pin are discharged to VSS.
Drive power conversion pin (with pull-down).
SEVTG2
I
46
Converts the maximum load current for the logic power supply series
regulators.
SEVTG2 Function
VSS
VDD
Normal load current mode. Maximum of 10mA load current
may be applied (during 1.8V output).
Large load current mode. Maximum of 40mA load current
may be applied (during 1.8V output).
SEVTG1
SEVTG0
I
45,
44
Output voltage conversion pin (with pull-down).
Sets the output voltage of the logic power supply voltage regulator.
SEVTG1 SEVTG0 Function
VSS
VDD
VDD
VDD
VSS
VDD
VSS
VDD
Outputs V18=1.8V.
Outputs V18=1.7V.
Outputs V18=1.6V.
Outputs V18=1.5V.
(4) Logic power supply voltage regulator
Pin Name
I/O
PAD No.
Function
V18
O
72
Logic power supply voltage regulator output pin.
Outputs 1.5 to 1.8V voltage as an external power supply to the LCD
controllers and other devices other than this IC.
Rev. 1.1
11
S1F75520 Series
(5) Primary booster circuit
Pin Name
I/O
PAD No.
Function
VP
O
20
Primary booster circuit positive output voltage pin.
Outputs the following voltage based on VSS=0V.
VP=(VDD–VSS)×N1 (N1=1.5 or 2)
Boosting (N1) is set by the CNT pin.
VN
O
14, 15
Primary booster circuit negative output voltage pin.
Outputs the following voltage based on VSS=0V.
VN=–VP
Also outputs the following voltage based on VSS=0V by changing the
external wiring.
VN=–(VDD–VSS)
CX1P
CX1N
CX2P
CX2N
CX3P
CX3N
(O)
(O)
(O)
(O)
(O)
(O)
19
18
21
22
17
16
Positive connection pin of the VP output voltage generator flying capacitor
Negative connection pin of the VP output voltage generator flying capacitor
Positive connection pin of the VP output voltage generator flying capacitor
Negative connection pin of the VP output voltage generator flying capacitor
Positive connection pin of the VN output voltage generator flying capacitor
Negative connection pin of the VN output voltage generator flying capacitor
(6) VCOM output voltage generator circuit
Pin Name
I/O
PAD No.
Function
Counter-voltage VCOM output pin.
VCOM
O
1, 2, 67
Outputs synchronous square waves as polarity reversal input pin
(POL). VCOM amplitude and VCOM central voltage are controlled by the
VCOM control circuit.
VCOM2
VCOMH
VCOML
V35
O
O
O
O
34
65
64
61
VCOM2 output pin.
Outputs voltage same as that of the VCOM pin.
VCOMH output pin.
Auxiliary output voltage pin for the VCOM output.
VCOML output pin.
Auxiliary output voltage pin for the VCOM output.
3.5V regulator output pin.
Regulator output pin. Outputs 3.5V (Typ.). Used for setting up the
VCOM amplitude and the VCOM central voltage. Connect a ladder
resistor between this pin and VSS (0V) and input the divided voltage to
the VSWIN and VCENT pins.
12
Rev. 1.1
S1F75520 Series
(7) Source driver voltage regulator
Pin Name
I/O
PAD No.
Function
VSCE
O
30
VSCE output pin.
Generates the source driver power supply voltage. Output voltage is
VSCE=3.5V(Typ.). By adding external resistors, the output voltage can
be set within 3.5 to 5V.
RVS
I
29
32
Voltage adjustment input pin for the VSCE output voltage.
Adjusts the VSCE voltage via an external resistor.
Tone voltage VREF1.
VREF1
O
Outputs antiphase square waves as polarity reversal input pin (POL).
The output voltage outputs the voltage between VSCE and VSS. It
reaches VSS level when XSLPX=VSS level.
VREF2
O
33
Tone voltage VREF2.
Outputs synchronous square waves as polarity reversal input pin
(POL). The output voltage outputs the voltage between VSCE and VSS.
It reaches VSS level when XSLPX=VSS level.
(8) Gate driver voltage regulator
Pin Name
I/O
PAD No.
Function
VRGP
O
26
VRGP output pin.
The gate output positive and negative power supply voltages to the
gate driver are generated from this regulator and the secondary and
tertiary booster circuit. The output of this regulator is VRGP=3.3V(Typ.).
By adding an external resistor, the output voltage can be set within 3.3
to 5V.
RVP
I
27
Voltage adjustment input pin for the VRGP output voltage.
Adjusts the VRGP voltage via an external resistor.
(9) Secondary booster circuit
Pin Name
I/O
PAD No.
Function
VGON
O
3
Secondary booster circuit output voltage pin.
Outputs the gate driver positive power supply voltage. Outputs the
following voltage based on VSS=0V.
VG=(VRGP–VSS)×N2 (N2=2 or 3 or 4)
Boosting (N2) can be set by changing the external wiring.
Secondary booster circuit intermediate output voltage pin.
Outputs the following voltage based on VSS=0V.
VEP2
O
4
CY1P
CY1N
CY2P
CY2N
(O)
(O)
(O)
(O)
13
12
11
10
Positive connection pin of the VEP2 output voltage generator flying capacitor.
Negative connection pin of the VEP2 output voltage generator flying capacitor.
Positive connection pin of the VGON output voltage generator flying capacitor.
Negative connection pin of the VGON output voltage generator flying capacitor.
Rev. 1.1
13
S1F75520 Series
(10) Tertiary booster circuit
Pin Name
I/O
PAD No.
Function
VGOFF
O
6
Tertiary booster circuit output voltage pin.
Outputs the gate driver negative power supply voltage. Outputs the
following voltage based on VSS=0V.
VG=(VRGP–VSS)×N3 (N3=–2 or –3 or –4)
Boosting (N3) can be set by changing the external wiring.
Negative connection pin of the VGOFF output voltage generator flying
capacitor.
CZ1N
(O)
9
Positive connection pins that correspond to this pin are the CY1N and
CY2N pins.
CZ2P
CZ2N
(O)
(O)
7
8
Positive connection pin of the VGOFF output voltage generator flying capacitor.
Negative connection pin of the VGOFF output voltage generator flying capacitor.
(11) VCOM control circuit
Pin Name
I/O
PAD No.
Function
XOFFCM
I
40
VCOM output off pin (with pull-up).
Changing this pin to VSS level turns off the VCOM circuit. Since the
VCOM output voltage generator circuit operates between the positive
and negative output voltages of the primary booster circuit, the VCOM
potential has the following relationship with the XSLPX and XSLPY
sleep pins when off.
XOFFCM XSLPY XSLPX VCOM potential (VSS=0V reference)
VSS
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VCOM=VSS
VCOM=(VSCE–VSS)/2
VCOM=VSS
VCOM=(VSCE–VSS)/2
VCOM=VSS
VDD
VCOM output voltage generator circuit
is operating.
POL
I
50
Polarity reversal input pin.
Synchronizes with the input signal to this pin and outputs synchronous
square waves from the VCOM and VREF1 output pins. Also, the VREF2
output pin outputs antiphase square waves as the input signal to this
signal.
14
Rev. 1.1
S1F75520 Series
(11) VCOM control circuit , continued
Pin Name
I/O
PAD No.
Function
SEVCOM
I
55, 56
VCOM central voltage adjustment selection pin (with pull-up).
This pin is used to select the control method for the VCOM central
voltage.
SEVCOM Function
VSS
Digital control mode.
Controls the VCOM central voltage via the digital input
signal. The resolution is 6-bits (BDATA, BCK, XBCS).
Analog control mode.
VDD
Controls the VCOM central voltage via the analog input
signal (VCENT).
BDATA
I
53, 54
VCOM central voltage serial data input pin (with pull-down).
This pin is used when the control method for the VCOM central voltage
is digital control mode. Input 6-bit serial data. The setup data is reset
with XSLPX=XSLPY=XOFFCM=VSS, and the electronic control value
becomes α=0.
BCK
XBCS
VCENT
I
I
I
52
51
66
Data transfer clock input pin (with pull-down).
This pin is used when the control method for the VCOM central voltage
is digital control mode. It receives BDATA's signal during clock rise.
Data writing permission input pin (with pull-up).
This is used when the control method for the VCOM central voltage is digital
control mode. It receives the first 6-bits of this signal as data during clock fall.
VCOM central voltage analog input pin.
This pin is used when the control method for the VCOM central voltage
is in analog control mode (SEVCOM=VDD). Connect a ladder resistor
between the V35 output pin and VSS (0V), and input the divided voltage
to this pin. Input voltage range is VCENT=1.5 to 2.5V. The relationship
between the input voltage and the VCOM central voltage are as follows:
VCOM central voltage =VCENT × 2.5 – 3.75 [V]
=0.0 to 2.5 [V] (Typ.)
VSWIN
I
62
VCOM amplitude analog input pin.
This pin is used to set the amplitude of the VCOM output voltage.
Connect a ladder resistor between the V35 output pin and VSS (0V),
and input the divided voltage to this pin. Input voltage range is
VSWIN=1.5 to 2.75V. The relationship between the input voltage and
the VSWIN amplitude voltage are as follows:
VCOM amplitude voltage=VSWIN × 2
=3.0 to 5.5 [V] (Typ.)
Rev. 1.1
15
S1F75520 Series
(11) VCOM control circuit , continued
Pin Name
PSAVE1
PSAVE0
I/O
PAD No.
48,
Function
VCOM generator circuit low consumption mode setup pin (with pull-
down).
I
47
(12) Power supply input pin.
Pin Name
VDD1
I/O
PAD No.
Function
I
I
I
69
68
Analog circuit input power supply pin (positive). <Note 1>
Digital circuit input power supply pin (positive). <Note 1>
VDD2
VSS
5, 23, 24, Input power supply pin (negative). <Note 2>
28, 31, 59,
63, 70, 71
<Note 1> Connect VDD1 and VDD2 externally and set them to the same potential.
<Note 2> If the shipment form is a chip, always supply potential externally for No.70 pin and No.71 pin.
(13) Test Pin
Pin Name
TEST
I/O
PAD No.
Function
Test pin. Always keep open (with pull-down).
Test pin. Always keep open (with pull-down).
I
I
35
36
FCLK
16
Rev. 1.1
S1F75520 Series
ꢀ FUNCTIONAL DESCRIPTION
ꢀOperation Description
The S1F75520 is a TFT liquid crystal panel power supply IC. A single power input generates the bias voltage
necessary for driving the liquid crystal. The voltage conversion circuit does not need any external transistors or
diodes, and since all internal CMOS transistors are configured from a charging pump type DC/DC converter, it
is most appropriate for lowering the power consumption of the LCD module.
Combining the S1D19200 or other source drivers and the S1D17917 or other gate drivers may further lower the
LCD module power consumption.
The voltage levels generated are:
• Source driver positive power supply voltage VSCE
• Gate driver positive power supply voltage VGON
• Gate driver negative power supply voltage VGOFF
• Counter-voltage VCOM
Each output voltage may be adjusted by changing the boosting setup for each booster circuit and by changing
the value of the external resistor for the voltage regulator.
For the counter-voltage VCOM output voltage, the VCOM central voltage and the VCOM amplitude voltage can be
adjusted by external resistors. VCOM central voltage can be controlled digitally (BDADA, BCK, XBCS).
This power supply IC has a built-in voltage regulator for the logic power supply which outputs 1.5 to 1.8V as an
external power supply to LCD controllers and other devices other than this IC.
The following is a typical configuration for power supply wiring.
TFT panel
LCD controller
V18
Source driver
Source driver
S1F75520
V
SCE
V
DD
V
DD
V
SS
V
SS
Fig. 4 System Configuration
Rev. 1.1
17
S1F75520 Series
The following is the potential relationship in the system shown in Fig. 5
4
VGON=(VRGP–VSS) × N2 , N2 = 4
VON
VGON
3
2
VSCE
VDDH
VDD
1
VDD
VSS
VDD
VDD
VSS
V18
0
VSS
VSS=0V
VCOM
Counter
electrode
–1
–2
–3
–4
VGOFF=(VRGP–VSS) × N3 , N3 = –4
VOFF
VGOFF
Power supply IC
(S1F75520)
TFT panel
Gate driver
Source driver
Fig. 5 Potential Relationship in the System
18
Rev. 1.1
S1F75520 Series
ꢀCR Oscillator Circuit
The S1F75520 has a built-in CR oscillator circuit for the booster clock. It is used as the primary-to-tertiary
booster circuit clock for the power supply IC. Connect an external resistor between the OSC1 and OSC2 pins.
[Outside IC]
[Inside IC]
OSC1
OSC2
Fig. 6 CR Oscillator Circuit External Resistor
1MΩ is the recommended resistance for the external resistor. The oscillation frequency can be adjusted by
changing the resistance of the external resistor.
The external input (PCK) of the charging pump clock can be made via the booster clock conversion pin
(MODE).
Table 1 MODE Pin Functions
MODE
VSS
Function
The booster clock is generated by the external clock PCK pin. The CR oscillator circuit stops.
The booster clock is generated by the CR oscillator circuit.
VDD
When both the XSLPX and XSLPY sleep pins are at the VSS level, the booster and CR oscillator circuits stop
regardless of the MODE pin setup. The following table shows their relationship.
Table 2 XSLPX, XSLPY and MODE Pin Functions
XSLPX
XSLPY
MODE
CR oscillator
circuit
Booster clock
Primary
boosting
Stop
Secondary and
tertiary boosting
Stop
VSS
VSS
VSS
VDD
*
Stop
Stop
VSS
VDD
VSS
VDD
VSS
VDD
Stop
PCK external input
CR oscillation clock
PCK external input
CR oscillation clock
PCK external input
CR oscillation clock
Boosting
Boosting
Boosting
Boosting
Boosting
Boosting
Boosting
Boosting
Stop
Oscillation
Stop
VDD
VDD
VSS
VDD
Oscillation
Stop
Stop
Boosting
Boosting
Oscillation
If only the PCK external input is used as the booster clock, that is, when the CR oscillator circuit is not used,
MODE=VSS and the OSC1 and OSC2 pins are kept open.
Rev. 1.1
19
S1F75520 Series
ꢀPrimary Booster Circuit
This is a positive and negative output booster circuit configured from the charging pump type DC/DC converter.
The positive output VP output voltage for this booster circuit is used as the positive input power supply to the
VCOM output voltage oscillator circuit, the source driver voltage regulator, and the gate driver voltage regulator
inside the power supply IC. The negative output VN output voltage is used as the negative input power supply
to the VCOM output oscillator circuit inside the power supply IC. Boosting for the primary booster circuit can be
set according to the counter-voltage VCOM output voltage, the source driver positive power supply VSCE output
voltage, the gate driver positive and negative power supply VGON output voltage and the VGOFF output voltage.
VP output voltage boosting of the positive output can be converted by the CNT pin.
Table 3 Setup for VP output voltage boosting
CNT
VSS
VP output voltage (VSS=0V reference)
1.5-times boosting mode
VP=(VDD–VSS)×1.5
VDD
2-times boosting mode
VP=(VDD–VSS)×2
The potential relationship is as shown in the following diagrams.
VP=(VDD–VSS) × 2
VP=(VDD–VSS) × 1.5
VDD
VDD
V
SS=0V
VSS=0V
Fig. 7 2-times Boosting mode (CNT=VDD)
Fig. 8 1.5-times Boosting mode (CNT=VSS)
VN output voltage boosting of the negative output can be setup via the CNT pin and external wiring.
Table 4 Setup for VN Output Voltage Boosting
Connection to the CP3X
flying capacitor
CNT
*
VN output voltage (VSS=0V reference)
Between CX1N and CX3N
–1-times boosting mode
VN=(VDD–VSS)×(–1)
Between CX3P and CX3N
VSS
VDD
–1.5-times boosting mode
VN=–VP=(VDD–VSS)×(–1.5)
–2-times boosting mode
VN=–VP=(VDD–VSS)×(–2)
20
Rev. 1.1
S1F75520 Series
The potential relationship is as shown in the following diagrams.
V
DD
VDD
VDD
V
SS=0V
VSS=0V
VSS=0V
VN=(VDD–VSS) × (–1)
VN=(VDD–VSS) × (–1.5)
VN=(VDD–VSS) × (–2)
Fig. 9 –1-times Boosting Mode
Fig. 10 –1.5-times Boosting Mode
Fig. 11 –2-times Boosting Mode
ꢀSource Driver Voltage Regulator
This generates a positive power supply voltage for the source driver. The output voltage is VSCE=3.5V(Typ.).
By adding an external resistor, the voltage can be set within 3.5 to 5V. The following is a typical connection
when an external resistor is added.
Inside S1F75520
Outside S1F75520
V
P
V
SCE
RSB
RVS
V
REF35 = 3.5V(Typ.)
(Note 1)
RSA
V
SS2
(Note 1) Try to avoid noise for the high impedance RVS pin.
Fig. 12 Source Driver Voltage Regulator
VSCE output voltage can be determined using the following equation.
RSB
VSCE=
+
× VREF35
(Equation 1)
1
(
)
RSA
However, RSA, RSB : external resistor
VREF35
: reference voltage inside the IC
VREF35 generates VREF35=3.5(Typ.) with a reference voltage inside the IC.
Rev. 1.1
21
S1F75520 Series
The voltage regulator uses the VP output voltage of the primary booster circuit as the input power supply
voltage. Boosting for the primary booster circuit must be set so that the VP output voltage is 0.4V or more
higher than the VSCE output voltage.
As shown in (equation 1), the desired output voltage can be generated by adjusting the ratio of the RSA and
RSB external resistors. If external resistors are used, set the value so that the current for the external resistors
is 5µA or higher. Current value IRG that flows through the external resistors can be determined using the
following equations.
VSCE
ISCE =
(Equation 2)
RSA+RSB
<Setup example: Setting VSCE output voltage to 4.85V>
From (equation 2)
VSCE
ISCE
4.85V
RSA+RSB =
=
= 970kΩ
········· 1
········· 2
5µA
From (equation 1)
RSB
RSA
VSCE
VREF35
4.85V
3.5V
=
–1 =
–1 = 0.3857
From 1 and 2
RSA=700kΩ, RSB=270kΩ
Also, by adding an external thermistor and other devices, a temperature gradient can be added to the VSCE
output voltage.
Outside S1F75520
Inside S1F75520
V
P
V
SCE
External
thermistor
RSB
RVS
V
REF35 = 3.5V(Typ.)
(Note 1)
RSA
V
SS2
(Note 1) Try to avoid noise for the high impedance RVS pin.
Fig. 13 When Temperature Gradient Is Added to the Output Voltage
22
Rev. 1.1
S1F75520 Series
The tone voltages VREF1 and VREF2 output voltages are generated.
The VREF1 output voltage outputs antiphase square waves as the polarity reversal input pin (POL). The VREF2
output voltage outputs synchronous square waves as the polarity reversal input pin (POL). The output voltage
outputs the voltages between VSCE and VSS. It reaches the VSS level when XSLPX=VSS.
[Input pin]
V
DD
PCK
XSLPY
POL
[Output pin]
VSCE
V
SCE
V
V
REF1
REF2
V
SS=0V
SCE
V
V
SS=0V
Fig. 14 Timing for VREF1 and VREF2 Pins
Rev. 1.1
23
S1F75520 Series
ꢀGate Driver Voltage Regulator
The gate output positive and negative power supply voltage to the gate driver is generated by this regulator and
the secondary and tertiary booster circuits. It boosts to positive from the secondary booster circuit based on the
output voltage of this regulator and generates VGON output voltage. It also boosts to negative from the tertiary
booster circuit based on the output voltage of this regulator and generates VGOFF output voltage.
The output voltage for this regulator is VRGP=3.3V(Typ.). By adding external resistors, the voltage can be set
within 3.3V to 5V. The following is a typical connection when external resistors is added.
Inside S1F75520
Inside S1F75520
V
P
V
RGP
RPB
RVP
V
REF35 = 3.3V(Typ.)
(Note 1)
RPA
V
SS2
(Note 1) Try to avoid noise for the high impedance RVS pin.
Fig. 15 Gate Driver Voltage Regulator
The VRGP output voltage can be determined using the following equation.
RPB
VRGP=
+
× VREF33
(Equation 3)
1
(
)
RPA
However, RPA, RPB : external resistor
VREF33
: reference voltage inside the IC
VREF33 generates VREF33=3.3V(Typ.) with a reference voltage inside the IC.
The voltage regulator uses the VP output voltage of the primary booster circuit as the input power supply
voltage. Boosting for the primary booster circuit must be set so that the VP output voltage is 0.4V or more
higher than the VRGP output voltage.
As shown in (equation 3), the desired output voltage can be generated by adjusting the ratio of the RPA and
RPB external resistors. If external resistors are used, set the value so that the current for the external resistors
is 5µA or higher.
A specific resistance value setup can be made using the same method of calculation as for the source driver
voltage regulator. Also, by adding an external thermistor and other devices, a temperature gradient can be
added to the VRGP output voltage.
24
Rev. 1.1
S1F75520 Series
ꢀSecondary and Tertiary Booster Circuits
These are the positive and negative output booster circuits configured from the charging pump type DC/DC
converters.
The secondary booster circuit boosts the gate driver voltage regulator VRGP output voltage 2-, 3-, or 4-times to
positive.
The tertiary booster circuit boosts the VRGP output voltage –2-, –3-, or –4-times. The boosting relationship
between the secondary and tertiary booster circuits is as shown in the following diagram.
V
GON
Secondary booster
circuit
VEP2
V
RGP
V
SS=0V
Tertiary booster circuit
V
GOFF
Fig. 16 Boosting Relationship Between the Secondary and Tertiary Booster Circuits
The theoretical equations for each potential are as follows:
Table 5 Theoretical Equations of Each Potential
Signal name Theoretical equation (VSS=0V reference)
VGON
VEP2
(VRGP–VSS)×N2, however, N2=2 or 3 or 4
(VRGP–VSS)×2
VGOFF
(VRGP–VSS)×N3, however, N3=–2 or –3 or –4
Boosting for the secondary and tertiary booster circuits can be set up independently. Setup for both the sec-
ondary and tertiary booster circuits is made via external wiring.
When setting the voltage for the VRGP output voltage and boosting for the tertiary booster circuit, set the voltage
of the VOFF output voltage so that the potential becomes –15V or higher based on VSS=0V, that is, set up so
that the following equation is satisfied.
VGOFF – VSS = VGOFF ≥ –15
(Equation 4)
Rev. 1.1
25
S1F75520 Series
The method of setting up for the secondary booster circuit boosting is as shown in Fig. 17 to 19, and that for
tertiary booster circuit boosting is as shown in Fig. 20 to 22.
V
RGP
CY1P
CY1N
CY2P
CY2N
CY1N
CY2N
CZ1N
CZ2N
VZ2P
CPY1
CPY2
V
GON=(VRGP–VSS) × 4
V
SS=0V
CPZ1
CPZ2
VSS2
VEP2
VGON
CBY1
CBON
CBOFF
VRGP
V
V
GOFF
SS2
VSS=0V
V
GOFF=(VRGP–VSS) × (–4)
V
SS
VSS
Fig. 17 4-times Boosting Mode (N2=4)
Fig. 20 –4-times Boosting Mode (N2=–4)
V
RGP
CY1P
CY1N
CY2P
CY2N
CY1N
CY2N
CZ1N
CZ2N
VZ2P
CPY1
CPY2
V
SS=0V
CPZ1
CPZ2
V
GON=(VRGP–VSS) × 3
VSS2
VEP2
VGON
CBY1
CBON
CBOFF
V
RGP
V
V
GOFF
SS2
V
GOFF=(VRGP–VSS) × (–3)
V
SS=0V
V
SS
VSS
Fig. 18 3-times Boosting Mode (N2=3)
Fig. 21 –3-times Boosting Mode (N2=–3)
V
RGP
CY1P
CY1N
CY2P
CY2N
CY1N
CY2N
CZ1N
CZ2N
VZ2P
CPY1
V
SS=0V
CPZ1
V
RGP=(VRGP–VSS) × 2
V
GOFF=(VRGP–VSS) × (–2)
V
V
V
SS2
EP2
GON
CBY1
CBOFF
V
RGP
V
V
GOFF
SS2
V
SS=0V
V
SS
V
SS
Fig. 19 2-times Boosting Mode (N2=2)
Fig. 22 –2-times Boosting Mode (N2=–2)
Rev. 1.1
26
S1F75520 Series
ꢀVCOM Output Voltage Generator Circuit
This generates a counter-voltage VCOM output voltage, and outputs synchronous square waves to the POL
polarity input signal. The VCOM amplitude voltage Vswing can be set within 3.0 to 5.5V. The central voltage
Vcenter can be set within 0.0 to 2.5V based on VSS=0V. Both voltages can be adjusted by the analog input
signal. Also, the VCOM central voltage can be controlled by the digital input signal.
VDD
POL input signal
VSS=0V
VCOMH
Vswing
Vcenter
VCOM output voltage
VCOML
Fig. 23 VCOM Output Voltage
Digital control mode or analog control mode can be selected for the VCOM central voltage by using the VCOM
central voltage adjustment selection pin.
Table 6 SEVCOM Pin Functions
SEVCOM
Function
VSS
Digital control mode.
Controls the VCOM central voltage via the digital input signal.
The resolution is 6 bits (BDATA, BCK, XBCS).
Analog control mode.
VDD
Controls the VCOM central voltage via the analog input signal
(VCENT).
When in digital control mode (SEVCOM=VSS), a 3-lined serial input (BDATA, BCK, XBCS) controls the VCOM
central voltage.
BDATA
BCK
S4
S1
S0
S5
S3
S2
1
2
3
4
5
6
XBCS
BCK input signal validity period
Fig. 24 BDATA BCK XBCS Timing
Rev. 1.1
27
S1F75520 Series
Serial data BDATA is input from the most significant bit. The BDATA serial data from the falling edge of the
XBCS signal to the first 6 BCK input signals are received and read at the rising edge of the BCK input signal.
The VCOM central voltage is set at the 6th rising edge timing of the BCK input signal. When the XBCS signal
becomes HIGH before the 6th BCK input signal is entered, the setup data up to the 5th BDATA becomes
invalid.
The relationship between the BDATA serial data and the VCOM central voltage Vcenter(Typ. value) is as shown
in the following equation based on VSS=0V.
Vcenter = 0.0397 × α [V]
(Equation 5)
However, α represents the electronic volume which is a variable con-
verted from a binary digit data S5 to S0 to a decimal digit data. It is one
of the α=0 to 63 and has the following relational expression.
α = 32 × S5 + 16 × S4 + 8 × S3 +4 × S2 + 2 × S1 + S0
(Equation 6)
The VCOM register is reset when XSLPX=XSLPY=XOFFCM=VSS, and the electronic volume becomes α=0.
In the analog control mode (SEVCOM=VDD), it is controlled from the VCENT analog input pin. By setting the
voltage to the VCENT input pin within 1.5 to 2.5V(VSS=0V reference), the VCOM central voltage can be set within
Vcenter= 0.0 to 2.5V(VSS=0V reference).
V
COM
V
CENT
Vcenter
1.5 to 2.5V
0.0 to 2.5V
V
SS=0V
Fig. 25 The Relationship Between VCENT and Vcenter
The relationship between the VCENT input voltage and the VCOM central voltage Vcenter (Typ. value) is as
shown in the following equation.
Vcenter = VCENT × 2.5 – 3.75 [V]
(Equation 7)
The analog input voltage to the VCENT pin can be set by connecting ladder resister to the 3.5V regulator output
pins V35 and VSS and dividing the voltages.
28
Rev. 1.1
S1F75520 Series
V35
RCEB
VCENT
RCEA
V
VSS2
SS=0V
Fig. 26 VCENT Setup
The VCOM amplitude voltage is controlled by the VSWIN analog input pin. By setting the voltage to the VSWIN
input pin within 1.5 to 2.75V (VSS=0V reference), the VCOM amplitude voltage can be set within Vswing=3.0 to
5.5V.
VCOM
VCOMH
VSWIN
Vswing
=3.0 to 5.5V
1.5 to 2.75V
VSS=0V
VCOML
Fig. 27 The Relationship between VSWIN and Vswing
The relationship between the VSWIN input voltage and the VCOM amplitude voltage Vswing (Typ. value) is as
shown in the following equation.
Vswing = VSWIN × 2 [V]
(Equation 8)
The analog input voltage to the VSWIN pin can be set by connecting a ladder resister to the 3.5V regulator output
pins V35 and VSS and dividing the voltages.
V35
RSWB
VSWIN
RSWA
VSS2
V
SS=0V
Fig. 28 VSWIN setup
Rev. 1.1
29
S1F75520 Series
Changing the VCOM output off pin XOFFCM to the VSS level turns off the VCOM output generator circuit. Since
the VCOM output voltage generator circuit operates between the positive and negative output voltage of the
primary booster circuit, the VCOM potential has the following relationship with the XSLPX and XSLPY sleep pins
when off.
Table 7 XOFFCM Pin Functions
XOFFCM
XSLPY
XSLPX
VSS
VCOM potential (VSS=0V reference)
VCOM = VSS
VSS
VSS
VDD
VSS
VCOM = (VSCE–VSS)/2
VCOM = VSS
VDD
VSS
VDD
VDD
VSS
VCOM = (VSCE–VSS)/2
VCOM = VSS
VDD
VDD
VSS
VCOM output voltage generator
circuit is operating.
VDD
In order to generate VCOM output voltage, the S1F75520 series IC generates VCOMH and VCOML output volt-
ages as auxiliary power. The VCOMH and the VCOML output voltages can be expressed as follows:
Vcenter + Vswing
VCOMH =
(Equation 9)
2
= VCENT × 2.5 – 3.75 + VSWIN
Vcenter – Vswing
VCOML =
(Equation 10)
2
= VCENT × 2.5 – 3.75 – VSWIN
30
Rev. 1.1
S1F75520 Series
The amplitude relationship is as shown in the following diagram.
6
5.25V
2.75V
4.0V
4
V
COMH
Vcenter=2.5V
2
1.5V
1.0V
V
SS=0
Vcenter=0.0V
–0.25V
–2.75V
–1.5V
–2
–4
V
COML
0
3
4
5
6
Vswing[V]
Fig. 28 The Relationship between VCOMH, VCOML and Vcenter, Vswing
The VP and VN output voltages of the primary booster circuit are used as the input power supply voltage of the
VCOM output generator circuit. Set boosting for the primary booster circuit so that the following equations hold
true.
VCOMH + 0.4 < VP
(Equation 11)
(Equation 12)
VCOML – 0.4 > VN
Rev. 1.1
31
S1F75520 Series
ꢀLogic Power Supply Voltage Regulator
This is the voltage regulator for the logic power supply, which outputs 1.5 to 1.8V as an external power supply
to LCD controllers and other devices other than this IC.
Outside S1F75520
Inside S1F75520
VDD1
V18
VREF18
=1.5 to 1.8V
VSS1
Fig. 29 Logic Power Supply Voltage Regulator
The SEVTG1 and SEVTG0 output voltage conversion pins set the output voltage.
Table 8 SEVTG1 and SEVTG0 Pin Functions
SEVTG1
SEVTG0
VSS
V18 output voltage (VSS=0V reference)
Outputs V18=1.8V.
VSS
VDD
Outputs V18=1.7V.
VDD
VSS
Outputs V18=1.6V.
VDD
Outputs V18=1.5V.
The SEVTG2 drive power conversion pin converts the maximum load current and can be set to an appropriate
circuit configuration according to the load current.
Table 9 SEVTG2 Pin Functions
SEVTG2
VSS
Normal load current mode. A maximum load current of 10mA
may be applied (during 1.8V output).
VDD
Large load current mode. A maximum load current of 40mA
may be applied (during 1.8V output).
When the XOFFCM logic power supply voltage regulator sleep pin is changed to VSS level, the logic power
supply voltage regulator is turned off, and the residual charge in the V18 pin is discharged to VSS.
32
Rev. 1.1
S1F75520 Series
ꢀPower On Sequence
An example of sequence during power on is as shown in the following diagram. Control is necessary depend-
ing on the specifications of the TFT panel and the driver being used.
[Input pin]
VDD
VSS=0V
PCK
XSLPY
XSLPX
XOFFCM
POL
[Output pin]
V18
VSS=0V
VGON
V
SS=0V
SS=0V
V
V
GOFF
SCE
V
V
SS=0V
SS=0V
V
COM
REF1
V
V
V
SS=0V
SS=0V
VREF2
V
1
2
3
4
5
6
7
1 Power is supplied from the system power supply IC to the S1F75520 power supply IC.
2 The logic power supply voltage regulator is turned on.
3 The booster clock PCK is entered.
4 The gate driver positive and negative power supply voltages VGON and VGOF rise.
5 The source driver positive power supply VSCE rises.
6 The VCOM output voltage outputs the voltage corresponding to the voltage level of the POL polarity rever-
sal signal .
7 The VCOM, VREF1 and VREF2 outputs are reversed, to synchronize them with the POL polarity reversal signal.
Rev. 1.1
33
S1F75520 Series
ꢀPower Off Sequence
An example of sequence during power off is as shown in the following diagram. Control is necessary depend-
ing on the specifications of the TFT panel and the driver used.
[Input pin]
VDD
VSS=0V
PCK
XSLPY
XSLPX
XOFFCM
POL
[Output pin]
V18
VSS=0V
VGON
V
SS=0V
SS=0V
V
VGOFF
VSCE
V
SS=0V
SS=0V
VCOM
V
V
REF1
REF2
V
SS=0V
SS=0V
V
V
1
2
3
4
5
6
7
1 The VCOM, VREF1 and VREF2 outputs are reversed, to synchronize them with the POL polarity reversal signal.
2 The VCOM output voltage is turned off, and the output voltage outputs a voltage of VSCE/2.
3 The source driver positive power supply VSCE output voltage is turned off and a VSS level voltage is output.
4 The gate driver positive and negative power supplies VGON and VGOFF are turned off and a VSS level
voltage is output.
5 The booster clock PCK stops.
6 Power supplied from the system power supply IC to the S1F75520 power supply IC is turned off.
7 The logic power supply voltage regulator is turned off.
34
Rev. 1.1
S1F75520 Series
ꢀ ABSOLUTE MAXIMUM RATINGS
Rating
Item
Symbol
Min.
–0.3
–0.3
–0.3
—
Max.
4.0
Unit
V
Applicable Pin
Condition
Input power supply
voltage
VDD
VDD1, VDD2
VDD1, VDD2
<Note 3>
VDD1, VDD2
VGON
<Note 1>
5.0
V
<Note 2>
Input pin voltage
Input current
VIN
IDD
VDD+0.3
70
V
—
mA
V
—
Output voltage 1
Output voltage 2
Output voltage 3
Output voltage 4
Output current 1
Output current 2
Output current 3
Output current 4
Output current 5
Output current 6
Output current 7
Allowable loss 1
VGON
VGOFF
VSCE
VRGP
IVGON
IVGOFF
IVSCE
IV18
–0.3
–16.8
–0.3
–0.3
—
22.4
0.3
7.0
7.0
0.5
0.5
10
—
V
VGOFF
—
V
VSCE
—
V
VRGP
—
mA
mA
mA
mA
mA
mA
mA
mW
VGON
—
—
VGOFF
—
—
VSCE
—
—
—
50
V18
IVCOM
IV35
—
1
VCOM
—
—
1
V35
—
IVREF
Pd1
—
1.5
180
VREF1, VREF2
—
—
—
Ta≤55˚C
TQFP12–48
Ta≤55˚C
QFN–48
—
Allowable loss 2
Pd2
—
180
mW
—
Operating temperature
Storage temperature
Soldering temperature and time
Topr
Tstg
Tsol
–30
–55
85
˚C
˚C
—
—
—
150
—
260 · 10 ˚C · s
at lead
<Note 1> Primary booster circuit Boosting of the VP output voltage is 2-times.
<Note 2> Primary booster circuit Boosting of the VP output voltage is 1.5-times.
<Note 3> The applicable pins are PCK, MODE, CNT, XSLPX, XSLPY, XOFF18, SEVTG2 to 0, XOFFCM, POL,
SEVCOM, BDATA, BCK, XBCS, VCENT, VSWIN, and PSAVE1 to 0.
<Note 4> Do not apply external voltage to the output pins and the capacitor connection pins.
<Note 5> Usage outside the absolute maximum rating conditions may cause malfunction or permanent
damage. Moreover, even though the IC operates normally temporarily, reliability may be significantly
decreased.
Rev. 1.1
35
S1F75520 Series
ꢀ ELECTRICAL CHARACTERISTICS
ꢀDC Characteristics
Unless otherwise specified: Ta=–30 to +85˚C <Note 1>
VSS=0V
Characteristics
Item
Symbol
VDD
VIH
Conditions
Min.
2.7
Typ.
3.0
—
Max. Unit Notes
Input power supply voltage
High level input voltage
Low level input voltage
Input leak current
Applicable pins:VDD1, VDD2
3.6
VDD
0.2VDD
0.5
V
—
2
—
0.8VDD
0
V
VIL
—
—
V
2
IILN1
IIH
VSS≤VI≤VDD, VDD=1.7 to 3.6V
VI=VDD, VDD=3.6V
VI=VSS, VDD=3.6V
—
–0.5
—
—
µA
µA
µA
µA
µA
3
High level input leak current
Low level input leak current
Self current consumption
Static current
—
10
4
IIL
–10
—
—
—
5
IOP
160
—
300
5
6
IQ
XSLPX=XSLPY=XOFF18
=XOFFCM=VSS
R=1MΩ
—
—
Oscillator frequency
fosc
16
22
28
3
kHz
—
—
OSC2 output impedance
Rosc2
—
—
—
kΩ
<Note 1> The operation mode and pin setups are as follows when not specified.
Connection conditions: Refer to "ꢀ EXTERNAL CONNECTION (EXAMPLES)" for standard connections.
Booster clock: PCK input. MODE pin is open (pull-down).
PCK frequency: 20kHz
Primary booster circuit, positive (VP output voltage): 2-times boosting mode. CNT pin is open (pull-up).
Primary booster circuit, negative (VN output voltage): –1-times boosting mode.
VSCE output voltage: External resistor RSA=700kΩ, RSB=270kΩ (4.85V output).
VRGP output voltage: RVP=VRGP connection (3.3V output)
Secondary booster circuit: 4-times boosting mode.
Tertiary booster circuit: –4-times boosting mode.
VCOM central voltage control method: analog control mode. SEVCOM pin is open (pull-up).
VCOM central voltage: RCEA=300kΩ, RCEB=400kΩ (Vcenter=0.0V).
VCOM amplitude voltage: RSWA=RSWB=330kΩ (Vswing=3.5V).
VCOM output voltage generator circuit operation mode: Low consumption is prioritized. PSAVE1 and
PSAVE0 pins are open (pull-down).
Logic power supply voltage regulator: outputs 1.8V. XOFF18 pin is open (pull-up).
SEVTG2-SEVTG0 pins are open (pull-down).
Polarity determination input pin: POL=VSS.
"VDD" in this manual implies the potential of "VDD1=VDD2".
<Note 2> The applicable pins are SEVCOM, BDATA, BCK, XBCS, POL, PSAVE1, PSAVE0, XOFFCM,
XSLPX, XSLPY, MODE, CNT, PCK, XOFF18 and SEVTG2 to 0.
<Note 3> The applicable pins are POL, XSLPX, XSLPY, PCK, VSWIN and VCENT.
<Note 4> The applicable pins are BDATA, BCK, PSAVE1, PSAVE0, MODE and SEVTG2 to 0
(with pull-down digital input pins).
<Note 5> The applicable pins are SEVCOM, XBCS, XOFFCM, CNT and XOFF18
(with pull-up digital input pins).
<Note 6> The load condition is "no load".
36
Rev. 1.1
S1F75520 Series
ꢀPrimary Booster Circuit Characteristics
Unless otherwise specified: Ta=–30 to +85˚C, VSS=0V
Characteristics
Item
Symbol
Conditions
Applicable pin: VP, IO=5mA,
VDD=2.7V
Min.
Typ.
Max. Unit Notes
VP output impedance
(1.5-times boosting)
VP output impedance
(2-times boosting)
VN output impedance
(–1-times boosting)
VN output impedance
(–1.5-times boosting)
VN output impedance
(–2-times boosting)
RVP1
—
—
165
170
285
410
470
Ω
Ω
Ω
Ω
Ω
1
1
2
3
2
RVP2
RVN1
RVN2
RVN3
Applicable pin: VP, IO=5mA,
VDD=2.7V
—
—
—
—
—
—
—
—
Applicable pin: VN, IO=1mA,
VDD=2.7V
Applicable pin: VN, IO=1mA,
VDD=2.7V
Applicable pin: VN, IO=1mA,
VDD=2.7V
<Note 1> The conditions are as follows:
Primary booster circuit, negative (VN output voltage): –1-times boosting mode
Pin setup: XOFFCM=VSS, XSLPX=VDD, XSLPY=VSS
<Note 2> The conditions are as follows:
Primary booster circuit, positive (VP output voltage): 2-times boosting mode
Pin setup: XOFFCM=VSS, XSLPX=VDD, XSLPY=VSS
Conditions not specified conforms to <Note 1> of "ꢀ DC Characteristics".
ꢀSecondary and Tertiary Booster Circuit Characteristics
Unless otherwise specified: Ta=–30 to +85˚C, VSS=0V
Characteristics
Item
Symbol
Conditions
Min.
Typ.
Max. Unit Notes
VGON output impedance
(2-times boosting)
RGON2 Applicable pin: VGON, IO=50µA,
VDD=2.7V
—
—
6.5
14
35
14
18
38
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
1
1
1
2
2
2
VGON output impedance
(3-times boosting)
RGON3 Applicable pin: VGON, IO=50µA,
VDD=2.7V
—
—
—
—
—
—
—
—
—
—
VGON output impedance
(4-times boosting)
RGON4 Applicable pin: VGON, IO=50µA,
VDD=2.7V
VGOFF output impedance RGOFF2 Applicable pin: VGOFF, IO=50µA,
(–2-times boosting) VDD=2.7V
VGOFF output impedance RGOFF3 Applicable pin: VGOFF, IO=50µA,
(–3-times boosting) VDD=2.7V
VGOFF output impedance RGOFF4 Applicable pin: VGOFF, IO=50µA,
(–4-times boosting) VDD=2.7V
<Note 1> The conditions are as follows:
Tertiary booster circuit (VGOFF output voltage): –2-times boosting mode
Pin setup: XOFFCM=VSS, XSLPX=VSS, XSLPY=VDD
<Note 2> The conditions are as follows:
Secondary booster circuit (VGON output voltage): 2-times boosting mode
Pin setup: XOFFCM=VSS, XSLPX=VSS, XSLPY=VDD
Rev. 1.1
37
S1F75520 Series
ꢀDC Source Driver Voltage Regulator Characteristics
Unless otherwise specified: Ta= 25˚C <Note 1>
VSS=0V
Characteristics
Min. Typ.
Item
Symbol
Conditions
Max. Unit Notes
VSCE output voltage
VSCE(E) Applicable pins: VSCE, VP=5.4V, VSCE(S) VSCE(S) VSCE(S)
V
2
VSCE(S)=3.5V, IO=1mA
VSCE(S)=3.5V
×0.98
2.5
5
×1.02
—
VSCE output current 1
VSCE output current 2
VSCE input and output
voltage difference 1
VSCE input and output
voltage difference 2
VSCE input stability 1
ISCE1
ISCE2
—
—
mA 2,3
mA 2,3
VSCE(S)=4.85V
—
VPSCE1 VSCE(S)=3.5V, IO=2.5mA
—
0.3
0.4
V
2,4
2,4
2
VPSCE2 VSCE(S)=4.85V, IO=5mA
—
—
0.3
4
0.4
10
10
10
10
10
10
350
50
50
V
∆VSCE1 4.0V≤VP≤7.2V, IO=1µA,
VSCE(S)=3.5V
mV
mV
mV
mV
mV
mV
VSCE input stability 2
VSCE input stability 3
VSCE input stability 4
VSCE load stability 1
VSCE load stability 2
∆VSCE2 4.0V≤VP≤7.2V, IO=2.5mA,
VSCE(S)=3.5V
—
4
2
∆VSCE3 5.4V≤VP≤7.2V, IO=1µA,
VSCE(S)=4.85V
—
4
2
∆VSCE4 5.4V≤VP≤7.2V, IO=5mA,
VSCE(S)=4.85V
—
4
2
∆VSCE5 VP=5.4V, IO=1µA to 2.5mA,
VSCE(S)=3.5V
—
5
2
∆VSCE6 VP=5.4V, IO=1µA to 5mA,
VSCE(S)=4.85V
—
5
2
VSCE Output voltage
TFSCE VP=5.4V, IO=1mA,
–30˚C to +85˚C, VSCE(S)=3.5V
RVREF1 VP=4.0V, IO=1µA to 1mA,
VSCE(S)=3.5V
–50
—
—
—
—
ppm 2,5
temperature coefficient
VREF1 output impedance
/˚C
Ω
Ω
2
2
VREF2 output impedance
RVREF2 VP=4.0V, IO=1µA to 1mA,
VSCE(S)=3.5V
—
<Note 1> The operation conditions are as follows:
Pin setup: XOFFCM=VSS, XSLPX=VDD, XSLPY=VSS, PCK=VSS.
Apply external power supply to VP pin.
Conditions not specified conforms to <Note 1> of "ꢀ DC Characteristics".
<Note 2> VSCE (E): actual output voltage.
VSCE(S)=3.5V:RVS=VSCE connection.
VSCE(S)=4.85V:RSA=700kΩ, RSB=270kΩ.
<Note 3> The output current when it is gradually increased and when the output voltage drops below 95% of
the VSCE(E).
<Note 4> VPSCE=VP–VSCE(E) × 0.98. The input current when it is gradually decreased and when the output
voltage drops to 98% of the VSCE(E).
<Note 5> The temperature difference [mV/˚C] of the output voltage is calculated using the following equation:
∆VSCE
VSCE(S) [V] × TFSCE [ppm/˚C]
[mV/˚C]
=
∆Ta
1000
(The temperature change of (The set output voltage) (The output voltage temperature
the output voltage)
coefficient shown above)
38
Rev. 1.1
S1F75520 Series
ꢀGate Driver Voltage Regulator Characteristics
Unless otherwise specified: Ta= 25˚C <Note 1>
VSS=0V
Characteristics
Item
Symbol
Conditions
Min.
Typ.
Max. Unit Notes
VRGP output voltage
VRGP(E) Applicable pins: VRGP, VP=5.4V, VRGP(S) VRGP(S) VRGP(S)
V
2
VRGP(S)=3.3V, IO=0.1mA
VRGP(S)=3.3V
×0.98
0.5
1
×1.02
—
VRGP output current 1
VRGP output current 2
VRGP input and output
voltage difference 1
VRGP input and output
voltage difference 2
VRGP input stability 1
ISCE1
ISCE2
—
—
mA 2,3
mA 2,3
VRGP(S)=4.43V
—
VPRGP1 VRGP(S)=3.3V, IO=0.5mA
—
0.2
0.4
V
2,4
2,4
2
VPRGP2 VRGP(S)=3.3V, IO=0.5mA
—
—
0.2
4
0.4
10
V
∆VRGP1 4.0V≤VP≤7.2V, IO=1µA,
VRGP(S)=3.3V
mV
mV
mV
mV
mV
mV
VRGP input stability 2
VRGP input stability 3
VRGP input stability 4
VRGP load stability 1
VRGP load stability 2
∆VRGP2 4.0V≤VP≤7.2V, IO=0.5mA,
VRGP(S)=3.3V
—
4
10
2
∆VRGP3 5.4V≤VP≤7.2V, IO=1µA,
VRGP(S)=4.43V
—
4
10
2
∆VRGP4 5.4V≤VP≤7.2V, IO=0.5mA,
VRGP(S)=4.43V
—
4
10
2
∆VRGP5 VP=5.4V, IO=1µA to 0.5mA,
VRGP(S)=3.3V
—
4
10
2
∆VRGP6 VP=5.4V, IO=1µA to 1mA,
VRGP(S)=4.43V
—
4
10
2
VRGP Output voltage
temperature coefficient
TFRGP VP=5.4V, IO=0.1mA,
–30˚C to +85˚C, VRGP(S)=3.3V
–50
—
350
ppm 2,5
/˚C
<Note 1> The operation conditions are as follows:
Pin setup: XOFFCM=VSS, XSLPX=VSS, XSLPY=VDD, PCK=VSS.
Apply external power supply to VP pin.
Conditions not specified conforms to <Note 1> of "ꢀ DC Characteristics".
<Note 2> VRGP (E): actual output voltage.
VRGP(S)=3.3V:RVP=VRGP connection.
VRGP(S)=4.43V:RPA=700kΩ, RPB=240kΩ.
<Note 3> The output current when it is gradually increased and when the output voltage drops below 95% of
the VRGP(E).
<Note 4> VPRGP=VP–VRGP(E) × 0.98. The input current when it is gradually decreased and when the output
voltage drops to 98% of the VRGP(E).
<Note 5> The temperature difference [mV/˚C] of the output voltage is calculated using the following equation:
∆VRGP
∆Ta
VRGP(S) [V] × TFRGP [ppm/˚C]
[mV/˚C]
=
1000
(The temperature change of (The set output voltage) (The output voltage temperature
the output voltage) coefficient shown above)
Rev. 1.1
39
S1F75520 Series
ꢀVCOM Output Voltage Generator Circuit Characteristics
Unless otherwise specified: Ta= 25˚C <Note 1>
VSS=0V
Characteristics
Item
Symbol
VCOM1 Applicable pins: VCOM, POL=VDD
IO=10µA (outlet)
Conditions
Min.
Typ.
Max. Unit Notes
VCOM output voltage 1
,
2.55
–2.95
2.55
2.75
2.95
–2.55
2.95
V
V
V
V
2
2
3
3
VCOM output voltage 2
VCOM output voltage 3
VCOM output voltage 4
VCOM2 Applicable pins: VCOM, PLL=VSS
,
–2.75
2.75
–2.75
—
IO=10µA (intake)
VCOM3 Applicable pins: VCOM, POL=VDD
,
IO=10µA (outlet)
VCOM4 Applicable pins: VCOM, PLL=VSS
,
–2.95
–50
–2.55
100
IO=10µA (intake)
VCOM Output voltage
TFCOM1 Applicable pins: VCOM, POL=VDD
,
ppm 3,4
temperature coefficient 1
IO=10µA (outlet)
/˚C
Ta=–30 to +85˚C
VCOM Output voltage
TFCOM1 Applicable pins: VCOM, PLL=VSS
,
–200
—
—
—
—
—
50
50
ppm 3,4
temperature coefficient 2
IO=10µA (intake)
Ta=–30 to +85˚C
/˚C
VCOM output impedance 1 RCOM1 Applicable pins: VCOM, POL=VDD
,
Ω
Ω
2
2
IO=1mA (outlet)
Ta=–30 to +85˚C
VCOM output impedance 2 RCOM2 Applicable pins: VCOM, POL=VSS
,
—
IO=1mA (intake)
Ta=–30 to +85˚C
Electronic volume
EFS
ELI
Applicable pins: VCOM, POL=VDD
,
–3
–1
—
—
—
3
1
5
5
5
Full scale tolerance
Electronic volume
IO=10µA (outlet)
Applicable pins: VCOM, POL=VDD
,
Linear tolerance
IO=10µA (outlet)
Electronic volume
EdLI
Applicable pins: VCOM, POL=VDD
,
–0.5
0.5
Differential linear tolerance
V35 output voltage
V35 output voltage
temperature coefficient
IO=10µA (outlet)
V35(E) Applicable pins: V35, IO=10µA, 3.43
3.50
3.57
350
V
—
TFV35 Applicable pins: V35, IO=10µA,
Ta=–30 to +85˚C
–50
—
ppm
/˚C
6
<Note 1> The operation conditions are as follows:
Pin setup: XOFFCM=VDD, XSLPX=VDD, XSLPY=VDD, PCK=VSS.
Apply external power supply to the VP pin and the VN pin. VP=6.0V, VN=–4.5V.
Conditions not specified conforms to <Note 1> of "ꢀ DC Characteristics".
<Note 2> The operation conditions are as follows:
SEVCOM=VDD, VCENT=1.5V, VSWIN=2.75V
(Vcenter= 0.0V, Vswing=5.5V)
<Note 3> The operation conditions are as follows:
SEVCOM=VSS, Electronic volume α=0V, VSWIN=2.75V.
40
Rev. 1.1
S1F75520 Series
<Note 4> The temperature difference [mV/˚C] of the output voltage is calculated using the following equation:
∆VCOM
∆Ta
VCOM(S) [V] × TFCOM [ppm/˚C]
[mV/˚C]
=
1000
(The temperature change of (The set output voltage) (The output voltage temperature
the output voltage)
coefficient shown above)
<Note 5> The operation conditions are as follows:
SEVCOM=VSS, VSWIN=2.75V (Vswing=5.5V)
The definitions of the tolerance are as follows.
VCOM(α=63)
Full scale tolerance: EFS=a
a
Ideal curve
Deviance from the ideal value of the full scale point
Linear tolerance: ELI=b
The difference between the endpoint line and the ac-
tual conversion curve
b
Actual conversion curve
Endpoint line
63
Differential linear tolerance:
(VI–VS)
VCOM(α=0)
EdLI=
VS
0
Electronic volume α
VS : Ideal width (1 LSB equivalent), VS=0.0397V
VI : Actual width, VI =VRG(α=I +1) – VRG(α=I)
I = 0 to 63
Fig. 30 Definition of the Electronic Volume Tolerance
<Note 6> The temperature difference [mV/˚C] of the output voltage is calculated using the following equation:
∆V35
∆Ta
V35(S) [V] × TFV35 [ppm/˚C]
[mV/˚C]
=
1000
(The temperature change of (The set output voltage) (The output voltage temperature
the output voltage)
coefficient shown above)
Rev. 1.1
41
S1F75520 Series
ꢀLogic Power Supply Voltage Regulator Characteristics
Unless otherwise specified: Ta= 25˚C <Note 1>
VDD1=VDD2=2.7V, VSS=0V
Characteristics
Min. Typ. Max. Unit Notes
V18(E) Applicable pins:V18, IO=1mA, V18(S) V18(S) V18(S)
Item
Symbol
Conditions
V18 output voltage
V
2
×0.97
10
×1.03
—
V18 output current 1
V18 output current 2
V18 input stability 1
IV181 SEVTG2=VSS
IV182 SEVTG2=VDD
∆V181 2.7≤VDD≤3.6V, IO=1µA,
SEVTG2=VSS
—
—
10
mA 2,3
mA 2,3
40
—
—
20
mV
mV
mV
mV
—
—
—
—
V18 input stability 2
V18 input stability 3
V18 input stability 4
∆V182 2.7≤VDD≤3.6V, IO=1µA,
SEVTG2=VDD
—
—
—
10
10
10
20
20
20
∆V183 2.7≤VDD≤3.6V, IO=1mA,
SEVTG2=VSS
∆V184 2.7≤VDD≤3.6V, IO=1mA,
SEVTG2=VDD
V18 load stability 1
V18 load stability 2
V18 Output voltage
temperature coefficient
∆V185
∆V186
I
O
=1µA to 10mA, SEVTG2=VSS
=1µA to 40mA, SEVTG2=VDD
—
—
12
40
—
15
50
mV
mV
ppm
/˚C
—
—
4
IO
TFV18 IO=1mA, –30˚C to +85˚C
–50
350
<Note 1> The operation conditions are as follows:
Pin setup: XOFF18=VDD, XOFFCM=VSS, XSLPX=VSS, XSLPY=VSS.
Setup SEVTG1 and SEVTG0 as desired.
Conditions not specified conforms to <Note 1> of "ꢀ DC Characteristics".
<Note 2> V18(E): actual output voltage. V18(S): set output voltage value
<Note 3> The output current when it is gradually increased and when the output voltage drops below 95% of
the V18(E).
<Note 4> The temperature difference [mV/˚C] of the output voltage is calculated using the following equation:
∆V18
∆Ta
V18(S) [V] × TFV18 [ppm/˚C]
[mV/˚C]
=
1000
(The temperature change of (The set output voltage) (The output voltage temperature
the output voltage)
coefficient shown above)
42
Rev. 1.1
S1F75520 Series
ꢀAC Characteristics
Measurement conditions of AC characteristics
• Input signal level
VIH=0.8VDD V
VIL=0.2VDD V
• Input signal rise time
• Input signal fall time
Tr=Max. 10ns
Tf=Max. 10ns
VDD1=VDD2=2.7 to 3.6V
Ta = –30 to +85˚C
(1) PCK input timing
t
WHPCK
VIH
VIH
VIH
PCK
VIL
VIL
t
WLPCK
t
CPCK
Item
Symbol
Characteristics
Unit Applicable Condition
Pin
Min.
25
Typ.
73
Max.
250
—
PCK cycle
tCPCK
tWHPCK
tWHPCK
µs
ns
ns
PCK
—
—
—
PCK HIGH pulse width
PCK LOW pulse width
100
100
—
—
—
(2) Electronic volume set input timing
V
IL
XSLPX
XSLPY
V
IL
t
WSLPX
V
IL
VIL
t
WSLPY
XOFFCM
V
IL
VIL
t
WOFFCM
Item
Symbol
Characteristics
Unit Applicable Condition
Pin
Min.
100
100
100
Typ.
—
Max.
—
XSLPX pulse width
XSLPY pulse width
XOFFCM pulse width
tWSLPX
tWSLPY
tWOFFCM
ns
ns
ns
XSLPX
XSLPY
—
—
—
—
—
—
—
XOFFCM
Rev. 1.1
43
S1F75520 Series
(3) BCK input timing
V
IH
VIH
BDATA
VALID
V
IL
VIL
t
DH
t
DS
t
WHBCK
V
IH
V
IH
VIH
BCK
V
IL
V
IL
V
IL
t
WLBCK
t
BCSH
t
BCSS
t
CBCK
V
IH
XBCS
V
IL
VIL
Item
BCK cycle
Symbol
Characteristics
Unit Applicable Condition
Pin
Min.
1
Typ.
—
Max.
tCBCK
tWHBCK
tWHBCK
tDS
tDH
tBCSS
tBCSH
—
—
—
—
—
—
—
µs
ns
ns
ns
ns
ns
ns
BCK
—
—
—
—
—
—
—
BCK HIGH pulse width
BCK LOW pulse width
BDATA setup time
BDATA hold time
XBCS setup time
100
100
100
100
100
100
—
—
—
BDATA,
BCK
—
—
BCK,
XBCS hold time
—
XBCS
(4) VREF1 and VREF2 output timing
POL
VIH
V
IL
VSS=0V
t
REF1R
t
t
REF1F
V
SCE=3.5V
V
SCE × 0.8
V
REF1
REF2
V
SCE
×
0.2
V
V
SS=0V
REF2R
t
REF2F
SCE=3.5V
V
SCE × 0.8
V
V
SCE × 0.2
V
SS=0V
Item
Symbol
Characteristics
Unit Applicable Condition
Pin
Min.
Typ.
—
Max.
2.0
VRREF1 rise delay time
VRREF1 fall delay time
tREF1R
tREF1F
tREF2R
tREF2F
—
—
—
—
µs
µs
µs
µs
VREF1
<Note 1>
VREF2
VSCE=3.5V
—
2.5
VRREF2 rise delay time
VRREF2 fall delay time
—
2.0
VSCE=3.5V
—
2.5
<Note 1>
<Note 1> The load condition is CL=20nF between the applied pin and VSS.
44
Rev. 1.1
S1F75520 Series
(5) VCOM output timing
tCPOL
tWHPOL
HIH
HIH
VIL
tWLPOL
tCOMF
HIH
POL
VIL
VSS=0V
tCOMR
VCOMH=1.25V
VIH
Vcenter=–0.5V
VCOML=–2.25
VCOM
Vswing=3.5V
VIL
Item
Symbol
Characteristics
Unit Applicable Condition
Pin
Min.
50
20
Typ.
146
—
Max.
—
POL cycle
tCPOL
tWHPOL
tWHPOL
tCOMR
tCOMF
µs
µs
µs
µs
µs
POL
—
—
—
—
—
POL HIGH pulse width
POL LOW pulse width
VCOM rise delay time
VCOM fall delay time
—
20
—
—
—
—
2.0
2.5
VCOM
—
—
<Note 1>
<Note 1> The load condition is CL=20nF between VCOM and VSS.
VSWIN=1.75V VCENT=1.5V. (Vcenter=0.0V, Vswing=3.5V)
Rev. 1.1
45
S1F75520 Series
ꢀ EXTERNAL CONNECTION (EXAMPLES)
ꢀStandard Connection 1 (CHIP)
To source driver (S1D19200)
54
34
33
55
SEVCOM
SEVCOM
CNT
V
REF2
XOFF18
V
V
SS2
SCE
V
REF1
V
SS2
CBVS
CB35
V35
V
SCE
V
V
V
SWIN
RSB
RSA
RVS
SS2
CBML
V
SS2
COML
RVP
CBGP
V
RGP
DD2
CBMH
V
DD
SS
V
V
V
V
V
V
V
V
COMH
CENT
COM
DD2
V
V
SS2
SS2
V
CX2N
CX2P
V
DD
DD1
CBDD
CPX2
CPX1
V
P
V
SS
SS2
CBX1
SS1
CXIP
CB18
CXIN
CX3P
CX3N
V18
VCOREVDD
72
15
1
CPX3
16
V
EE
OFF
V
V
ON
V
DDH
V
COM
[Set]
Primary booster circuit, positive (VP output voltage): 2-times boosting
Primary booster circuit, negative (VN output voltage): –1-times boosting
Secondary booster circuit:
Tertiary booster circuit:
VGON output voltage:
VGOFF output voltage:
VSCE output voltage:
4-times boosting
–4-times boosting
VGON=13.2V (Typ.)
VGON=–13.2V (Typ.)
set by external resistors.
46
Rev. 1.1
S1F75520 Series
ꢀStandard Connection 2 (TQFP12–48pin, QFN7–48pin)
To source driver
36
25
CB35
24
VREF2
VREF1
VSCE
RVS
37
CNT
XOFF18
V35
CBVS
VSWIN
VCOML
VCOMH
CBML
CBMH
RVP
VRGP
VCENT
VCOM
VDD2
VDD1
VSS1
V18
CBGP
CX2N
VDD
VSS
CX2P
VP
CPX2
CPX1
CBDD
CBX1
CX1P
CX1N
CX3P
CB18
VCOREVDD
48
13
1
12
VEE
VOFF
VON
VDDH
[Set]
Primary booster circuit, positive (VP output voltage): 1.5-times boosting
Primary booster circuit, negative (VN output voltage): –1-times boosting
Secondary booster circuit:
Tertiary booster circuit:
VGON output voltage:
VGOFF output voltage:
VSCE output voltage:
4-times boosting
–4-times boosting
VGON=13.2V (Typ.)
VGON=–13.2V (Typ.)
set by external resistors.
Rev. 1.1
47
S1F75520 Series
ꢀRecommended Capacity of the Capacitor and the Theoretical Voltages
The recommended capacity of the capacitors and the theoretical voltages biased to both sides are as follows.
Circuit name
Capacitor type
Capacitor Capacity Theoretical voltages biased to both
name
CPX1
CPX2
CBX1
CPX3
CBX2
CPY1
CPY2
CBY1
CBON
CPZ1
CPZ2
[µF]
2.2
ends of the capacitor <Note 1>
(VDD–VSS) × (Np1–1)
(VDD–VSS) × (Np1–1)
(VDD–VSS) × Np1
(VDD–VSS) × |Nn1|
(VDD–VSS) × |Nn1|
VRGP–VSS
Primary booster circuit
Flying capacitor
Flying capacitor
2.2
Accumulation capacitor
Flying capacitor
2.2
2.2
Accumulation capacitor
Flying capacitor
2.2
Secondary booster circuit
Tertiary booster circuit
0.47
0.47
0.47
0.47
0.47
0.47
0.47
1.0
Flying capacitor
(VRGP–VSS) × 2
(VRGP–VSS) × 2
(VRGP–VSS) × N2
(VRGP–VSS) × (|N3|–2)
(VRGP–VSS) × |N3|
(VRGP–VSS) × |N3|
VCOMH–VSS
Accumulation capacitor
Accumulation capacitor
Flying capacitor
Flying capacitor
Accumulation capacitor CBOFF
VCOM output voltage
generator circuit
Smoothing capacitor
Smoothing capacitor
CBMH
CBML
CBVS
CBGP
CB18
CB35
CBDD
1.0
|VCOML–VSS|
Source driver voltage regulator Smoothing capacitor
Gate driver voltage regulator Smoothing capacitor
Logic power supply voltage regulator Smoothing capacitor
1.0
VSCE–VSS
1.0
VRGP–VSS
2.2
V18–VSS
Standard voltage circuit
Smoothing capacitor
1.0
V35–VSS
Power supply bypass capacitor Bypass capacitor
2.2
VDD–VSS
<Note 1> Symbols for the theoretical voltages are as follows:
Np1: primary booster circuit, positive (VP output voltage) with boosting of Np1=1.5 or 2.
Nn1: primary booster circuit, negative (VN output voltage) with boosting of Nn1=–1 or –1.5 or –2.
N2: secondary booster circuit with boosting of Np1=2 or 3 or 4.
N3: tertiary booster circuit with boosting of Np1=–2 or –3 or –4.
<Note 2> "ꢀ ELECTRICAL CHARACTERISTICS" describe characteristics when the above characteristics are
applied. However, characteristics change depending on the evaluation environment, parts used,
etc. Test and confirm for each application, and set to a capacity that stabilizes the liquid drive
voltage.
48
Rev. 1.1
S1F75520 Series
ꢀ DIMENSIONAL OUTLINE DRAWING
ꢀTQFP12-48pin
[Note] The dimensions are subject to change without notice
Plastic TQFP 48pin Body size 7 × 7 × 1mm (TQFP12)
Reference
HD
D
36PIN
25PIN
37PIN
24PIN
48PIN
13PIN
12PIN
1PIN
e
b1
θ
2
R1
R
θ
C1
L2
L
θ
3
Unit : mm
L1
Dimension in Milimeter
Symbol
E
Min.
Typ.
7.0
7.0
—
Max.
—
—
—
—
—
0.9
—
—
—
0˚
D
—
Amax
A1
A2
e
1.2
—
0.1
1.0
0.5
0.2
0.125
—
1.1
—
b1
—
c1
—
θ
10˚
—
L
—
—
—
—
—
—
—
—
0.08
0.5
1
L1
—
L2
0.5
9
—
HE
HD
θ2
—
9
—
12˚
12˚
0.14
—
—
θ3
—
R
—
R1
—
Rev. 1.1
49
S1F75520 Series
ꢀQFN7-48pin
[Note] The dimensions are subject to change without notice
Plastic QFN 48pin
Reference
D
D1
24
13
25
12
b
36
1
e
P
37
48
θ
Unit : mm
Dimension in Milimeter
Symbol
Min.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Typ.
7.0
Max.
—
D
E
7.0
—
D1
E1
P
6.75
6.75
0.42
0.85
0.01
0.65
—
—
—
—
A
1.0
—
A1
A2
θ
—
12˚
—
b
0.23
0.5
e
—
L
0.4
—
Q
R
x
0.2
—
0.17
0.1
—
—
y
0.08
—
50
Rev. 1.1
S1F75520 Series
ꢀ CHARACTERISTIC GRAPH
Characteristic graph displays the general characteristic trend, which changes by evaluation environment and
parts used, etc. The conditions of the pins are as follows:
Power supply voltage
Frequency
: VDD = 3.0V
: PCK = 20kHz (External clock input)
: VP = 2-times boosting VN = –2-times boosting
Primary booster circuit
Secondary booster circuit : VGON = 4-times boosting
Tertiary booster circuit
VSCE output voltage
VRGP output voltage
Load conditions
: VGOFF = –4-times boosting
: RVS = VSCE connection (3.5V output)
: RVP = VRGP connection (3.3V output)
: No-load
Fig. 30 Output voltage waveform at boost
start time (XSLPX)
Fig. 31 Output voltage waveform at electric
discharge (XSLPX)
Fig. 32 Output voltage waveform at boost
start time (XSLPY)
Fig. 33 Output voltage waveform at electric
discharge (XSLPY)
Rev. 1.1
51
S1F75520 Series
NOTICE:
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson
reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any
inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this
material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights
is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free
from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to
strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry
of International Trade and Industry or other approval from another government agency.
© Seiko Epson Corporation 2003, All rights reserved.
All other product names mentioned herein are trademarks and/or registered trademarks of their respective companies.
ELECTRONIC DEVICES MARKETING DIVISION
IC Marketing & Engineering Group
ꢀ EPSON Electronic Devices Website
http://www.epsondevice.com/
ED International Marketing Department
421-8 Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone: 042
–587
–5814 FAX: 042
–587
–5117
First issue October, 2001
Printed in Japan H
Rev. 1.1
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