SPWNE555D [SECOS]
Single Timer; 单TIMER
| 型号： | SPWNE555D |
| 厂家： | 
SECOS HALBLEITERTECHNOLOGIE GMBH |
| 描述： | Single Timer |
| 文件： | 总5页 (文件大小：1139K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPWNE555D
Single Timer
Elektronische Bauelemente
RoHS Compliant Product
DIP-8
Description
D
GAUGE PLANE
The SPWNE555D is a highly stable timer integrated circuit. It
can be operated in Astable mode and Monostable mode. With
monostable operation, the time delay is controlled by one
external and one capacitor. With a stable operation, the frequency
and duty cycle are accurately controlled with two external resistors
and one capacitor.
Features
* Turn Off Time Less Than 2uSec
SEATING PLANE
b
Z
Z
*
Adjustable Duty Cycle
SECTION Z - Z
* Timing From uSec to Hours
e
b
* High Current Driver Capability (=200mA)
Millimeter
Millimeter
REF.
REF.
Min.
-
Max.
0.5334
-
Min.
0.203
9.017
6.096
7.620
Max.
0.279
10.16
7.112
8.255
Applications
A
A1
A2
b
b1
b2
b3
c
c1
D
E
E1
e
HE
L
0.381
2.921
0.356
0.356
1.143
0.762
0.203
4.953
0.559
0.508
1.778
1.143
0.356
* Time Delay Generation
*
2.540 BSC
Pulse Generation
-
10.92
3.810
* Precistion Timing
2.921
Block Diagram & Pin Configuration
http://www.SeCoSGmbH.com/
Any changing of specification will not be informed individual
01-Jun-2002 Rev. A
Page 1 of 5
SPWNE555D
Elektronische Bauelemente
Single Timer
:
Absolute Maximum Ratings (Ta=25к)
Parameter
Symbol
Value
16
200
600
300
Unit
V
mA
mW
к
Supply Voltage
Output Current
VCC
IO
Power Dissipation
Pd
Lead Temperature (10sec)
Operating Temperature
Storage Temperature
Tlead
Topr
Tstg
0 ~ 70
-65 ~ 150
к
к
Electrical Characteristics (T
A
=25к VCC=5 ~ 15V)
Parameter
Symbol
Test Conditions
Min
Typ. Max. Unit
Supply Voltage
VCC
4.5
-
-
-
3
10
16
6
15
V
mA
mA
VCC=5V, RL=∞
VCC=15V, RL=∞
ICC
Supply Current (Note 1)
Timing Error(monostable)
Initial Accurary (Note 1)
Drift with Temperature
Drift with Supply Voltage
Timing Error(astable)
Initial Accurary (Note 1)
Drift with Temperature
Drift with Supply Voltage
ACCUR RA=1k to 100kꢀ
Ϧt/ϦT C=0.1ꢁF
Ϧt/ϦVCC
-
-
-
1.0
50
0.1
-
-
-
%
ppm/к
%/V
ACCUR RA=1k to 100kꢀ
Ϧt/ϦT C=0.1ꢁF
Ϧt/ϦVCC
-
-
-
2.25
150
0.3
10.0 11.0
3.33 4.0
10.0 10.8
3.33 3.55
0.1
1.67
5
-
-
-
%
ppm/к
%/V
V
V
V
V
ꢁA
V
V
ꢁA
V
VCC=15V
VCC=5V
9.0
2.6
9.2
3.1
-
1.1
4.5
-
Control Voltage
VC
VCC=15V
VCC=5V
Threshold Voltage
Threshold Current (Note 3)
Trigger Voltage
VTH
ITH
0.25
2.2
5.6
2.0
1.0
0.4
VCC=5V
VCC=15V
Vtr
Itr
Trigger Current
Reset Voltage
Reset Current
Vtr=0
-
Vrst
Irst
0.4
-
0.7
0.1
mA
VCC=15V, Isink=10mA
VCC=15V, Isink=50mA
VCC=5V, Isink=5mA
VCC=15V, Isink=200mA
VCC=15V, Isink=100mA
VCC=5V, Isink=100mA
-
-
-
-
0.06 0.25
0.3 0.75
0.05 0.35
Low Output Voltage
High Output Voltage
VOL
VOH
V
V
12.5
-
15
5
12.75 13.3
2.75
3.3
100
100
20
Reset Time of Output
Fall Time of Output
Discharge leakage Current
tR
tF
ILKG
-
-
-
-
-
nSec
nSec
nA
100
Note1: Supply current when output is high typically 1mA less at VCC=5V.
Note2: Tested at VCC=5V and VCC=15V.
Note3: This will determine the maximum value of RA+RB for 15V operation, the maximum total is R=20Mꢀ, and for 5V operation the
maximum total is R=6.7Mꢀ.
http://www.SeCoSGmbH.com/
Any changing of specification will not be informed individual
01-Jun-2002 Rev. A
Page 2 of 5
SPWNE555D
Single Timer
Elektronische Bauelemente
Characteristics Curve
VCC = 15 V
ht tp://www.SeCoSGmbH.com/
Any changing of specification will not be informed individual
01-Jun-2002 Rev. A
Page 3 of 5
SPWNE555D
Single Timer
Elektronische Bauelemente
http://www.SeCoSGmbH.com/
Any changing of specification will not be informed individual
01-Jun-2002 Rev. A
Page 4 of 5
SPWNE555D
Elektronische Bauelemente
Single Timer
Application Circuit
FLIP-FLOP
Application Notes
The application circuit shows astable mode configuration.
Pin 6 (Threshold) is tied to Pin 2 (Trigger) and Pin 4 (Reset) is tied to VCC (Pin 8). The external capacitor C1
of Pin 6 and Pin 2 charges through RA, RB and discharge through RB only. In the internal circuit of SPWNE555D,
one input of the upper comparator is at voltage of 2/3VCC (R1=R2=R3), another input is connected to Pin 6. As
soon as C1 is charging to higher than 2/3VCC, transistor Q1 is turned ON and discharge C1 to collector voltage
of transistor Q1. Therefore, the flip-flop circuit is reset and output is low. One input of lower comparator is at
voltage of 1/3VCC, discharge transistor Q1 turn off and C1 charges through RA and RB. Therefore, flip-flop
circuit is set output high.
That is, when C1 charges through RA and RB, output is high and when C1 discharge through RB, output is
low. The charge time (output is high) t1 is 0.693 (RA+RB) C1 and the discharge time (output is low) T2 is
0.693RB*C1.
1
3
-
-
Vcc
Vcc
Vcc
Vcc
In
=0.693
2
3
T1=0.693*(RA+RB)*C1
T2=0.693*RB*C1
Thus the total period time T is given by
T=T1+T2=0.693(RA+2RB)*C1.
Then the frequency of astable mode is given by
1
T
1.44
f =
=
(RA+2RB)*C1
The duty cycle is given by
T2
RB
RA+2RB
D.C. =
=
.
T
http://www.SeCoSGmbH.com/
Any changing of specification will not be informed individual
01-Jun-2002 Rev. A
Page 5 of 5
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