LC99063-LF2 [SANYO]
CCD Digital Signal Processing IC; CCD的数字信号处理集成电路
| 型号： | LC99063-LF2 |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | CCD Digital Signal Processing IC |
| 文件： | 总8页 (文件大小：123K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : EN5787
CMOS IC
LC99063-LF2
CCD Digital Signal Processing IC
Overview
Package Dimensions
unit: mm
The LC99063-LF2 is a color video signal processor for
use with the LC9997M/FL.
3181B-SQFP100
[LC99063-LF2]
SANYO: SQFP100
Specifications
Absolute Maximum Ratings at V = 0 V
SS
Parameter
Symbol
Conditions
Ratings
–0.3 to +4.6
–0.3 to VDD +0.3
–0.3 to +7.3
400
Unit
V
Supply voltage
I/O voltage
V
DD max
VI1, VO
VI2
For pin type 1
For pin type 2
V
Input voltage
V
Allowable power dissipation
Operating temperature
Pd max
Topr
mW
°C
°C
°C
°C
mA
–15 to +70
–55 to +125
350
Storage temperature
Tstg
Solder resistance (Hand soldering)
Solder resistance (Reflow)
I/O current
3s
10s
*
235
Ii, Io
±20
The pin types above refer to the following groups.
(1) DIN[32:9], DEVICE, MIRRO, SUPER, INMODE, WBHL, DOSL, SSET [2:1], OMODE [4:1], RES, DOUT [24:1], HREF, VDO, HDO, CLKOUT, ANA1,
ANA2, IREFOT1, IREFOT2, VREF1, VREF2, COMP1, COMP2
(2) DIN[8:1], CLK14M, CLK10M, HDI, VDI, HREF53, ENS, DATAS, CLKS, REGRES
*: This value is for a single I/O basic cell.
Allowable Operating Ranges at Ta = –15 to +70°C, V = 0 V
SS
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
max
3.6
Supply voltage
VDD
Vin1
Vin2
3
0
0
3.3
V
V
V
Input voltage range 1
Input voltage range 2
For pin type 1
For pin type 2
VDD
+5.3
(1) DIN[32:9], DEVICE, MIRRO, SUPER, INMODE, WBHL, DOSL, SSET [2:1], OMODE [4:1], RES
(2) DIN[8:1], CLK14M, CLK10M, HDI, VDI, HREF53, ENS, DATAS, CLKS, REGRES
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
51398RM (OT) No. 5787-1/8
LC99063-LF2
Electrical Characteristics for Logic Circuits
DC Characteristics at Ta = –15 to +70°C, V = 3.0 to 3.6 V, V = 0 V
DD
SS
Ratings
typ
Parameter
Input high-level voltage
Symbol
Conditions
Unit
min
max
VIH
VIL
VIH
VIL
VOH
VOL
IL
CMOS level ; for pin type 1
0.7 VDD
V
V
Input low-level voltage
Input high-level voltage
Input low-level voltage
Output high-level voltage
Output low-level voltage
Input leak current
CMOS level ; for pin type 1
0.2 VDD
0.15 VDD
CMOS level with Schmitt ; for pin type 2
CMOS level with Schmitt ; for pin type 2
IOH = –2 mA; for pin types 3 and 4
IOL = +2 mA; for pin types 3 and 4
VI = VDD; for pin types 1 and 2
0.75 VDD
VDD – 0.8
V
V
V
0.4
+10
+10
V
–10
–10
µA
µA
Output leak current
Ioz
High-impedance output; for pin type 3
The pin types above refer to the following groups.
INPUT
(1) DIN [32:9], DEVICE, MIRRO, SUPER, INMODE, WBHL, DOSL, SSET [2:1], OMODE [4:1], RES
(2) DIN [8:1], CLK14M, CLK10M, HDI, VDI, HREF53, ENS, DATAS, CLKS, REGRES
OUTPUT
(3) DOUT [24:1]
(4) HREF, VDO, HDO, CLKOUT
Note: The ANA1, ANA2, IREFOT1, IREFOT2, VREF1, VREF2, COMP1, and COMP2 pins fall outside these DC characteristic specifications.
Electrical Characteristics for Analog Circuits
Recommended operating conditions for D/A converter
Ratings
Parameter
Symbol
Conditions
Unit
min
typ
max
1.11
Reference voltage
VREF1/2
V
Ω
Analog output resistance
Reference voltage resistance
Phase compensation capacitor
VREF capacitor
Ra
Ri
200
Ra × 4
Ω
Cc
Cv
0.1
0.1
µF
µF
No. 5787-2/8
LC99063-LF2
Electrical Characteristics for D/A Converter at Ta = 25°C, V = 3.3 V, Rv = 200 Ω, Ri = 800 Ω
DD
Ratings
Parameter
Symbol
Conditions
Unit
min
typ
max
Resolution
8
Bits
MSPS
mV
Conversion frequency
Zero scale output voltage
Full scale output voltage
Linearity error
15
+15
–15
0
1.01
1.1
1.19
±1.0
±0.5
1.11
V
LSB
LSB
V
Differential linearity error
Reference output voltage
1.09
1.1
Pin Assignment
No. 5787-3/8
LC99063-LF2
Pin Functions
Pin No.
1
Symbol
I/O
I
Function
DEVICE
MIRRO
SUPER
INMODE
WBHL
0 : LC9997FL 1 : LC9997M
0 : NORMAL 1 : MIRROR
2
I
3
I
Superimpose control 0 : Superimpose 1 : Camera through
Input mode select
4
I
5
I
Auto white balance hold 0 : Hold 1 : Auto
Pin 55 output select 0 : HD 1 : C.SYNC
Color sampling phase select
6
DOSL
I
7
SSET1
I
8
SSET2
I
Color sampling phase select
9
V
DD (DAC-A)
VREF2
VREF1
P
O
O
P
O
I
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
DAC2 reference voltage output
DAC1 reference voltage output
V
SS (DAC-A)
ANA2
DAC2 output
COMP2
IREFOT2
ANA1
DAC2 bias pin
O
O
I
DAC2 reference current
DAC1 output
COMP1
IREFOT1
SS (DAC-D)
DAC1 bias pin
O
P
P
I
DAC1 reference current
V
V
DD (DAC-D)
ENS
Serial resister enable
Serial resister data
Serial resister CLK
Serial resister reset
CCIR601, square PIX mode CLK
Output Channel1 = CH1 (LSB)
Output Channel1
DATAS
CLKS
B
I
REGRES
CKOUT
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7
DOUT8
DOUT9
DOUT10
DOUT11
DOUT12
DOUT13
DOUT14
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Output Channel1
Output Channel1
Output Channel1
Output Channel1
Output Channel1
Output Channel1 = CH1 (MSB)
Output Channel2 = CH2 (LSB)
Output Channel2
Output Channel2
Output Channel2
Output Channel2
Output Channel2
V
SS (logic)
V
DD (logic)
DOUT15
DOUT16
DOUT17
DOUT18
DOUT19
DOUT20
DOUT21
DOUT22
DOUT23
DOUT24
RES
O
O
O
O
O
O
O
O
O
O
I
Output Channel2
Output Channel2 = CH2 (MSB)
Output Channel3 = CH3 (LSB)
Output Channel3
Output Channel3
Output Channel3
Output Channel3
Output Channel3
Output Channel3
Output Channel3 = CH3 (MSB)
0 : Test 1 : Real
HREF
O
O
O
Horizontal reference
VD output
VDO
HDO
HD or C.SYNC output
Continued on next page.
No. 5787-4/8
LC99063-LF2
Continued from preceding page.
Pin No.
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Symbol
OMODE1
OMODE2
OMODE3
OMODE4
HREF53
CLK14M
VDI
I/O
I
Function
I
Output mode select
I
I
I
Horizontal reference (from LC99053)
I
FSC4 (LC99053 pin 58), VD (LC99053 pin 56), HD (LC99053 pin 55)
or HTCLK (LC99053 pin 51), fixed at high level, C.SYNC (LC99053 pin 54)
I
HDI
I
CLK14M
I
HTCLK (LC99053 pin 51)
VDD (logic)
P
P
I
V
SS (logic)
DIN1
8 bit data input (from LC99053) [LSB]
8 bit data input
DIN2
I
DIN3
I
8 bit data input
DIN4
I
8 bit data input
DIN5
I
8 bit data input
DIN6
I
8 bit data input
DIN7
I
8 bit data input
DIN8
I
8 bit data input (from LC99053) [MSB]
8 bit Y input [LSB]
8 bit Yinput
DIN9
I
DIN10
DIN11
DIN12
DIN13
DIN14
DIN15
DIN16
DIN17
DIN18
DIN19
DIN20
DIN21
DIN22
DD (logic)
I
I
8 bit Y input
I
8 bit Y input
I
8 bit Y input
I
8 bit Y input
I
8 bit Y input
I
8 bit Y input [MSB]
8 bit U or UV input [LSB]
8 bit U or UV input
8 bit U or UV input
8 bit U or UV input
8 bit U or UV input
8 bit U or UV input
I
I
I
I
I
I
V
P
P
I
V
SS (logic)
DIN23
DIN24
DIN25
DIN26
DIN27
DIN28
DIN29
DIN30
DIN31
DIN32
8 bit U or UV input
8 bit U or UV input [MSB]
8 bit V input [LSB]
8 bit V input
I
I
I
I
8 bit V input
I
8 bit V input
I
8 bit V input
I
8 bit V input
I
8 bit V input
I
8 bit V input [MSB]
No. 5787-5/8
LC99063-LF2
Block Diagram
No. 5787-6/8
LC99063-LF2
Major Functions
Luminance (Y) signal processing
• This block includes an 11-tap low pass filter.
• This block includes a gamma correction circuit using a five-segment curve with user-specified data points.
• This block provides vertical and horizontal outline enhancement with user-specified gain and coreling.
• This block includes a circuit for generating the 1.5× oversampling frequency.
Chrominance (U.V, U/V) signal processing
• This block uses a 9-tap low pass filter and color matrices to convert YUV input to an RGB signal.
• This block includes an auto white balance subblock.
— This subblock contains all circuits necessary for automatic white balance adjustment.
— This subblock offers a choice of automatic or manual operation.
— This subblock supports holding of automatic operation results.
— This subblock offers a choice of seven patterns—one for skin tones, for example.
• This block includes a gamma correction circuit using a three-segment curve.
• This block uses adjustable linear matrices to convert the color difference signals.
• This block includes an adjustable circuit for suppressing color noise at low luminance levels.
• This block includes an adjustable circuit for suppressing false-color signals occurring at edges and high-luminance
blocks.
• This block includes a circuit for generating the 1.5× oversampling frequency.
NTSC encoder
• This block encodes the RGB data using the timing from the HD, VD, and CLK (14.31818 MHz) input signals.
• This block supports color burst phase adjustment.
• The pedestal and burst levels are both adjustable.
I/O modes
• Input modes
— In addition to LC99053 output signals, the chip supports the Y, U, and V input configuration (Y.U.V) and the Y
and U/V one (Y.U/V).
— The chip can mix (superimpose) the signals from these two sources.
• Output modes
— Digital outputs: Digital composite video, digital Y.C, R.G.B, Y.U.V, and Y.U/V.
— Analog outputs using two 8-bit digital-to-analog converters: Composite video and Y.C
Other functions
• Registers are accessible via a 3-pin serial interface.
• The chip is capable of stand-alone operation.
• The chip supports mirror imaging (reversal of left and right).
• The chip supports pseudo interlacing.
• The chip supports negative imaging (creation of photographic negatives).
Important Notes
When used in combination with the LC99053-Z28, this chip supports the following modes with field periods longer than
1/60 second: extended exposure, M3, M4, and external ST and FT trigger. In these modes, however, the system requires
even more careful evaluation of circuit constants, trigger inputs, and other factors affecting CCD and driver operation.
Camera characteristics depend heavily on part layout and circuit design, so follow the guidelines set forth in
recommended circuit diagrams issued by Sanyo.
No. 5787-7/8
LC99063-LF2
■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of May, 1998. Specifications and information herein are subject to change
without notice.
PS No. 5787-8/8
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