LC99012A-S [SANYO]
Black-and-White CCD Timing Generator; 黑白CCD时序发生器
| 型号： | LC99012A-S |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | Black-and-White CCD Timing Generator |
| 文件： | 总6页 (文件大小：62K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : EN*5281A
CMOS LSI
LC99012A-S
Black-and-White CCD Timing Generator
Preliminary
Overview
Package Dimensions
The LC99012A-S is a timing generator for the 1/5-inch
LC9947G and LC9948G and the 1/6-inch LC9949G
black-and-white CCD image sensors.
unit: mm
3190-SQFP64
[LC99012A-S]
Features
• 5 V single-voltage power supply
• Generates all pulses required for CCD drivers.
• Generates all pulses required for video signal
processing.
• Built-in synchronizing signal generator that supports
both EIA and CCIR.
• Includes buffer circuits for directly driving the CCD
horizontal transfer and reset gates.
• Includes light metering and control systems for an
automatic electronic iris function.
• Fixed rate-of-change control allows a smooth electronic
iris function to be implemented (an iris state output is
provided).
SANYO: SQFP64
• Supports AGC control and a light metering mode that
compensates for backlighting.
• Selectable CCD storage mode (non-interlaced or
interlaced)
• Selectable TV scan mode (non-interlaced or interlaced)
• Allows all types of external synchronization.
• Built-in EXT-C.SYNC sync separator circuit
• Built-in phase comparator for external synchronization
• Control from external electronic shutter pulses and
frame shift pulses supports one-shot imaging.
• Package: 0.5 mm lead pitch flat package (SQFP-64)
• Flickerless function
• Sensitivity-increasing function
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
22896HA (OT) No. 5281-1/6
LC99012A-S
Specifications
Absolute Maximum Ratings at V = 0 V
SS
Parameter
Maximum supply voltage
Symbol
max
Conditions
Ratings
Unit
V
V
–0.3 to +7.0
DD
Input and output voltages
Allowable power dissipation
Operating temperature
Storage temperature
V , V
–0.3 to V
DD
+ 0.3
290
V
I
O
Pd max
Topr
Ta ≤ 65°C
mW
°C
°C
°C
°C
mA
–30 to +65
–55 to +125
350
Tstg
Hand soldering: 3 seconds
Soldering heat resistance
Reflow soldering: 10 seconds
235
Input and output currents
I , I
±20*
I
O
Note: * Per individual I/O reference cell
Allowable Operating Ranges at Ta = –30 to +65°C, V = 0 V
SS
Parameter
Supply voltage
Input voltage range
Symbol
Conditions
min
4.5
0
typ
5.0
max
5.5
Unit
V
V
DD
V
V
V
IN
DD
DC Characteristics: Input and Output Levels at V = 0 V, V = 4.5 to 5.5 V, Ta = –30 to +65°C
SS
DD
See the note on next page.
Parameter
Input high-level voltage
Input low-level voltage
Input high-level voltage
Input low-level voltage
Input high-level voltage
Input low-level voltage
Input high-level voltage
Input low-level voltage
Input high-level voltage
Input low-level voltage
Output high-level voltage
Output low-level voltage
Output low-level voltage
Output high-level voltage
Output low-level voltage
Output high-level voltage
Output low-level voltage
Output high-level voltage
Output low-level voltage
Output high-level voltage
Output low-level voltage
Output high-level voltage
Output low-level voltage
Input leakage current
Output leakage current
Pull-up resistance
Symbol
Conditions
min
typ
max
Unit
V
V
1
1
2
TTL levels: (6)
2.2
IH
V
V
TTL levels: (6)
0.8
V
IL
CMOS levels: (1), (3)
CMOS levels: (1), (3)
0.7 V
0.8 V
0.7 V
0.7 V
V
IH
DD
DD
DD
DD
V
2
0.3 V
0.2 V
0.3 V
0.3 V
V
IL
DD
DD
DD
DD
V
3
3
4
CMOS levels, Schmitt inputs: (4)
CMOS levels, Schmitt inputs: (4)
V
IH
V
V
V
IL
CMOS levels, inputs with pull-up resistors: (2)
CMOS levels, inputs with pull-up resistors: (2)
CMOS levels, inputs with pull-up resistors: (5)
CMOS levels, inputs with pull-up resistors: (5)
V
IH
V
4
V
IL
V
5
5
V
IH
V
V
IL
V
1
1
2
3
I
I
I
I
I
I
I
I
I
I
I
I
I
= –3 mA: (6), (13), (14), (15)
= 3 mA: (6), (13), (14), (15)
= 3 mA: (9)
V
V
– 2.1
SS
V
OH
OH
OL
OL
OH
OL
OH
OL
OH
OL
OH
OL
OH
OL
V
V
V
0.4
0.4
V
OL
OL
V
= –6 mA: (12)
– 2.1
– 2.1
– 2.1
– 2.1
– 1.5
V
OH
DD
DD
DD
DD
DD
V
3
= 6 mA: (12)
0.4
0.4
0.4
0.4
V
OL
V
4
4
5
= –6 mA: (7)
V
V
V
V
V
OH
V
V
= 2 mA: (7)
V
OL
= –30 mA: (11)
= 10 mA: (11)
V
OH
V
5
V
OL
V
6
6
6
= –12 mA: (8)
V
OH
V
V
= 12 mA: (8)
V
OL
= –12 mA: (10)
= 6 mA: (8)
V
OH
V
7
0.4
+10
+10
40
V
OL
I
V = V , V : (1), (3), (4), (6)
–10
–10
10
µA
µA
kΩ
kΩ
IL
I
SS DD
I
In high-impedance output mode: (6), (9), (13)
OZ
R
(2)
(5)
20
50
UP
Pull-down resistance
R
25
100
DN
No. 5281-2/6
LC99012A-S
Note: The applicable pin sets are defined as follows:
Input
(1) ......AI, CKI
(2) ......FLESS, STR, TEST
(3) ......EXT1, EXT2, KISYU, TV
(4) ......HR, SELMET1, SELMET2, VR
(5) ......CCDSCAN, EXT3, EXT4, MSENS, SENS, SSGSCAN
I/O
(6) ......STEPSTOP
Output
(7) ......PCO
(8) ......DHTR
(9) ......IRRES
(10) ....A0, CKO
(11) ....DHT1, DHT2
(12) ....DS1, DS2
(13) ....AGCC2, IRSTA
(14) ....CLK14M, CLP1, CLP2, FLD, HD, NSUB1, NSUB2, VD
(15) ....CBLK, C.SYNC, NSUB3, PBLK, VI1 to VI4, VS1 to VS4
*
......VIDI, VIDO, DCH, DCL, IRIS (These pins are not covered in the DC characteristics.)
Pin Assignment
I/O → I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: Unconnected pin
No.
1
Symbol
I/O
P
O
I
No.
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Symbol
DCL
I/O
I
V
SS
2
PCO
AI
DCH
I
3
IRIS
I
4
AO
O
I
IRRES
VIDO
VIDI
O
O
I
5
CKI
6
CKO
O
I
7
CCDSCAN
SSGSCAN
CLK14M
HD
IRSTA
AGCC2
O
O
P
I
8
I
9
O
O
O
O
P
I
V
DD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
TV
C.SYNC
CBLK
PBLK
CLP2
CLP1
VD
O
O
O
O
O
P
O
O
P
O
O
O
P
O
O
O
O
O
O
O
O
I
FLD
V
DD
KISYU
HR
I
VR
I
V
SS
V
P
I
DS1
DS2
SS
SELMET1
SELMET2
EXT1
I
V
DD
I
DHT2
DHT1
DHTR
EXT2
I
EXT3
I
EXT4
I
V
SS
V
P
B
I
VS3
VS2
VS1
VS4
VI4
DD
STEPSTOP
SENS
MSENS
FLESS
STR
I
I
I
VI2
NSUB3
NSUB2
NSUB1
O
O
O
VI3
VI1
32
TEST
Note: All V
and V pins must be connected to the power supply or ground. Do not leave any of these pins open.
SS
DD
No. 5281-3/6
LC99012A-S
Block Diagram
No. 5281-4/6
LC99012A-S
Pin Functions
Pin No.
Symbol
I/O
Function
1
2
3
4
GND
PCO
AI
O
I
Phase comparator output
PCO output signal low-pass filter amplifier input
PCO output signal low-pass filter amplifier output
AO
O
Reference clock input (resonator inverter input)
LC9947G: 28.63636 MHz
LC9948G: 28.375 MHz
5
CKI
I
LC9949G: 14.31818 MHz
6
7
CKO
O
I
Resonator inverter output
Low/open: CCD interlaced storage mode
High: CCD non-interlaced storage mode
CCDSCAN
Low/open: C.SYNC interlaced mode
High: C.SYNC non-interlaced mode
8
9
SSGSCAN
CLK14M
I
LC9947G/9949G: 14.31818 MHz
LC9948G: 14.1875 MHz
O
10
11
HD
VD
O
O
HD output
VD output
Field identifier signal
High: odd
Low: even
12
FLD
O
Must be tied high if SSGSCAN is high.
13
14
15
16
17
18
19
20
21
22
23
24
V
DD
KISYU
HR
I
I
I
Must be tied high when used with the LC9949G. Otherwise must be tied low.
Horizontal reset, C.SYNC reset, and vertical reset pulse input
VR
Vertical reset pulse input and external synchronization mode setup
GND
SELMET1
SELMET2
EXT1
I
I
I
I
I
I
I
Light metering mode control
Light metering mode control
External synchronization mode control
External synchronization mode control
CCD drive external control mode control
CCD drive external control mode control
EXT2
EXT3
EXT4
V
DD
Normally used to control the electronic iris step (rate of change)
25
26
27
28
29
STEPSTOP
SENS
I/O
Low: 1/8
Hifh: 1/16
Sensitivity increasing switch
Low/open: normal
High: Increased sensitivity mode
I
I
I
I
Increased sensitivity mode type switching
Low or open: In field units
High: In single scan line (1H) units
MSENS
FLESS
STR
Flickerless mode* switch
Low: Flickerless mode
High/open: normal
CCD storage mode control
This pin must be left open or tied high when the LC99012A-S is used with an LC9947G/49G, and must
be tied low when used with an LC9948G.
30
31
32
NSUB3
NSUB2
NSUB1
O
O
O
CCD NSUB pulses
CCD NSUB pulses
CCD NSUB pulses
Low: test mode
High/open: normal operating mode
33
TEST
I
34
35
36
37
38
VI1
VI3
VI2
VI4
VS4
O
O
O
O
O
CCD imaging block transfer clock (ø1)
CCD imaging block transfer clock (ø3)
CCD imaging block transfer clock (ø2)
CCD imaging block transfer clock (ø4)
CCD imaging block transfer clock (øS4)
Note: * Flickerless mode can be used when the auto-iris function is off, i.e. when EXT3 is high and EXT4 is low.
Continued on next page.
No. 5281-5/6
LC99012A-S
Pin No.
39
Symbol
VS1
I/O
O
Function
CCD imaging block transfer clock (øS1)
CCD imaging block transfer clock (øS2)
CCD imaging block transfer clock (øS3)
40
VS2
O
41
VS3
O
42
GND
DHTR
DHT1
DHT2
43
CCD output block reset pulse
44
O
O
CCD horizontal transfer clock (øH1)
CCD horizontal transfer clock (øH2)
45
46
V
DD
47
DS2
DS1
GND
O
O
CCD output floating level sampling pulse
CCD output video signal sampling pulse
48
49
50
51
52
53
CLP1
CLP2
PBLK
CBLK
O
O
O
O
OPB clamp pulse
OPB clamp pulse
Pre-blanking pulse
Composite blanking pulse
Composite sync pulse
54
55
C.SYNC
TV
O
I
Low: EIA (LC9947G/49G)
High: CCIR (LC9948G)
56
57
V
DD
AGCC2
O
O
AGC detection signal weighting processing pulse
Electronic iris state output
High: The iris is in the fully stopped down state.
Low: The iris is in the fully open state.
58
IRSTA
High-impedance: The iris is in an appropriate state.
59
60
61
62
63
64
VIDI
VIDO
IRRES
IRIS
I
O
O
I
Analog switch input for iris detection signal window processing
Analog switch output for iris detection signal window processing
Reset (discharge) pulse that is input by the iris signal detection (integration) circuit
Iris integration signal input
DCH
DCL
I
High-level reference voltage for the iris level detection comparator
Low-level reference voltage for the iris level detection comparator
I
■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of February, 1997. Specifications and information herein are subject to
change without notice.
No. 5281-6/6
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