LC86P7148 [SANYO]
8-Bit Single Chip Microcontroller with One-Time Programmable PROM; 8位单芯片微控制器，带有一次性可编程PROM
| 型号： | LC86P7148 |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | 8-Bit Single Chip Microcontroller with One-Time Programmable PROM |
| 文件： | 总21页 (文件大小：663K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENN*6692
CMOS IC
LC86P7148
8-Bit Single Chip Microcontroller
with One-Time Programmable PROM
Preliminary
Overview
The LC86P7148 is a CMOS 8-bit single chip microcontroller with one-time PROM for the LC867100 series. This
microcontroller has the function and the pin description of the LC867100 series mask ROM version, and 48K-byte PROM.
QFP package are available for shipping as well as LC867100 series. It is suitable to set up first release, prototyping,
developing and testing of set.
Features
(1) Option switching by PROM data
The option function of the LC867100 series can be specified by the PROM data.
LC86P7148 can be checked the functions of the trial pieces using the mass production board.
(2) Internal one-time PROM capacity : 49152 bytes
(3) Internal RAM capacity
:
1152 bytes
Used PROM or RAM capacity are equal ROM or RAM capacity of mask ROM version which applies LC86P7148.
Mask ROM version
LC867148
LC867140
LC867132
LC867128
LC867124
LC867120
LC867116
LC867112
LC867108
PROM capacity
49152 bytes
40960 bytes
32768 bytes
28672 bytes
24576 bytes
20480 bytes
16384 bytes
12288 bytes
8192 bytes
RAM capacity
1152 bytes
1152 bytes
768 bytes
768 bytes
768 bytes
640 bytes
640 bytes
512 bytes
512 bytes
Programming service
We offers various services at nominal charges. These include the ROM writing, the ROM reading, the package stamping
and the screening. Contact our representative for further information.
Ver.1.00
D2994
91400 RM (IM) HK No.6692-1/21
LC86P7148
(4) Operating supply voltage
(5) Instruction cycle time
(6) Operating temperature
:
:
:
4.5V to 6.0V
1µs to 366µs
-30°C to +70°C
(7) The pin compatible with the LC867100 series mask ROM devices
(8) Applicable mask ROM version
(9) Factory shipment
:
:
LC867148/LC867140/LC867132/LC867128/LC867124/LC867120
/LC867116/LC867112/LC867108
QFP80E
Notice for use
LC86P7148 is provided for the first release and small shipping of the LC867100 series.
At using, take notice of the followings.
(1) A point of difference LC86P7148 and LC867100 series
Item
LC86P7148
LC867148/40/32/28/24/20/16/12/08
Operation after reset
releasing
The option is specified until 3ms after going The program is executed from 00H of the
to a ‘H’ level to the reset terminal by program counter immediately after going to
degrees. The program is executed from 00H a ‘H’ level to the reset terminal.
of the program counter.
Operating supply
voltage range (VDD)
Total output current
[∑IOAL(2)]
4.5V to 6.0V
2.5V to 6.0V
Refer to ‘electrical characteristics’ on the semiconductor news.
[∑IOAL(3)]
Power dessipation
LC86P7148 uses 256 bytes that is addressed on 0FF00H to FFFFH in the program memory as the option configuration data
area. This option configuration can execute all options which LC867100 series have. Next tables show the options that
correspond and not correspond to LC86P7148.
• A kind of the option corresponding of the LC86P7148
A kind of option
Input/output form of
input/output ports
Pins, Circuits
Contents of the option
1. Input : No Pull-up MOS Tr.
Port 0
(specified in a bit)
Output: N-channel open drain
2. Input : Pull-up MOS Tr.
Output: CMOS
*1
*2
Port 1
(specified in a bit)
1. Input : Programmable pull-up MOS Tr.
Output: N-channel open drain
2. Input : Programmable pull-up MOS Tr.
*1
Output
: CMOS
Pull-up MOS Tr. of
input port
Port 7
1. No Pull-up MOS Tr.
2. Pull-up MOS Tr.
(specified in a bit) *1
Each of P74 and P75 has no
option
*1) Specified in a bit.
*2) Specified in nibble unit. Pull-up MOS Tr. is not provided in N-channel open drain output port.
No.6692-2/21
LC86P7148
(2) Option
The option data is created by the option specified program “SU86K.EXE”. The created option data is linked to the
program area by linkage loader “L86K.EXE”.
(3) ROM space
LC86P7148 and LC867100 series use 256 bytes that is addressed on 0FF00H to 0FFFFH in the program memory as the
option specified data area. These program memory capacity are 49152 bytes that is addressed on 0000H to 0BFFFH.
0FFFFH
0FF00H
0EFFFH
0DFFFH
0CFFFH
0BFFFH
0AFFFH
9FFFH
8FFFH
7FFFH
6FFFH
5FFFH
4FFFH
3FFFH
2FFFH
1FFFH
0FFFH
0000H
Option data
area 256 bytes
Option
Data Area
Option
Data Area
Option
Data Area
Option
Data Area
Program area
48K bytes
Program area
40K bytes
Program area
32K bytes
Program area
28K bytes
Program area
24K bytes
LC867148
LC867140
LC867132
LC867128
LC867124
0FFFFH
0FF00H
0EFFFH
0DFFFH
0CFFFH
0BFFFH
0AFFFH
9FFFH
8FFFH
7FFFH
6FFFH
5FFFH
4FFFH
3FFFH
2FFFH
1FFFH
0FFFH
0000H
Option data
area 256 bytes
Option
Data Area
Option
Data Area
Option
Data Area
Program area
20K bytes
Program area
16K bytes
Program area
12K bytes
Program area
8K bytes
LC867120
LC867116
LC867112
LC867108
(4) Ordering information
1. When ordering the identical mask ROM and PROM devices simultaneously.
Provide an EPROM containing the target memory contents together with the separate order forms for each of the mask
ROM and PROM versions.
2. When ordering a PROM device.
Provide an EPROM containing the target memory contents together with an order form.
No.6692-3/21
LC86P7148
How to use
(1) Specification of option
The LC86P7148 must be programmed after specifying option data. The option is specified by “SU86K.EXE”. The
specified option file and the file created by our macro assembler “M86K.EXE” are linked by our linkage loader
“L86K.EXE” which creates .HEX file, then the option code is put in the option specified area (0FF00H to 0FFFFH) of
its .HEX file.
(2) How to program for the EPROM
The LC86P7148 can be programmed by EPROM programmer with attachment ; W86EP7148Q
• Recommended EPROM programmer
Productor
Advantest
Andou
EPROM programmer
R4945, R4944, R4943
AF-9704
AVAL
Minato electronics
PKW-1100, PKW-3000
MODEL1890A
• “27512 (Vpp=12.5V) Intel high speed programming” mode available. The address must be set to “0 to 0FFFFH” and a
jumper (DASEC) must be set to ‘OFF’ at programming.
(3) How to use the data security function
“Data security” is the disabled function to read the data of the EPROM.
The following is the process in order to execute the data security.
1. Set ‘ON’ the jumper of attachment.
2. Program again. Then EPROM programmer displays the error. The error means normally activity of the data
security. It is not a trouble of the EPROM programmer or the LSI.
Notes
• Data security is not executed when the data of all address have ‘FFH’ at the sequence 2 above.
• The programming by a sequential operation “BLANK=>PROGRAM=>VERIFY” cannot be executed data security at the
sequence 2 above.
• Set to ‘OFF’ the jumper after executing the data security.
Data security
Not data security
W86EP7148Q
No.6692-4/21
LC86P7148
Pin Assignment
COM1/PL1
COM2/PL2
COM3/PL3
VSS2
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
S11/PB3
S10/PB2
S9/PB1
S8/PB0
S7/PA7
S6/PA6
S5/PA5
S4/PA4
S3/PA3
S2/PA2
S1/PA1
S0/PA0
P73/INT3/T0IN
P72/INT2/T0IN
P71/INT1
P93/DA3/AN11
VDD2
P00
P01
P02
P03
P04
P05
P06
P07
P10/SO0
P11/SI0/SB0
P12/SCK0
Package Dimension
(unit : mm)
3174
SANYO : QIP-80E
Notes •The QFP packages should be heat-soaked for 12 hours at 125°C immediately prior to mounting (This baking is called
pre-baking).
•After pre-baking a controlled environment must be maintained until soldering. The environment must be held at a
temperature of 30°C or less and a humidity level of 70% or less. Please solder within 24 hours.
No.6692-5/21
LC86P7148
System Block Diagram
Interrupt Control
IR
PLA
A15-A0
D7-D0
TA
CE
Stand-by Control
PROM
Control
OE
DASEC
CF
RC
PROM(48KB)
X’tal
PC
Base Timer
SIO0
Bus Interface
ACC
Port 1
Port 7
Port 8
Port 9
ADC
B Register
C Register
SIO1
Timer 0
ALU
Timer 1
Real Time Service
PSW
RAR
RAM
128 bytes
INT0 - 3
Nose Filter
LCD
Controller
DAC
RAM
S0 – S7 (PA)
S8 – S13 (PB)
Stack Pointer
Port 0
S16 – S23 (PC)
S24 – S31 (PD)
COM0 – COM3(PL)
Watchdog Timer
No.6692-6/21
LC86P7148
Pin Description
Pin name I/O
Function description
Power pin (–)
Power pin (–)
Power pin (–)
Power pin (+)
Power pin (+)
Power pin (+)
Option
PROM mode
VSS1 *1
VSS2 *1
VSS3 *1
VDD1 *1
VDD2 *1
VDD3 *1
PORT0
-
-
-
-
-
-
-
-
-
-
-
-
I/O • 8-bit input/output port
Input/output in nibble units
• Input for port 0 interrupt
• Input for HOLD release
• Pull-up resistor :
P00 - P07
Provided/Not provided
(specified in nibble units)
• Output form (P00 – P07) :
CMOS/N-channel open drain
(specified in a bit)
PORT1
P10 - P17
I/O • 8-bit input/output port
Input/output can be specified in bit unit
• Other pin functions
• Output form :
CMOS/N-channel open drain
(specified in a bit)
Data line
D0 to D7
P10 SIO0 data output
P11 SIO0 data input/bus input/output
P12 SIO0 clock input/output
P13 SIO1 data output
P14 SIO1 data input/bus input/output
P15 SIO1 clock input/output
P16 Buzzer output
P17 Timer1 output (PWM output)
• 6-bit input port
• Other pin functions
P70 : INT0 input/HOLD release input/
N-channel Tr. output for watchdog
timer
P71 : INT1 input/HOLD release input
P72 : INT2 input/timer 0 event input
P73 : INT3 input with noise filter/timer 0
event input
PORT7
P70
Pull-up resistor :
Provided/Not provided
(specified in a bit)
(P70, P71, P72, P73)
* P74 , P75 don’t have the
pull-up resistor option.
Power for
programming
I/O
I
P71 - P73
PROM control
signals
DASEC(*2)
(*3)
OE
CE
(*4)
• Interrupt received form, vector address
rising falling rising high
low vector
&
level level
falling
INT0 enable enable disable enable enable 03H
INT1 enable enable disable enable enable 0BH
INT2 enable enable enable disable disable 13H
INT3 enable enable enable disable disable 1BH
I
I
P74 - P75
P74 : XT1 terminal for crystal oscillation
P75 : XT2 terminal for crystal oscillation
Port8
P80 – P87
• 8-bit input port
• Other function
AD input port (8 port pins)
I/O • 4-bit input/output port
• Other function
-
-
PORT9
P90 - P93
DA output port (4 port pins)
AD input port (4 port pins)
No.6692-7/21
LC86P7148
Function description
Pin name
I/O
Option
PROM mode
PORT A
(S0/PA0 –
S7/PA7)
I/O • Segment output terminal for LCD display
• Can be used as a general input/output port
-
-
-
Address
input
A0 to A7
Address
input
A8 to A13
PROM
control
signal input
•TA(*5)
Address input
•A14,A15
PORT B
I/O • Segment output terminal for LCD display
• Can be used as a general input/output port
(S8/PB0 –
S13/PB5)
PORT C
(S16/PC0 –
S23/PC7)
I/O • Segment output terminal for LCD display
• Can be used as a general input/output port
PORT D
I/O • Segment output terminal for LCD display
• Can be used as a general input/output port
-
-
-
(S24/PD0 –
S31/PD7)
PORT L
(COM0/PL0 –
COM3/PL3)
V1/PL4 –
V3/PL6
I/O • Common output terminal for LCD display
• Can be used as a general input port
I
• Bias power terminal for LCD drive
• Can be used as a general input port
Reset pin
I
I
-
-
RES
• Input pin for 32.768kHz crystal oscillation
In case of non use, connect to VDD.
• Other function
XT1/ P74
A general input port P74
XT2/P75
O
• Output pin for 32.768kHz crystal oscillation
In case of non use, should be left unconnected
-
( I ) • Other function
A general input port P75
CF1
CF2
I
O
Input pin for ceramic resonator oscillation
Output pin for ceramic resonator oscillation
-
-
* All of port options can be specified in bit unit except the pull-up resistor of port 0.
[Notes] • The VDD1, VDD2 and VDD3 terminals must be shorted electrically each other.
• The VSS1, VSS2 and VSS3 terminals must be shorted electrically each other.
*1 Connect like the following figure to reduce noise into a VDD terminals.
LSI
VDD1
Power
Supply
VDD2
VDD3
VSS1 VSS2 VSS3
*2 Memory select input for data security
*3 Output enable input
*4 Chip enable input
*5 TA ! PROM control signal input
No.6692-8/21
LC86P7148
1. Absolute Maximum Ratings at Ta=25°C, VSS=VSS1=VSS2=VSS3=0V
Ratings
typ.
Parameter
Symbol
Pins
Conditions
unit
V
VDD[V]
min.
-0.3
max.
+7.0
Supply voltage
VDDMAX VDD1, VDD2
VDD3
VDD1=VDD2=
VDD3
LCD display
voltage
Input voltage
VLCD
V1/PL6, V2/PL5
V3/PL4
•Ports 71, 72, 73
VDD1=VDD2=
VDD3
-0.3
-0.3
VDD
VI
VDD+0.3
•Ports 74, 75
•Port 8, Port L
• RES
Input/output
voltage
VIO
•Ports 0, 1
•Port 9
-0.3
VDD+0.3
•Ports A, B, C, D
Ports 0, 1
Ports A, B, C, D
Port 9
Ports 0, 1
Ports A, B
Ports C, D
Port 9
High
level
output current
Peak
output
IOPH(1)
IOPH(2)
IOPH(3)
•CMOS output
•At each pins
-4
-4
-4
-30
-20
-20
-20
mA
current
Total
output
current
Total all pins
Total all pins
Total all pins
Total all pins
At each pins
At each pins
At each pins
At each pins
Total all pins
Total all pins
Total all pins
Total all pins
Total all pins
Ta=-30 to+70°C
ΣIOAH(1)
ΣIOAH(2)
ΣIOAH(3)
ΣIOAH(4)
IOPL(1)
IOPL(2)
IOPL(3)
IOPL(4)
ΣIOAL(1)
ΣIOAL(2)
ΣIOAL(3)
ΣIOAL(4)
ΣIOAL(5)
Low
level
output current
current
Peak
output
Ports 0, 1
Ports A, B, C, D
Port 9
20
20
20
15
40
24
24
15
10
515
Port 70
Total
output
current
Ports 0, 1
Ports A, B
Ports C, D
Port 9
Port 70
QFP80E
Maximum power Pdmax
dissipation
mW
Operating
temperature
range
Topr
-30
-65
+70
°C
Storage
Tstg
+150
temperature
range
Notes •The QFP packages should be heat-soaked for 12 hours at 125°C immediately prior to mounting (This baking is called
pre-baking).
•After pre-baking a controlled environment must be maintained until soldering. The environment must be held at a
temperature of 30°C or less and a humidity level of 70% or less. Please solder within 24 hours.
No.6692-9/21
LC86P7148
2. Recommended Operating Range at Ta=-30°C to +70°C, VSS=VSS1=VSS2=VSS3=0V
Ratings
typ.
Parameter
Operating
supply voltage
range
Symbol
VDD(1)
Pins
Conditions
unit
V
VDD[V]
min.
4.5
max.
6.0
VDD1,VDD2,VDD3
0.98µs ≤ tCYC
≤ 400µs
3.9µs ≤ tCYC
≤ 400µs
RAMs and the
registers hold
voltage at HOLD
mode.
VDD(2)
VHD
2.5
2.0
6.0
6.0
Hold voltage
VDD1,VDD2,VDD3
Port 0
Input high
voltage
VIH(1)
VIH(2)
Output disable
4.5-6.0 0.4VDD
+0.9
4.5-6.0 0.75VDD
VDD
VDD
•Ports 1, 9
Output disable
•Ports A, B, C, D
•Ports 72, 73 (Schmitt)
•Port 70
Port input/interrupt
•Port 71
VIH(3)
Output N-channel
Tr. OFF
4.5-6.0 0.75VDD
VDD
• RES
(Schmitt)
VIH(4)
VIH(5)
Port 70
Watchdog timer
•Port 8
Output N-channel
Tr. OFF
Using as port
4.5-6.0 0.9VDD
4.5-6.0 0.75VDD
VDD
VDD
•Ports
Port 0
•Ports 1, 9
, 75
74
Input low
voltage
VIL(1)
VIL(2)
Output disable
Output disable
4.5-6.0
4.5-6.0
VSS
VSS
0.2VDD
0.25VDD
•Ports A, B, C, D
•Ports 72, 73 (Schmitt)
•Port 70
Port input/interrupt
•Port 71
VIL(3)
Output N-channel
Tr. OFF
4.5-6.0
VSS
0.25VDD
• RES (Schmitt)
Port 70
Watchdog timer
•Port 8
VIL(4)
VIL(5)
Output N-channel
Tr. OFF
Using as port
4.5-6.0
4.5-6.0
VSS
VSS
0.8VDD
-1.0
0.25VDD
•Ports
, 75
74
Operation
cycle time
tCYC
4.5-6.0
0.98
400
µs
No.6692-10/21
LC86P7148
Ratings
typ.
Parameter
Symbol
Pins
Conditions
unit
VDD[V]
4.5-6.0
min.
5.88
max.
6.12
Oscillation
frequency
range
FmCF(1)
CF1, CF2
CF1, CF2
•6MHz
(ceramic resonator
oscillation)
•Refer to figure 1
•3MHz
(ceramic resonator
oscillation)
•Refer to figure 1
RC oscillation
•32.768kHz
(crystal oscillation)
•Refer to figure 2
•6MHz
(ceramic resonator
oscillation)
•Refer to figure 3
•3MHz
6
MHz
(Note 1)
FmCF(2)
4.5-6.0
2.94
0.4
3
3.06
3.0
FmRC
FsXtal
4.5-6.0
4.5-6.0
0.8
32.768
XT1, XT2
CF1, CF2
kHz
ms
Oscillation
stabilizing
time period
tmsCF(1)
tmsCF(2)
tssXtal
4.5-6.0
4.5-6.0
4.5-6.0
0.05
0.10
0.5
(Note 1)
CF1, CF2
XT1, XT2
1.00
(ceramic resonator
oscillation)
•Refer to figure 3
•32.768kHz
s
(crystal oscillation)
•Refer to figure 3
(Note 1) The oscillation constant is shown on table 1 and table 2.
No.6692-11/21
LC86P7148
3. Electrical Characteristics at Ta=-30°C to +70°C, VSS=VSS1=VSS2=VSS3=0V
Ratings
typ.
Parameter
Input high
Symbol
IIH(1)
Pins
Conditions
unit
VDD[V]
4.5-6.0
min.
max.
1
•Port 1
•Output disable
•Pull-up MOS Tr.
OFF. VIN=VDD
(including the off-
leak current of the
output Tr.)
µA
current
•Port 0 without
pull-up MOS Tr.
IIH(2)
•Port 7 without
pull-up MOS Tr.
•Port 8
VIN=VDD
4.5-6.0
1
IIH(3)
IIH(4)
IIH(5)
Port 9
Ports A, B, C, D, L
VIN=VDD
VIN=VDD
VIN=VDD
4.5-6.0
4.5-6.0
4.5-6.0
1
1
1
RES
IIH(6)
Using as port
VIN=VDD
4.5-6.0
1
Ports 74 ,75
Input low
current
IIL(1)
•Port 1
•Port 0 without
pull-up MOS Tr.
•Output disable
•Pull-up MOS Tr.
OFF. VIN=VSS
(including the off-
leak current of the
output Tr.)
4.5-6.0
-1
-1
IIL(2)
•Port 7 without
pull-up MOS Tr.
•Port 8
VIN=VSS
4.5-6.0
IIL(3)
IIL(4)
IIL(5)
Port 9
Ports A, B, C, D, L
VIN=VSS
VIN=VSS
VIN=VSS
4.5-6.0
4.5-6.0
4.5-6.0
-1
-1
-1
RES
IIL(6)
Using as port
VIN=VSS
IOH=-1.0mA
4.5-6.0
4.5-6.0
4.5-6.0
-1
Ports 74 ,75
Output high
voltage
VOH(1)
VOH(2)
Ports 0,1 of
VDD-1
VDD-1
V
CMOS output
•Port 9 of CMOS
output
IOH=-1.0mA
•Ports A, B, C, D
of CMOS output
Ports 0, 1
Output low
voltage
VOL(1)
VOL(2)
VOL(3)
VOL(4)
VOL(5)
VOL(6)
VOL(7)
IOL=10mA
IOL=1.6mA
IOL=1mA
IOL=6mA
IOL=1.2mA
IOL=8mA
IOL=1.6mA
Continue.
4.5-6.0
4.5-6.0
4.5-6.0
4.5-6.0
4.5-6.0
4.5-6.0
4.5-6.0
1.5
0.4
0.4
1.5
0.4
1.5
0.4
Port 70
Port 9
Ports A, B, C, D
of CMOS output
No.6692-12/21
LC86P7148
Ratings
typ.
Parameter
Symbol
VODLS
Pins
S0 to S13,
Conditions
unit
V
VDD[V] min.
max.
±0.2
LCD output
regulation
•Deference voltage
to ideal value
4.5-6.0
0
S16 to S31
•VLCD, 2/3VLCD,
1/3VLCD
VODLC COM0 to COM3
•Deference voltage
to ideal value
4.5-6.0
0
±0.2
•VLCD, 2/3VLCD,
1/2VLCD, 1/3VLCD
Resistance at a
ladder resistor
•Resistance at a
ladder resistor
LCD ladder
resistor
RLCD(1)
RLCD(2)
4.5-6.0
4.5-6.0
60
30
kΩ
•1/2R mode
Pull-up MOS
Tr. resistor
Rpu
•Ports 0, 1
VOH=0.9VDD
4.5-6.0
4.5-6.0
15
40
70
•Ports A, B, C, D
•Ports 70, 71, 72, 73
•Ports 0, 1
Hysteresis
voltage
VHIS
Output disable
0.1VDD
V
•Ports 70, 71, 72, 73
• RES
Pin capacitance CP
All pins
•f=1MHz
4.5-6.0
10
pF
•Unmeasurement
terminals for the
input are set to
VSS level.
•Ta=25°C
4. Serial Input/Output Characteristics at Ta=-30°C to +70°C, VSS=VSS1=VSS2=VSS3=0V
Ratings
typ.
Parameter
Symbol
Pins
Conditions
unit
VDD[V] min.
max.
Cycle
Low Level
pulse width
High Level
pulse width
Cycle
tCKCY(1) SCK0,
Refer to figure 5.
4.5-6.0
4.5-6.0
2
1
tCYC
SCK1
tCKL(1)
tCKH(1)
4.5-6.0
1
2
tCKCY(2) SCK0,
•Use pull-up
resistor (1kΩ)
when open drain
output.
•Refer to figure 5.
•Data set-up to
SCK0, 1
4.5-6.0
4.5-6.0
SCK1
Low Level
pulse width
High Level
pulse width
Data set up time
tCKL(2)
tCKH(2)
tICK
1/2
tCKCY
1/2
4.5-6.0
4.5-6.0
tCKCY
•SI0,SI1
0.1
0.1
µs
•SB0,SB1
•Data hold from
SCK0, 1
Data hold time
tCKI
4.5-6.0
4.5-6.0
•Refer to figure 5.
•Use pull-up
resistor (1kΩ)
when open drain
output.
Output delay time
(Serial clock is
external clock)
tCKO(1)
•SO0, SO1
•SB0, SB1
7/12tCYC
+0.2
Output delay time
(Serial clock is
internal clock)
tCKO(2)
•Data hold from
SCK0, 1
•Refer to figure 5.
4.5-6.0
1/3tCYC
+0.2
No.6692-13/21
LC86P7148
5. Pulse Input Conditions at Ta=-30°C to +70°C, VSS=VSS1=VSS2=VSS3=0V
Ratings
typ.
Parameter
Symbol
Pins
Conditions
unit
VDD[V] min.
max.
High/low level tPIH(1)
•INT0, INT1
•INT2/T0IN
INT3/T0IN
(The noise rejection
clock is selected to
1/1.)
•Interrupt acceptable
•Timer0-countable
•Interrupt acceptable
•Timer0-countable
4.5-6.0
1
tCYC
pulse width
tPIL(1)
tPIH(2)
tPIL(2)
4.5-6.0
2
tPIH(3)
tPIL(3)
INT3/T0IN
•Interrupt acceptable
•Timer0-countable
4.5-6.0
4.5-6.0
4.5-6.0
32
(The noise rejection
clock is selected to
1/16.)
tPIH(4)
tPIL(4)
INT3/T0IN
•Interrupt acceptable
•Timer0-countable
128
200
(The noise rejection
clock is selected to
1/64.)
tPIL(5)
Reset acceptable
µs
RES
6. AD Converter Characteristics at Ta=-30°C to +70°C, VSS=VSS1=VSS2=VSS3=0V
Ratings
typ.
Parameter
Resolution
Absolute precision ETAD
(Note 2)
Symbol
NAD
Pins
Conditions
unit
VDD[V] min.
4.5-6.0
4.5-6.0
max.
±1.5
8
bit
LSB
Conversion time
tCAD
AD conversion time =
16 × tCYC
(ADCR2=0)
(Note 3)
4.5-6.0
15.68
(tCYC=
0.98µs)
65.28
(tCYC=
4.08µs)
µs
AD conversion time =
32 × tCYC
(ADCR2=1)
(Note 3)
31.36
(tCYC=
0.98µs)
130.56
(tCYC=
4.08µs)
Analog input
voltage range
Analog port
input current
VAIN
AN0 - AN11
4.5-6.0
VSS
-1
VDD
1
V
IAINH
IAINL
VAIN=VDD
VAIN=VSS
4.5-6.0
4.5-6.0
µA
(Note 2) Absolute precision excepts quantizing error (±1/2 LSB).
(Note 3) The conversion time means the time from executing the AD conversion instruction to setting the complete digital
conversion value to the register.
No.6692-14/21
LC86P7148
7. DA Converter Characteristics at Ta=-30°C to +70°C, VSS=VSS1=VSS2=VSS3=0V
Ratings
typ.
Parameter
Resolution
Symbol
NDA
Pins
Conditions
unit
VDD[V]
4.5-6.0
4.5-6.0
min.
max.
8
bit
%
Total error
8 bit mode
1.0
0.8
0.7
9 bit mode
9.5 bit mode
(Note 4)
8 bit mode
9 bit mode (1)
9 bit mode (2)
9.5 bit mode
(Note 5)
Settling time
Analog output
voltage range
tSAD
VAOUT
4.5-6.0
4.5-6.0
0.5
µs
V
DA0 to DA3
VSS
VSS
1/2VDD
1/3VDD
VDD
1/2VDD
VDD
2/3VDD
Output resistor
RODA
4.5-6.0
4
kΩ
(Note 4) Settling time means the time from executing the DA conversion instruction to generating the analog voltage output
corresponding to the digital data on the specific port.
(Note 5) DA data = 80H
8. Current Dissipation Characteristics at Ta=-30°C to +70°C, VSS=VSS1=VSS2=VSS3=0V
Ratings
typ.
15
Parameter
Symbol
Pins
Conditions
•FmCF=6MHz
Ceramic resonator
oscillation
unit
mA
VDD[V]
4.5-6.0
min.
max.
30
Current dissipation
during basic
operation
IDDOP(1)
VDD1=
VDD2=
VDD3
(Note 6)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/1 divided
IDDOP(2)
•FmCF=3MHz
Ceramic resonator
oscillation
4.5-6.0
6
15
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/2 divided
IDDOP(3)
IDDOP(4)
•FmCF=0Hz
4.5-6.0
4.5-6.0
4
4
13
(when oscillation stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
•1/2 divided
•FmCF=0Hz
9
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
crystal oscillation
•Internal RC
oscillation stops
•1/2 divided
Continue.
No.6692-15/21
LC86P7148
Ratings
typ.
Parameter
Symbol
Pins
Conditions
unit
mA
VDD[V]
4.5-6.0
min.
max.
11
Current dissipation
in HALT mode
IDDHALT(1)
VDD1=
VDD2=
VDD3
•HALT mode
6
•FmCF=6MHz
Ceramic resonator
oscillation
(Note 6)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/1 divided
IDDHALT(2)
•HALT mode
•FmCF=3MHz
Ceramic resonator
oscillation
4.5-6.0
2.2
9
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/2 divided
IDDHALT(3)
•HALT mode
FmCF=0Hz
4.5-6.0
500
1700
µA
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
•1/2 divided
IDDHALT(4)
IDDHALT(5)
IDDHOLD(1)
•HALT mode
FmCF=0Hz
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
crystal oscillation
•Internal RC
4.5-6.0
25
100
oscillation stops
•1/2 divided
HOLD mode
Current dissipation
in HOLD mode
VDD1=
VDD2=
VDD3
4.5-6.0
0.05
30
(Note 6)
(Note 6) The currents of the output transistors and the pull-up MOS transistors are ignored.
No.6692-16/21
LC86P7148
Table 1. Ceramic resonator oscillation recommended constant (main clock)
Oscillation type
Maker
Oscillator
C1
C2
6MHz ceramic resonator
oscillation
Murata
CSA6.00MG
CST6.00MGW
KBR-6.0MSA
PBRC6.00A(chip
type)
33pF
33pF
on chip
33pF
33pF
Kyocera
33pF
33pF
KBR-6.0MKS
PBRC6.00B(chip
type)
on chip
3MHz ceramic resonator
oscillation
Murata
CSA3.00MG
CST3.00MGW
KBR-3.0MS
33pF
on chip
47pF
33pF
47pF
Kyocera
* Both C1 and C2 must use K rank (±10%) and SL characteristics.
Table 2. Crystal oscillation guaranteed constant (sub clock)
Maker Oscillator C3
Oscillation type
C4
32.768kHz crystal
oscillation
(Notes) •Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation
pins as possible with the shortest possible pattern length.
•If you use other oscillators herein, we provide no guarantee for the characteristics.
CF1
CF2
XT1
XT2
X’tal
CF
C1
C2
C3
C4
Figure 1 Ceramic oscillation circuit
Figure 2 Crystal oscillation circuit
No.6692-17/21
LC86P7148
VDD
VDD limit
0V
Power supply
RES
Reset time
Internal RC
resonator oscillation
tmsCF
CF1, CF2
XT1, XT2
tssXtal
Instruction
execution mode
OCR6=1
Operation mode
Unfixed
Reset
Instruction execution mode
<Reset time and oscillation stable time>
HOLD release signal
Valid
Internal RC
resonator oscillation
tmsCF
CF1, CF2
XT1, XT2
tssXtal
Operation mode
HOLD
Instruction execution mode
<HOLD release signal and oscillation stable time>
Figure 3 Oscillation stable time
No.6692-18/21
LC86P7148
VDD
RRES
(Note) Fix the value of CRES, RRES that is
sure to reset until 200µs, after Power
supply has been over inferior limit of
supply voltage.
RES
CRES
Figure 4 Reset circuit
0.5VDD
<AC timing point>
tCKCY
VDD
tCKL
tCKH
SCK0
SCK1
1kΩ
tICK
tCKI
SI0
SI1
tCKO
50pF
SO0, SO1
SB0, SB1
<Timing>
<Test load>
Figure 5 Serial input / output test condition
tPIL
tPIH
Figure 6 Pulse input timing condition
No.6692-19/21
LC86P7148
Notice for use
• The construction of the one-time programmable microcomputer with a blank built-in PROM makes it impossible for SANYO
to completely factory-test it before shipping. To probe reliability of the programmed devices, the screening procedure shown
in the following figure should always be followed.
• It is not possible to perform a writing test on the blank PROM.. 100% yield, therefore, cannot be guaranteed.
• Keeping the dry packing
The environment must be held at a temperature of 30°C or less and a humidity level of 70% or less.
• After opening the packing
The preparation procedures shown in the following figure should always be followed prior to mounting the packages on the
substrate. Note that the QFP package should be heat-soaked for 12 hours at 125°C immediately prior to mounting (This
baking is called pre-baking). After pre-baking, a controlled environment must be maintained until soldering. The environment
must be held at a temperature of 30°C or less and a humidity level of 70% or less. Please solder within 24 hours.
a. Shipping with a blank PROM
b. Shipping with a programmed PROM
(Programming the data by Sanyo)
(Programming the data by yourself)
QFP
QFP
Writing data for program/Verifying
Baking before mounting
125 C, 12 hours
°
Recommended process of screening
Baking
Heat-soak
+1
150±5 C, 24
Hr
°
-0
Mounting
Reading ascertain of program
VDD=5±0.5V
Baking before mounting
125 C, 12 hours
°
Baking
Mounting
No.6692-20/21
LC86P7148
No.6692-21/21
PS
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