LC872G04A(MFP24S) [ONSEMI]
IC,MICROCONTROLLER,8-BIT,CMOS,SOP,24PIN,PLASTIC;
| 型号： | LC872G04A(MFP24S) |
| 厂家： | 
ONSEMI |
| 描述： | IC,MICROCONTROLLER,8-BIT,CMOS,SOP,24PIN,PLASTIC 微控制器 光电二极管 外围集成电路 |
| 文件： | 总27页 (文件大小：168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENA1400A
LC872G08A
LC872G06A
LC872G04A
CMOS IC
8K/6K/4K-byte ROM and 256-byte RAM integrated
8-bit 1-chip Microcontroller
Overview
The SANYO LC872G08A/06A/04A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus
cycle time of 83.3ns, integrates on a single chip a number of hardware features such as 8K/6K/4K-byte ROM, 256-byte
RAM, sophisticated 16-bit timers/counters (may be divided into 8-bit timers), a 16-bit timer/counter (may be divided into
8-bit timers/counters or 8-bit PWMs), two 8-bit timers with a prescaler, a base timer serving as a time-of-day clock, a
high-speed clock counter, a synchronous SIO interface, an asynchronous/synchronous SIO interface, a UART interface
(full duplex), a 12-bit/8-bit 8-channel AD converter, a system clock frequency divider, an internal reset and a 18-source
10-vector interrupt feature.
Features
ROM
• 8192 × 8 bits (LC872G08A)
• 6144 × 8 bits (LC872G06A)
• 4096 × 8 bits (LC872G04A)
RAM
• 256 × 9 bits (LC872G08A/06A/04A)
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer
's products or
equipment.
Ver. 0.41
11310HKIM 20091224-S00005 No.A1400-1/27
LC872G08A/06A/04A
Minimum Bus Cycle
• 83.3ns (12MHz at V =2.7V to 5.5V)
DD
• 100ns (10MHz at V =2.2V to 5.5V)
DD
• 250ns (4MHz at V =1.8V to 5.5V)
DD
Note: The bus cycle time here refers to the ROM read speed.
Minimum Instruction Cycle Time
• 250ns (12MHz at V =2.7V to 5.5V)
DD
• 300ns (10MHz at V =2.2V to 5.5V)
DD
• 750ns (4MHz at V =1.8V to 5.5V)
DD
Ports
• Normal withstand voltage I/O ports
Ports I/O direction can be designated in 1-bit units
Ports I/O direction can be designated in 4-bit units
• Dedicated oscillator ports/input ports
• Reset pin
11 (P1n, P20, P21, P70)
8 (P0n)
2 (CF1/XT1, CF2/XT2)
1 (
RES
)
• Power pins
2 (V 1, V 1)
SS DD
Timers
• Timer 0: 16-bit timer/counter with a capture register.
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register)
+ 8-bit counter (with an 8-bit capture register)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)
Mode 3: 16-bit counter (with a 16-bit capture register)
• Timer 1: 16-bit timer/counter that supports PWM/toggle outputs
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/
counter with an 8-bit prescaler (with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also possible from the lower-order 8 bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs)
(The lower-order 8 bits can be used as PWM)
• Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts are programmable in 5 different time schemes
High-Speed Clock Counter
• Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz).
• Can generate output real time.
SIO
• SIO0: 8-bit Synchronous serial interface
1) LSB first/MSB first mode selectable
2)
transfer clock cycle=4/3tCYC)
Built-in 8-bit baudrate generator (maximum
• SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
No.A1400-2/27
LC872G08A/06A/04A
UART
• Full duplex
• 7/8/9 bit data bits selectable
• 1 stop bit (2 bits in continuous data transmission)
• Built-in baudrate generator
AD Converter: 12 bits/8 bits × 8 channels
• 12 bits/8 bits AD converter resolution selectable
Remote Control Receiver Circuit (sharing pins with P15, SCK1, INT3, and T0IN)
• Noise rejection function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC)
Clock Output Function
• Can generate clock outputs with a frequency of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 of the source clock selected as
the system clock.
• Can generate the source clock for the subclock
Watchdog Timer
• External RC watchdog timer
• Interrupt and reset signals selectable
Interrupts
• 18 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of
the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
1
Vector Address
00003H
Level
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
Interrupt Source
INT0
2
0000BH
00013H
INT1
3
INT2/T0L/INT4
INT3/base timer
T0H
4
0001BH
00023H
5
6
0002BH
00033H
T1L/T1H
7
SIO0/UART1 receive
SIO1/UART1 transmit
ADC/T6/T7
Port 0
8
0003BH
00043H
9
10
0004BH
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
Subroutine Stack Levels: 128levels (The stack is allocated in RAM.)
High-speed Multiplication/Division Instructions
• 16 bits × 8 bits
• 24 bits × 16 bits
• 16 bits ÷ 8 bits
• 24 bits ÷ 16 bits
(5 tCYC execution time)
(12 tCYC execution time)
(8 tCYC execution time)
(12 tCYC execution time)
No.A1400-3/27
LC872G08A/06A/04A
Oscillation Circuits
• Internal oscillation circuits
Low-speed RC oscillation circuit :
For system clock (100kHz)
Medium-speed RC oscillation circuit : For system clock (1MHz)
Multifrequency RC oscillation circuit : For system clock (8MHz)
• External oscillation circuits
Hi-speed CF oscillation circuit:
For system clock, with internal Rf
Low speed crystal oscillation circuit:
For low-speed system clock, with internal Rf
1) The CF and crystal oscillation circuits share the same pins. The active circuit is selected under program control.
2) Both the CF and crystal oscillator circuits stop operation on a system reset. When the reset is released, only the
CF oscillation circuit resumes operation.
System Clock Divider Function
• Can run on low current.
• The minimum instruction cycle selectable from 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs, and
76.8μs (at a main clock rate of 10MHz).
Internal Reset Function
• Power-on reset (POR) function
1) POR reset is generated only at power-on time.
2) The POR release level can be selected from 8 levels (1.67V, 1.97V, 2.07V, 2.37V, 2.57V, 2.87V, 3.86V, and
4.35V) through option configuration.
• Low-voltage detection reset (LVD) function
1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls
below a certain level.
2) The use/disuse of the LVD function and the low voltage threshold level (7 levels: 1.91V, 2.01V, 2.31V, 2.51V,
2.81V, 3.79V, 4.28V).
Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) There are three ways of resetting the HALT mode.
(1) Setting the reset pin to the low level
(2) System resetting by watchdog timer or low-voltage detection
(3) Occurrence of an interrupt
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, and crystal oscillators automatically stop operation.
2) There are four ways of resetting the HOLD mode.
(1) Setting the reset pin to the lower level.
(2) System resetting by watchdog timer or low-voltage detection
(3) Having an interrupt source established at either INT0, INT1, INT2 or INT4
* INT0 and INT1 HOLD mode reset is available only when level detection is set.
(4) Having an interrupt source established at port 0.
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer.
1) The RC oscillator automatically stop operation.
2) The state of crystal oscillations established when the X'tal HOLD mode is entered is retained.
3) There are five ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level.
(2) System resetting by watchdog timer or low-voltage detection.
(3) Having an interrupt source established at either INT0, INT1, INT2 or INT4
* INT0 and INT1 HOLD mode reset is available only when level detection is set.
(4) Having an interrupt source established at port 0.
(5) Having an interrupt source established in the base timer circuit.
Note: Available only when X’tal oscillation is selected.
No.A1400-4/27
LC872G08A/06A/04A
Package Form
• MFP24S (300mil): Lead-/Halogen-free type
• SSOP24 (225mil): Lead-/Halogen-free type
Development Tools
• On-chip-debugger: TCB87 TypeB + LC87D2G08A
: TCB87 TypeB + LC87F2G08A
: TCB87 TypeC (3 wire version) + LC87D2G08A
: TCB87 TypeC (3 wire version) + LC87F2G08A
Note: LC87F2G08A has an On-chip debugger but its function is limited.
Flash ROM Version
• LC87F2G08A
Package Dimensions
unit : mm (typ)
Package Dimensions
unit : mm (typ)
3112B
3287
12.5
6.5
24
13
24
13
12
1
1
12
1.0
0.15
0.35
0.5
0.22
0.15
(0.75)
(0.5)
SANYO : MFP24S(300mil)
SANYO : SSOP24(225mil)
No.A1400-5/27
LC872G08A/06A/04A
Pin Assignment
P70/INT0/T0LCP/AN8
RES
1
2
3
4
5
6
7
8
9
24
23
22
21
20
P07/T7O
P06/AN6/T6O
P05/AN5/CKO
P04/AN4
V
1
SS
CF1/XT1
CF2/XT2
P03/AN3
V
1
DD
19
P02/AN2
LC872G08A
LC872G06A
LC872G04A
P10/SO0
P11/SI0/SB0
18
P01/AN1
17
P00/AN0
P12/SCK0
16
P21/URX/INT4/T1IN
P20/UTX/INT4/T1IN
P17/T1PWMH/BUZ/INT1/T0HCP
P16/T1PWML/INT2/T0IN
P13/SO1
10
11
12
15
14
13
P14/SI1/SB1
P15/SCK1/INT3/T0IN
Top view
SANYO: MFP24S (300mil) “Lead-/Halogen-free type”
SANYO: SSOP24 (225mil) “Lead-/Halogen-free type”
MFP24S
MFP24S
NAME
NAME
SSOP24
1
SSOP24
P70/INT0/T0LCP/AN8
RES
13
14
15
16
17
18
19
20
21
22
23
24
P16/T1PWML/INT2/T0IN
P17/T1PWMH/BUZ/INT1/T0HCP
P20/UTX/INT4/T1IN
P21/URX/INT4/T1IN
P00/AN0
2
3
V
1
SS
4
CF1/XT1
CF2/XT2
5
6
V
1
P01/AN1
DD
7
P10/SO0
P11/SI0/SB0
P12/SCK0
P02/AN2
8
P03/AN3
9
P04/AN4
10
11
12
P13/SO1
P05/AN5/CKO
P06/AN6/T6O
P14/SI1/SB1
P15/SCK1/INT3/T0IN
P07/T7O
No.A1400-6/27
LC872G08A/06A/04A
System Block Diagram
Interrupt control
IR
PLA
Flash ROM
Standby control
CF/
X'tal
SRC
RC
PC
MRC
ACC
RES
B register
WDT
Reset circuit
(LVD/POR)
C register
SIO0
SIO1
Bus interface
Port 0
ALU
PSW
RAR
Timer 0
Port 1
Port 2
Port 7
ADC
Timer 1
RAM
Timer 6
Timer 7
Stack pointer
INT0 to 2 INT3
(Noise filter)
Base timer
UART1
Port 2 INT4
No.A1400-7/27
LC872G08A/06A/04A
Pin Description
Pin Name
I/O
Description
Option
No
V
V
1
-
- Power supply pin
+ Power supply pin
• 8-bit I/O port
SS
1
-
No
DD
Port 0
I/O
• I/O specifiable in 4-bit units
P00 to P07
• Pull-up resistors can be turned on and off in 4-bit units.
• HOLD reset input
• Port 0 interrupt input
Yes
• Pin functions
P05: System clock output
P06: Timer 6 toggle output
P07: Timer 7 toggle output
P00(AN0) to P06(AN6): AD converter input
Port 1
I/O
• 8-bit I/O port
• I/O specifiable in 1-bit units
P10 to P17
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P10: SIO0 data output
P11: SIO0 data input/bus I/O
P12: SIO0 clock I/O
P13: SIO1 data output
P14: SIO1 data input / bus I/O
P15: SIO1 clock I/O / INT3 input (with noise filter) / timer 0 event input / timer 0H capture input
P16: Timer 1PWML output / INT2 input/HOLD reset input/timer 0 event input / timer 0L capture
Yes
input
P17: Timer 1PWMH output / beeper output / INT1 input / HOLD reset input / timer 0H capture
input
Interrupt acknowledge type
Rising &
Rising
Falling
H level
L level
Falling
disable
enable
enable
INT1
INT2
INT3
enable
enable
enable
enable
enable
enable
enable
disable
disable
enable
disable
disable
Port 2
I/O
• 2-bit I/O port
• I/O specifiable in 1-bit units
P20 to P21
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P20: UART transmit
P21: UART receive
P20 to P21: INT4 input / HOLD reset input / timer 1 event input / timer 0L capture input / timer
Yes
0H capture input
Interrupt acknowledge types
Rising &
Rising
Falling
H level
disable
L level
disable
Falling
enable
INT4
enable
enable
Continued on next page.
No.A1400-8/27
LC872G08A/06A/04A
Continued from preceding page.
Pin Name
Port 7
I/O
I/O
Description
Option
• 1-bit I/O port
• I/O specifiable in 1-bit units
P70
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P70: INT0 input / HOLD reset input / timer 0L capture input / watchdog timer output
P70(AN8): AD converter input
Interrupt acknowledge types
Rising &
No
Rising
Falling
H level
enable
L level
enable
Falling
disable
INT0
enable
enable
RES
I/O
I
External reset input / internal reset output
No
No
CF1/XT1
• Ceramic resonator or 32.768kHz crystal oscillator input pin
• Pin function
General-purpose input port
CF2/XT2
I/O
• Ceramic resonator or 32.768kHz crystal oscillator output pin
• Pin function
No
General-purpose input port
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Option selected in
Port Name
Option type
Output type
Pull-up resistor
units of
1 bit
P00 to P07
1
2
CMOS
Programmable (Note 1)
No
Nch-open drain
CMOS
P10 to P17
P20 to P21
P70
1 bit
1 bit
-
1
Programmable
Programmable
Programmable
Programmable
Programmable
2
Nch-open drain
CMOS
1
2
Nch-open drain
Nch-open drain
No
Note 1: The control of the presence or absence of the programmable pull-up resistors for port 0 and the switching
between low-and high-impedance pull-up connection is exercised in nibble (4-bit) units (P00 to 03 or
P04 to 07).
User Option Table
Mask
Version *1
{
Flash
Version
{
Option Name
Option Type
Option Selected in Units of
1 bit
Option Selection
CMOS
Port output form
P00 to P07
Nch-open drain
CMOS
P10 to P17
P20 to P21
-
{
{
{
{
{
{
1 bit
Nch-open drain
CMOS
1 bit
Nch-open drain
00000h
Program start
address
×
-
-
*2
01E00h
Low-voltage
detection reset
function
Detect function
{
Enable:Use
Disable:Not Used
7-level
Detect level
{
{
{
{
-
-
Power-on reset
function
Power-On reset level
8-level
*1: Mask option selection – No change possible after mask is completed.
*2: Program start address of the mask version is 00000h.
No.A1400-9/27
LC872G08A/06A/04A
Recommended Unused Pin Connections
Recommended Unused Pin Connections
Port Name
Board
Software
P00 to P07
Open
Open
Open
Open
Output low
Output low
P10 to P17
P20 to P21
P70
Output low
Output low
CF1/XT1
CF2/XT2
Pulled low with a 100kΩ resistor or less
Pulled low with a 100kΩ resistor or less
General-purpose input port
General-purpose input port
Notes on CF1/XT1 and CF2/XT2 pins
• When using as general-purpose input ports
Since the CF1/XT1 and CF2/XT2 pins are configured as CF oscillator pins at system reset time, it is necessary to
add a current limiting resistor of 1kΩ or greater to the CF2/XT2 pin in series when using them as general-purpose
input pins.
• Differences between flash and mask ROM version
System Reset Time State
Set high via the internal Rf resistor
Set high
After System Reset is Released
CF oscillation state
CF1/XT1
CF2/XT2
CF1/XT1
CF2/XT2
Flash ROM version
LC87F2G08A
CF oscillation state
CF oscillation state
CF oscillation state
Set low via the internal Rf resistor
Set low
Mask ROM version
LC872G08A/06A/04A
Power Pin Treatment Recommendations (V 1, V 1)
DD SS
Connect bypass capacitors that meet the following conditions between the V 1 and V 1 pins:
DD SS
• Connect among the V 1 and V 1 pins and bypass capacitors C1 and C2 with the shortest possible heavy lead
DD SS
wires, making sure that the impedances between the both pins and the bypass capacitors are as equal as possible
(L1=L1’, L2=L2’).
• Connect a large-capacity capacitor C1 and a small-capacity capacitor C2 in parallel.
The capacitance of C2 should be approximately 0.1μF.
L2
L1
V
1
SS
C2
C1
V
1
DD
L1’
L2’
No.A1400-10/27
LC872G08A/06A/04A
Absolute Maximum Ratings at Ta = 25°C, V 1 =0V
SS
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
-0.3
unit
V
DD
Maximum supply
voltage
V
max
V 1
DD
DD
+6.5
+0.3
+0.3
Input voltage
V
V
CF1, CF2
-0.3
-0.3
V
V
I
DD
Input/output
voltage
Ports 0, 1, 2,
P70
IO
DD
Peak output
current
IOPH
IOMH
Ports 0, 1, 2
CMOS output select
Per 1 applicable pin
CMOS output select
Per 1 applicable pin
-10
Mean output
current
Ports 0, 1, 2
-7.5
(Note 1-1)
Total output
current
ΣIOAH(1)
ΣIOAH(2)
P10 to P14
Total of all applicable pins
Total of all applicable pins
-20
-20
-25
Ports 0, 2
P15 to P17
Ports 0, 1, 2
ΣIOAH(3)
Total of all applicable pins
Per 1 applicable pin
Peak output
current
IOPL(1)
P02 to P07
Ports 1, 2
P00, P01
20
mA
IOPL(2)
IOPL(3)
IOML(1)
Per 1 applicable pin
Per 1 applicable pin
Per 1 applicable pin
30
10
P70
Mean output
current
P02 to P07
Ports 1, 2
P00, P01
15
(Note 1-1)
IOML(2)
IOML(3)
ΣIOAL(1)
ΣIOAL(2)
Per 1 applicable pin
20
7.5
50
P70
Per 1 applicable pin
Total output
current
P10 to P14
Total of all applicable pins
Total of all applicable pins
Port 0, 2,
60
P15 to P17
Ports 0, 1, 2
ΣIOAL(3)
ΣIOAL(4)
Pd max(1)
Total of all applicable pins
Total of all applicable pins
70
P70
7.5
Power
MFP24S(300mil)
Ta=-40 to +85°C
Package only
129
229
111
334
+85
Dissipation
Pd max(2)
Ta=-40 to +85°C
Package with thermal
resistance board
(Note 1-2)
mW
Pd max(3)
Pd max(4)
SSOP24(225mil)
Ta=-40 to +85°C
Package only
Ta=-40 to +85°C
Package with thermal
resistance board
(Note 1-2)
Operating ambient
temperature
Topr
Tstg
-40
-55
°C
Storage ambient
temperature
+125
Note 1-1: The mean output current is a mean value measured over 100ms.
Note 1-2: SEMI standards thermal resistance board (size: 76.1×114.3×1.6tmm, glass epoxy) is used.
No.A1400-11/27
LC872G08A/06A/04A
Allowable Operating Conditions at Ta = -40°C to +85°C, V 1 = 0V
SS
Specification
typ max
Parameter
Symbol
Pin/Remarks
1
DD
Conditions
V
[V]
min
2.7
unit
DD
Operating
V
V
V
(1)
V
0.245μs ≤ tCYC ≤ 200μs
0.294μs ≤ tCYC ≤ 200μs
0.735μs ≤ tCYC ≤ 200μs
5.5
5.5
5.5
DD
supply voltage
(2)
2.2
1.8
DD
(3)
DD
Memory
VHD
V
1
RAM and register contents sustained
in HOLD mode.
DD
sustaining
supply voltage
High level
1.6
V
(1)
Ports 1, 2,
P70 port input/
interrupt side
Ports 0
IH
input voltage
1.8 to 5.5 0.3V +0.7
DD
V
DD
V
V
(2)
(3)
1.8 to 5.5 0.3V +0.7
DD
V
V
V
IH
DD
DD
DD
V
Port 70 watchdog
timer side
IH
1.8 to 5.5
0.9V
DD
V
V
(4)
CF1,
RES
1.8 to 5.5
4.0 to 5.5
0.75V
IH
DD
Low level
(1)
Ports 1, 2,
P70 port input/
interrupt side
Ports 0
V
0.1V +0.4
DD
IL
SS
SS
input voltage
1.8 to 4.0
V
0.2V
DD
V
(2)
4.0 to 5.5
1.8 to 4.0
V
V
0.15V +0.4
DD
IL
SS
0.2V
DD
SS
V
V
(3)
(4)
Port 70 watchdog
timer side
IL
1.8 to 5.5
V
V
0.8V -1.0
DD
SS
CF1,
RES
1.8 to 5.5
2.7 to 5.5
2.2 to 5.5
1.8 to 5.5
2.7 to 5.5
0.25V
DD
IL
SS
Instruction
cycle time
tCYC
0.245
0.294
0.735
0.1
200
200
200
12
(Note 2-1)
μs
External
FEXCF
CF1
• CF2 pin open
system clock
frequency
• System clock frequency division
ratio=1/1
1.8 to 5.5
3.0 to 5.5
2.0 to 5.5
0.1
0.2
0.2
4
24.4
8
• External system clock duty=50 5%
• CF2 pin open
MHz
• System clock frequency division
ratio=1/2
• External system clock duty=50 5%
12MHz ceramic oscillation.
See Fig. 1.
Oscillation
frequency
range
FmCF(1)
FmCF(2)
FmCF(3)
CF1, CF2
CF1, CF2
CF1, CF2
2.7 to 5.5
2.2 to 5.5
12
10MHz ceramic oscillation.
See Fig. 1.
10
4
(Note 2-2)
4MHz ceramic oscillation.
CF oscillation normal amplifier size selected.
(CFLAMP=0) See Fig. 1.
4MHz ceramic oscillation.
CF oscillation low amplifier size
selected. (CFLAMP=1)
See Fig. 1.
1.8 to 5.5
2.2 to 5.5
2.7 to 5.5
MHz
4
FmMRC
Frequency variable RC oscillation.
1/2 frequency division ratio.
(RCCTD=0) (Note 2-3)
Internal medium-speed RC oscillation
7.44
8.0
8.56
FmRC
FmSRC
FsX’tal
1.8 to 5.5
1.8 to 5.5
0.5
50
1.0
2.0
Internal low-speed RC oscillation
100
200
kHz
XT1, XT2
32.768kHz crystal oscillation
See Fig. 1.
1.8 to 5.5
32.768
Note 2-1: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at
a division ratio of 1/2.
Note 2-2: See Tables 1 and 2 for the oscillation constants.
Note 2-3: When switching the system clock, allow an oscillation stabilization time of 100μs or longer after the
multifrequency RC oscillator circuit transmits from the "oscillation stopped" to "oscillation enabled" state.
No.A1400-12/27
LC872G08A/06A/04A
Electrical Characteristics at Ta = -40°C to +85°C, V 1 = 0V
SS
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
unit
DD
High level input
current
I
(1)
Ports 0, 1, 2,
Output disabled
Pull-up resistor off
=V
IH
P70,
RES
V
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1
IN DD
(Including output Tr's off leakage
current)
I
I
(2)
IH
CF1
V
=V
15
IN DD
μA
Low level input
current
(1)
Ports 0, 1, 2,
Output disabled
IL
P70,
Pull-up resistor off
RES
V
=V
-1
IN SS
(Including output Tr's off leakage
current)
I
(2)
CF1
V
I
=V
1.8 to 5.5
4.5 to 5.5
2.7 to 5.5
1.8 to 5.5
4.5 to 5.5
2.7 to 5.5
1.8 to 5.5
2.7 to 5.5
1.8 to 5.5
4.5 to 5.5
2.7 to 5.5
1.8 to 5.5
-15
-1
IL
IN SS
High level output
voltage
V
V
V
V
V
V
V
V
V
V
V
(1)
Ports 0, 1, 2
Ports 0, 1, 2
=-1mA
V
OH
OH
OH
OH
DD
(2)
(3)
I
I
I
I
I
I
I
I
I
I
=-0.35mA
V
V
-0.4
OH
DD
=-0.15mA
-0.4
OH
DD
Low level output
voltage
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
=10mA
=1.4mA
=0.8mA
=1.4mA
=0.8mA
=25mA
=4mA
1.5
0.4
0.4
0.4
0.4
1.5
0.4
0.4
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
V
P70
P00, P01
=2mA
Pull-up resistance
Rpu(1)
Rpu(2)
Rpu(3)
Ports 0, 1, 2
P70
V
=0.9V
OH
DD
4.5 to 5.5
1.8 to 4.5
15
18
35
80
When Port 0 selected
50
230
low-impedance pull-up.
kΩ
Port 0
V
=0.9V
OH
DD
When Port 0 selected
1.8 to 5.5
100
210
400
high-impedance pull-up.
Hysteresis voltage
Pin capacitance
VHYS(1)
VHYS(2)
CP
Ports 1, 2, P70,
RES
2.7 to 5.5
1.8 to 2.7
0.1V
DD
V
0.07V
DD
All pins
For pins other than that under test:
V
=V
IN SS
1.8 to 5.5
10
pF
f=1MHz
Ta=25°C
No.A1400-13/27
LC872G08A/06A/04A
Serial I/O Characteristics at Ta = -40°C to +85°C, V 1 = 0V
SS
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Specification
Pin/
Parameter
Symbol
Conditions
• See Fig. 5.
Remarks
V
[V]
min
typ
max
unit
DD
Frequency
tSCK(1)
SCK0(P12)
2
1
Low level
tSCKL(1)
tSCKH(1)
1.8 to 5.5
pulse width
High level
pulse width
Frequency
tCYC
1
tSCK(2)
SCK0(P12)
• CMOS output selected
• See Fig. 5.
4/3
Low level
pulse width
tSCKL(2)
1/2
1/2
1.8 to 5.5
1.8 to 5.5
tSCK
High level
tSCKH(2)
tsDI(1)
pulse width
Data setup time
SB0(P11),
SI0(P11)
• Must be specified with
respect to rising edge of
SIOCLK.
0.05
0.05
Data hold time
thDI(1)
• See Fig. 5.
Output delay
time
tdD0(1)
SO0(P10),
SB0(P11)
• Continuous data
transmission/reception mode
(Note 4-1-2)
(1/3)tCYC
+0.08
μs
tdD0(2)
tdD0(3)
• Synchronous 8-bit mode
(Note 4-1-2)
1tCYC
+0.08
1.8 to 5.5
(Note 4-1-2)
(1/3)tCYC
+0.08
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of
output state change in open drain output mode. See Fig. 5.
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Specification
Pin/
Parameter
Frequency
Symbol
tSCK(3)
Conditions
Remarks
V
[V]
min
typ
max
unit
DD
SCK1(P15)
See Fig. 5.
2
1
1
2
Low level
tSCKL(3)
tSCKH(3)
tSCK(4)
tSCKL(4)
tSCKH(4)
tsDI(2)
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
pulse width
High level
pulse width
Frequency
tCYC
SCK1(P15)
• CMOS output selected
• See Fig. 5.
Low level
pulse width
High level
1/2
1/2
tSCK
pulse width
Data setup time
SB1(P14),
SI1(P14)
• Must be specified with respect
to rising edge of SIOCLK.
• See Fig. 5.
0.05
0.05
Data hold time
thDI(2)
tdD0(4)
μs
Output delay time
SO1(P13),
SB1(P14)
• Must be specified with respect
to falling edge of SIOCLK.
• Must be specified as the time
to the beginning of output state
change in open drain output
mode.
(1/3)tCYC
+0.08
1.8 to 5.5
• See Fig. 5.
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
No.A1400-14/27
LC872G08A/06A/04A
Pulse Input Conditions at Ta = -40°C to +85°C, V 1 = 0V
SS
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
unit
tCYC
μs
DD
High/low level
pulse width
tPIH(1)
tPIL(1)
INT0(P70),
• Interrupt source flag can be set.
• Event inputs for timer 0 or 1 are
enabled.
INT1(P17),
1.8 to 5.5
1
2
INT2(P16),
INT4(P20, P21)
INT3(P15) when noise
filter time constant is
1/1
tPIH(2)
tPIL(2)
• Interrupt source flag can be set.
• Event inputs for timer 0 are
enabled.
1.8 to 5.5
1.8 to 5.5
tPIH(3)
tPIL(3)
INT3(P15) when noise
filter time constant is
1/32
• Interrupt source flag can be set.
• Event inputs for timer 0 are
nabled.
64
tPIH(4)
tPIL(4)
INT3(P15) when noise
filter time constant is
1/128
• Interrupt source flag can be set.
• Event inputs for timer 0 are
enabled.
1.8 to 5.5
1.8 to 5.5
256
200
RES
tPIL(5)
• Resetting is enabled.
No.A1400-15/27
LC872G08A/06A/04A
AD Converter Characteristics at V 1 = 0V
SS
<12bits AD Converter Mode/Ta = -40°C to +85°C >
Specification
typ max
12
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
unit
bit
DD
Resolution
N
AN0(P00) to
AN6(P06),
AN8(P70)
2.4 to 5.5
3.0 to 5.5
2.4 to 3.6
4.0 to 5.5
3.0 to 5.5
Absolute
accuracy
ET
(Note 6-1)
(Note 6-1)
16
20
LSB
Conversion time
TCAD
• See Conversion time calculation
32
64
115
115
formulas. (Note 6-2)
μs
• See Conversion time calculation
2.4 to 3.6
2.4 to 5.5
410
425
formulas. (Note 6-2)
Analog input
voltage range
Analog port
input current
VAIN
V
V
V
SS
DD
IAINH
IAINL
VAIN=V
DD
2.4 to 5.5
2.4 to 5.5
1
μA
VAIN=V
SS
-1
<8bits AD Converter Mode/Ta = -40°C to +85°C >
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
unit
bit
DD
Resolution
N
AN0(P00) to
AN6(P06)
AN8(P70)
2.4 to 5.5
2.4 to 5.5
8
Absolute
ET
(Note 6-1)
1.5
LSB
accuracy
Conversion time
TCAD
• See Conversion time calculation
4.0 to 5.5
3.0 to 5.5
20
40
90
90
formulas. (Note 6-2)
μs
• See Conversion time calculation
2.4 to 3.6
2.4 to 5.5
250
265
formulas. (Note 6-2)
Analog input
voltage range
Analog port
input current
VAIN
V
V
V
SS
DD
IAINH
IAINL
VAIN=V
DD
2.4 to 5.5
2.4 to 5.5
1
μA
VAIN=V
SS
-1
Conversion time calculation formulas:
12bits AD Converter Mode: TCAD(Conversion time) = ((52/(AD division ratio))+2)×(1/3)×tCYC
8bits AD Converter Mode: TCAD(Conversion time) = ((32/(AD division ratio))+2)×(1/3)×tCYC
AD conversion time
(TCAD)
External
oscillation
(FmCF)
Operating supply
voltage range
AD division
ratio
System division ratio
(SYSDIV)
Cycle time
(tCYC)
(V
)
(ADDIV)
12bit AD
8bit AD
DD
4.0V to 5.5V
3.0V to 5.5V
4.0V to 5.5V
3.0V to 5.5V
3.0V to 5.5V
2.4V to 3.6V
1/1
1/1
1/1
1/1
1/1
1/1
250ns
250ns
300ns
300ns
750ns
750ns
1/8
1/16
1/8
34.8μs
69.5μs
41.8μs
83.4μs
104.5μs
416.5μs
21.5μs
42.8μs
25.8μs
51.4μs
64.5μs
256.5μs
CF-12MHz
CF-10MHz
CF-4MHz
1/16
1/8
1/32
Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must
be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog
input channel.
Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the
time the conversion results register(s) are loaded with a complete digital conversion value corresponding to
the analog input value.
The conversion time is 2 times the normal-time conversion time when:
• The first AD conversion is performed in the 12-bit AD conversion mode after a system reset.
• The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit
conversion mode.
No.A1400-16/27
LC872G08A/06A/04A
Power-on Reset (POR) Characteristics at Ta = -40°C to +85°C, V 1 = 0V
SS
Specification
Parameter
Symbol
Pin/Remarks
Conditions
Option selected
voltage
min
1.55
typ max
unit
POR release
voltage
PORRL
• Select from option.
1.67V
1.97V
2.07V
2.37V
2.57V
2.87V
3.86V
4.35V
1.67
1.97
2.07
2.37
2.57
2.87
3.86
4.35
1.79
2.09
2.19
2.49
2.69
2.99
3.99
4.49
(Note 7-1)
1.85
1.95
2.25
2.45
2.75
3.73
4.21
V
Detection voltage
unknown state
Power supply rise
time
POUKS
PORIS
• See Fig. 7.
0.7
0.95
100
(Note 7-2)
• Power supply rise
time from 0V to 1.6V.
ms
Note7-1: The POR release level can be selected out of 8 levels only when the LVD reset function is disabled.
Note7-2: POR is in an unknown state before transistors start operation.
Low Voltage Detection Reset (LVD) Characteristics at Ta = -40°C to +85°C, V 1=0V
SS
Specification
Parameter
Symbol
Pin/Remarks
Conditions
Option selected
voltage
min
1.81
typ
1.91
max
2.01
unit
LVD reset voltage
(Note 8-2)
LVDET
• Select from option.
(Note 8-1)
1.91V
2.01V
2.31V
2.51V
2.81V
3.79V
4.28V
1.91V
2.01V
2.31V
2.51V
2.81V
3.79V
4.28V
1.91
2.21
2.41
2.71
3.69
4.18
2.01
2.31
2.51
2.81
3.79
4.28
55
2.11
2.41
2.61
2.91
3.89
4.38
(Note 8-3)
• See Fig. 8.
V
LVD hysteresys
width
LVHYS
55
55
mV
55
60
65
65
Detection voltage
unknown state
LVUKS
TLVDW
• See Fig. 8.
(Note 8-4)
0.7
0.95
V
Low voltage
• LVDET-0.5V
• See Fig. 9.
detection
0.2
ms
minimum width
(Reply sensitivity)
Note8-1: The LVD reset level can be selected out of 7 levels only when the LVD reset function is enabled.
Note8-2: LVD reset voltage specification values do not include hysteresis voltage.
Note8-3: LVD reset voltage may exceed its specification values when port output state changes and/or when a large
current flows through port.
Note8-4: LVD is in an unknown state before transistors start operation.
No.A1400-17/27
LC872G08A/06A/04A
Consumption Current Characteristics at Ta = -40°C to +85°C, V 1 = 0V
SS
Specification
typ max
Pin/
Parameter
Symbol
Conditions
Remarks
V
[V]
min
unit
DD
Normal mode
consumption
current
IDDOP(1)
V
1
• FmCF=12MHz ceramic oscillation mode
• System clock set to 12MHz side
• Internal low speed and medium speed RC
oscillation stopped.
DD
2.7 to 5.5
2.7 to 3.6
3.0 to 5.5
3.0 to 3.6
2.2 to 5.5
2.2 to 3.6
1.8 to 5.5
1.8 to 3.6
6.2
3.5
6.6
3.8
5.3
3.0
2.5
1.3
10.5
5.8
(Note 9-1)
(Note 9-2)
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
IDDOP(2)
IDDOP(3)
IDDOP(4)
IDDOP(5)
• CF1=24MHz external clock
• System clock set to CF1 side
11.2
6.3
• Internal low speed and medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
• FmCF=10MHz ceramic oscillation mode
• System clock set to 10MHz side
• Internal low speed and medium speed RC
oscillation stopped.
9.5
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
5.3
• FmCF=4MHz ceramic oscillation mode
• System clock set to 4MHz side
• Internal low speed and medium speed RC
oscillation stopped.
5.5
mA
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
2.7
• CF oscillation low amplifier size selected.
(CFLAMP=1)
2.2 to 5.5
2.2 to 3.6
0.9
0.5
2.2
1.0
• FmCF=4MHz ceramic oscillation mode
• System clock set to 4MHz side
• Internal low speed and medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/4 frequency division ratio
IDDOP(6)
IDDOP(7)
IDDOP(8)
IDDOP(9)
• FsX’tal=32.768kHz crystal oscillation mode
• Internal low speed RC oscillation stopped.
• System clock set to internal medium speed
RC oscillation.
1.8 to 5.5
1.8 to 3.6
0.5
0.3
1.3
0.6
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
• FsX’tal=32.768kHz crystal oscillation mode
• Internal low speed and medium speed RC
oscillation stopped.
2.7 to 5.5
2.7 to 3.6
1.8 to 5.5
1.8 to 3.6
4.2
2.6
55
8.8
5.0
• System clock set to 8MHz with
frequency variable RC oscillation
• 1/1 frequency division ratio
•
External FsX’tal and FmCF oscillation stopped.
• System clock set to internal low speed RC
197
108
oscillation.
•
Internal medium speed RC oscillation sopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
33
μA
•
External FsX’tal and FmCF oscillation stopped.
5.0
3.3
2.5
55
33
23
153
90
• System clock set to internal low speed RC
oscillation.
•
Internal medium speed RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
• Ta=-10 to +50°C
64
Note9-1: Values of the consumption current do not include current that flows into the output transistors and internal
pull-up resistors.
Note9-2: The consumption current values do not include operational current of LVD function if not specified.
Continued on next page.
No.A1400-18/27
LC872G08A/06A/04A
Continued from preceding page.
Specification
typ max
Pin/
Parameter
Symbol
Conditions
Remarks
V
[V]
min
unit
DD
Normal mode
consumption
current
IDDOP(10)
V
1
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz side
• Internal low speed and medium speed RC
oscillation stopped.
DD
1.8 to 5.5
1.8 to 3.6
33
12
101
41
(Note 9-1)
(Note 9-2)
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
μA
IDDOP(11)
IDDHALT(1)
IDDHALT(2)
IDDHALT(3)
IDDHALT(4)
IDDHALT(5)
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz side
• Internal low speed and medium speed RC
oscillation stopped.
5.0
3.3
33
12
68
27
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
2.5
6.1
2.5
15
• Ta=-10 to +50°C
HALT mode
consumption
current
• HALT mode
• FmCF=12MHz ceramic oscillation mode
• System clock set to 12MHz side
• Internal low speed and medium speed RC
oscillation stopped.
2.7 to 5.5
4.4
(Note 9-1)
(Note 9-2)
2.7 to 3.6
3.0 to 5.5
3.0 to 3.6
2.2 to 5.5
2.2 to 3.6
1.8 to 5.5
1.8 to 3.6
1.3
2.8
1.6
2.2
1.1
1.3
0.6
2.1
4.8
2.6
3.9
1.9
3.1
1.2
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
• HALT mode
• CF1=24MHz external clock
• System clock set to CF1 side
• Internal low speed and medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
• HALT mode
• FmCF=10MHz ceramic oscillation mode
• System clock set to 10MHz side
• Internal low speed and medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
• HALT mode
mA
• FmCF=4MHz ceramic oscillation mode
• System clock set to 4MHz side
• Internal low speed and medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
• HALT mode
• CF oscillation low amplifier size selected.
(CFLAMP=1)
2.2 to 5.5
2.2 to 3.6
0.6
0.3
1.6
0.6
• FmCF=4MHz ceramic oscillation mode
• System clock set to 4MHz side
• Internal low speed and medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/4 frequency division ratio
IDDHALT(6)
• HALT mode
• FsX’tal=32.768kHz crystal oscillation mode
• Internal low speed RC oscillation stopped.
• System clock set to internal medium speed
RC oscillation
1.8 to 5.5
1.8 to 3.6
0.3
0.2
0.9
0.4
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
Note9-1: Values of the consumption current do not include current that flows into the output transistors and internal
pull-up resistors.
Note9-2: The consumption current values do not include operational current of LVD function if not specified.
Continued on next page.
No.A1400-19/27
LC872G08A/06A/04A
Continued from preceding page.
Specification
typ max
Pin/
Parameter
Symbol
Conditions
remarks
V
[V]
min
unit
mA
DD
HALT mode
consumption
current
IDDHALT(7)
V
1
• HALT mode
DD
• FsX’tal=32.768kHz crystal oscillation mode
• Internal low speed and medium speed RC
oscillation stopped.
2.7 to 5.5
1.6
3.5
(Note 9-1)
(Note 9-2)
• System clock set to 8MHz with
frequency variable RC oscillation
• 1/1 frequency division ratio
• HALT mode
2.7 to 3.6
1.8 to 5.5
1.1
19
2.0
88
IDDHALT(8)
•
External FsX’tal and FmCF oscillation stopped.
• System clock set to internal low speed RC
oscillation.
•
Internal medium speed RC oscillation stopped.
1.8 to 3.6
11
46
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
• HALT mode
IDDHALT(9)
5.0
3.3
2.5
19
11
55
32
22
•
External FsX’tal and FmCF oscillation stopped.
• System clock set to internal low speed RC
oscillation.
•
Internal medium speed RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
• Ta=-10 to +50°C
7.7
IDDHALT(10)
• HALT mode
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz side
• Internal low speed and medium speed RC
oscillation stopped.
1.8 to 5.5
27
100
1.8 to 3.6
5.0
8.5
27
38
65
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
• HALT mode
IDDHALT(11)
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz side
• Internal low speed and medium speed RC
oscillation stopped.
μA
3.3
2.5
8.5
3.8
23
11
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
• Ta=-10 to +50°C
HOLD mode
consumption
current
IDDHOLD(1)
IDDHOLD(2)
HOLD mode
1.8 to 5.5
1.8 to 3.6
5.0
0.02
0.01
0.02
0.01
0.009
3.0
20
9.0
1.7
0.8
0.6
23
• CF1=V
DD
or open (External clock mode)
HOLD mode
• CF1=V
(Note 9-1)
(Note 9-2)
or open (External clock mode)
DD
3.3
• Ta=-10 to +50°C
2.5
IDDHOLD(3)
IDDHOLD(4)
HOLD mode
1.8 to 5.5
• CF1=V
DD
• LVD option selected
or open (External clock mode)
1.8 to 3.6
2.3
12
HOLD mode
5.0
3.3
3.0
2.3
5.7
3.9
• CF1=V
DD
or open (External clock mode)
• Ta=-10 to +50°C
2.5
2.0
3.3
• LVD option selected
Timer HOLD
mode
IDDHOLD(5)
IDDHOLD(6)
Timer HOLD mode
1.8 to 5.5
1.8 to 3.6
5.0
22
7.5
22
95
35
60
21
10
• FsX’tal=32.768 kHz crystal oscillation mode
consumption
current
Timer HOLD mode
• FsX’tal=32.768kHz crystal oscillation mode
• Ta=-10 to +50°C
3.3
7.5
2.9
(Note 9-1)
(Note 9-2)
2.5
Note9-1: Values of the consumption current do not include current that flows into the output transistors and internal
pull-up resistors.
Note9-2: The consumption current values do not include operational current of LVD function if not specified.
No.A1400-20/27
LC872G08A/06A/04A
UART (Full Duplex) Operating Conditions at Ta = -40°C to +85°C, V 1 = 0V
SS
Specification
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
16/3
typ max
unit
DD
Transfer rate
UBR
UTX(P20)
URX(P21)
1.8 to 5.5
8192/3
tCYC
Data length:
Stop bits:
Parity bits:
7/8/9 bits (LSB first)
1 bit (2-bit in continuous data transmission)
None
Example of Continuous 8-bit Data Transmission Mode Processing (First Transmit Data=55H)
Start bit
Stop bit
End of
transmission
Start of
transmission
Transmit data (LSB first)
UBR
Example of Continuous 8-bit Data Reception Mode Processing (First Receive Data=55H)
Start bit
Stop bit
End of
reception
Start of
Receive data (LSB first)
reception
UBR
No.A1400-21/27
LC872G08A/06A/04A
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a
SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values
with which the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
• CF oscillation normal amplifier size selected (CFLAMP=0)
MURATA
Operating
Voltage
Range
[V]
Oscillation
Circuit Constant
Nominal
Stabilization Time
Type
Oscillator Name
Remarks
Frequency
C1
C2
Rf
Rd
typ
max
[ms]
[pF]
[pF]
[Ω]
[Ω]
[ms]
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
680
1.0k
680
2.7 to 5.5
2.9 to 5.5
2.2 to 5.5
2.3 to 5.5
2.4 to 5.5
2.7 to 5.5
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
2.5 to 5.5
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
1.8 to 5.5
2.0 to 5.5
1.9 to 5.5
2.0 to 5.5
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.2
0.2
0.2
0.2
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.6
0.6
0.6
0.6
12MHz
10MHz
SMD
SMD
LEAD
SMD
LEAD
SMD
LEAD
SMD
LEAD
CSTCE12M0G52-R0
CSTCE10M0G52-R0
CSTLS10M0G53-B0
CSTCE8M00G52-R0
CSTLS8M00G53-B0
CSTCR6M00G53-R0
CSTLS6M00G53-B0
CSTCR4M00G53-R0
CSTLS4M00G53-B0
(10)
(10)
(15)
(10)
(15)
(15)
(15)
(15)
(15)
(10)
(10)
(15)
(10)
(15)
(15)
(15)
(15)
(15)
1.0k
680
1.0k
1.0k
1.5k
1.0k
1.5k
1.5k
2.2k
1.5k
2.2k
1.5k
3.3k
1.5k
3.3k
8MHz
6MHz
4MHz
Internal C1,C2
• CF oscillation low amplifier size selected (CFLAMP=1)
MURATA
Operating
Voltage
Range
[V]
Oscillation
Stabilization Time
Circuit Constant
Nominal
Type
Oscillator Name
Remarks
Frequency
C1
C2
Rf
Rd
typ
max
[ms]
[pF]
[pF]
[Ω]
[Ω]
[ms]
Open
Open
Open
Open
Open
Open
Open
Open
1.0k
2.2k
1.0k
2.2k
1.0k
2.2k
1.0k
2.2k
2.2 to 5.5
2.3 to 5.5
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
2.3 to 5.5
2.2 to 5.5
2.2 to 5.5
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
CSTCR4M00G53-R0
CSTCR4M00G53095-R0
CSTLS4M00G53-B0
(15)
(15)
(15)
(15)
(15)
(15)
(15)
(15)
SMD
4MHz
Internal C1,C2
LEAD
CSTLS4M00G53095-B0
The oscillation stabilizing time is a period until the oscillation becomes stable after V
minimum operating voltage. (See Fig. 3)
becomes higher than
DD
• Time till the oscillation gets stabilized after the CPU reset state is released
• Till the oscillation gets stabilized after the instruction for starting the main clock oscillation circuit is executed
• Till the oscillation gets stabilized after the HOLD mode is reset.
• Till the oscillation gets stabilized after the X'tal HOLD mode is reset with CFSTOP (OCR register, bit 0) set to 0
No.A1400-22/27
LC872G08A/06A/04A
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYO-
designated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
EPSON TOYOCOM
Operating
Voltage
Range
[V]
Oscillation
Circuit Constant
Nominal
Oscillator
Name
Stabilization Time
Type
Remarks
Frequency
C1
C2
Rf
Rd
typ
[s]
max
[s]
[pF]
[pF]
[Ω]
[Ω]
Applicable
CL value =
7.0pF
32.768kHz
SMD
MC-306
9
9
Open
330k
1.8 to 5.5
1.4
4.0
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the
oscillation to get stabilized after the HOLD mode is reset (see Figure 3).
(Notes on the implementation of the oscillator circuit)
• Oscillation is influenced by the circuit pattern layout of printed circuit board. Place the oscillation-related
components as close to the CPU chip and to each other as possible with the shortest possible pattern length.
• Keep the signal lines whose state changes suddenly or in which large current flows as far away from the oscillator
circuit as possible and make sure that they do not cross one another.
• Be sure to insert a current limiting resistor (Rd) so that the oscillation amplitude never exceeds the input voltage
level that is specified as the absolute maximum rating.
• The oscillator circuit constants shown above are sample characteristic values that are measured using the SANYO-
designated oscillation evaluation board. Since the accuracy of the oscillation frequency and other characteristics vary
according to the board on which the IC is installed, it is recommended that the user consult the resonator vendor for
oscillation evaluation of the IC on a user's production board when using the IC for applications that require high
oscillation accuracy. For further information, contact your resonator vendor or SANYO Semiconductor sales
representative serving your locality.
• It must be noted, when replacing the flash ROM version of a microcontroller with a mask ROM version, that their
operating voltage ranges may differ even when the oscillation constant of the external oscillator is the same.
CF2/XT2
CF1/XT1
Rf
Rd
C1
C2
CF/X’tal
Figure 1 CF and XT Oscillator Circuit
0.5V
DD
Figure 2 AC Timing Measurement Point
No.A1400-23/27
LC872G08A/06A/04A
V
DD
Operating V
lower limit
Power supply
DD
0V
Reset time
RES
Internal Medium speed
RC oscillation
tmsCF/tmsXtal
CF1, CF2
Instruction execution (Note2)
Instruction execution
Operating
mode
Unpredictable
Reset
Reset Time and Oscillation Stabilization Time
HOLD reset signal
absent
HOLD reset
signal
HOLD reset signal valid
Internal Medium speed
RC oscillation or
Low speed RC oscillation
tmsCF
CF1, CF2
(Note1)
tmsX’tal
CF1, CF2
(Note2)
State
HOLD
HALT
HOLD Reset Signal and Oscillation Stabilization Time
Note1: Mainclock oscillation circuit is selected.
Note2: Subclock oscillation circuit is selected.
Figure 3 Oscillation Stabilization Times
No.A1400-24/27
LC872G08A/06A/04A
V
DD
Note:
External circuits for reset may vary
R
RES
depending on the usage of POR and LVD.
Please refer to the user’s manual for more
information.
RES
C
RES
Figure 4 Reset Circuit
SIOCLK:
DATAIN:
DATAOUT:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
tSCK
tSCKL
tSCKH
thDI
SIOCLK:
DATAIN:
tsDI
tdDO
DATAOUT:
Figure 5 Serial I/O Output Waveforms
tPIL
tPIH
Figure 6 Pulse Input Timing Signal Waveform
No.A1400-25/27
LC872G08A/06A/04A
POR release voltage
(PORRL)
(a)
(b)
V
DD
Reset period
Reset period
100μs or longer
Unknown-state
(POUKS)
RES
Figure 7 Waveform observed when only POR is used (LVD not used)
(RESET pin: Pull-up resistor R only)
RES
• The POR function generates a reset only when power is turned on starting at the V level.
SS
• No stable reset will be generated if power is turned on again when the power level does not go down to the V level
SS
as shown in (a). If such a case is anticipated, use the LVD function together with the POR function or implement an
external reset circuit.
• A reset is generated only when the power level goes down to the V level as shown in (b) and power is turned on
SS
again after this condition continues for 100μs or longer.
LVD hysteresis width
LVD release voltage
(LVHYS)
(LVDET+LVHYS)
V
DD
LVD reset voltage
(LVDET)
Reset period
Reset period
Reset period
Unknown-state
(LVUKS)
RES
Figure 8 Waveform observed when both POR and LVD functions are used
(RESET pin: Pull-up resistor R only)
RES
• Resets are generated both when power is turned on and when the power level lowers.
• A hysteresis width (LVHYS) is provided to prevent the repetitions of reset release and entry cycles near the detection
level.
No.A1400-26/27
LC872G08A/06A/04A
V
DD
LVD release voltage
LVD reset voltage
LVDET-0.5V
TLVDW
V
SS
Figure 9 Low voltage detection minimum width
(Example of momentary power loss/Voltage variation waveform)
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,
without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellectual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of December, 2009. Specifications and information herein are subject
to change without notice.
No.A1400-27/27
PS
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