LA76850 [SANYO]
Monolithic Linear IC Black & White Television IC; 单片线性集成电路黑白电视机IC
| 型号： | LA76850 |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | Monolithic Linear IC Black & White Television IC |
| 文件： | 总31页 (文件大小：280K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENA0017
Monolithic Linear IC
LA76850
Black & White Television IC
Overview
LA76850 is a Black & White Television IC.
Functions
• I2C Bus Control VIF/SIF/Y/Deflection/Implemented in a Single Chip
Specifications
Maximum Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
V
Maximum supply voltage
V
max
max
7.0
7.0
14
8
V
V
V
27
Maximum supply current
I16 max
max
I
35
V
20
Allowable power dissipation
Operating temperature
Storage temperature
Pd max
Topg
Ta ≤ 65°C *
1.1
mW
°C
°C
-10 to +65
Tstg
-55 to +150
* Provided with a glass epoxy board (114.3×76.1×1.6 mm)
Operating Conditions at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
V
Recommended supply voltage
V
8
5.0
5.0
V
V
27
Recommended supply current
Operating supply voltage range
Operating supply current range
I
9
mA
mA
V
16
I
29
20
V
op
4.7 to 5.3
4.7 to 5.3
7 to 11
24 to 33
8
V
I
op
V
27
op
op
mA
mA
16
20
I
Any and all SANYO Semiconductor products described or contained herein do not have specifications
that can handle applications that require extremely high levels of reliability, such as life-support systems,
aircraft's control systems, or other applications whose failure can be reasonably expected to result in
serious physical and/or material damage. Consult with your SANYO Semiconductor representative
nearest you before using any SANYO Semiconductor products described or contained herein in such
applications.
SANYO Semiconductor assumes no responsibility for equipment failures that result from using products
at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor
products described or contained herein.
N2206 / N1105 MS OT B8-7024 No.A0017-1/31
LA76850
Electrical Characteristics Ta = 25°C, V L = V = V = 5.0V, I
CC 27
= I = 9mA, I
CC 16
= I = 27mA
CC 20
8
Parameter
Symbol
Conditions
min
typ
max
unit
[Circuit voltage, current]
IF supply current
I
V
= 5V, V = 2.5V
8 3
67
mA
V
8
RGB supply voltage
V
I
= 9mA
= 27mA
= 5V
8.0
5.0
65
16
16
25
27
Horizontal supply voltage
Video supply current
[VIF block]
V
I
I
V
20
I
mA
27
Maximum RFAGC voltage
Minimum RFAGC voltage
RF AGC Delay Pt (@DAC = 0)
VRFH
VRFL
CW = 80dBµ, DAC = 0
CW = 80dBµ, DAC = 63
DAC = 0
8.5
9
Vdc
Vdc
dBµ
dBµ
0
0.3
0.7
RFAGC0
RFAGC63
90
RF AGC Delay Pt
(@DAC = 63)
DAC = 63
80
Input sensitivity
Vi
VOn
Output-3dB
46
4.0
dBµ
Vdc
Vdc
Vp-p
dB
No-signal video output voltage
Sync signal tip level
Video output amplitude
Video S/N
No signal
3.4
1.1
3.7
1.4
VOtip
VO
CW = 80dBµ
1.7
80dBµ, AM = 78%, fm = 15kHz
CW = 80dBµ
1.57
40
2.05
45
2.52
S/N
C-S beat level
IC-S
V4.43MHz/V1.07MHz
80dBµ, 87.5% Video MOD
80dBµ, 87.5% Video MOD
CW = 80dBµ, frequency variations
CW = 80dBµ, frequency variations
CW = 80dBµ, frequency variations
35
dB
Differential gain
DG
5.0
1.0
10.0
10.0
5
%
Differential phase
DP
deg
Vdc
Vdc
mV/kHz
MHz
MHz
dB
Maximum AFT output voltage
Minimum AFT output voltage
AFT detection sensitivity
APC pull-in range (U)
APC pull-in range (L)
NT Trap1 (4.5MHz)
NT Trap1 (4.8MHz)
BG Trap1 (5.5MHz)
BG Trap2 (5.85MHz)
I Trap1 (6.0MHz)
VAFTH
VAFTL
VAFTS
fPU
4.3
0.0
8.0
1.5
1.5
4.7
0.3
0.7
15.0
22.0
fPL
NTR1
NTR2
BTR1
BTR2
ITR1
ITR2
DTR1
-30
-20
-30
-20
-30
-17
-30
dB
dB
dB
dB
I Trap1(6.55MHz)
dB
DK Trap1(6.5MHz)
dB
[SIF block]
FM detection output voltage
FM limiting sensitivity
SOADJ
SLS
FM = 30kHz
Output -3dB
fm = 100kHz
245
-0.5
310
5.0
390
53
mVrms
dBµ
FM detection output
f characteristics
SF
8.0
dB
FM detection output distortion
STHD
SAMR
SSN
FM = 30kHz
AM = 30%
DIN.Andio
1.0
%
AM rejection ratio
SIF S/N
40
51.5
2.4
dB
dB
dB
dB
PAL de-emph time constant
SPTC
SGD
3.0
0.0
3.6
PAL/NT Difference of voltage
gain
-1.5
+1.5
NT de-emph time constant
SNTC
1.9
2.5
3.1
dB
Continued on next page.
No.A0017-2/31
LA76850
Continued from preceding page.
Parameter
Symbol
Conditions
min
typ
max
unit
[AUDIO block]
Maximum gain
AGMAX
ARANGE
AF
1kHz500mVrms
-2.0
0.5
+3.0
dB
dB
dB
dB
%
Variable range
60
-3.0
70
74
Frequency characteristics
Mute
20kHz
0.0
3.0
0.5
AMUTE
ATHD
ASN
20kHz
Distortion
1kHz, 500mVrms, Vol: MAX
S/N
DIN. Audio
1kHz
65
70
73
dB
dB
Crosstalk
ACT
[Video block]
Video signal input 1DC voltage
Video signal input 1AC voltage
V
V
1DC
1AC
2.2
2.5
1
2.8
V
IN
Vp-p
dB
IN
Video overall gain
(Contrast max)
CONT127
12.0
-6.5
14.0
16.0
-3.5
Contrast adjustment
characteristics
CONT63
-5.0
dB
dB
(Normal/max)
Contrast adjustment
characteristics
CONT0
-18.0
-15.0
-12.0
(Min/max)
Video frequency
Characteristics 1 NTSC
Video frequency
characteristics 2 PAL
Chroma trap amount PAL
BW1
BW2
1.8MHz/100kHz
Filter sys = 0000
2.2MHz/100kHz
Filter sys = 0010
-6.0
-6.0
-3.0
-3.0
0.0
0.0
dB
dB
CtrapP
CtrapN
-36.0
-36.0
95.0
5.0
-26.0
-26.0
100.0
8.0
-22.0
-22.0
105.0
11.0
dB
dB
%
Chroma trap amount NTSC
DC transmission amount
ClampG1
Sharp32T2
Sharp63T2
Sharp0T2
Sharp63T5
Sharpness variability range
(trap 2 mid)
F = 2.7MHz, FILTER SYS = 0010
F = 2.7MHz, FILTER SYS = 0010
F = 2.7MHz, FILTER SYS = 0010
dB
dB
dB
dB
8.5
11.5
13.5
(trap 2 max)
-6.5
8.5
-3.5
-0.5
(trap 2 min)
F = 3.0MHz, FILTER SYS = 0000
Y APF = 1
11.5
13.5
Sharp0T5
F = 3.0MHz, FILTER SYS = 0000
Y APF = 1
-6.5
-3.5
-0.5
dB
Y gamma effective point 1
Y gamma effective point 2
Y gamma effective point 3
YG1
YG2
YGAMMA = 01
%
%
%
V
89.0
85.0
80.0
0.1
93.0
89.0
84.0
0.4
97.0
93.0
88.0
0.7
YGAMMA = 10
YGAMMA = 11
YG3
Horizontal/vertical blanking
output level
RGBBLK
[OSD block]
OSD Fast SW threshold
OSD output level
FSTH
0.7
0.9
1.1
V
OSDH
Digital osd = 1
Osd cont = 63
140
175
210
IRE
[RGB output (cutoff drive) block]
Brightness control (Normal)
Brightness control (Normal-H)
Hi brightness (max)
BRT63
BRT63H
BRT127
BRT0
V
2.3
3.0
20
2.8
3.3
25
3.3
3.6
30
V
IRE
IRE
Low brightness (min)
-30
-25
16
-20
Bright control Resolution
Vbiassns
mV
/Bit
mV
/Bit
Sub-bias control Resolution
Vsbiassns
7
Continued on next page.
No.A0017-3/31
LA76850
Continued from preceding page.
Parameter
Symbol
FH
Conditions
min
typ
max
unit
Hz
[Deflection block]
Horizontal free-running
frequency
15500
15670
15900
Horizontal pull-in range
fH PULL
Hduty
400
36.1
0
Hz
µs
V
Horizontal output pulse width
37.6
0.2
39.1
0.4
Horizontal output pulse
saturation voltage
V Hsat
Vertical free-running cycle 50
VFR50
VFR60
312.0
262.0
9.5
312.5
262.5
10.5
10.5
2.4
313.0
263.0
11.5
H
H
Vertical free-running cycle 60
Horizontal output pulse phase
Horizontal output pulse phase
HPHCENpal
HPHCENnt
HPHrange
µs
µs
µs
9.5
11.5
Horizontal position
5bit
adjustment range
Horizontal position adjustment
maximum variability width
Horizontal blanking left @0
HPHstep
350.0
ns
BLKL0
BLKL7
BLKL:000
BLKL:111
BLKR:000
BLKR:111
7500
10800
1800
-1100
5.3
8300
11600
2600
-300
5.6
9100
12400
3400
500
5.9
ns
ns
ns
ns
V
Horizontal blanking left @7
Horizontal blanking right @0
Horizontal blanking right @7
Sand castle pulse crest value H
Sand castle pulse crest value M1
Sand castle pulse crest value M2
Sand castle pulse crest value L
Burst gate pulse width
BLKR0
BLKR7
SANDH
SANDM1
SANDM2
SANDL
BGPWD
BGPPH
Hstop
3.7
4.0
4.3
V
1.7
2.0
2.3
V
0.1
0.4
0.7
V
2.5
3.0
3.5
µs
µs
V
Burst gate pulse phase
4.9
5.4
5.9
Horizontal output stop voltage
<Vertical screen size adjustment>
3.30
3.60
3.90
Vertical ramp output amplitude
PAL@64
Vspal64
Vsnt64
VSIZE: 1000000
VSIZE: 1000000
VSIZE: 0000000
VSIZE: 0000000
VSIZE: 1111111
VSIZE: 1111111
0.85
0.85
0.41
0.41
1.15
1.15
0.95
0.95
0.51
0.51
1.30
1.30
1.05
1.05
0.61
0.61
1.45
1.45
Vp-p
Vp-p
Vp-p
Vp-p
Vp-p
Vp-p
Vertical ramp output amplitude
NTSC@64
Vertical ramp output amplitude
PAL@0
Vspal0
Vertical ramp output amplitude
NTSC@0
vsnt0
Vertical ramp output amplitude
PAL@127
Vspal127
Vspal127
Vertical ramp output amplitude
NTSC@127
Continued on next page.
No.A0017-4/31
LA76850
Continued from preceding page.
Parameter
Symbol
Conditions
min
typ
max
unit
<High-voltage dependent vertical size correction>
Vertical size correction @0
Vsizecomp
VCOMP: 000
0.89
0.93
0.97
ratio
<Vertical screen position adjustment>
Vertical ramp DC voltage
PAL@32
Vdcpal32
Vdcnt32
Vdcpal0
Vdcpal0
Vdcpal63
Vdcpal63
VDC: 100000
VDC: 100000
VDC: 000000
VDC: 000000
VDC: 111111
VDC:111111
2.25
2.25
1.85
1.85
2.65
2.65
2.40
2.40
2.00
2.00
2.80
2.80
2.55
2.55
2.15
2.15
2.95
2.95
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vertical ramp DC voltage
NTSC@32
Vertical ramp DC voltage
PAL@0
Vertical ramp DC voltage
NTSC@0
Vertical ramp DC voltage
PAL@63
Vertical ramp DC voltage
NTSC@63
Vertical linearity @16
Vlin16
Vlin0
VLIN: 10000
VLIN: 00000
VLIN: 11111
VSC: 10000
VSC: 00000
VSC: 11111
0.85
1.17
0.57
0.75
1.08
0.49
1.00
1.32
0.72
0.90
1.23
0.64
1.15
1.47
0.87
1.05
1.38
0.79
ratio
ratio
ratio
ratio
ratio
ratio
Vertical linearity @0
Vertical linearity @31
Vlin31
Vertical S-shaped correction @16
Vertical S-shaped correction @0
Vertical S-shaped correction @31
Vscor16
Vscor0
Vscor31
Package Dimensions
unit : mm
3170A
No.A0017-5/31
LA76850
Application Circuit Example
No.A0017-6/31
LA76850
Test Conditions Ta = 25°C, V
= V = V = V = 5.0V, l = 19mA, I
= l = 27mA
CC 25
CC
8
31
43
18
Parameter
Symbol
Test point
Input signal
Test method
Bus conditions
Initial
[Circuit voltage, current]
RGB supply voltage (pin 20)
RGB supply voltage (pin 16)
IF supply current (pin 8)
V
No signal
No signal
No signal
Apply a current of 27mA to pin 20 and
measure the voltage at pin 20.
20
20
16
V
Apply a current of 19mA to pin 16 and
measure the voltage at pin 16.
Initial
Initial
16
I
Apply a voltage of 5.0V to pin 8 and measure
the incoming DC current (mA).
(IF AGC 2.5V applied)
8
(CDDI
)
CC
8
Video/vertical supply current
(pin 27)
I
No signal
Apply a voltage of 5.0V to pin 27 and
measure the incoming DC current (mA).
Initial
27
27
(DEFI
)
CC
NoA0017-7/31
LA76850
VIF Block Input Signals
1. Input signals must all be input to the PIF IN (pin 6) in the Test Circuit.
2. All input signal voltage values are the levels at the VIF IN (pin 6) in the Test Circuit.
3. Signal contents and signal levels
4. Bus conditions: VIF SYS = "01", S.TRAP.SW = "1", OVER.MOD.SW = "0"
Input signal
Waveform
Conditions
SG1
38.9MHz
CW
CW
SG2
SG3
SG4
SG5
34.47MHz
33.4MHz
CW
CW
Frequency variable
38.9MHz
87.5% Video Mod.
10-stairstep wave
(Subcarrier: 4.43MHz)
SG6
SG7
38.9MHz
fm = 15kHz, AM = 78%
38.9MHz, 80dBµ
87.5% Video Mod.
50IRE Luma
50IRE
(Carrier: variable)
50IRE Luma
NoA0017-8/31
LA76850
VIF Block Test Conditions
Input signal
Symbol
Test point
Input signal
Test method
Bus conditions
Maximum RF AGC
voltage
VRFH
SG1
Measure the DC voltage at pin 4.
RF.AGC = "000000"
4
80dBµ
SG1
Minimum RF AGC
voltage
VRFL
RFAGC0
RFAGC63
Vi
Measure the DC voltage at pin 4.
RF.AGC = "111111"
RF.AGC = "000000"
RF.AGC = "111111"
4
80dBµ
SG1
RF AGC Delay Pt
(@DAC = 0)
Obtain the input level at which the DC voltage at
pin 4 becomes 4.5V.
4
4
RF AGC Delay Pt
(@DAC = 63)
Input sensitivity
SG1
SG6
Obtain the input level at which the DC voltage at
pin 4 becomes 4.5V.
Using an oscilloscope, observe the level at pin 29
and obtain the input level at which the waveform's
p-p value becomes 1.4Vp-p.
29
29
No-signal
video output
voltage
VOn
No signal
Set IF AGC = “1” and measure the DC voltage at
pin 29.
Sync signal tip
level
VOtip
VO
SG1
Measure the DC voltage at pin 29.
29
29
80dBµ
SG6
Video output
amplitude
Video S/N
Using an oscilloscope, observe the level at pin 29
and measure the waveform’s p-p value.
80dBµ
SG1
S/N
Measure the noise voltage (Vsn) at pin 29 with an
RMS voltmeter through a 10kHz to 5.0MHz
band-pass filter and calculate 20 log (1.43/Vsn).
Input a 80dBµ SG1 signal and measure the DC
voltage (V3) at pin 3. Mix SG1 = 74dBµ, SG2 = 64
dBµ, and SG3 = 64 dBµ to enter the mixture in the
VIF IN. Apply V3 to pin 3 from an external DC
power supply. Using a spectrum analyzer,
29
29
80dBµ
C-S beat level
IC-S
SG1
SG2
SG3
measure the difference between pin 29’s 4.43MHz
component and 1.07MHz component.
Differential gain
DG
DP
SG5
Using a vector scope, measure the level at Pin 29.
29
29
10
80dBµ
SG5
Differential phase
Using a vector scope, measure the level at Pin 29.
80dBµ
SG4
Maximum AFT
output voltage
VAFTH
Set and input the SG4 frequency to 37.9MHz to be
input. Measure the DC voltage at pin 10 at that
moment.
80dBµ
Minimum AFT
output voltage
VAFTL
VAFTS
SG4
Set and input the SG4 frequency to 39.9MHz to be
input. Measure the DC voltage at pin 10 at that
moment.
10
10
80dBµz
AFT detection
sensitivity
SG4
Adjust the SG4 frequency and measure
frequency deviation ∆f when the DC voltage at pin
10 changes from 1.5V to 3.5V.
80dBµz
VAFTS = 2000/∆f [mV/kHz]
Continued on next page.
NoA0017-9/31
LA76850
Continued from preceding page.
Input signal
Symbol
Test point
29
Input signal
Test method
Bus conditions
APC pull-in
fPU, fPL
SG4
Connect an oscilloscope to pin 29 and adjust the
SG4 frequency to a frequency higher than
38.9MHz to bring the PLL into unlocked mode.
(A beat signal appears.) Lower the SG4 frequency
and measure the frequency at which the PLL locks
again. In the same manner, adjust the SG4
frequency to a lower frequency to bring the PLL
into unlocked mode. Higher the SG4 frequency
and measure the frequency at which the PLL locks
again.
range (U), (L)
80dBµ
NT Trap1 (4.5MHz),
2 (4.8MHz)
NTR1
NTR2
SG7
SG7
SG7
SG7
Determine the output level difference between
carrier frequencies of 1Mhz, 4.5MHz and 4.8MHz.
(Reference:1MHz)
SIF.SYS = "00"
SIF.SYS = "01"
SIF.SYS = "10"
SIF.SYS = "11"
29
29
29
29
BG Trap1 (5.5MHz),
2 (5.85MHz)
BTR1
BTR2
Determine the output level difference between
carrier frequencies of 1Mhz, 5.5MHz and
5.85MHz. (Reference:1MHz)
I Trap1 (6.0MHz)
2 (6.55MHz)
ITR1
ITR2
Determine the output level difference between
carrier frequencies of 1MHz, 6.0MHz and
6.55MHz. (Reference:1MHz)
DK Trap1 (6.5MHz)
DTR1
Determine the output level difference between
carrier frequencies of 1MHz and 6.5MHz.
(Reference:1MHz)
NoA0017-10/31
LA76850
SIF Block (FM block) Input Signals and Test Conditions
Unless otherwise specified, the following conditions apply when each measurement is made.
1. Bus control condition:
IF.AGC.SW = "1", SIF.SYS = "01", DEEM-TC = "0", FM.GAIN = "0", A.MONI.SW = "0", A2.SW = "0"
2. SW:IF1 = "ON", 24pin = 5V
3. Input signals are input to pin 54 and the carrier frequency is 5.5MHz.
Input signal
Symbol
Test point
Input signal
Test method
Bus conditions
FM detection
SOADJ
90dBµ,
Measure the 400 Hz component (SV1: mVrms) of
the FM detection output at pin 2.
2
output voltage
fm = 400Hz,
FM =
30kHz
FM limiting
sensitivity
SLS
SF
fm = 400Hz,
FM =
Measure the input level (dBµ) at which the 400Hz
component of the FM detection output at pin 2
becomes -3dB relative to SV1.
2
2
30kHz
FM detection
90dBµ,
Set SW: IF1 = "OFF".
output f characteristics
(fm=100kHz)
fm = 100kHz
FM =
Measure (SV2: mVrms) the FM detection output of
pin 2. Calculate as follows:
30kHz
SF = 20*LOG (SV1/SV2) [dB]
FM detection output
distortion
STHD
SAMR
90dBµ,
Measure the distortion factor of the 400Hz
component of the FM detection output at pin 2.
2
2
fm = 400Hz,
FM =
30kHz
AM rejection
ratio
90dBµ,
Measure the 400Hz component (SV3: mVrms) of
the FM detection output at pin 2.
Assign the measured value to SV3 and
calculate as follows:
fm = 400Hz,
AM = 30%
SAMR = 20*log (SV1/SV3) [dB]
SIF.S/N
SSN
90dBµ,
Measure the noise level (DIN AUDIO, SV4:
mVrms) at pin 2. Calculate as follows:
SSN=20*log(SV1/SV4) [dB]
2
2
CW
PAL de-emph time
constant
SPTC
90dBµ,
fm =
Measure the 3.18kHz component (SV5: mVrms) of
the FM detection output at pin 2 and calculate as
follows:
3.18KHz
FM =
SNTC = 20*LOG (SV1/SV5) [dB]
30KHz
fo = 4.5MHz
90dBµ,
fm = 400Hz
FM =
PAL/NT
SGD
Measure the 400Hz component (SV6: mVrms) of
the FM detection output at pin 2 and calculate as
follows:
SIF.SYS = "00"
DEEM-TC = "1"
FM.GAIN = "1"
Difference of voltage
gain
2
2
SNTC = 20*LOG (SV1/SV6) [dB]
15KHz
fo = 4.5MHz
90dBµ,
fm =
NT de-emph
time constant
SNTC
Measure the 2.12kHz component (SV7: mVrms) of
the FM detection output at pin 2 and calculate as
follows:
SIF.SYS = "00"
DEEM-TC = "1"
FM.GAIN = "1"
2.12kHz
FM =
SNTC = 20*LOG (SV6/SV7) [dB]
15kHz
NoA0017-11/31
LA76850
Audio Block Input Signals and Test Conditions
Unless otherwise specified, the following conditions apply when each measurement is made.
1. Bus control condition:
AUDIO.MUTE = "0", A.MONI.SW = "0", AUDIO.SW = "1", VOL.FIL = "0", SIF.SYS = "01", IF.AGC.SW = "1"
2. Input 5.5MHz, 90dBµ and CW at pin 54.
3. Enter an input signal from pin 51.
Input signal
Symbol
Test point
1
Input signal
Test method
Bus conditions
VOLUME =
Maximum gain
AGMAX
1kHz, CW
500mVrms
Measure the 1kHz component (V1: mVrms) at
the pin 1 and calculate as follows:
AGMAX = 20*LOG(V1/500) [dB]
"1111111"
Variable range
ARANGE
AF
1kHz, CW
500mVrms
Measure the 1kHz component (V2: mVrms) at
the pin 1 and calculate as follows:
ARANGE = 20*LOG(V1/V2) [dB]
VOLUME =
"0000000"
1
1
1
Frequency
20kHz, CW
500mVrms
Measure the 20kHz component (V3: mVrms) at
the pin 1 and calculate as follows:
AF = 20*Log(V3/V1) [dB]
VOLUME =
"1111111"
characteristics
Mute
AMUTE
20kHz, CW
500mVrms
Measure the 20kHz component (V4: mVrms) at
the pin 1 and calculate as follows:
AMUTE = 20*Log(V3/V4) [dB]
VOLUME =
"1111111"
AUDIO.MUTE = ”1”
VOLUME =
"1111111"
Distortion
S/N
ATHD
ASN
1kHz, CW
500mVrms
No signal
Measure the distortion of the 1kHz component at
the pin 1.
1
1
Measure the noise level (DIN AUDIO, V5: mVrms)
at the pin 1 and calculate as follows:
ASN = 20*log(V1/V5) [dB]
VOLUME =
"1111111"
Crosstalk
ACT
1kHz, CW
500mVrms
Measure the 1kHz component (V6: mVrms) at
the pin 1 and calculate as follows:
ACT = 20*LOG(V1/V6) [dB]
VOLUME =
1
"1111111"
AUDIO.SW = "0"
NoA0017-12/31
LA76850
Video Block Input Signals
Y IN inpt signal 100IRE: 714mV
Bus control bit conditions: Initial test state
0IRE signal (L-0): NTSC standard sync signal
PEDESTAL LEVEL
(H/V SYNC:40IRE: 286mV)
H SYNC
4.7µs
XIRE signal (L-X)
XIRE (X = 0 to 100)
0IRE
CW signal (L-CW)
20IRE CW signal
50IRE
BLACK STRETCH 0IRE signal (L-BK)
50µs
100IRE
5µs
(Point A)
OSD IN Input signal
OSD Input signal 1 (0-1)
to each 20µs
0.35V
0.7V
A
B
0.0VDC
OSD Input signal 2 (0-2)
1.0VDC
20µs
30µs
0.0VDC
NoA0017-13/31
LA76850
Video Block Test Conditions
Input signal
Symbol
Test point
28
Input signal
Test method
Bus conditions
VIDEO SW:1
Video signal input
1DC voltage
V
1DC
L-100
Input signals to pin 28 and measure the voltage of
the pedestal.
IN
Video signal input
1 AC voltage
V
1AC
Pin 28 recommended input level
IN
28
17
Video overall gain
(Contrast max)
CONT127
CONT63
L-50
L-50
Measure the output signal’s 50IRE amplitude
(CNTHB Vp-p) and calculate
CONTRAST:
1111111
CONT127 = 20log (CNTHB/0.357).
Measure the output signal’s 50IRE amplitude
(CNTCB Vp-p) and calculate
Contrast
CONTRAST:
0111111
17
17
17
adjustment
characteristics
(normal/max)
Contrast
CONT63 = 20log (CNTCB/0.357).
CONT0
BW1
L-50
Measure the output signal’s 50IRE amplitude
(CNTLB Vp-p) and calculate
CONTRAST:
0000000
adjustment
characteristics
(min/max)
CONT0 = 20log (CNTLB/0.357).
Video frequency
Characteristics 1
(NTSC)
L-CW
With the input signal’s continuous
FILTER SYS: 0000
SHARPNESS:
000000
Wave = 100kHz, measure the output signal’s
continuous wave amplitude (PEAKDC Vp-p).
With the input signal’s continuous
wave = 1.8MHz, measure the output signal’s
continuous wave amplitude (CW1.8 Vp-p).
Calculate BW1 = 20Log (CW1.8/PEAKDC).
With the input signal’s continuous
Video frequency
Characteristics 2
(PAL)
BW2
L-CW
L-CW
FILTER SYS: 0010
SHARPNESS:
000000
17
17
wave = 2.2MHz, measure the output signal’s
continuous wave amplitude (CW2.2 Vp-p).
Calculate BW2 = 20Log (CW2.2/PEAKDC).
With the input signal’s continuous
Chroma trap amount
PAL
CtraPP
FILTER SYS: 010
Sharpness: 000000
wave = 4.43MHz, measure the output signal’s
continuous wave amplitude (F0P Vp-p).
Calculate CtraP = 20Log (F0P/PEAKDC).
Chroma trap amount
NTSC
CtraPN
L-CW
With the input signal’s continuous
FILTER SYS: 000
Sharpness: 000000
17
17
wave = 3.58MHz, measure the output signal’s
continuous wave amplitude (F0N Vp-p).
Calculate CtraN = 20Log (F0N/PEAKDC).
DC transmission
amount
ClampG1
L-0
Measure the output signal’s 0IRE DC level
(BRTPL V).
Brightness:
0000000
CONTRAST:
1111111
L-100
Measure the output signal’s 0IRE DC level
(DRVPH V) and 100IRE amplitude (DRVH Vp-p)
and calculate ClampG = 100 ×
Brightness:
0000000
Contrast:
(1+(DRVPH - BRTPL)/DRVH).
1111111
DCREST = 00
BLK.ST.DEF = 1
WPL = 0
Sharpness variable
range (PAL)
Sharp32T2
Sharp63T2
Sharp0T2
L-CW
L-CW
L-CW
With the input signal’s continuous
wave = 2.7MHz, measure the output signal’s
continuous wave amplitude (F02S32 Vp-p).
Calculate Sharp32T3 = 20Log
Filter Sys:0010
Sharpness: 100000
17
17
(F02S32/PEAKDC).
(max)
(min)
With the input signal’s continuous
wave = 3MHz, measure the output signal’s
continuous wave amplitude (F02S63 Vp-p).
Calculate Sharp63T2 = 20Log
Filter Sys:0010
Sharpness: 111111
(F02S63/PEAKDC).
With the input signal’s continuous
wave = 3MHz, measure the output signal’s
continuous wave amplitude (F02S0 Vp-p).
Calculate Sharp0T2 = 20Log (F02S0/PEAKDC).
Filter Sys:0010
17
Sharpness: 000000
Continued on next page.
NoA0017-14/31
LA76850
Continued from preceding page.
Input signal
Symbol
YG1
Test point
17
Input signal
Test method
Bus conditions
Y GAMMA = 1
Y gamma effective
point1
L-100
L-100
L-100
L-100
Measure the output amplitude (0 to 100 IR) when
the Y gamma is 0 (GAM0). Then set Y gamma to 1
and measure the output amplitude (0 to 100 IR)
again (GAM1).
Calculate YG1 = (GAM1/GAM0) × 100.
Measure the output amplitude (0 to 100 IR) when
the Y gamma is 0 (GAM0). Then set Y gamma to 2
and measure the output amplitude (0 to 100 IR)
again (GAM2).
Y gamma effective
point12
YG2
YG3
Y GAMMA = 2
Y GAMMA = 3
17
Calculate YG2 = (GAM2/GAM0) × 100.
Measure the output amplitude (0 to 100 IR) when
the Y gamma is 0 (GAM0). Then set Y gamma to 3
and measure the output amplitude (0 to 100 IR)
again (GAM3).
Y gamma effective
point1
17
17
Calculate YG3 = (GAM3/GAM0) × 100.
Measure the DC level (RGBBLK V) for the output
signal’s blanking period.
Horizontal/vertical
blanking output
level
RGBBLK
[OSD block]
Bus control bit conditions:
Contrast: 0111111
Brightness:
Contrast = 63, Brightness = 63
0111111
OSD
FSTH
L-0
Apply voltage to pin 15 and measure the voltage at
pin 15 at the point where the output signal switches
to the OSD signal.
Pin 14A: O-2
applied
17
17
Fast SW threshold
O-2
OSD output
level
OSDH
L-50
Measure the output signal’s 50IRE amplitude
(CNTCB Vp-p).
Osd cont = 0111111
Digital osd = 1
Pin 15: 3.5V
Pin 14A: O-2
applied
L-0
Measure the OSD output amplitude
(OSDHB Vp-p).
O-2
Calculate OSDH =
50 × (OSDHB/CNTCB)
[Y output block] (Cutoff, drive block)
Bus control bit conditions: Contrast = 127
Contrast:
1111111
Brightness control
(normal)
BRT63
BRT63H
BRT127
L-0
L-0
L-0
Measure the 0IRE DC levels of the
respective output signals of Y output
(17)
Brightness:
01111111
17
17
17
Brightness control
(normal-H)
Measure the 0IRE DC level of the output Signal of
Y output (17) and assign the Measured value to
BRTPC.
Brightness:
0111111
Sub Bias: 1111111
Brightness:
Brightness control
(max)
Measure the 0IRE DC level of the output Signal of
Y output (17) and assign the Measured value to
BRTPH.
1111111
Sub Bias: 1111111
Calculate BRT127 =
50×(BRTPH-BRTPC)/CNTHB.
Measure the 0IRE DC level of the output
Signal of Y output (17) and assign the
Measured value to BRTPL.
Brightness control
(min)
BRT0
L-0
Brightness:
17
0000000
Sub Bias: 1111111
Calculate BRT0 =
50× (BRTPL-BRTPC)/CNTHB.
Measure the 0IRE DC levels (BTPM V) of the
respective output signals of Y output (17).
Vbiassns = (BRTPH-BTPM)/127
Bright control
resolution
Vsiassns
L-50
L-50
Brightness:
0000000
17
17
Sub Bias:
1111111
Sub-bias control
resolution
Vsbiassns
Measure the 0IRE DC levels (SBTPM V) of the
respective output signals of Y output (17).
Vsbiassns = (BRTPCH-SBTPM)/127
Brightness:
0111111
Sub Bias: 0000000
NoA0017-15/31
LA76850
Deflection Block Input Signals
Unless otherwise specified, the following conditions apply when each measurement is made.
1. VIF, SIF blocks: No signal
2. C input: No. signal
3. Sync input: A horizontal/vertical composite sync signal
PAL:
43IRE, horizontal sync signal (15.625kHz) and vertical sync signal (50kHz)
NTSC: 40IRE, horizontal sync signal (15.734264kHz) and vertical sync signal (59.94kHz)
Note: No burst signal, chroma signal shall exist below the pedestal level.
Signal unsuitable
for Y input
Signal suitable
for Y input
Chroma signal
Burst signal
4. Bus control conditions: Initial conditions unless otherwise specified.
5. The delay time from the rise of the horizontal output (pin 22 output) to the fall of the FBP IN (pin 23 input) is 9µs.
6. Pin 13 (vertical size correction circuit input terminal) is connected to V
(5.0V).
CC
NoA0017-16/31
LA76850
Deflection Block Test Conditions
Input signal
Symbol
Test point
Input signal
Test method
Bus conditions
Horizontal free-running
frequency
fH
Y IN:
Connect a frequency counter to the output of pin
22 (H out) and measure the horizontal free-running
frequency.
22
No signal
Horizontal output
pulse length
Hduty
Y IN:
Measure the voltage for the pin 22 horizontal
output pulse’s low-level period.
22
22
18
Horizontal/
vertical sync
signal
PAL
Horizontal output pulse
saturation voltage
V Hsat
Y IN:
Measure the voltage for the pin 22 horizontal
output pulse’s low-level period.
Horizontal/
vertical sync
signal
PAL
Vertical free-running
period 50 (PAL)
VFR50
VFR60
Y IN:
Measure the vertical output period T at pin 18
T×15.625kHz (PAL)
CDMODE: 001
(PAL)
No signal
Vertical free-running
period 60 (NTSC)
T×15.734kHz (NTSC)
CDMODE: 002
(NTSC)
Vertical output
2.5V
T
Horizontal output pulse
HPHCEN
(PAL)
Y IN:
Measure the delay time from to the rise of the pin
22 horizontal output pulse to the fall of the Y IN
horizontal sync signal.
22
28
Horizontal/
vertical sync
signal
(NTSC)
HPHCEN
PAL
NTSC
20IRE
2.5V
Horizontal output
Horizontal position
adjustment range
HPHrange
Y IN:
With H PHASE: 0 and 31, measure the delay time
from the rise of the pin 22 horizontal output pulse
to the fall of the Y IN horizontal sync signal and
calculate the difference from H PHCEN.
H PHASE: 00000
H PHASE: 11111
22
28
Horizontal/
vertical sync
signal
PAL
Measuring
20IRE
2.5V
Horizontal output
Continued on next page.
NoA0017-17/31
LA76850
Continued from preceding page.
Input signal
Symbol
Test point
22
Input signal
Test method
Bus conditions
Horizontal position
adjustment maximum
variable width
HPHstep
Y IN:
With H PHASE: 0 to 31 varied, measure the delay
time from to the rise of the pin 22 horizontal output
pulse to the fall of the Y IN horizontal sync signal
and calculate the variation at each step. Retrieve
data for maximum variation.
H PHASE: 00000
to
Horizontal/
vertical sync
signal
H PHASE: 11111
28
PAL
Measuring
20IRE
2.5V
Horizontal output
Horizontal blanking
BLKL0
Y IN:
Measure the time T from the left end of Hsync at
pin 28 Y IN to the left end of blanking at pin 17
BlueOUT with BLKL = 000.
BLKL: 000
22
28
left variable range@0
Horizontal/
vertical sync
signal
Hsync
Y IN
T
PAL
Blue
Horizontal blanking
BLKL7
Y IN:
Measure the time T from the left end of Hsync at
pin 28 Y IN to the left end of blanking at pin 17
BlueOUT with BLKL = 111.
BLKL:111
17
28
left variable range@7
Horizontal/
vertical sync
signal
Hsync
Y IN
T
PAL
Blue
Continued on next page.
NoA0017-18/31
LA76850
Continued from preceding page.
Input signal
Symbol
BLKR0
Test point
17
Input signal
Test method
Bus conditions
BLKR:000
Horizontal blanking
Y IN:
Measure the time T from the left end of Hsync at
pin 28 Y IN to the left end of blanking at pin 17
BlueOUT with BLKR = 000.
right variable range@0
Horizontal/
vertical sync
signal
Hsync
T
Y IN
28
PAL
Blue
Horizontal blanking
BLKR7
Y IN:
Measure the time T from the left end of Hsync at
pin 28 Y IN to the left end of blanking at pin 17
BlueOUT with BLKR = 111.
BLKR:111
17
28
right variable range@7
Horizontal/
vertical sync
signal
Hsync
T
Y IN
PAL
Blue
Sand castle pulse crest
value H
SANDH
Y IN:
Measure the supply voltage at point H of the pin 23
23
23
Horizontal/
vertical sync
signal
FBP IN wave form for Hsync period.
H
PAL
Sand castle pulse crest
value M1
SANDM1
Y IN:
Measure the supply voltage at point M1 of the pin
23 FBP IN wave form for Hsync period.
Horizontal/
vertical sync
signal
M1
PAL
Sand castle pulse crest
value L
SANDL
Y IN:
Measure the supply voltage at point L of the pin 23
FBP IN wave form for Hsync period.
23
23
Horizontal/
vertical sync
signal
PAL
L
Sand castle pulse crest
value M2
SANDM2
Y IN:
Measure the supply voltage at point M2 of the pin
23 FBP IN wave form for Vsync period.
Horizontal/
vertical sync
signal
PAL
L
Continued on next page.
NoA0017-19/31
LA76850
Continued from preceding page.
Input signal
Symbol
Test point
23
Input signal
Test method
Bus conditions
Burst gate pulse length
BGPWD
Y IN:
Measure the BGP width T of the pin 28 FBP IN
wave form for Hsync period.
Horizontal/
vertical sync
signal
T
PAL
Burst gate pulse
I phase
BGPPH
Y IN:
Measure the time from the left end of Hsync at pin
42 Y IN to the left end of the pin 23 FBP IN wave
form for Hsync period.
23
42
Horizontal/
vertical sync
signal
Hsync
Y IN
PAL
T
FBPIN
Horizontal output stop
voltage
Hstop
Y IN:
Decrease the current from a source connected to
pin 20 and measure the pin 20 voltage at which
HOUT stops.
20
22
Horizontal/
vertical sync
signal
Continued on next page.
NoA0017-20/31
LA76850
Continued from preceding page.
Input signal
Symbol
Test point
18
Input signal
Test method
Bus conditions
<Vertical screen size correction>
Vertical ramp output
Amplitude
Vspal64
Y IN:
Monitor the pin 18 vertical ramp output and
measure the voltage at line 24 (22:NTSC) and line
310 (262:NTSC).
Vsnt64
Horizontal/
vertical sync
signal
PAL@64
NTSC@64
Calculate as follows:
PAL
Vspal64 = Vline310-Vline24
NTSC
Vsnt64 = Vline262-Vline22
Vertical ramp output
Line 310
Line 24
Vertical ramp output
amplitude PAL@0
NTSC@0
Vspal0
Vsnt0
Y IN:
Monitor the pin 18 vertical ramp output and
measure the voltage at line 24 (22:NTSC) and line
310 (262:NTSC).
VSIZE: 0000000
18
Horizontal/
vertical sync
signal
Calculate as follows:
PAL
Vspal0 = Vline310-Vline24
NTSC
Vsnt0 = Vline262-Vline22
Vertical ramp output
Line 310
Line 24
Vertical ramp output
amplitude PAL@127
NTSC@127
Vspal127
Vsnt127
Y IN:
Monitor the pin 18 vertical ramp output and
measure the voltage at line 24 (22: NTSC) and line
310 (262: NTSC).
VSIZE: 1111111
18
Horizontal/
vertical sync
signal
Calculate as follows:
PAL
Vspal27 = Vline310-Vline24
NTSC
Vsnt127 = Vline262-Vline22
Vertical ramp output
Line 310
Line 24
<High-voltage dependent vertical size correction>
Vertical size
Vsizecomp
Y IN:
Monitor the pin 18 vertical ramp output and
measure the voltage at the line 24 and line 310
with VCOMP = 000. Calculate as follows:
Va = Vline310-Vline24
VCOMP: 000
18
correction@0
Horizontal/
vertical sync
signal
PAL
Apply 4.1V to pin 13 and measure the voltage at
the line 24 and line 310 again. Calculate as
follows:
Va = Vline310-Vline24
Calculate as follows:
Vsizecomp = Vb/Va
Vertical ramp output
Line 310
Line 24
Continued on next page.
NoA0017-21/31
LA76850
Continued from preceding page.
Input signal
Symbol
Test point
18
Input signal
Test method
Bus conditions
<Vertical screen position adjustment>
Vertical ramp DC
voltage
Vdcpal32
Vdcnt32
Y IN:
Monitor the pin 18 vertical ramp output and
measure the voltage at line 167. (PAL)
Monitor the pin 18 vertical ramp output and
measure the voltage at line 142. (NTSC)
Horizontal/
vertical sync
signal
PAL@32
NTSC@32
PAL
Vertical ramp output
NTSC
Line 167
Vertical ramp DC
voltage
Vdcpal0
Vdcnt0
Y IN:
Monitor the pin 18 vertical ramp output and
measure the voltage at line 167. (PAL)
Monitor the pin 18 vertical ramp output and
measure the voltage at line 142. (NTSC)
VDC: 000000
18
Horizontal/
vertical sync
signal
PAL@0
NTSC@0
PAL
Vertical ramp output
NTSC
Line 167
Vertical ramp DC
voltage
Vdcpal63
Vdcnt63
Y IN:
Monitor the pin 18 vertical ramp output and
measure the voltage at line 167. (PAL)
Monitor the pin 18 vertical ramp output and
measure the voltage at line 142. (NTSC)
VDC: 111111
Horizontal/
vertical sync
signal
18
PAL@63
NTSC@63
PAL
Vertical ramp output
NTSC
Line 167
Continued on next page.
NoA0017-22/31
LA76850
Continued from preceding page.
Input signal
Symbol
Vlin16
Test point
18
Input signal
Test method
Bus conditions
Vertical linearity@16
Y IN:
Monitor the pin 18 vertical ramp output and
measure the voltage at line 24, line 167 and 310.
Assign the respective measured values to Va, Vb
and Vc. Calculate as follows:
Horizontal/
vertical sync
signal
PAL
Vlin16 = (Vb-Va)/(Vc-Vb)
Vertical ramp output
Line 310
Line 167
Line 24
Vertical linearity@0
Vlin0
Y IN:
Monitor the pin 18 vertical ramp output and
measure the voltage at line 24, line 167 and 310.
Assign the respective measured values to Va, Vb
and Vc. Calculate as follows:
VLIN: 00000
Horizontal/
vertical sync
signal
18
PAL
Vlin0 = (Vb-Va)/(Vc-Vb)
Vertical ramp output
Line 310
Line 167
Line 24
Vertical linearity@31
Vlin31
Y IN:
Monitor the pin 18 vertical ramp output and
measure the voltage at line 24, line 167 and 310.
Assign the respective measured values to Va, Vb
and Vc. Calculate as follows:
VLIN: 11111
Horizontal/
vertical sync
signal
18
PAL
Vlin31 = (Vb-Va)/(Vc-Vb)
Vertical ramp output
Line 310
Line 167
Line 24
Continued on next page.
NoA0017-23/31
LA76850
Continued from preceding page.
Input signal
Symbol
Test point
18
Input signal
Test method
Bus conditions
VS: 10000
Vertical S-shaped
correction @16
VScor16
Y IN:
Monitor the pin 18 vertical ramp output and
measure the voltage at line 36, line 60, line 155,
line 179, line 274 and 298. Assign the
respective measured values to Va, Vb, Vc, Vd, Ve
and Vf. Calculate as follows:
Horizontal/
vertical sync
signal
PAL
VScor16 = 0.5((Vb-Va)+(Vf-Ve))/ (Vd-Vc)
Line 298
Vertical ramp output
Line 179
Line 60
Line 274
Line 155
Line 36
Vertical S-shaped
correction @0
VScor0
Y IN:
Monitor the pin 18 vertical ramp output and
measure the voltage at the line 36, line 60, line
155, line 179, line 274 and line 298
Horizontal/
vertical sync
signal
with VSC = 00000.
18
PAL
Assign the respective measured values to Va, Vb,
Vc, Vd, Ve and Vf. Calculate as follows:
VScor0 = 0.5((Vb-Va)+(Vf-Ve))/ (Vd-Vc)
Line 298
Vertical ramp output
Line 179
Line 60
Line 274
Line 155
Line 36
Vertical S-shaped
correction @31
VScor31
Y IN:
Monitor the pin 18 vertical ramp output and
measure the voltage at line 36, line 60, line 155,
line 179, line 274 and 298. Assign the
respective measured values to Va, Vb, Vc, Vd, Ve
and Vf. Calculate as follows:
VSC: 11111
18
Horizontal/
vertical sync
signal
PAL
VScor16 = 0.5((Vb-Va)+(Vf-Ve))/ (Vd-Vc)
Line 298
Vertical ramp output
Line 179
Line 60
Line 274
Line 155
Line 36
NoA0017-24/31
LA76850
Control Register Bit Allocation Map
Control Register Bit Allocations (continued)
Sub
MSB
DATA BITS
DA5
LSB
DA7
Address
DA0
DA1
DA2
0
DA3
0
DA4
DA6
0
00010000
OSD
Cnt.Test
0
OSD Contrast
1
0
0
0
10001
10010
10011
10100
10101
10110
Coring Gain(W/Defeat)
Sharpness
0
0
*
0
*
0
*
0
0
*
0
*
0
*
*
*
(0)
(0)
*
(0)
*
(0)
*
(0)
(0)
*
(0)
*
(0)
*
*
*
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
*
(0)
Trap Test
Filter.Sys
1
0
0
0
*
0
*
0
*
1
*
0
*
Gray Mode
0
Cross B/W
0
*
(0)
(0)
(0)
(0)
*
(0)
*
VBLK SW
FBPBLK.
Y_APF
Pre/Over-shoot adj.
SW
1
0
(0)
*
0
0
*
0
*
(0)
(0)
*
10111
11000
11001
Y Gamma Start
*
*
0
*
0
*
(0)
*
(0)
(0)
*
(0)
*
(0)
(0)
*
*
(0)
*
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Cont.
Test
0
Digital
OSD
0
Brt.Abl.
Def
Mid.Stp.Def
RGB Temp
Bright.Abl.Threshold
SW
0
0
0
*
1
*
0
*
0
*
11010
11011
11100
11101
*
(0)
*
*
*
*
(0)
*
(0)
*
(0)
*
(0)
(0)
*
(0)
*
(0)
*
*
(0)
(0)
*
(0)
(0)
(0)
(0)
(0)
(0)
Volume
0
(0)
0
0
1
0
0
0
0
0
0
OVER.
MOD.SW
0
VOL.FIL
RF.AGC
0
0
0
0
11110
11111
FM.Mute
0
deem.TC
VIF.Sys.SW
SIF.Sys.SW
FM.Gain
IF.AGC
0
0
0
1
*
0
*
1
*
0
*
0
*
VIDEO.LEVEL
0
1
(0)
(0)
(0)
(0)
(0)
(Bits are transmitted in this order.)
NoA0017-25/31
LA76850
Control Register Truth Table
Register Name
0 HEX
Tset Enable
Auto (Gain)
Auto (Gate)
Normal
1 HEX
2 HEX
3 HEX
T.Disable
Test Disable
Gain:Fast
Non-Gate
1/4H Shift
Mute
AFC gain&gate
V Reset Timing
Audio.Mute
Video.Mute
Sync.Kill
Active
Active
Mute
Sync active
normal
Sync killed
Vsepup
Vsepup
V.KILL
Vrt active
Normal
Vrt killed
Vrt S Corr
Test Mode
→
Vertical Test
Drive.Test
Vrt Lin
Vrt Size
Max
Normal
Half Tone
Min (Dark)
Half Tone on
Blanking
Bypass ON
Normal
→
Half Tone Def
Blank.Def
Half Tone off
No Blank
Bypass OFF
Test Mode
Min
S.TRAP.SW
OSD Cnt.Test
Coring Gain(w/Defeat)
Color.Test
Defeat
→
Max
Normal
Test Mode
External Mode
Gray OSD
Black
Video.SW
Internal Mode
Normal
Gray Mode
Cross B/W
G-Y Angle
Normal
White
Cross
240deg
253deg
VBLK SW
24H to 262H (NTSC)
25H to 309H (PAL)
FBP not or
Y Trap
29H to 256H (NTSC)
30H to 304H (PAL)
FBP or
FBPBLK.SW
Y APF
Y APF
Pre/Over-shoot adj.
Y Gamma Start
Digital OSD
Normal
+10ns
+20ns
+30ns
Max
Y Gamma off
Analogue
Min
→
Digital
Brt.ABL.Def
Mid.Stp.Def
Brt ABL On
Mid Stp On
-1Vbe
Brt ABL Off
Mid Stp Off
Flat
RGB Temp SW
OVER.MOD.(circuit)SW
VOL.FIL
circuit OFF
Normal
circuit ON
Filte OFF
Mute
FM.Mute
Active
de-em TC.
50µs
75µs
VIF.Sys.SW
FM Gain
38.0MHz
38.9MHz
25kHz dev
AGC defeat
Over-shoot Adj.
Normal
45.75MHz
39.5MHz
50kHz dev.
AGC active
Pre-shoot Adj.
Individual Operation
direction: Minus
IF.AGC
Pre/Over SW
Hlock.Vdet
VIDEO.LEVEL.OFFSET
Center
direction: Plus
NoA0017-26/31
LA76850
Control Register Truth Table
COUNT DOWN MODE
50Hz/60Hz MODE
Standard/Non-Standard MODE
0 HEX
1 HEX
2 HEX
3 HEX
4 HEX
5 HEX
6 HEX
7 HEX
Auto
50Hz
60Hz
Auto
Auto
50Hz
60Hz
Auto
Auto
Auto
Auto
Auto
Non-Standard
Non-Standard
Non-Standard
Non-Standard
Filter System
Y Filter
Chroma Filter
0 HEX
1 HEX
2 HEX
3 HEX
4 HEX
5 HEX
6 HEX
7 HEX
8-15HEX
3.58MHz Trap
3.58MHz Trap
4.43MHz Trap
4.43MHz Trap
6.0MHz Trap
6.0MHz Trap
6.0MHz Trap
6.0MHz Trap
4.286MHz Trap
Peaked 3.58MHz BPF
Symmetrical 3.58MHz BPF
Peaked 4.43MHz BPF
Symmetrical 4.43MHz BPF
Peaked 3.58MHz BPF
Symmetrical 3.58MHz BPF
Peaked 4.43MHz BPF
Symmetrical 4.43MHz BPF
Symmetrical 4.43MHz BPF
Snd.Trap & FM.Det
A2.SW
0 HEX
SIF.Sys.SW
0 HEX
1 HEX
2 HEX
3 HEX
0 HEX
1 HEX
2 HEX
3 HEX
Snd.Trap
FM.det
4.5MHz
5.5MHz
6.0MHz
6.5MHz
-----------
5.74MHz
-----------
-----------
4.5MHz
5.5MHz
6.0MHz
6.5MHz
-----------
5.5NHz
-----------
-----------
1 HEX
Audio Monitor Output
A.MONI.SW
0 HEX
AUDIO.SW
0 HEX
1pin Output
Internal
2pin Output
Internal
1 HEX
External
Internal
1 HEX
0 HEX
Internal
External
1 HEX
External
(before VOLUME)
Status Byte Truth Table
Register
RF.AGC
IF.LOCK
V.TRI
0 HEX
RF.AGC.OUT = "L"
IF.PLL Lock
V.Triger Undetected
50
1 HEX
RF.AGC.OUT = "H"
IF.PLL Unlock
V.Triger Detected
60
50/60
ST/NONST
Non-Standard
Standard
NoA0017-27/31
LA76850
Initial Conditions
Initial Test Conditions
Register Name
Initial Test Conditions (continued)
Register Name
Value
1 HEX
Value
0 HEX
T.Disable
AFC gain&gate
H.FREQ
VBLK SW
0 HEX
3F HEX
0 HEX
0 HEX
0 HEX
10 HEX
0 HEX
40 HEX
0 HEX
0 HEX
20 HEX
4 HEX
4 HEX
10 HEX
00 HEX
0 HEX
7 HEX
0 HEX
0 HEX
1 HEX
1 HEX
0 HEX
0 HEX
40 HEX
0 HEX
40 HEX
1 HEX
40 HEX
0 HEX
0 HEX
FBPBLK.SW
Y_APF
1 HEX
0 HEX
0 HEX
0 HEX
0 HEX
0 HEX
0 HEX
0 HEX
4 HEX
00 HEX
0 HEX
0 HEX
20 HEX
0 HEX
0 HEX
1 HEX
1 HEX
0 HEX
0 HEX
4 HEX
0 HEX
0 HEX
1 HEX
0 HEX
8 HEX
0 HEX
00 HEX
4 HEX
2 HEX
0 HEX
0 HEX
V Reset Timing
Audio.Mute
Video.Mute
H.PHASE
Sync.Kill
Pre/Over-shoot Adj.
Y Gamma
Digitsl OSD
Brt.Abl.Def
Mid.Stp.Def
RGB Temp SW
Bright.Abl.Threshold
Volume
V.SIZE
VSEPUP
V.KILL
V.POSI
OVER.MOD.SW
VOL.FIL
H BLK L
H BLK R
RF.AGC
V.LIN
FM.Mute
V.SC
deem.TC
V.TEST
VIF.Sys.SW
SIF.Sys.SW
FM.Gain
V.COMP
COUNT.DOWN.MODE
RGB Test 4
Half Tone
Half Tone Def
A2 SW
IF.AGC
VIDEO.LEVEL
Pre/Over SW
H lock.Vdet
Blank.Def
Sub.Bias
VIDEO.LEVEL.OFFSET
IF.TEST1
A.MONI.SW
Bright
OVER.MOD.LEVEL
Coring Gain (w/Defeat)
Sharpness
S.TRAP.SW
Contrast
Trap.Test
OSD Cnt.Test
OSD Contrast
Filter.Sys
Gray Mode
Cross B/W
NoA0017-28/31
LA76850
Control Register Descriptions
Register Name
Bits
General Description
T Disable
1
1
6
1
1
1
5
1
7
1
1
6
3
3
5
5
2
3
1
2
1
1
1
7
1
7
1
7
1
2
2
Disable the Test SW & enable Audio/Video Mute SW
Select horizontal first loop gain & H-sync gating on/off
Align ES Sample horizontal frequency
Select Vertical Reset Timing
Disable audio outputs
AFC Gain & gate
H Freq.
V Reset Timing
Audio Mute
Video Mute
Disable video outputs
H PHASE
Align sync to flyback phase
Sync Kill
Force free-run mode
Vertical Size
Align vertical amplitude
Vsep.up
Select vertical sync. separation sensitivity
Disable vertical output
Vertical Kill
V POSI (Vertical DC)
H BLK L
Align vertical DC bias
H-Blanking Control (Left side of the screen)
H-Blanking Control (Right side of the screen)
Align vertical linearity
H BLK R
V LIN (Vertical Linearity)
Vertical S-Correction
Vertical Test
Align vertical S-correction
Select vertical DAC test modes
Align vertical size compensation
Select vertical countdown mode
Adjust half tone DC level
Vertical Size Compensation
Count Down Mode
Half Tone
Half Tone Defeat
A2.SW
Half tone defeat SW
Select 5.74MHz FM.Det
Blank Def
Disable RGB output blanking
Align common RGB DC level
Sub Bias
A.MONI.SW
Select FM Output/Selected Audio Output
Customer brightness control
Select Snd Trap bypass
Brightness Control
S.TRAP.SW
Contrast Control
OSD Contrast Test
OSD Contrast Control
Customer contrast control
Enable OSD Contrast DAC test mode
Align OSD AC level
Coring Gain Select
(with Defeat)
Select Coring Gain (0hex: Defeat)
Customer sharpness control
Trap Test
Sharpness Control
Trap.Test
6
3
3
1
2
1
1
1
Select Y/C Filter mode
Filter System
OSD Gray Tone Enable
Service Test Mode (normal/Black/White/Cross)
Select VBLK Period
Gray Mode
Cross B/W
Vertical Blanking SW
FBPBLK.SW
Enable RGB Blanking or FBP
Y APF Enable SW
Select the frequency caracteristic of 3.58MHzTrap.
It is useful for 3.58MHzTrap or APF
Pre/Over-shoot Adjustmant
Y Gamma Start
2
2
2
1
1
1
1
1
3
7
1
Select Pre-shoot Width
Enable luminance coring
DC Restoration Select
Cont Test
Select Luma DC Restoration
Enable contrast DAC test mode
Select Digital/Analogue OSD
Disable brightness ABL
Digital OSD SW
Bright ABL Defeat
Bright Mid Stop Defeat
RGB Temp SW
Disable brightness mid stop
Select temprature caracteristic of RGB Output
Align brightness ABL threshold
Customer volume control
Bright ABL Threshold
Volume Control
OVER.MOD.SW
Select overmodulation circuit ON/OFF
Continued on next page.
NoA0017-29/31
LA76850
Continued from preceding page.
Register Name
Bits
1
General Description
Volume Filter Defeat
RF AGC Delay
FM Mute
Disable volume DAC filter
Align RF AGC threshold
Disable FM outputs
6
1
de-em TC.
1
Select de-emphasis Time Constant
Select 38.0/38.9/39.5/45.75
Select 4.5/5.5/6.0/6.5
VIF System SW
SIF System SW
FM Gain
2
2
1
Select FM Output Level
Disable IF and RF AGC
Align IF video level
IF AGC Defeat
Video Level
1
3
FM Level
5
Align FM output level
Pre/Over SW
H Lock Vdet
1
Select control for Pre/Over-shoot Adjustmant
Select vertical sync. Operation
Align IF video level
1
VIDEO.LEVEL.OFFSET
IF TEST1
2
1
Select test modes
OVER.MOD.LEVEL
4
Align overmodulation performance
NoA0017-30/31
LA76850
Read Status Description
RF.AGC
IF.LOCK
V.TRI
0: RF AGC = low, 1: RF AGC = high. See the separately provided documentation (Application Note) for details.
0: IF.PLL = Locked, 1: IF.PLL = Unlocked
Returns the output of the VCD internal vertical trigger detection circuit to the bus. The state of the internal memory is updated every vertical
period.
1HEX: Detected
50/60
Returns the output of the VCD internal 50/60 Hz detection output to the bus.
Returns to the bus whether a standard (262.5H) VCD or a nonstandard internal vertical trigger detection circuit output VCD is used.
Returns the FF output determined by the VCD internal mode in real time.
1HEX: Standard
ST/NONST
H.Lock
Performs FBP and Hsync phase detection, integrates that output, and detects at a point about 40H after the HVCO locks.
Returns, in real time, the state with respect to bus reads.
1Hex: Locked
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performance, characteristics, and functions of the described products in the independent state, and are
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In the event that any or all SANYO Semiconductor products (including technical data,services) described
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Any and all information described or contained herein are subject to change without notice due to
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Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
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This catalog provides information as of November, 2005. Specifications and information herein are subject to
change without notice.
This catalog provides information as of November, 2005. Specifications and information herein are subject
to change without notice.
PS NoA0017-31/31
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