SX5433M14X-X0B0 [SAMSUNG]
1/4 Optical Size 640x480 (VGA) CIS Camera Module; 1/4光学尺寸640×480 （ VGA ） CIS摄像头模块
| 型号： | SX5433M14X-X0B0 |
| 厂家： | 
SAMSUNG |
| 描述： | 1/4 Optical Size 640x480 (VGA) CIS Camera Module |
| 文件： | 总17页 (文件大小：261K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1/4 INCH VGA CIS CAMERA MODULE
SX5433M14X-X0B0
SX5433M14X-X0B0
(1/4” VGA CIS Camera Module)
PRELIMINARY
Revision 1.3
May. 2004
1
SX5433M14X-X0B0
1/4” VGA CIS CAMERA MODULE
DOCUMENT TITLE
1/4” Optical Size 640x480 (VGA) CIS Camera Module
REVISION HISTORY
Revision No.
History
Draft Date
Remark
0.0
0.1
0.2
1.0
Initial draft
Oct. 18, 2003 Preliminary
Nov. 7, 2003 Preliminary
Nov. 13, 2003 Preliminary
Nov. 25, 2003 Preliminary
Added module dimension
I2C timing modified
Specification is released
(Changed operating current, min MCLK and storage
temperature lower value and added AC characteristics).
1.1
1.2
1.3
Added ESD sensitivity
Changed product code
Nov. 27, 2003 Preliminary
Jan. 07, 2004 Preliminary
Stroke out the register map
(published a new document, ‘Register Map for 433’)
Modified the optical characteristics
May. 4, 2004 Preliminary
PRELIMINARY
This document is a general product description and is subject to change without any notice.
2
1/4 INCH VGA CIS CAMERA MODULE
SX5433M14X-X0B0
INTRODUCTION
SX5433M14X-X0B0 is a fully functional camera module with a built-in lens. A low-noise low-power color
CMOS image sensor, S5K433CA03 and an image signal processor, S5C7322X produce high-quality digital video
output in CCIR656 format at maximum 30 frames per second for full frame readout. With SAMSUNG 0.35µm
CMOS image sensor process technology which is dedicated to higher sensitivity and lower-dark level compared
to standard CMOS process, and on-chip CDS and 10-bit column ADC circuit embedded, the CMOS image sensor
provides high signal-to-noise ratio with low power consumption. This compact camera system consists of an
image sensor, a signal processor and some passive components packed with IR-cut filter and lens units. The
system works with 2.8V single power supply and a clock. All the functions are controlled with control register
setting through the standard 2-wire serial interface.
FEATURES
— Optical Size: 1/4 inch
— Unit Pixel: 5.6 µm X 5.6 µm
— Effective Resolution: 640X480, VGA
— 8.5mm X 9.5mm X 6.6mm module size
— 8-bit CCIR656 (YCrCb) Video Output
— VGA Output Capability
— Programmable Gamma Correction
— Auto White Balance and Auto Exposure Control
— Horizontal and/or Vertical Mirror Output
PRELIMINARY
— Standby-Mode for Power Saving
— Maximum 30 Frame per Second
— Single Power Supply Voltage: 2.8V
— I2C Type Control Interface
3
SX5433M14X-X0B0
1/4” VGA CIS CAMERA MODULE
BLOCK DIAGRAM
S5C7322X
Image Signal Processor
S5K433CA03
CMOS Image Sensor
Lens Unit
Line Buffer
Pixel Array
640(H) X 480(V)
Pre Processor
Iuminance
Signal
Chroma
Signal
Processor
Processor
Timing Controller
Post Processor
MCLK
RISC Processor
VSYNC
Output
HSYNC
PCLK
Formatter
PREL
(AE, AWB processor)
DATA[0:7]
I2C Bus
SDA
SCL
STBY
RST
4
1/4 INCH VGA CIS CAMERA MODULE
SX5433M14X-X0B0
OPTICAL CHARACTERISTICS
Characteristic
Effective Pixels
Pixel Size
EFL
Value
640 (H) X 480 (V), VGA
5.6µm (H) X 5.6µm (V), square pixel
3.385mm
F/#
2.8
Diagonal
67.87°
FOV
MTF
Horizontal
Vertical
TV-Distortion
Relative Illumination
56.44°
43.59°
-0.33%
54.40%
59.90% at 80 lp/mm
72.60% at 50 lp/mm
21.30% at 80 lp/mm
42.30% at 50 lp/mm
All Plastic Lens (2P)
22cm ~ ∞
Center
0.7 Field
Lens Construction
Focus Range
PRELIMINARY
5
SX5433M14X-X0B0
1/4” VGA CIS CAMERA MODULE
IO PIN DESCRIPTION
(Connector type and pin numbers can be changed as customer’s request.)
Module
Pad
Connector
Pin
Pin Name
Type
Notation
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
9
VDDDI
GNDI
SCL
SDA
RST
STBY
MCLK
VSYNC
HSYNC
PCLK
DATA0
DATA1
DATA2
DATA3
Power
Ground
In / Out
In / Out
In
In
In
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Power supply for signal processor (digital)
Ground for signal processor
I2C serial communication clock
I2C serial communication data
Reset control (active low)
Standby mode control (active low)
Master input clock
Vertical synchronization clock
Horizontal synchronization clock
Pixel output clock
10
15
16
11
12
20
17
18
19
8
7
6
5
4
3
8-bit digital video output
PRELIMINARY
DATA4
DATA5
DATA6
DATA7
GNDC
2
1
13
9
14
Ground
Power
Power
Ground for sensor circuit block
Power supply for sensor digital circuit block
Power supply for sensor analog circuit block
VDDCD
VDDCA
6
1/4 INCH VGA CIS CAMERA MODULE
SX5433M14X-X0B0
MAXIMUM ABSOLUTE RATINGS
Characteristic
Symbol
Rating
Unit
Maximum supply voltage
(VDDDI, VDDAC, VDDC supply
relative to GNDI, GNDC)
VDD
-0.3 to 3.8
V
VIN
-0.3 to VDD+0.3 (Max. 3.8)
-20 to +60
DC Input voltage
TOPR
TSTG
Operating temperature
Storage temperature
°C
-40 to +85
ELECTRICAL CHARACTERISTICS
DC Characteristics
(TA = -20 to +60°C, CL = 15pF)
Characteristics
Operating voltage
Symbol
VDD
Condition
VDDDI, VDDAC, VDDC
Min
2.55
2.0
-
Typ
Max
3.05
-
Unit
2.8
V
VIH
VIL
IIL
-
-
-
-
Input voltage (1)
V
-
0.8
10
Input leakage current(1)
VIN = VDD to VSS
IOH = -4mA(2)
OH = -8mA(3)
IOL = 4mA(2)
OL = 8mA(3)
-10
µA
PRELIMINARY
High Level Output
voltage
VOH
0.8VDD
-
-
I
V
Low Level Output
voltage
VOL
0.2VDD
10
-
-
I
High-Z output leakage
current (4)
IOZ
VOUT = VDD
-
-
µA
STBYN = Low (active)
All input clocks = Low
fMCLK = 13.5MHz, 15 fps
ISTB
IDD
-
-
15
31
-
µA
Supply current
36
mA
NOTES:
1. MCLK, RST, STBY, SCL, and SDA pin.
2. HSYNC, VSYNC, SCL, and SDA pin
3. PCLK, DATA0 to DATA7 pin
4. SCL and SDA pin when in High-Z output state
7
SX5433M14X-X0B0
1/4” VGA CIS CAMERA MODULE
Sensor Imaging Characteristics
(Light source with 3200K of color temperature and IR cut filter (CM-500S, 1mm thickness) is used. Electrical
operating conditions follow the recommended typical values. The control registers are set to the default values.
The ambient temperature, TA is 25°C if not specified.)
Characteristic
Saturation level(1)
Symbol
VSAT
Condition
Min
850
Typ
900
Max
-
Unit
mV
Sensitivity (G)(2)
S
-
-
2000
9
-
mV/lux sec
18
TA = 40°C
TA = 60°C
Dark level(3)
VDARK
mV/sec
-
50
100
Dynamic range(4)
Signal to noise ratio(5)
Dark signal non-uniformity(6)
DR
S/N
-
-
-
60
40
-
-
-
dB
mV/sec
%
DSNU
100
TA = 60°C
Photo response non-
PRNU
-
4
8
uniformity(7)
Vertical fixed pattern noise(8)
Horizontal fixed pattern noise(9)
VFPN
HFPN
4
4
8
8
%
%
NOTES:
1. Measured minimum output level at 100lux illumination for exposure time 1/30 sec. 7X7 rank filter is applied for the whole
PRELIMINARY
pixel area to eliminate the values from defective pixels.
2. Measured average output at 25% of saturation level illumination for exposure time 1/30 sec. Green channel output values
are used for color version.
3. Measured average output at zero illumination without any offset compensation for exposure time 1/30 sec.
4. 20 log (saturation level/ dark level RMS noise excluding fixed pattern noise). 10-bit ADC limits 60dB.
5. 20 log (average output level/RMS noise excluding fixed pattern noise) at 25% of saturation level illumination for exposure
time 1/30 sec.
6. Difference between maximum and minimum pixel output levels at zero illumination for exposure time 1/30 sec. 7X7 median
filter is applied for the whole pixel area to eliminate the values from defective pixels.
7, Difference between maximum and minimum pixel output levels divided by average output level at 25% of saturation level
illumination for exposure time 1/30 sec. 7X7 median filter is applied for the whole pixel area to eliminate the values from
defective pixels.
8. For the column-averaged pixel output values, maximum relative deviation of values from 7-depth median filtered values for
neighboring 7 columns at 25% of saturation level illumination for exposure time 1/30 sec.
9. For the row-averaged pixel output values, maximum relative deviation of values from 7-depth median filtered values for
neighboring 7 columns at 25% of saturation level illumination for exposure time 1/30 sec.
8
1/4 INCH VGA CIS CAMERA MODULE
AC Characteristics
SX5433M14X-X0B0
°
(VDD = 2.55V to 3.05V, Ta = -20 to + 60 C)
Characteristic
Symbol
Condition
Min
Typ
Max
Unit
fMCLK
Main input clock frequency
Duty = 50%
5
24.54
30
MHz
(VDDH = 2.8V ± 0.25, Ta = 0 to + 70 °C)
Characteristic
Output Data Delay Time, Data [0:7]
Symbol
TDLY
Min
0.5
Typ
-
Max
3
Unit
ns
PCLK
Tdly
Data [0:7]
Setup and Hold Time
(VDDL = 1.8V ± 0.15, Ta = 0 to + 70 °C, CL = 0.011pF)
PRELIMINARY
Characteristic
Output Data Setup Time, Data [0:7]
Output Data Hold Time, Data [0:7]
Symbol
TSU
Min
0.217
0.217
Typ
-
-
Max
-
-
Unit
ns
THD
ns
DATA[0:7]
CLK
50%
50%
50%
Thd
Tsu
9
SX5433M14X-X0B0
1/4” VGA CIS CAMERA MODULE
Rise and Fall Transition Time
(VDDL = 1.8V ± 0.15, Ta = 0 to + 70 °C, CL = 0.011pF)
Characteristic
Output Data, Data [0:7]
Symbol
Min
-
-
Typ
-
-
Max
4.709
4.338
Unit
ns
TR
TF
ns
90%
90%
10%
TR
10%
TF
ESD Sensitivity
(CMOS Image Sensor IC)
Item
Condition
C = 100 pF, R = 1.5KΩ
Result
Human Body Model (HBM)
±1500V↑
±200V↑
±800V↑
PRELIMINARY
Machine Model (MM)
C = 200 pF, R = 0Ω
Charged Device Model (CDM)
(Image Signal Processor IC)
Item
Human Body Model (HBM)
Machine Model (MM)
Charged Device Model (CDM)
Condition
Result
±2000V↑
±200V↑
±500V↑
C = 100 pF, R = 1.5KΩ
C = 200 pF, R = 0Ω
OUTPUT IMAGE MODE
No.
Mode
Resolution
(H X V)
1
2
3
VGA
QVGA
QQVGA
640X480
320X240
160X120
10
1/4 INCH VGA CIS CAMERA MODULE
SX5433M14X-X0B0
OUTPUT DATA FORMAT
YCRCB 4:2:2 FORMAT
VSYNC
HSYNC
DATA
Y0
CB0
CR0
Y0
Y1
CR0
CB0
Y1
Y0
CB0
CR0
Y0
Y1
CR0
CB0
Y1
(Mode1)
DATA
Y0
Y1
Y0
Y1
(Mode2)
DATA
CB0
CR0
CR0
CB0
CB0
CR0
CR0
CB0
(Mode3)
DATA
Y0
Y1
Y0
Y1
(Mode4)
RGB565 FORMAT
VSYNC
HSYNC
DATA
RG0 GB0 RG1 GB1
RG0 GB0 RG1 GB1
(Mode1)
PRELIMINARY
R0[4:0] / G0[5:3]
G0[2:0] / B0[4:0]
DATA
BG0 GR0 BG1 GR1
BG0 GR0 BG1 GR1
(Mode2)
B0[4:0] / G0[5:3]
G0[2:0] / R0[4:0]
SENSOR RAW IMAGE (BAYER MOSAIC PATTERN) FORMAT
VSYNC
HSYNC
D0H D0L D1H D1L
D0H D0L D1H D1L
DATA
6’b000000, D0[9:8]
D0[7:0]
11
SX5433M14X-X0B0
1/4” VGA CIS CAMERA MODULE
Address: FAh[5:4]=2, F7h[7:0]=B0
OUTPUT TIMING DIAGRAMS
HORIZONTAL TIMING
Address: FAh[7:6]=0, F6h[7:0]=30
1 row
HSYNC
PCLK
( 640 columns )
DATA [0:7]
VGA OUTPUT TIMING
Address: FAh[3:2]=0, F8h[7:0]=03
Address: FAh[1:0]=0, F9h[7:0]=05
1 frame
2H
VSYNC
1 row
HSYNC
PRELIMINARY
DATA [0:7]
(480 rows )
(525 rows )
NOTES:
1. Falling and rising time of HSYNC and VSYNC can be controlled by register settings.
2. Each default value of rising and falling time control registers is described in the diagram above.
12
1/4 INCH VGA CIS CAMERA MODULE
SX5433M14X-X0B0
Remarks
IMAGE PROCESSING FUNCTIONS
Function
Description
Defect detection and
correction
If enabled, the function detects the defective pixel by
comparing its level with horizontally neighboring pixels, and
replaces it with the average value of neighboring pixels.
De-mosaic
The sensor produces one color component from a pixel
according to Bayer color filter array. The de-mosaic function
performs color interpolation to produce all three-color
components at each pixel location.
Color correction
Gamma correction
The spectral response of image sensor is different from that
of human eye. To match the spectral response, the sensor
output components are pivoted by user programmable 3X3
matrix production.
Gamma correction translating the linear response of the
sensor into the non-linear characteristics of the display. Non-
linear conversion requires a piecewise linear approximation
method based on user programmable lookup table.
Horizontal mirror
Vertical mirror
The output image can be mirrored in horizontal direction.
The output image can be mirrored in vertical direction.
Edge enhancement
Enhancing the edge component provides a clear output
image. The edge enhancement function is performed through
horizontal and vertical edge detecting and enhancing.
Auto exposure
According to the incident light level, the auto exposure
function controls the sensor gain and effective integration time
PRELIMINARY
to maintain the proper output level. Setting the control registers
can change the sensing area used in the AE algorithm.
Auto white balance
The auto white balance function adjusts the gain of the
sensor’s red and blue channels relative to the green channel,
and compensates the spectral unbalancing of the light source.
Setting the control registers can change the sensing area used
in the AWB algorithm.
Output format conversion
4 types of output format are available.
(CCIR656 format, CCIR601 format, RGB format and sensor
raw image output format)
Sub-sampling Control
The user can read out the pixel data in sub-sampling rate in
both horizontal and vertical direction. Sub-sampling can be
done in two rates: full and 1/2. The user controls the sub-
sampling using the Sub-sampling Control Registers, subsr and
subsc. The sub-sampling is performed only in the Bayer
space.
13
SX5433M14X-X0B0
1/4” VGA CIS CAMERA MODULE
I2C SERIAL INTERFACE
The I2C contains a serial two-wire half duplex interface that features bi-directional operation, master or slave
mode. The general SDA and SCL are the bi-directional data and clock pins, respectively. These pins are open-
drain type ports and will require a pull-up resistor to VDD. The image sensor operates in salve mode only and the
SCL is input only. The I2C bus interface is composed of following parts: START signal, 7-bit slave device address
(0101101Xb) transmission followed by a read/write bit, an acknowledgement signal from the slave, 8-bit data
transfer followed by an acknowledgement signal and STOP signal. The SDA bus line may only be changed while
SCL is low. The data on the SDA bus line is valid on the high-to-low transition of SCL.
T1
T2
T1
T1
SCL
SDA
D7 D6 D5 D4 D5 D2 D1 D0
I2C Register Address
“0” “1” “0” “1” “1” “0” “1”
“0”
I2C Bus Address
Ack
Start
Write Ack
T1
PRELIMINARY
SCL
SDA
D7 D6 D5 D4 D3 D2 D1 D0
Data to Write
Ack
Stop
I2C Bus Write Cycle
14
1/4 INCH VGA CIS CAMERA MODULE
SX5433M14X-X0B0
T1
T2
T1
SCL
SDA
D7 D6 D5 D4 D5 D2 D1 D0
“0” “1” “0” “1” “1” “0” “1” “1”
I2C Bus Address
Read
ACK
ACK
I2C Register Address
START
T1
T1
SCL
SDA
D7 D6 D5 D4 D3 D2 D1 D0
Data to be Read
ACK
STOP
I2C Bus Read Cycle
Main Clock - 13.5MHz
PRELIMINARY
Characteristic
Low period of SCL clock
Clock period
Symbol
T1
T2
TBUF
Min
13.5
13.5
100
Typ
15
15
Max
Unit
-
-
-
µsec
µsec
µsec
Bus free time between a STOP and START condition
NOTES:
1. The basic frequency of main clock is 13.5MHz for all the followed comments.
2. If you don’t have ACK signal on the way of communications through I2C, it means that I2C error is generated.
3. If you have any I2C error, try again after 2VSYNC (The I2C error is reset every 2VSYNC automatically).
4. If any error is not generated till one command is completed, you can transfer another after 4msec
5. The time value of T1, T2, T3, and TBUF is proportional to the change of MCLK.
6. I2C Bus read format is different from I2C standard format.
15
SX5433M14X-X0B0
1/4” VGA CIS CAMERA MODULE
MECHANICAL DIMENSION (UNIT = MM)
PRARY
16
1/4 INCH VGA CIS CAMERA MODULE
SX5433M14X-X0B0
PRELIMINARY
©2003 Samsung Electronics
All right reserved. No part of this publication may be reproduced, stored in a
retrieval system, or transmitted in any form or by any means, electric or
mechanical, by photocopying, recording, or otherwise, without the prior written
consent of Samsung Electronics.
Samsung Electronics Co., Ltd.
San #24 Nongseo-Ri, Giheung-Eup
Yongin-City, Gyeonggi-Do, Korea
C.P.O. Box #37, Suwon 449-900
Homepage: http://www.samsungsemi.com/
17
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