SX5437M21X-X0B0 [SAMSUNG]
1/4 Optical Size 640x480(VGA) CIS Camera Module; 1/4光学尺寸640×480 ( VGA ) CIS摄像头模块型号: | SX5437M21X-X0B0 |
厂家: | SAMSUNG |
描述: | 1/4 Optical Size 640x480(VGA) CIS Camera Module |
文件: | 总18页 (文件大小:266K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
1/4 INCH VGA CIS CAMERA MODULE
PRELIMINARY
SX5437M21X-X0B0
SX5437M21X-X0B0
(1/4” VGA CIS Camera Module)
PRELIMINARY
Preliminary Specification
Revision 1.3
May. 2004
1
SX5437M21X-X0B0
PRELIMINARY
1/4 VGA CIS CAMERA MODULE
DOCUMENT TITLE
1/4” Optical Size 640x480(VGA) CIS Camera Module
REVISION HISTORY
Revision No.
History
Draft Date
Remark
Aug 14, 2003 Preliminary
Oct. 31, 2003 Preliminary
0.0
0.1
Initial draft
Added register map and changed timing diagram
Added module dimension
0.2
1.0
Fixed some bugs
Nov. 19, 2003 Preliminary
Dec. 31, 2003 Preliminary
Changed I2C timing diagram
Changed product code
(S5X437CX03-20R0 Æ SX5437M21X-X0B0)
1.1
1.2
Changed the register map
Jan. 7, 2004
Preliminary
Stroke out the register map
(published a new document, ‘Register Map for 437’)
Apr.29, 2004 Preliminary
May.4, 2004 Preliminary
1.3
Modified the optical characteristics
PRELIMINARY
This document is a general product description and is subject to change without any notice.
2
1/4 INCH VGA CIS CAMERA MODULE
PRELIMINARY
SX5437M21X-X0B0
INTRODUCTION
The SX5437M21X-X0B0 is fully functional camera module with a built-in lens. A low-noise low-power color
CMOS image sensor, S5K437CX03 and an image signal processor, S5C7323X produce high-quality digital video
output including CCIR656 format with maximum 30 frames per second for full frame readout. With SAMSUNG
0.35µm CMOS image sensor process technology which is dedicated to higher sensitivity and lower-dark level
compared to standard CMOS process, and on-chip CDS and 10-bit column ADC circuit embedded, the CMOS
image sensor provides high signal-to-noise ratio with low power consumption. This compact camera system
consists of an image sensor, a signal processor and some passive components packed with IR-cut filter and lens
units. The system works with 2.8V single power supply and a clock. All the functions are controlled with control
register setting through the standard 2-wire serial interface.
FEATURES
— Optical Size: 1/4 inch format
— Unit Pixel: 5.6 µm X 5.6 µm
— Effective Resolution: 640(H) X 480(V), VGA
— 8.5mm X 9.5mm X 6.6mm module size
— 8-bit ITU.R-656 (YCrCb) Video Output
— Programmable Gamma Correction
— Auto White Balance and Auto Exposure Control
— Horizontal and/or Vertical Mirror Output
— Standby-Mode for Power Saving
PRELIMINARY
— Maximum 30 Frame per Second
— Single Power Supply Voltage: 2.8V
— I2C Type Control Interface
— Bad Pixel Replacement Function
— Noise Canceling Function
— Shading Correction Function
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SX5437M21X-X0B0
PRELIMINARY
1/4 VGA CIS CAMERA MODULE
BLOCK DIAGRAM
S5C7323X
Image Signal Processor
S5K437CA03
CMOS Image Sensor
Lens Unit
Line Buffer
Pixel Array
640(H) X 480(V)
Pre Processor
Chroma
Signal
Luminance
Signal
Processor
Processor
Timing Controller
Post Processor
MCLK
RISC Processor
(AE, AWB processor)
VSYNC
HSYNC
PCLK
Output
Formatter
PREL
DATA[0:7]
I2C Bus
SDA
SCL
STBY
RST
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1/4 INCH VGA CIS CAMERA MODULE
PRELIMINARY
SX5437M21X-X0B0
OPTICAL CHARACTERISTICS
Characteristic
Effective Pixels
Pixel Size
EFL
Value
640 (H) X 480 (V), VGA
5.6µm (H) X 5.6µm (V), square pixel
3.385mm
F/#
2.8
Diagonal
67.87°
FOV
MTF
Horizontal
Vertical
TV-Distortion
Relative Illumination
56.44°
43.59°
-0.33%
54.40%
59.90% at 80 lp/mm
72.60% at 50 lp/mm
21.30% at 80 lp/mm
42.30% at 50 lp/mm
All Plastic Lens (2P)
22cm ~ ∞
Center
0.7 Field
Lens Construction
Focus Range
PRELIMINARY
5
SX5437M21X-X0B0
PRELIMINARY
1/4 VGA CIS CAMERA MODULE
MODULE PAD DESCRIPTION
(Module pad numbers and name can be changed as customer’s request.)
Module
Pad No.
Connector
Name
Type
Description
Pin No. (*)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
VDDDI
GNDI
SCL
SDA
RST
9
10
15
16
11
12
20
17
18
19
8
Power
Ground
In/Out
In/Out
In
In
In
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Power supply for signal processor (digital)
Ground for signal processor
I2C serial communication clock
I2C serial communication data
Reset control (active low)
Standby control(active low)
Master input clock
Vertical synchronization clock
Horizontal synchronization clock
Pixel output clock
STBY
MCLK
VSYNC
HSYNC
PCLK
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
GNDC
VDDDC
VDDAC
7
6
5
8-bit digital video output
4
PRELIMINARY
3
2
1
13
9
14
Ground
Power
Power
Ground for sensor circuit block
Power supply for sensor digital circuit block
Power supply for sensor analog circuit block
NOTES: (*) See [Cf] p. 32.
PAD 1
PAD 21
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1/4 INCH VGA CIS CAMERA MODULE
PRELIMINARY
Symbol
SX5437M21X-X0B0
MAXIMUM ABSOLUTE RATINGS
Characteristic
Rating
Unit
Maximum supply voltage (VDDDI, VDDAC, VDDC
supply relative to GNDI, GNDC)
VDD
-0.3 to 3.8
V
VIN
-0.3 to VDD+0.3 (Max. 3.8)
*-20 to +60
DC Input voltage
TOPR
TSTG
*Operating temperature
*Storage temperature
°C
*-40 to +85
NOTES: *Operating temperature and *Storage temperature are not confirmed.
ELECTRICAL CHARACTERISTICS
DC Characteristics
(TA = -20 to +60°C, CL = 15pF)
Characteristics
Symbol
Condition
Min
Typ
Max
Unit
VDD
Operating voltage
VDDCA, VDDCD, VDDI
2.55
2.8
3.1
V
VIH
VIL
-
-
2.05
-
-
-
-
Input voltage (1)
V
0.8
Input leakage
current(1)
High level output
voltage
IIL
VIN = VDD to VS
-10
-
10
-
µA
PRELIM
S
INARY
IOH = -1mA(2)
OH = -4mA(3)
IOL = 1mA(2)
OL = 4mA(3)
VOH
0.8VDD
-
I
V
Low level output
voltage
VOL
0.2VDD
10
-
-
I
High-Z output
IOZ
VOUT = VDD
-
-
µA
leakage current (4)
STBY = Low (active)
All input clocks = Low
fMCLK = 12MHz, 15fps
ISTB
IDD
-
-
-
TBD
-
µA
Supply current
TBD
mA
NOTES:
1. MCLK, RSTN, STBY, SCL, and SDA pin.
2. HSYNC, VSYNC, SCL, and SDA pin
3. PCLK, YCO0 to YCO7 pin
4. SCL and SDA pin when in High-Z output state
7
SX5437M21X-X0B0
PRELIMINARY
1/4 VGA CIS CAMERA MODULE
Sensor Imaging Characteristics
(Light source with 3200K of color temperature and IR cut filter (CM-500S, 1mm thickness) is used. Electrical
operating conditions follow the recommended typical values. The control registers are set to the default values.
The ambient temperature, TA is 25°C if not specified.)
Characteristic
Saturation level(1)
Symbol
VSAT
Condition
Min
850
Typ
900
Max
-
Unit
mV
Sensitivity (G)(2)
S
-
-
1500
9
-
mV/lux sec
18
TA = 40°C
TA = 60°C
Dark level(3)
VDARK
mV/sec
-
50
100
Dynamic range(4)
Signal to noise ratio(5)
Dark signal non-uniformity(6)
DR
S/N
-
-
-
60
40
-
-
-
dB
mV/sec
%
DSNU
100
TA = 60°C
Photo response non-
PRNU
-
4
8
uniformity(7)
Vertical fixed pattern noise(8)
Horizontal fixed pattern noise(9)
VFPN
HFPN
4
4
8
8
%
%
NOTES:
1. Measured minimum output level at 100lux illumination for exposure time 1/30 sec. 7X7 rank filter is applied for the whole
pixel area to eliminate the values from defective pixels.
PRELIMINARY
2. Measured average output at 25% of saturation level illumination for exposure time 1/30 sec. Green channel output values
are used for color version.
3. Measured average output at zero illumination without any offset compensation for exposure time 1/30 sec.
4. 20 log (saturation level/ dark level RMS noise excluding fixed pattern noise). 10-bit ADC limits 60dB.
5. 20 log (average output level/RMS noise excluding fixed pattern noise) at 25% of saturation level illumination for exposure
time 1/30 sec.
6. Difference between maximum and minimum pixel output levels at zero illumination for exposure time 1/30 sec. 7X7 median
filter is applied for the whole pixel area to eliminate the values from defective pixels.
7, Difference between maximum and minimum pixel output levels divided by average output level at 25% of saturation level
illumination for exposure time 1/30 sec. 7X7 median filter is applied for the whole pixel area to eliminate the values from
defective pixels.
8. For the column-averaged pixel output values, maximum relative deviation of values from 7-depth median filtered values for
neighboring 7 columns at 25% of saturation level illumination for exposure time 1/30 sec.
9. For the row-averaged pixel output values, maximum relative deviation of values from 7-depth median filtered values for
neighboring 7 columns at 25% of saturation level illumination for exposure time 1/30 sec.
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1/4 INCH VGA CIS CAMERA MODULE
AC Characteristics
PRELIMINARY
SX5437M21X-X0B0
(VDDH = 2.8V ± 0.25V, VDDL = 1.8V ± 0.15V, Ta = -20 to + 60 °C, CL = 50pF)
Characteristic
Main input clock frequency
Symbol
fMCLK
Condition
Duty = 50%
Min
3(1)
Typ
24.54
Max
30
Unit
MHz
Output data delay time
from PCLK
tDLY
Ta =0~70℃
0.7
3.5
ns
tWRST
tWSTB
Reset input pulse width
RSTN=low(active)
STBYN=low(active)
5
4
-
-
-
-
(2)
TMCLK
Standby input pulse width
NOTES:
1. 8-bit ADC resolution case. If 10-bit ADC resoultion is used, the frequency should be over 12MHz.
2. The period time of main input clock, MCLK.
(VDDH = 2.8V ± 0.25, Ta = 0 to + 70 °C)
Characteristic
Symbol
Min
Typ
Max
Unit
Output Data Delay Time, Data [0:7]
TDLY
0.7
-
3.5
ns
PCLK
Tdly
PRELIMINARY
Data [0:7]
9
SX5437M21X-X0B0
PRELIMINARY
1/4 VGA CIS CAMERA MODULE
Setup and Hold Time
(VDDL = 1.8V ± 0.15, Ta = 0 to + 70 °C)
Characteristic
Output Data Setup Time, Data [0:7]
Output Data Hold Time, Data [0:7]
Symbol
TSU
Min
0.217
0.217
Typ
-
-
Max
-
-
Unit
ns
THD
ns
DATA[0:7]
CLK
50%
50%
50%
Thd
Tsu
Rise and Fall Transition Time
(VDDL = 1.8V ± 0.15, Ta = 0 to + 70 °C)
Characteristic
Output Data, Data [0:7]
Symbol
TR
Min
-
Typ
-
Max
4.709
4.338
Unit
ns
TF
-
-
ns
PRELIMINARY
90%
90%
10%
10%
TR
TF
OUTPUT IMAGE MODE
No.
Mode
Resolution
(H X V)
Data rate
(PCLK)
Zoom
Frame Rate
1
VGA
640 X 480
MCLK
-
30 FPS
10
1/4 INCH VGA CIS CAMERA MODULE
PRELIMINARY
SX5437M21X-X0B0
OUTPUT DATA FORMAT
YCRCB 4:2:2 FORMAT
VSYNC
HSYNC
DATA
Y0
CB0
CR0
Y0
Y1
CR0
CB0
Y1
Y0
CB0
CR0
Y0
Y1
CR0
CB0
Y1
(Mode1)
DATA
Y0
Y1
Y0
Y1
(Mode2)
DATA
CB0
CR0
CR0
CB0
CB0
CR0
CR0
CB0
(Mode3)
DATA
Y0
Y1
Y0
Y1
(Mode4)
RGB565 FORMAT
VSYNC
HSYNC
DATA
RG0 GB0 RG1 GB1
RG0 GB0 RG1 GB1
(Mode1)
PRELIMINARY
R0[4:0] / G0[5:3]
G0[2:0] / B0[4:0]
DATA
BG0 GR0 BG1 GR1
BG0 GR0 BG1 GR1
(Mode2)
B0[4:0] / G0[5:3]
G0[2:0] / R0[4:0]
SENSOR RAW IMAGE (BAYER MOSAIC PATTERN) FORMAT
VSYNC
HSYNC
DATA
D0H D0L D1H D1L
D0H D0L D1H D1L
6’b000000, D0[9:8]
D0[7:0]
11
SX5437M21X-X0B0
PRELIMINARY
1/4 VGA CIS CAMERA MODULE
Address: FAh[5:4]=2, F7h[7:0]=B0
OUTPUT TIMING DIAGRAMS
HORIZONTAL TIMING
Address: FAh[7:6]=0, F6h[7:0]=30
1 row
HSYNC
PCLK
( 640 columns )
DATA [0:7]
VGA OUTPUT TIMING
Address: FAh[3:2]=0, F8h[7:0]=03
Address: FAh[1:0]=0, F9h[7:0]=05
1 frame
2H
VSYNC
1 row
HSYNC
DATA [0:7]
PRELIMINARY
(480 rows )
(525 rows )
NOTES:
1. Falling and rising time of HSYNC and VSYNC can be controlled by register settings.
2. Each default value of rising and falling time control registers is described in the diagram above.
12
1/4 INCH VGA CIS CAMERA MODULE
PRELIMINARY
SX5437M21X-X0B0
Remarks
IMAGE PROCESSING FUNCTIONS
Function
Description
Defect detection and
correction
If enabled, the function detects the defective pixel by
comparing its level with horizontally neighboring pixels, and
replaces it with the average value of neighboring pixels.
De-mosaic
The sensor produces one color component from a pixel
according to Bayer color filter array. The de-mosaic function
performs color interpolation to produce all three-color
components at each pixel location.
Color correction
Gamma correction
The spectral response of image sensor is different from that
of human eye. To match the spectral response, the sensor
output components are pivoted by user programmable 3X3
matrix production.
Gamma correction translating the linear response of the
sensor into the non-linear characteristics of the display. Non-
linear conversion requires a piecewise linear approximation
method based on user programmable lookup table.
Horizontal mirror
Vertical mirror
The output image can be mirrored in horizontal direction.
The output image can be mirrored in vertical direction.
Edge enhancement
Enhancing the edge component provides a clear output
image. The edge enhancement function is performed through
horizontal and vertical edge detecting and enhancing.
Auto exposure
According to the incident light level, the auto exposure
function controls the sensor gain and effective integration time
PRELIMINARY
to maintain the proper output level. Setting the control registers
can change the sensing area used in the AE algorithm.
Auto white balance
The auto white balance function adjusts the gain of the
sensor’s red and blue channels relative to the green channel,
and compensates the spectral unbalancing of the light source.
Setting the control registers can change the sensing area used
in the AWB algorithm.
Output format conversion
4 types of output format are available.
(CCIR656 format, CCIR601 format, RGB format and sensor
raw image output format)
Sub-sampling Control
The user can read out the pixel data in sub-sampling rate in
both horizontal and vertical direction. Sub-sampling can be
done in two rates: full and 1/2. The user controls the sub-
sampling using the Sub-sampling Control Registers, subsr and
subsc. The sub-sampling is performed only in the Bayer
space.
13
SX5437M21X-X0B0
PRELIMINARY
1/4 VGA CIS CAMERA MODULE
I2C SERIAL INTERFACE
The I2C contains a serial two-wire half duplex interface that features bi-directional operation, master or slave
mode. The general SDA and SCL are the bi-directional data and clock pins, respectively. These pins are open-
drain type ports and will require a pull-up resistor to VDD. The image sensor operates in salve mode only and the
SCL is input only. The I2C bus interface is composed of following parts: START signal, 7-bit slave device address
(0101101Xb) transmission followed by a read/write bit, an acknowledgement signal from the slave, 8-bit data
transfer followed by an acknowledgement signal and STOP signal. The SDA bus line may only be changed while
SCL is low. The data on the SDA bus line is valid on the high-to-low transition of SCL.
A5
A4
A3
A2
A1
A0
A7
A6
SDA
SCL
“0”
“1” “0” “1” “1” “0” “1” “0”
WRITE ACK
START
ACK
BUS ADDRESS
REGISTER ADDRESS
PRELIMINARY
SDA
SCL
D5
D4
D3
D2
D1
D0
D7
D6
ACK
STOP
DATA
I2C Bus Write Format
14
1/4 INCH VGA CIS CAMERA MODULE
PRELIMINARY
SX5437M21X-X0B0
A5
A4
A3
A2
A1
A0
A7
A6
SDA
SCL
“0”
“1” “0” “1” “1” “0” “1” “0”
WRITE ACK
START
ACK
BUS ADDRESS
REGISTER ADDRESS
D5
D4
D3
D2
D1
D0
D7
D6
SDA
SCL
“0”
“1” “0” “1” “1” “0” “1” “1”
READ ACK
NOACK
STOP
RESTART
BUS ADDRESS
DATA
I2C Bus Read Format
PRELIMINARY
SDA
SCL
tHIGH
tHD:STO
tHD:BUF
tHD:STA tLOW
tHD:BYTE
tHD:STA
I2C Bus Timing
15
SX5437M21X-X0B0
PRELIMINARY
1/4 VGA CIS CAMERA MODULE
PARAMETER
SCL clock frequency
Low period of the SCL clock
High period of the SCL clock
Hold time START condition
Hold time STOP condition
Symbol
Min
Max
400
Unit
kHZ
µsec
µsec
µsec
µsec
tMCLK
tMCLK
fClk
tLOW
tHIGH
tSTA
tSTO
tBYTE
tBUF
1.3
0.6
0.6
0.6
130
130
Bus free time between BYTE and BYTE data
Bus free time between a STOP and START condition
NOTES:
1. tMclk : Main clock period
PRELIMINARY
16
1/4 INCH VGA CIS CAMERA MODULE
PRELIMINARY
SX5437M21X-X0B0
MODULE DIMENSION
PREARY
17
SX5437M21X-X0B0
PRELIMINARY
1/4 VGA CIS CAMERA MODULE
PRELIMINARY
©2003 Samsung Electronics
All right reserved. No part of this publication may be reproduced, stored in a retrieval
system, or transmitted in any form or by any means, electric or mechanical, by
photocopying, recording, or otherwise, without the prior written consent of Samsung
Electronics.
Samsung Electronics Co., Ltd.
San #24 Nongseo-Ri, Giheung-Eup
Yongin-City, Gyeonggi-Do, Korea
C.P.O. Box #37, Suwon 449-900
Homepage: http://www.samsungsemi.com/
18
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