S5N8947 [SAMSUNG]
MCU for ADSL/Cable Modem; MCU的ADSL / Cable Modem的
| 型号： | S5N8947 |
| 厂家： | 
SAMSUNG |
| 描述： | MCU for ADSL/Cable Modem |
| 文件： | 总49页 (文件大小：399K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S5N8947X
MCU for ADSL/Cable Modem
(Revision 0.1)
May. 23, 2000
SAMSUNG ELECTRONICS PROPRIETARY
Copyright ©1999-2000 Samsung Electronics, Inc. All Rights Reserved
ELECTRONICS
S5N8947 (ADSL/Cable Modem MCU)
CONTENTS
1. GENERAL DESCRIPTION ................................................................................................................................4
2. FEATURES ..........................................................................................................................................................5
3. FUNCTIONAL BLOCK DESCRIPTIONS.........................................................................................................6
3.1.
3.2.
3.3.
3.4.
3.5.
3.6.
3.7.
3.8.
BLOCK DIAGRAM .........................................................................................................................................6
ARCHITECTURE............................................................................................................................................7
SYSTEM MANAGER ......................................................................................................................................7
UNIFIED INSTRUCTION/DATA CACHE ............................................................................................................7
SAR/UTOPIA INTERFACE..............................................................................................................................7
ETHERNET MAC..........................................................................................................................................7
USB CONTROLLER ......................................................................................................................................8
DMA CONTROLLER.....................................................................................................................................8
UART (SERIAL I/O).....................................................................................................................................8
TIMERS....................................................................................................................................................8
PROGRAMMABLE I/O................................................................................................................................8
INTERRUPT CONTROLLER .........................................................................................................................8
I2C SERIAL INTERFACE.............................................................................................................................9
PLL (FOR SYSTEM/USB)..........................................................................................................................9
3.9.
3.10.
3.11.
3.12.
3.13.
3.14.
4. PIN DESCRIPTIONS.........................................................................................................................................10
4.1.
4.2.
4.3.
PIN CONFIGURATION..................................................................................................................................10
PIN DESCRIPTIONS .....................................................................................................................................11
PIN DESCRIPTIONS WITH THE PIN NUMBER AND PAD TYPE ............................................................................13
5. OPERATION DESCRIPTION ..........................................................................................................................16
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
CPU CORE OVERVIEW ...............................................................................................................................16
INSTRUCTION SET ......................................................................................................................................17
OPERATING STATES.............................................................................................................................17
OPERATING MODES .............................................................................................................................18
REGISTERS.............................................................................................................................................18
EXCEPTIONS..........................................................................................................................................18
6. HARDWARE STRUCTURE.............................................................................................................................20
6.1.
6.1.3.
6.1.4.
6.1.5.
6.2.
6.3.
6.4.
6.4.1.
6.4.2.
6.5.
6.5.1.
6.5.2.
6.6.
6.6.1.
6.7.
SYSTEM MANAGER ....................................................................................................................................20
Overview.........................................................................................................................................20
System Manager Registers...............................................................................................................20
System Memory Map .......................................................................................................................21
INSTRUCTION / DATA CACHE......................................................................................................................23
I2C BUS CONTROLLER................................................................................................................................24
ETHERNET CONTROLLER............................................................................................................................25
Block Diagram................................................................................................................................25
Features and Benefits......................................................................................................................25
SAR AND UTOPIA INTERFACE.....................................................................................................................27
Block Diagram................................................................................................................................27
Features and Benefits......................................................................................................................27
USB CONTROLLER ....................................................................................................................................28
Block Diagram................................................................................................................................28
DMA CONTROLLER...................................................................................................................................29
UART(SERIAL I/O)....................................................................................................................................30
TIMERS......................................................................................................................................................31
6.8.
6.9.
MagIC Team
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SAMSUNG ELECTRONICS
ELECTRONICS
S5N8947 (ADSL/Cable Modem MCU)
6.10.
6.11.
I/O PORTS..............................................................................................................................................32
INTERRUPT CONTROLLER........................................................................................................................33
7. SPECIAL FUNCTION REGISTERS ................................................................................................................34
8. ELECTRIC CHARACTERISTICS...................................................................................................................37
8.1.
8.2.
8.3.
8.4.
ABSOLUTE MAXIMUM RATINGS........................................................................................................37
RECOMMENDED OPERATING CONDITIONS ...................................................................................................37
DC ELECTRICAL CHARACTERISTICS ................................................................................................38
A.C ELECTRICAL CHARACTERISTICS...........................................................................................................39
9. PACKAGE DIMENSION ..................................................................................................................................48
SAMSUNG ELECTRONICS
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MagIC Team
ELECTRONICS
S5N8947 (ADSL/Cable Modem MCU)
1. GENERAL DESCRIPTION
Samsung's S5N8947 16/32-bit RISC microcontroller is a cost-effective, high-performance
microcontroller solution. The S5N8947 is designed as an integrated Ethernet controller for use in managed
communication hubs and routers. The S5N8947 also provides ATM Layer SAR (Segmentation and
Reassembly) function with UTOPIA interface and the full-rate USB (Universal Serial Bus) function.
The S5N8947 is built around an outstanding CPU core: the 16/32-bit ARM7TDMI RISC processor
designed by Advanced RISC Machines, Ltd. The ARM7TDMI core is a low-power, general purpose,
microprocessor macro-cell that was developed for use in application-specific and custom-specific
integrated circuits. Its simple, elegant, and fully static design is particularly suitable for cost-sensitive and
power-sensitive applications.
Important peripheral functions including an UART channel, 2-channel GDMA, two 32-bit timers, I2C bus
controller, and programmable I/O ports are supported. Built-in logic including an interrupt controller,
DRAM controller, and a controller for ROM/SRAM and flash memory are also supported. The
S5N8947’ s System Manager includes an internal 32-bit system bus arbiter and an external memory
controller.
To reduce total system cost, the S5N8947 offers a unified cache, Ethernet controller, SAR and USB. Most
of the on-chip function blocks have been designed using an HDL synthesizer and the S5N8947 has been
fully verified in Samsung's state-of-the-art ASIC test environment.
MagIC Team
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SAMSUNG ELECTRONICS
ELECTRONICS
S5N8947 (ADSL/Cable Modem MCU)
2. FEATURES
ü 4-Kbyte unified cache
ü SAR (Segmentation and Reassembly)
ü UTOPIA (the Universal Test & Operations PHY Interface for ATM) Level 2 Interface
ü Ethernet MAC
ü Full-rate USB controller
ü 2-CH GDMA (General Purpose Direct Memory Access)
ü UART (Universal Asynchronous Receiver and Transmtter)
ü 2 programmable 32bits Timers
ü 18 Programmable I/O ports
ü Interrupt controller
ü I2C controller
ü Built-in PLLs for System/USB
ü Cost effective JTAG-based debug solution
ü Boundary scan
ü Operating Voltage Range(2.5V +/- 0.2V)
ü Operating Frequency Up to 50MHz
ü
208 TQFP Package
SAMSUNG ELECTRONICS
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MagIC Team
ELECTRONICS
S5N8947 (ADSL/Cable Modem MCU)
3. FUNCTIONAL BLOCK DESCRIPTIONS
3.1. Block Diagram
4- Bank
ROM
SRAM
FLASH
ARM7TDMI
32bit RISC CPU
ICE
Breaker
32- bit
System
Bus
4- Bank
DRAM
Memory
Controller
with
Refresh
Control
CPU Interface
4- Bank
External
I/O
Unified
CACHE
Device
External
Bus
Master
4-word
Write
Buffer
System Bus
Arbiter
Connection
Memory
Bus Router
General I/O Ports
Interrupt Controller
UART
SAR/UTOPIA
Ethernet MAC
USB Interface
32bit Timer 0, 1
GDMA 0, 1
X'tal Osc
PLL* (USB)
PLL* (System)
IIC Controller
TAP Controller for JTAG
Figure 1 Top Block Diagram
MagIC Team
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ELECTRONICS
S5N8947 (ADSL/Cable Modem MCU)
3.2. Architecture
Integrated system for embedded Ethernet / USB / SAR
Fully 16/32-bit RISC architecture
Efficient and powerful ARM7TDMI core
Little/Big-Endian mode is supported basically, but the internal architecture is big-endian.
Cost-effective JTAG-based debug solution
Supports Boundary Scan
3.3. System Manager
8/16/32-bit external bus support for ROM/SRAM, flash memory, DRAM and external I/O
One external bus master with bus request/acknowledge pins
Supports for EDO/normal or SDRAM
Programmable access cycle
Four-word depth write buffer
Cost-effective memory-to-peripheral DMA interface
3.4. Unified Instruction/Data Cache
Two-way set-associative unified cache (4Kbytes)
Supports for LRU (least recently used) Protocol
Cache is configurable as internal SRAM
3.5. SAR/Utopia Interface
Directly supports ATM Adaptation Layer Five (AAL5) Segmentation And Reassembly
Segments and reassembles data up to 70Mbps
A glueless UTOPIA level 2 interface is supprted (for receiving and transmitting ATM cells with SAR, it
is a standard ATM interface between ATM link and physical layer).
3.6. Ethernet MAC
2 DMA engines with burst mode
Full compliance with IEEE standard 802.3
Supports MII interface (7-wire 10-Mbps interface is also supported).
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MagIC Team
ELECTRONICS
S5N8947 (ADSL/Cable Modem MCU)
3.7. USB Controller
Supports 12Mbps full rate function for universal serial bus
3.8. DMA Controller
2-channel general purpose DMA (for memory-to-memory, memory-to-USB, USB-to-memory, UART-
to-memeory, memory-to-UART data transfers without CPU intervention)
Initiated by a software or a external DMA request
Increments or decrements source or destination address in 8-bit, 16-bit or 32-bit data transfers
3.9. UART (Serial I/O)
UART (Serial I/O) block with DMA-based or interrupt-based operation
Supports for 5-bit, 6-bit, 7-bit, or 8-bit serial data transmit and receive
Programmable baud rates
Infra-red (IR) TX/RX support (IrDA)
3.10. Timers
Two programmable 32-bit timers
Interval mode or toggle mode operation
Supports a watchdog timer.
3.11. Programmable I/O
18 programmable I/O ports
Pins individually configurable to input, output, or I/O mode for dedicated signals
3.12. Interrupt Controller
18 interrupt sources, including 4 external interrupt sources
Normal or fast interrupt mode (IRQ, FIQ)
Prioritized interrupt handling
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ELECTRONICS
S5N8947 (ADSL/Cable Modem MCU)
3.13. I2C Serial Interface
Single Master mode operation only
3.14. PLL (for System/USB)
The external clock can be multiplied by on-chip PLLs to provide high frequency System/USB clock
The input frequency is fixed to 12 MHz
The output frequency is 4.167 times the input clock for System.
The output frequency is 4 times the input clock for USB.
SAMSUNG ELECTRONICS
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MagIC Team
ELECTRONICS
S5N8947 (ADSL/Cable Modem MCU)
4. PIN DESCRIPTIONS
4.1. Pin Configuration
VSS 104
VDD 103
157
158 VSS
VDD
XDATA[19] 102
XDATA[18] 101
XDATA[17] 100
XDATA[16] 99
XDATA[15] 98
XDATA[14] 97
XDATA[13] 96
XDATA[12] 95
XDATA[11] 94
XDATA[10] 93
XDATA[9] 92
XDATA[8] 91
XDATA[7] 90
XDATA[6] 89
VSS 88
159
160
UTO_RXADR[0]
UTO_RXADR[1]
161 UTO_RXADR[2]
162
UTO_RXD[0]
163 UTO_RXD[1]
164
165
UTO_RXD[2]
UTO_RXD[3]
166 UTO_RXD[4]
167
UTO_RXD[5]
168 UTO_RXD[6]
169
170
UTO_RXD[7]
UTO_RXSOC
171 UTO_RXENB
172
UTO_RXCLAV
173 UTO_CLK
VDD 87
174
175
176 SCL
177
VDD
VSS
XDATA[5] 86
XDATA[4] 85
XDATA[3] 84
XDATA[2] 83
XDATA[1] 82
XDATA[0] 81
S5N8947
SDA
178 UCLK
179 UARXD
180
UATXD
181 nUADTR
182
208- TQFP- 2828
(Top View)
ADDR[21]
ADDR[20]
ADDR[19]
ADDR[18]
ADDR[17]
ADDR[16]
ADDR[15]
ADDR[14]
ADDR[13]
80
79
78
77
76
75
74
73
72
nUADSR
183 MDC
184 MDIO
185
186 RXD[0]
187
188
COL
RXD[1]
RXD[2]
189 RXD[3]
190
VSS 71
VDD 70
RX_DV
191 VDD
ADDR[12]
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
192
193
194 RX_ERR
195
196 TXD[0]
197
198
VSS
RX_CLK
ADDR[11]
ADDR[10]
ADDR[9]
ADDR[8]
ADDR[7]
ADDR[6]
ADDR[5]
ADDR[4]
ADDR[3]
ADDR[2]
ADDR[1]
ADDR[0]
nWBE[3]
nWBE[2]
TX_CLK
TXD[1]
TXD[2]
199 TXD[3]
200
TX_EN
201 TX_ERR
202
203
204 USB_DN
205
206 CLKSEL
207
208
CRS
USB_DP
TMODE
VSS 54
VDD 53
VDD
VSS
Figure 2 S5N8947 Pin Configuration
MagIC Team
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ELECTRONICS
S5N8947 (ADSL/Cable Modem MCU)
4.2. Pin Descriptions
Pin
Counts
I/O
Type
I
Group
Pin Name
XCLK_I
Description
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
22
32
4
4
1
4
1
4
2
1
4
1
1
1
1
1
External System Clock Source Input.
MCLKO
CLKSEL
nRESET
O
I
I
I
I
O
I
O
I
I
I
I
O
I
O
I/O
O
O
O
I/O
I
O
I
O
O
I
O
O
I/O
I
System Clock Out.
Clock Frequency Select from the internal PLL.
System Reset, Low Active.
System Clock Out Enable.
Big endian mode select pin.
PLL filter pin for System Clock Generation.
12MHz Reference Clock.
Crystal Clock Output.
Test Mode Enable.
JTAG Test Clock Input.
JTAG Test Mode Select.
JTAG Test Data Input.
JTAG Test Data Output.
JTAG Reset Signal, Low Active.
Address Bus.
External Bidirectional 32bit Data Bus.
Row AddressSstrobe for DRAM, Low Active.
Column Address Strobe for DRAM, Low Active.
Write Enable, Low Active.
External I/O Select, Low Active.
External Data Acknowledge Signal.
ROM/SRAM/Flash Chip Select, Low Active.
Bank 0 Data Bus Size for Boot ROM.
Output Enable, Low Active.
Write Byte Enable, Low Active.
External Master Bus Request.
External Bus Acknowledge.
Management data clock.
System
Configurations CLKOEN
(9)
BIGEND
FILTER_S
OSC_XIN
OSC_XO
TMODE
TCK
TMS
TDI
TDO
TAP
Control
(5)
nTRST
ADDR[21:0]
XDATA[31:0]
nRAS[3:0]
nCAS[3:0]
nDWE
nECS[3:0]
nDTACK
nRCS[3:0]
B0SIZE[1:0]
nOE
Memory
Interface
(81)
nWBE[3:0]
ExtMREQ
ExtMACK
MCD
MDIO
Management data I/O.
Collision detected/Collision detected for 10M.
COL/COL_10M
TX_CLK/
TX_CLK_10M
TXD[3:0]/
TXD_10M/
LOOP_10M
TX_EN/
TXEN_10M
TX_ERR/
PCOMP_10M
CRS/CRS_10M
RX_CLK/
RXCLK_10M
RXD[3:0]/
RXD_10M
RX_DV/
1
4
1
I
Transmit clk/Transmit clk for 10M.
Transmit data/Transmit data for 10M.
Transmit enable/Transmit enable for 10M.
O
O
Ethernet
Controller
(18)
1
1
1
O
I
Transmit error/Packet compression enable for 10M.
Carrier sense/Carrier sense for 10M.
I
Receive clock/Receive clock for 10M.
4
1
I
I
Receive data/Receive data for 10M.
Receive data valid.
LINK_10M
RX_ERR
UCLK
UARXD
UATXD
1
1
1
1
I
I
I
Receive error.
UART
(5)
External Clock Input for UART.
UART Receive Data.
UART Transmit Data.
O
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MagIC Team
ELECTRONICS
S5N8947 (ADSL/Cable Modem MCU)
nUADTR
nUADSR
1
1
I
O
UART Data Terminal Ready, Low Active.
UART Data Set Ready, Low Active.
P[7:0]
8
4
I/O
I/O
General I/O ports for Bi-directional Data Only.
General
Purpose
In/Out
xINTREQ[3:0]
/P[11:8]
External Interrupt Requests/General I/O Ports.
Ports
XDREQ[1:0]/
P[13:12]
nXDACK[1:0]/
P[15:14]
TIMER0/
P[16]
(including
xINTREQ
nXDREQ
nXDACK
TIMER0,1)
(18)
2
2
1
I/O
I/O
I/O
External DMA Requests for GDMA/General I/O Ports.
External DMA Acknowledge from GDMA/General I/O
Ports.
TIMER0 Out/General I/O Port.
TIMER1/
P[17]
1
I/O
TIMER1 Out /General I/O Port.
I2C Serial Clock.
I2C
(2)
SCL
SDA
1
1
3
8
1
1
1
3
8
1
1
1
1
1
1
1
I/O
I/O
O
O
O
O
I
O
I
I
O
I
O
I/O
I/O
O
I2C Seral Data.
UTO_TXADR[2:0]
UTO_TXD[7:0]
UTO_TXSOC
UTO_TXENB
UTO_TXCLAV
UTO_TXADR[2:0]
UTO_RXD[7:0]
UTO_RXSOC
UTO_RXENB
UTO_RXCLAV
UTO_CLK
Transmit Address Bus.
Transmit Data Bus to the ATM PHY.
Start Of Cell Indicator for Transmit Data.
Transmit Data Transfer Enable, Low Active.
Cell Buffer Available for Transmit Data.
Receive Address Bus.
Receive Data Bus from the ATM PHY.
Start Of Cell Indicator for Receive Data.
Receive Data Transfer Enable, Low Active.
Cell Buffer Available for Receive Data.
Transfer/Receive interface byte clock.
USB data D+
Utopia
(Level 2)
(30)
USB_DP
USB_DN
FILTER_U
USB
(3)
USB data D-
USB PLL filter pin.
Table 1 Signal Pin Descriptions for Each Group
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S5N8947 (ADSL/Cable Modem MCU)
4.3. Pin Descriptions with the Pin number and Pad type
Pin
No
1
I/O
Type
Pin Name
Pad type
Descriptions
VDD
VSS
2
3
4
5
6
OSC_XIN
OSC_XO
XCLK_I
VSS
I
O
I
12MHz reference clock
USB crystal clock out
S5N8947 System Source Clock
Psoscm2
ptic
7
8
9
10
11
12
13
14
FILTER_S
VDDA_S
VSSA/VBBA_S
FILTER_U
VDDA_U
VSSA/VBBA_U
nTRST
O
PWR
GND
O
PWR
GND
I
I
Poa_bb
vdda
vbba
poa_bb
vdda
vssa
pticu
pticu
ptot2
pticu
ptic
System PLL filter pin
Analog power for PLL
Analog / bulk ground for PLL
USB PLL filter pin
Analog power for PLL
Analog / bulk ground for PLL
JTAG Not Reset
TDI
TDO
TMS
TCK
JTAG Test Data In
15
16
17
O
I
I
JTAG Test Data Out
JTAG Test Mode Select
JTAG Test Clock
18
19
20
21
22
23-24
25
26
27
CLKOEN
MCLKO
VDD
I
O
PWR
GND
I
I
I
O
I
I
O
B
O
O
O
O
O
ptic
pob8
Clock Out Enable/Disable
System Clock Out
VSS
nRESET
B0SIZE[0:1]
ExtMREQ
ExtMACK
BIGEND
nDACK
nOE
nECS[0:3]
nRCS[0:3]
nRAS[0:3]
nCAS[0:3]
nDWE
ptis
ptic
ptic
Not Reset
Bank 0 Data Bus Access Size
External Master bus request
External bus Acknowledge
Big endian mode select pin
Not external acknowledge signal
Not output enable
pob1
pticd
ptic
ptot4
pbct4
ptot4
ptot4
ptot4
ptot4
ptot4
28
29
30-33
34-39
40-43
44-47
48
49-50
51
52
53
54
55-56
57-69
70
Not external I/O select
Not ROM/SRAM/Flash Chip select
Not Row address strobe for DRAM
Not Column address strobe for DRAM
Not Write Enable
NWBE[0:1]
VDD
Not Write Byte Enable
PWR
GND
PWR
GND
O
VSS
VDD
VSS
NWBE[2:3]
ADDR[0:12]
VDD
ptot4
ptot6
Not Write Byte Enable
Address bus
O
PWR
GND
O
B
PWR
GND
71
VSS
72-80
81-86
87
ADDR[13:21]
XDATA[0:5]
VDD
ptot6
ptbsut6
Address bus
External bidirectional data bus
88
VSS
89-
102
103
104
XDATA[6:19]
B
ptbsut6
External bidirectional data bus
VDD
VSS
PWR
GND
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S5N8947 (ADSL/Cable Modem MCU)
107-
XDATA[20:31]
P[0:2]
B
B
ptbsut6
External bidirectional data bus
General I/O ports
118
119-
121
122
123
124-
138
139
140
141-
143
144-
151
152
153
154
155
156
157
158
159-
161
162-
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186-
189
190
191
192
ptbst4sm
VDD_P
VSS_P
PWR
GND
P[3:17]
B
ptbst4sm
General I/O ports
VDD_P
VDD_S
PWR
GND
UTO_TXADR[0:2]
UTO_TXD[0:7]
O
O
Address bus for TX
Data bus for TX
pob4
UTO_TXSOC
UTO_TXENB
UTO_TXCLAV
VDD_P
O
O
I
PWR
GND
PWR
GND
pob4
pob4
ptis
vdd3op
vssop
vdd3op
vssop
Start Of Cell for TX
Enable data transfers (active low)
Cell Buffer Available
I/O pad power
I/O pad ground
I/O pad power
VSS_P
VDD_P
VSS_P
I/O pad ground
UTOP_RXADR[0:2]
UTO_RXD[0:7]
O
I
Address bus for RX
Data bus for RX
ptis
UTO_RXSOC
UTO_RXENB
UTO_RXCLAV
UTO_CLK
VDD_I
I
O
I
O
PWR
GND
B
B
I
I
O
I
O
O
O
I
ptic
pob4
ptis
Start Of Cell for RX
Enable data transfers (active low)
Cell Buffer available
pob4
Transfer/Receive interface byte clock
VSS_I
SCL
SDA
UCLK
UARXD
UATXD
nUADTR
nUADSR
MDC
ptbcd4
ptbcd4
ptis
ptic
pob4
ptic
pob4
pob4
ptbbcut4
ptis
I2C serial clock
I2C serial data
UART external clock for UART
UART receive data
UART transmit data
Not UART0 data terminal ready
Not UART0 data set ready
Management data clock
Management data I/O
Collision detected/Collision detected for 10M
Receive data/Receive data for 10M
Receive data valid
MDIO
COL/COL_10M
RXD[0:3]/RXD_10M
I
ptis
ptis
RX_DV/LINK_10M
I
VDD
VSS
PWR
GND
RX_CLK/RXCLK_10
193
194
195
I
I
I
ptis
ptis
ptis
Receive clock/Receive clock for 10M
Receive error
M
RX_ERR
TX_CLK/TX_CLK_10
M
Transmit clock/Transmit clock for 10M
196- TXD[0:3]/TXD_10M/
O
O
O
I
pob4
pob4
pob4
ptis
Transmit data/Transmit data for 10M
199
200
LOOP_10M
TX_EN/TXEN_10M
TX_ERR/PCOMP_10
M
Transmit enable/Transmit enable for 10M
Transmit error/Packet compression enable for 10M
Carrier sense/Carrier sense for 10M
201
202
CRS/CRS_10M
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203
204
205
206
207
208
USB_DP
USB_DN
TMODE
CLKSEL
VDD
B
B
I
USB data D+
USB data D-
Test Mode
Clock Out Enable/Disable
pbusb1
ptic
ptic
I
PWR
GND
VSS
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5. OPERATION DESCRIPTION
5.1. CPU Core Overview
The S5N8947 CPU core is the ARM7TDMI processor, a general purpose, 32-bit microprocessor
developed by Advanced RISC Machines, Ltd. (ARM). The core's architecture is based on Reduced
Instruction Set Computer (RISC) principles. The RISC architecture makes the instruction set and its
related decoding mechanisms simpler and more efficient than those with microprogrammed Complex
Instruction Set Computer (CISC) systems. The resulting benefit is high instruction throughput and
impressive real-time interrupt response. Pipelining is also employed so that all components of the
processing and memory systems can operate continuously. The ARM7TDMI has a 32-bit address bus.
An important feature of the ARM7TDMI processor, and one which differentiates it from the ARM7
processor, is a unique architectural strategy called THUMB. The THUMB strategy is an extension of the
basic ARM architecture and consists of 36 instruction formats. These formats are based on the standard
32-bit ARM instruction set, but have been re-coded using 16-bit wide opcodes.
Address
Register
Address
Incrementer
Instruction
Register Bank
Decoder and
Logic Controll
Multiplier
Barrel
Shifter
32-BIT ALU
Instruction
Pipeline and Read
Data Register
Write Data
Register
Figure 3 ARM7TDMI Core Block Diagram
Because THUMB instructions are one-half the bit width of normal ARM instructions, they produce very high-density
code. When a THUMB instruction is executed, its 16-bit opcode is decoded by the processor into its equivalent instruction in
the standard ARM instruction set. The ARM core then processes the 16-bit instruction as it would a normal 32-bit
instruction. In other words, the THUMB architecture gives 16-bit systems a way to access the 32-bit performance of the ARM
core without incurring the full overhead of 32-bit processing. Because the ARM7TDMI core can execute both standard 32-bit
ARM instructions and 16-bit THUMB instructions, it lets you mix routines of THUMB instructions and ARM code in the
same address space. In this way, you can adjust code size and performance, routine by routine, to find the best programming
solution for a specific application.
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5.2. Instruction Set
The S5N8947 instruction set is divided into two subsets: a standard 32-bit ARM instruction set and
a 16-bit THUMB instruction set.
The 32-bit ARM instruction set is comprised of thirteen basic instruction types which can be divided
into four broad classes:
l Four types of branch instructions which control program execution flow, instruction privilege levels,
and switching between ARM code and THUMB code.
l Three types of data processing instructions which use the on-chip ALU, barrel shifter, and multiplier
to perform high-speed data operations in a bank of 31 registers (all with 32-bit register widths).
l Three types of load and store instructions which control data transfer between memory locations and
the registers. One type is optimized for flexible addressing, another for rapid context switching, and
the third for swapping data.
l Three types of co-processor instructions which are dedicated to controlling external co-processors.
These instructions extend the off-chip functionality of the instruction set in an open and uniform way.
NOTE : All 32-bit ARM instructions can be executed conditionally.
The 16-bit THUMB instruction set contains 36 instruction formats drawn from the standard 32-bit
ARM instruction set. The THUMB instructions can be divided into four functional groups:
l Four branch instructions.
l Twelve data processing instructions, which are a subset of the standard ARM data processing
instructions.
l Eight load and store register instructions.
l Four load and store multiple instructions.
NOTE : Each 16-bit THUMB instruction has a corresponding 32-bit ARM instruction with the identical
processing model.
The 32-bit ARM instruction set and the 16-bit THUMB instruction sets are good targets for
compilers of many different high-level languages. When assembly code is required for critical code
segments, the ARM programming technique is straightforward, unlike that of some RISC processors
which depend on sophisticated compiler technology to manage complicated instruction interdependencies.
Pipelining is employed so that all parts of the processor and memory systems can operate
continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third
instruction is being fetched from memory.
5.3. OPERATING STATES
From a programmer's point of view, the ARM7TDMI core is always in one of two operating states.
These states, which can be switched by software or by exception processing, are:
l ARM state (when executing 32-bit, word-aligned, ARM instructions), and
l
THUMB state (when executing 16-bit, half-word aligned THUMB instructions).
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5.4. OPERATING MODES
The ARM7TDMI core supports seven operating modes:
l User mode: the normal program execution state
l FIQ (Fast Interrupt Request) mode: for supporting a specific data transfer or channel process
l IRQ (Interrupt ReQuest) mode: for general purpose interrupt handling
l Supervisor mode: a protected mode for the operating system
l Abort mode: entered when a data or instruction pre-fetch is aborted
l System mode: a privileged user mode for the operating system
l Undefined mode: entered when an undefined instruction is executed
Operating mode changes can be controlled by software, or they can be caused by external interrupts
or exception processing. Most application programs execute in User mode. Privileged modes (that is, all
modes other than User mode) are entered to service interrupts or exceptions, or to access protected
resources.
5.5. REGISTERS
The S5N8947 CPU core has a total of 37 registers: 31 general-purpose 32-bit registers, and 6 status
registers. Not all of these registers are always available. Which registers are available to the programmer at
any given time depends on the current processor operating state and mode.
NOTE : When the S5N8947 is operating in ARM state, 16 general registers and one or two status
registers can be accessed at any time. In privileged mode, mode-specific banked registers are
switched in.
Two register sets, or banks, can also be accessed, depending on the core's current state: the ARM
state register set and the THUMB state register set:
l The ARM state register set contains 16 directly accessible registers: R0-R15. All of these registers,
except for R15, are for general-purpose use, and can hold either data or address values. An additional
(seventeenth) register, the CPSR (Current Program Status Register), is used to store status
information.
l The THUMB state register set is a subset of the ARM state set. You can access eight general
registers, R0-R7, as well as the program counter (PC), a stack pointer register (SP), a link register
(LR), and the CPSR. Each privileged mode has a corresponding banked stack pointer, link register,
and saved process status register (SPSR).
The THUMB state registers are related to the ARM state registers as follows:
l THUMB state R0-R7 registers and ARM state R0-R7 registers are identical
l THUMB state CPSR and SPSRs and ARM state CPSR and SPSRs are identical
l THUMB state SP, LR, and PC map directly to ARM state registers R13, R14, and R15, respectively
In THUMB state, registers R8-R15 are not part of the standard register set. However, you can access
them for assembly language programming and use them for fast temporary storage, if necessary.
5.6. EXCEPTIONS
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An exception arises whenever the normal flow of program execution is interrupted. For example,
when processing must be diverted to handle an interrupt from a peripheral. The processor's state just prior
to handling the exception must be preserved so that the program flow can be resumed when the exception
routine is completed. Multiple exceptions may arise simultaneously.
To process exceptions, the S5N8947 uses the banked core registers to save the current state. The
old PC value and the CPSR contents are copied into the appropriate R14 (LR) and SPSR register. The PC
and mode bits in the CPSR are forced to a value which corresponds to the type of exception being
processed.
The S5N8947 core supports seven types of exceptions. Each exception has a fixed priority and a
corresponding privileged processor mode, as shown in following Table
Exception
Mode on Entry
Supervisor mode
Abort mode
Priority
Reset
1 (highest)
Data abort
2
FIQ mode
FIQ
3
IRQ mode
IRQ
4
Abort mode
Prefetch abort
Undefined instruction
SWI
5
6
Undefined mode
Supervisor mode
6 (lowest)
Table 2 S5N8947 CPU Exceptions
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6. HARDWARE STRUCTURE
6.1. System Manager
6.1.3. Overview
The S5N8947 microcontroller’ s System Manager has the following functions.
l To arbitrate system bus access requests from several master blocks, based on fixed priorities.
l To provide the required memory control signals for external memory accesses. For example, if a
master block such as the DMA controller or the CPU generates an address which corresponds to a
DRAM bank, the System Manager’ s DRAM controller generates the required normal/EDO or
SDRAM access signals. The interface signals for normal/EDO or SDRAM can be switched by
SYSCFG[31].
l To provide the required signals for bus traffic between the S5N8947 and ROM/SRAM and the
external I/O banks.
l To compensate for differences in bus width for data flowing between the external memory bus and the
internal data bus.
l To support both little and big endian for external memory or I/O devices. Internal registers, however,
operate under big-endian mode.
Note : By generating an external bus request (ExtMREQ), an external device can access the S5N8947’ s
external memory. The S5N8947 can access slow external devices using a nDTACK signal. The DTACK
signal, which is generated by the external device, extends the duration of the CPU’ s memory access cycle
beyond its programmable value.
6.1.4. System Manager Registers
To control external memory operations, the System Manager uses a dedicated set of special registers.
By programming the values in the System Manager special registers, you can specify such things as :
l Memory type
l External bus width access cycle
l Control signal timing (RAS and CAS, for example)
l Memory bank locations
l Size of each memory bank to be used for arbitrary address spacing
The System Manager uses special register setting to control the generation and processing of the
control signals, addresses, and data that are required by external devices in a standard system
configuration. Special registers are also used to control access to ROM/SRAM/Flash banks, up to four
DRAM banks and four external I/O banks, and a special register mapping area.
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The address resolution for each memory bank base pointer is 64 Kbytes (16 bits). The base address
pointer is 10 bits. This gives a total addressable memory bank space of 16 M words.
0x3FFFFFF
Reserved
Special Register bank
Internal SRAM
16 K words (Fixed)
4 K bytes (Fixed)
External I/O bank 3
External I/O bank 2
Continuous 16 K word space
for 4 external I/O banks
External I/O bank 1
4 K words
(Fixed for all I/O banks)
External I/O bank 0
16 M words
(16 M x 32 bits)
SA[ 25:0]
DRAM/SDRAM bank 3
DRAM/SDRAM bank 2
DRAM/SDRAM bank 1
DRAM/SDRAM bank 0
ROM/SRAM/Flash bank 3
ROM/SRAM/Flash bank 2
ROM/SRAM/Flash bank 1
ROM/SRAM/Flash bank 0
16 K words - 4 M words (32 bits)
ADDR[ 21:0]
0x0000000
Figure 4 S5N8947 System Memory Map
6.1.5. System Memory Map
Followings are several important features to note about the S5N8947 system memory map :
l The size and location of each memory bank is determined by the register settings for “current bank
base pointer” and “current bank end pointer”. You can use this base/next bank pointer concept to set
up a consecutive memory map. To do this, you set the base pointer of the “next bank” to the same
address as the next pointer of the “current bank”. Please note that when setting the bank control
registers, the address boundaries of consecutive banks must not overlap. This can be applied even if
one or more banks are disabled.
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l Four external I/O banks are defined in a continuous address space. A programmer can only set the
base pointer for external I/O bank 0. The start address of external I/O bank 1 is then calculated as the
external I/O bank 0 start address +16 K. Similary, the start address for external I/O bank 2 is the
external I/O bank 0 start address + 32 K, and the start address for external I/O bank 3 is the external
I/O bank 0 start address + 48 K. Therefore, the total consecutive addressable space of the four
external banks is defined as the start address of external I/O bank 0 + 64 K bytes.
l Within the addressable space, the start address of each I/O bank is not fixed. You can use bank
control registers to assign a specific bank start address by setting the bank’ s base pointer. The address
resolution is 64 K bytes. The bank’ s start address is defined as “base pointer << 16” and the bank’ s
end address (except for external I/O banks) is “next pointer << 16 – 1”.
After a power-on or system reset, all bank address pointer registers are initialized to their default
values. In this means that a system reset automatically defines ROM bank 0 as a 32-Mbyte space with a
start address of zero. This means that, except for ROM bank 0, all banks are undefined following a system
startup.
The reset value for the next pointer and base pointer of ROM bank 0 are 0x200 and 0x000,
respectively. This means that a system reset automatically defines ROM bank 0 as a 32-Mbyte space with a
start address of zero. This initial definition of ROM bank 0 lets the system power-on or reset operation
pass control to the user-supplied boot code that is stored in external ROM. (This code is located at address
0 in the system memory map.) When the boot code (i.e. ROM program) executes, it performs various
system initialization tasks and reconfigures the system memory map according to the application’ s actual
external memory and device configuration.
The initial system memory map following system startup is shown in following :
0x3FFFFFF
Special Function
Registers
0x3FF0000
Undefined Area
64 M Bytes
SA[ 25:0]
0x2000000
ROM/SRAM/FLASH
Bank 0 Area
(Accessible)
32 M
ROM/SRAM/FLASH
Bank 0 Area
(Accessible)
4 M Address[ 21:0]
0x0000000
Figure 5 Initial system memory map (After reset)
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6.2. Instruction / Data Cache
The S5N8947 CPU has a unified internal 4-Kbyte instruction/data cache. The cache is configured
using two-way, set-associative addressing. The replacement algorithm is pseudo-LRU (Least Recently
Used). The cache line size is four words (16 bytes). When a miss occurs, four word must be fetched
consecutively from external memory. Typically, RISC processors take advantage of unified
instruction/data caches to improve performance.
31 30 29 28 27 26 25
10 9
4 3 2 1 0
Tag Address (15-bit)
Enable non-cacheable control
2-bit
6-bit
15
switch
100: Set 0 direct access
101: Set 1 direct access
110: TAG direct access
2
15
15
Height = 128
CS
Set 1 Tag
Set 0 Tag
7-bit
Decoder
Tag RAM (32-bit)
Set 1 Icache line = 4 instruction/data (128-bit)
Set 0 Icache line = 4 instruction/data (128-bit)
Instr3
Instr2
Instr1
Instr0
Instr3
Instr2
Instr1
Instr0
7-bit
Height =
128
32-bit
32-bit
2
32
32
2
32
(Set 0 Hit)
(Set 1 Hit)
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S5N8947 (ADSL/Cable Modem MCU)
6.3. I2C Bus Controller
The S5N8947’ s Internal IC bus (I2C-bus) controller has the following important features :
l It requires only two bus lines, a serial data line (SDA) and a serial clock line (SCL). When the I2C-bus
is free, both lines are High level.
l Each device that is connected to the bus is software-addressable by a unique address. Slave
relationships on the bus are constant. The bus master can be either a master-transmitter or a master-
receiver. The I2C bus controller supports only single master mode.
l It supports 8-bit, bi-directional, serial data transfers.
l The number of ICs that you can connect to the same I2C-bus is limited only by the maximum bus
capacitance of 400 pF.
Following figure shows a block diagram of the S5N8947’ s I2C-bus controller.
Data
Control
SDA
SCL
Shift buffer register (IICBUF)
System clock (fMCLK)
Serial
Clock
Prescaler
SCL
Control
16
Prescaler register (IICPS)
0
BUSY COND1 COND0
ACK
LRB
IEN
BF
Control status register (IICCON)
Figure 6 I2C-Bus block diagram
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6.4. Ethernet Controller
The S5N8947 has an Ethernet controller which operates at either 100/10-Mbits per second in half-
duplex or full-duplex mode. In half-duplex mode, the controller supports the IEEE 802.3 Carrier Sense
Multiple Access with Collision Detection (CSMA/CD) protocol. In full-duplex mode, it supports the IEEE
802.3 MAC Control Layer, including the Pause operation for flow control.
6.4.1. Block Diagram
BDMA+SBUS I/F
MAC
MAX Tx
Buffer
BDMA Tx
Buffer
Controller
Controller
BDMA Tx
Buffer
(64 words)
MAX Tx
Buffer
(80 bytes)
M
I
I
8
32
32
MAX Rx
Buffer
controller
/
B
D
I
Bus Arbiter/
Controller
S
Y
S
T
E
M
10
M
b
p
s
MAX Rx
Buffer
(16 bytes)
BDMA Rx
Buffer
(64 words)
8
32
32
Address
CAM
Interface
and
comparator
BDMA Rx
Buffer
Controller
7
-
W
i
B
U
S
Flow
Controller
CAM
Contents
Memory
(32-words)
32
32
r
e
CRC
Checker
BDMA
control and
status
MAC control
and status
register
Station
Manager
register
Figure 7 Ethernet controller block diagram
6.4.2. Features and Benefits
The most important features and benefits of the S5N8947 Ethernet controller are follows :
l Cost-effective connection to an external Repeater Interface Controller(RIC)/Ethernet backbone
l Buffered DMA (BDMA) engine using Burst mode
l BDMA Tx/Rx buffers (256 bytes/256 bytes)
l MAC Tx/Rx FIFOs (80 bytes/16 bytes) to support re-transmit after collision without DMA request
and to handle DMA latency
l Data alignment logic
l Supports for old and new media (compatible with existing 10-Mbit/s networks)
l Full IEEE 802.3 compatibility for existing applications
l Provides a standard Media Independent Interface (MII)
l Provides an external 7-wire interface, also.
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l Station Management (STA) signaling for external physical layer configuration and link negotiation
l On-chip CAM (21 addresses)
l Full-duplex mode for doubled bandwidth
l Pause operation hardware support for full-duplex flow control
l Long packet mode for specialized environments
l Short packet mode for fast testing
l PAD generation for ease of processing and reduced processing time
l Support for old and new media : Compatible with existing 100/10Mbit/s networks.
l Full IEEE 802.3 compatibility : Compatible with existing hardware and software.
l Standard CSMA/CD,Full duplex capability at 100/10 Mbit/s : Increase in data throughput
performance.
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6.5. SAR and Utopia Interface
The S5N8947 provides ATM layer Segmentation and Reassembly (SAR) function over a 8bit
UTOPIA interface. The S5N8947 delivers an integrated solution for performing the SAR tasks required to
communicate over an ATM network. The device translates packet-based data into 53-byte ATM cells that
are asynchronously mapped into various physical media. The S5N8947 can be effectively applied for
equipment requiring an interface between packet-based data and ATM-based networks.
6.5.1. Block Diagram
Reassembler
AAL5, 3/ 4, 0
UTOPIA
and
FIFOs
Segmentor
AAL5, 3/4, 0
System
I/F and
FIFOs
Scheduler
(CBR,UBR,rt-VBR,nrt-VBR)
Registers
Connection Memory
(Internal and/or External)
Figure 8 SAR function block diagram
6.5.2. Features and Benefits
l Supports CBR, UBR, rt-VBR and nrt-VBR traffic with rates set on a per-VC or per-VP basis.
l Supports AAL0 (raw cells) and AAL5 segmentation and reassembly.
l Segments and reassembles data up to about 70M bps via UTOPIA interface.
l Generates and verifies CRC-10 for OAM cells and AAL3/4 cells.
l Supports concurrent OAM cells and AAL5 cells on each active connection.
l Supports simultaneous segmentation and reassembly of up to 32 connections with internal memory
and up to 4K connections with external memory.
l On chip 8K bytes SRAM for internal connection memory.
l Supports Contents Addressable Memory (CAM) for channel mapping (up to 32 connections).
l Supports packet sizes up to 64K bytes.
l Supports scatter and gather packet capability for large packets
l Start of Packet offset available for ease of implementing bridging and routing between different
protocols.
l Provides glue-less UTOPIA level 2 interface (up to 7 PHYs).
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S5N8947 (ADSL/Cable Modem MCU)
6.6. USB Controller
The Universal Serial Bus (USB) is an industry standard bus architecture for computer peripheral
attachment. The USB provides a single interface for easy, plug-and-play, hot-plug attachment of
peripherals such as keyboard, mouse, speakers, printers, scanners, and communication devices. The USB
allows simultaneous use of many different peripherals with a combined transfer rate of up to 12 Mbit/s.
The S5N8497 controller includes a highly flexible integrated USB peripheral controller that lets
designers implement a variety of microcontroller-based USB peripheral devices for telephony, audio, or
other high-end applications. The S5N8947 controller is intended for USB peripherals that use the full-
speed signalling rate of 12 Mbit/s. The USB low-speed rate (1.5 Mbit/s) is not supported. An integrated
USB transceiver is provided to minimize system device count and cost, but an external transceiver can be
used instead, if required. The USB peripheral controller’ s features meet or exceed all of the USB device
class resource requirements defined by the USB specification Version 1.0 and 1.1. Consult the USB
specification for details about overall USB system design. The integrated USB peripheral controller
provides a very efficient and easy-to-use interface, so that device software (or firmware) does not incur the
overhead of managing low-level USB protocol requirements.
The USB peripheral controller hardware implements a number of USB standard commands directly;
the rest can be implemented in device software. In addition, the USB peripheral controller provides a high
degree of flexibility to help designers accommodate vendor- or device-class-specific commands, as well as
any new features that might be added in future USB specifications.
Specialized hardware is provided to support Bulk data transfers. Using the Microcontroller’ s DMA
features, large size of bulk transfers from an off-chip peripheral, can be automatically synchronized to the
USB data rate with little or no CPU overhead.
Robust error detection and management features are provided so the device software can manage
transfers in any number of ways as required by the application. The USB suspend/ resume, reset, and
remote wake up features are also supported.
6.6.1. Block Diagram
Serial Interface Unit
(SIE)
Endpoint 0 FIFO
Endpoint 1
16 out FIFO
Serial
Interface
Engine
Endpoint 2
16 in FIFO
(SIE)
X 2
X 2
Endpoint 3
64 out FIFO
Endpoint 4
64 in FIFO
Figure 9 USB Module Block Diagram
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6.7. DMA Controller
The S5N8947 has a two-channel general DMA controller, called the GDMA. The two-channel
GDMA performs the following data transfers without CPU intervention:
l Memory-to-memory (memory to/from memory)
l UART-to-memory (serial port to/from memory)
l USB-to-memory (USB port to/from memory)
The on-chip GDMA can be started by software and/or by an external DMA request (nXDREQ).
Software can also be used to restart a GDMA operation after it has been stopped.
The CPU can recognize when a GDMA operation has been completed by software polling and/or
when it receives an appropriate internally generated GDMA interrupt. The S5N8947 GDMA controller
can increment or decrement source or destination addresses and conduct 8-bit (byte), 16-bit (half-word),
or 32-bit (word) data transfers.
System BUS
Mode Selection
GDMA Channel 0
nXDREQ 0
UART
USB
(to Memory)
nDREQ
nDACK
nXDACK 0
GDMA0
Port 14 Data
IOPCON [27:26]
GDMA Channel 1
USB
(from Memory)
nXDREQ 1
nDREQ
nDACK
nXDACK 1
GDMA1
Mode Selection
IOPCON [29:28]
Port 15 Data
Figure 10 GDMA controller block diagram
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6.8. UART(Serial I/O)
The S5N8947 UART (Universal Asynchronous Receiver/Transmitter) unit provides an asynchronous
serial I/O (SIO) port. This can operate in interrupt-based or DMA-based mode. That is, the UART can
generate internal interrupts or DMA requests to transfer data between the CPU and the serial I/O port.
The most important features of the S5N8947 UART include:
l Programmable baud rates
l Infra-red (IR) transmit/receive
l Insertion of one or two Stop bits per frame
l Selectable 5-bit, 6-bit, 7-bit, or 8-bit data transfers
l Parity checking
This unit has a baud rate generator, transmitter, receiver, and a control unit, as shown in next figure.
The baud-rate generator can be driven by the internal system clock, MCLK. The transmitter and receiver
block use this baud rate clock and have independent data buffer registers and data shifters.
Transmit data is written first to the transmit buffer register. From there, it is copied to the transmit
shifter and then shifted out by the transmit data pin, UATXDn. Receive data is shifted in by the receive
data pin, UARXDn. It is then copied from the shifter to the receive buffer register when one data byte has
been received.
This unit provides software controls for mode selection, and for status and interrupt generation.
Transmit Buffer Register
(UTXBUFn)
Baud Rate Divisor
(UTBUFn)
Baud Rate Generator
UATxDn
Transmit Shift Register
0
1
IR Rx
Decoder
Line Control Register
(ULCONn)
UART Control Register
(UCONn)
UART Status Register
(USTATn)
nUADTRn
nUADSRn
Receive Buffer Register
(URXBUFn)
UARxDn
0
1
Receive Shift Register
IR Rx
Decoder
Figure 11 UART block diagram
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S5N8947 (ADSL/Cable Modem MCU)
6.9. Timers
The S5N8947 has two 32-bit timers. These timers can operate in interval mode or in toggle mode.
The output signals are TOUT0 and TOUT1, respectively.
You enable or disable the timers by setting control bits in the timer mode register, TMOD. An
interrupt request is generated whenever a timer count-out (down count) occurs.
Watchdog timer is also implemented in the S5N8947. The following guidelines apply to watchdog
timer functions:
— When a watchdog timer is enabled, it loads a data value to its count register and begins decrementing
the count register value by the system clock.
— If the reset from the watchdog timer (WDRESET) reaches to zero, the Watchdog will start its reset
sequence. The reset value is then reloaded and the watchdog timer is disabled.
— The WDRESET performs the same function as the External Reset (System Reset) to each block.
32-Bit Timer Data
Register (TDATAn)
Auto
Re-load
INTPND and
INTMSK
32-Bit Timer Count
Register (TCNTn)
[Down Counter]
fMCLK
Interrupt
Request
PND
TMOD.TEn
Pulse
Generator
TMOD.TMDn
TMOD.TCLRn
TOUTn
Port 16, Port 17
Data Out
IOPCON.TOENn
Figure 12 32-bit timer block diagram
SAMSUNG ELECTRONICS
Page : 31
MagIC Team
ELECTRONICS
S5N8947 (ADSL/Cable Modem MCU)
6.10. I/O Ports
The S5N8947 has 18 programmable I/O ports. You can configure each I/O port to input mode,
output mode, or special function mode. To do this, you write the appropriate settings to the IOPMOD and
IOPCON registers. User can set filtering for the input ports using IOPCON register.
The modes of the ports from port0 to port7 are determined only by the IOPMOD register. But
port[11:8] can be used as xINTREQ[3:0], port[13:12] as nXDREQ[1:0], port[15:14] as nXDACK[1:0],
port[16] as TOUT0, or port[17] as TOUT1 depending on the settings in IOPCON register.
VDD
IOPMOD
IOPCON
Alternate Functions
Port0 - Port7
Port8/xINTREQ0
Output
Latch
IOPDATA
(Write)
Port11/xINTREQ3
Port12/nXDREQ0
Port13/nXDREQ1
Port14/nXDACK0
Port15/nXDACK1
Port16/TOUT0
IOPDATA
(Read)
Port17/TOUT1
Active
Input
Latch
On/Off &
Edge
Filter
On/Off
Detection
Interrupt or DMA
Request
IOPCON
IOPCON
Figure 13 I/O port function diagram
MagIC Team
Page : 32
SAMSUNG ELECTRONICS
ELECTRONICS
S5N8947 (ADSL/Cable Modem MCU)
6.11. Interrupt Controller
The S5N8947 interrupt controller has a total of 18 interrupt sources. Interrupt requests can be generated
by internal function blocks and external pins.
The ARM7TDMI core recongnizes two kinds of interrupts: a normal interrupt request (IRQ), and a fast
interrupt request (FIQ). Therefore all S5N8947 interrupts can be categorized as either IRQ or FIQ. The
S5N8947 interrupt controller has an interrupt pending bit for each interrupt source.
Four special registers are used to control interrupt generation and handling:
l Interrupt priority registers. The index number of each interrupt source is written to the pre-defined
interrupt priority register field to obtain that priority. The interrupt priorities are pre-defined from 0 to
17.
l Interrupt mode register. Defines the interrupt mode, IRQ or FIQ, for each interrupt source.
l Interrupt pending register. Indicates that an interrupt request is pending. If the pending bit is set, the
interrupt pending status is maintained until the CPU clears it by writing a "1" to the appropriate
pending register. When the pending bit is set, the interrupt service routine starts whenever the
interrupt mask register is "0". The service routine must clear the pending condition by writing a "1" to
the appropriate pending bit. This avoids the possibility of continuous interrupt requests from the same
interrupt pending bit.
l Interrupt mask register. Indicates that the current interrupt has been disabled if the corresponding
mask bit is "1". If an interrupt mask bit is "0" the interrupt will be serviced normally. If the global
mask bit (bit 18) is set to "1", no interrupts are serviced. However, the source's pending bit is set if the
interrupt is generated. When the global mask bit has been set to "0", the interrupt is serviced.
Index Values
[17]
[16]
[15]
[14]
[13]
[12]
[11]
[10]
[9]
Interrupt Sources
I2C-bus interrupt
Ethernet controller MAC Rx interrupt
Ethernet controller MAC Tx interrupt
Ethernet controller BDMA Rx interrupt
Ethernet controller BDMA Tx interrupt
SAR Tx/Rx done interrupt
SAR Tx/Rx error interrupt
USB interrupt
GDMA channel 1 interrupt
GDMA channel 0 interrupt
Timer 1 interrupt
[8]
[7]
[6]
Timer 0 interrupt
[5]
[4]
[3]
UART receive and error interrupt
UART transmit interrupt
External interrupt 3
[2]
External interrupt 2
[1]
External interrupt 1
[0]
External interrupt 0
Table 3 S5N8947 Interrupt Sources
SAMSUNG ELECTRONICS
Page : 33
MagIC Team
ELECTRONICS
S5N8947 (ADSL/Cable Modem MCU)
7. SPECIAL FUNCTION REGISTERS
Group
System
Manager
Registers
SYSCFG
SYSCON
Offset
0x0000
R/W
R/W
Description
System configuration register
System control register
External I/O timing register 1
External I/O timing register 2
Data bus width for each memory bank
ROM/SRAM/Flash bank 0 control register
ROM/SRAM/Flash bank 1 control register
ROM/SRAM/Flash bank 2 control register
ROM/SRAM/Flash bank 3 control register
DRAM bank 0 control register
DRAM bank 1 control register
DRAM bank 2 control register
DRAM bank 3 control register
Refresh and external I/O control register
Buffered DMA receive control register
Buffered DMA transmit control register
Transmit trame descriptor start address
Receive frame descriptor start address
Receive frame maximum size
Reset/Value
0x23FF0000
0x00000000
0x00000000
0x00000000
0x00000000
0x20000060
0x00000060
0x00000060
0x00000060
0x00000000
0x00000000
0x00000000
0x00000000
0x83FD0000
0x00000000
0x00000000
0x00000000
0x00000000
Undefined
0x3000
0x3008
0x300C
0x3010
0x3014
0x3018
0x301C
0x3020
0x3024
0x3028
0x302C
0x3030
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EXTACON0
EXTACON1
EXTDBWTH
ROMCON0
ROMCON1
ROMCON2
ROMCON3
DRAMCON0
DRAMCON1
DRAMCON2
DRAMCON3
REFEXTCON 0x3034
BDMATXCON 0x9000
BDMARXCON 0x9004
BDMATXPTR 0x9008
BDMARXPTR 0x900C
BDMARXLSZ 0x9010
Ethernet
(BDMA)
BDMASTAT
CAM
0x9014
0x9100-
0x917C
Buffered DMA status
CAM content (32 words)
0x00000000
Undefined
BDMATXBUF 0x9200-
0x92FC
BDMARXBUF 0x9800-
0x99FC
R/W
R/W
BDMA Tx buffer (64 words) for test mode Undefined
addressing
BDMA Rx buffer (64 words) for test mode Undefined
addressing
Ethernet
(MAC)
MACON
CAMCON
0xA000
0xA004
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Ethernet MAC control register
CAM control register
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00006000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x0000001F
0x00000004
0x00000000
MACTXCON 0xA008
MACTXSTAT 0xA00C
MACRXCON 0xA010
MACRXSTAT 0xA014
STADATA
STACON
CAMEN
EMISSCNT
EPZCNT
ERMPZCNT
ETXSTAT
FA
PM
EI
UI
EIE
UIE
LBFN
MAC transmit control register
MAC transmit status register
MAC receive control register
MAC receive status register
Station management data
Station management control and address
CAM enable register
0xA018
0xA01C
0xA028
0xA03C
0xA040
0xA044
0x9040
0x7000
0x7004
0x7008
0x700C
0x7010
0x7014
0x7018
Missed error count register
Pause count register
R
R
Remote pause count register
Transmit control frame status
Function address register
Power management register
Endpoint interrupt register
USB interrupt register
Endpoint interrupt enable register
USB interrupt enable register
Frame number1 register
USB
R/W
R/W
R/W
R/W
R/W
R/W
R
MagIC Team
Page : 34
SAMSUNG ELECTRONICS
ELECTRONICS
S5N8947 (ADSL/Cable Modem MCU)
HBFN
I E0M
*E0C
*E0BC
*O1M
*O1C1
*O1C2
*E1BC
*I 2M
*I 2C1
*I 2C2
*O3M
*O3C1
*O3C2
*E3BC
*I4M
*I4C1
*I4C2
*PDC
*EP0D
*EP1D
*EP2D
*EP3D
*EP4D
SW_RESET
0x701C
0x7020
0x7024
0x7028
0x7030
0x7034
0x7038
0x703C
0x7040
0x7044
0x7048
0x7050
0x7054
0x7058
0x705C
0x7060
0x7064
0x706C
0x7070
0x7100
0x7104
0x7108
0x710C
0x7110
R
Frame number2 register
Input EP0 MAXP register
EP0 Control register
0x00000000
0x00000000
0x00000000
0x00000000
0x00000001
0x00000000
0x00000000
0x00000000
0x00000001
0x00000000
0x00000000
0x00000004
0x00000000
0x00000000
0x00000000
0x00000004
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EP0 Write Byte Counter
EP1 OUT MAXP register
EP1 OUT Control register 1
EP1 OUT Control register 2
EP1 Write Byte Counter
EP2 IN MAXP register
EP2 IN Control register 1
EP2 IN Control register 2
EP3 OUT MAXP register
EP3 OUT Control register 1
EP3 OUT Control register 2
EP3 Write Byte Counter
EP4 IN MAXP register
EP4 IN Control register 1
EP4 IN Control register 2
Power-down Counter Register
EP0 FIFO data register
EP1 FIFO data register
EP2 FIFO data register
EP3 FIFO data register
EP4 FIFO data register
Software reset register
Global mode register
Base multiple for receive packet timeout register 0x00FF7FFF
Transmit ready first packet or subpacket address 0x00000000
Transmit ready last packet or subpacket address
Transmit packet done queue base address register 0x00000000
Transmit packet done queue size register
Receive queue 0 base address register
Receive queue 0 size register
Receive queue 1 base address register
Receive queue 1 size register
Receive queue 2 base address register
Receive queue 2 size register
Receive queue 3 base address register
Receive queue 3 size register
SAR
0x00
0x08
0x0C
0x10
0x14
GLOBAL_MODE
TIMEOUT_BASE
TX_READY1
TX_READY2
0x00000000
TX_DONE_ADDR 0x18
TX_DONE_SIZE 0x1C
RX_POOL0_ADDR 0x20
RX_POOL0_SIZE 0x24
RX_POOL1_ADDR 0x28
RX_POOL1_SIZE 0x2C
RX_POOL2_ADDR 0x30
RX_POOL2_SIZE 0x34
RX_POOL3_ADDR 0x38
RX_POOL3_SIZE 0x3C
0x00C00000
0x00000000
0x00C00000
0x00000000
0x00C00000
0x00000000
0x00C00000
0x00000000
0x00C00000
RX_DONE0_ADDR 0x40
RX_DONE0_SIZE 0x44
RX_DONE1_ADDR 0x48
RX_DONE1_SIZE 0x4C
Receive packet done queue 0 base address register 0x00000000
Receive packet done queue 0 size register 0x00C00000
Receive packet done queue 1 base address register 0x00000000
Receive packet done queue 1 size register
UTOPIA interface configuration register
0x00C00000
0x00000000
0x50
UTOPIA_CONFIG
UTOPIA_TIMEOUT 0x54 R/W
UTOPIA interface timeout register
0xFFFFFFFF
0x0000008E
0xFFFFFFFF
0xFFFFFFFF
0x00000000
0x00000000
0x00000000
0x00000200
CLOCK_RATIO
DONE_INT_MASK 0x70
ERR_INT_MASK 0x74
DONE_INT_STAT 0x78
ERR_INT_STAT 0x7C
0x64
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Ratio of SAR clock freq toUNI interface speed
Interrupt mask for done interrupt register
Interrupt mask for error interrupt register
Interrupt status for done interrupt register
Interrupt status for error interrupt register
Base address of 1/Rate lookup table
Base address of VP lookup table
Base address and entry number of UBR schedule 0x00000300
Base address and entry number of CBR schedule 0x00000380
1/R_LOOKUP_TBL 0x80
VP_LOOKUP_TBL 0x84
UBR_SCH_TBL
CBR_SCH_TBL
0x88
0x8C
SAMSUNG ELECTRONICS
Page : 35
MagIC Team
ELECTRONICS
S5N8947 (ADSL/Cable Modem MCU)
CELL_BUFF
SCH_CONN_TBL
0x90
0x94
R/W
R/W
Base address and entry number of cell buffer
Base address and entry number of scheduler 0x00000500
connection table
0x00000400
AAL_CONN_TBL 0x98
SAR_CONN_TBL 0x9C
R/W
R/W
Base address and entry number of AAL 0x00000600
connection table
Base address and entry number of SAR 0x00000700
connection table
CAM_VPVC/CN 0x100-1FC R/W CAM VPCI, VCI and connection number register 0x00000000
CONFIGURATION 0x200 R/W
Clock control and connection memory 0x00000044
configuration register
EXT_CMBASE
IOPMOD
IOPCON
IOPDATA
INTMOD
INTPND
INTMSK
INTPRI0
INTPRI1
INTPRI2
0x204 R/W
External connection memory base address register 0x00000000
I/O Ports
0x5000
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
I/O port mode register
I/O port control register
Input port data register
0x00000000
0x00000000
Undefined
0x5004
0x5008
0x4000
0x4004
0x4008
0x400C
0x4010
0x4014
0x4018
0x401C
0x4020
0x4024
0x4028
0x402C
Interrupt
Controller
Interrupt mode register
Interrupt pending register
Interrupt mask register
0x00000000
0x00000000
0x003FFFFF
0x03020100
0x07060504
0x0B0A0908
0x0F0E0D0C
0x00001110
0x00000000
0x00000054
0x00000000
0x00000000
0x00000054
0x00000054
0x00000000
Undefined
0x00000000
0x00000000
0x00000000
0x00000000
Undefined
Undefined
Undefined
Undefined
Undefined
Interrupt priority register 0
Interrupt priority register 1
Interrupt priority register 2
Interrupt priority register 3
Interrupt priority register 4
Interrupt priority register 5
Interrupt offset address register
Interrupt pending priority register
Interrupt pending test register
FIQ interrupt offset register
IRQ interrupt offset register
I2C bus control status register
I2C bus shift buffer register
I2C bus prescaler register
INTPRI3
INTPRI4
INTPRI5
INTOFFSET
INTPNDPRI
INTPNDTST
INTOSET_FIQ 0x4030
INTOSET_IRQ 0x4034
IICCON
IICBUF
IICPS
IICCOUNT
GDMACON0 0xB000
GDMACON1 0xC000
GDMASRC0
GDMADST0
GDMASRC1
GDMADST1
GDMACNT0 0xB00C
GDMACNT1 0xC00C
R
W
R
R
I 2C Bus
GDMA
0XF000
0xF004
0xF008
0xF00C
R/W
R/W
R/W
R
I2C bus prescaler counter register
GDMA channel 0 control register
GDMA channel 1 control register
GDMA source address register 0
GDMA destination address register 0
GDMA source address register 1
GDMA destination address register 1
GDMA channel 0 transfer count register
GDMA channel 1 transfer count register
UART line control register
UART control register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
0xB004
0xB008
0xC004
0xC008
Undefined
UART
Timers
ULCON
UCON
0xD000
0xD004
0xD008
0xD00C
0xD010
0xD014
0x6000
0x6004
0x6008
0x600C
0x6010
0x6014
0x6018
0xXXXXXX00
0xXXXXXX00
0xXXXXXXC0
Undefined
USTAT
UTXBUF
URXBUF
UBRDIV
TMOD
TDATA0
TDATA1
TCNT0
UART status register
W
R
UART transmit holding register
UART receive buffer register
Baud rate divisor register
Timer mode register
Timer 0 data register
Timer 1 data register
Timer 0 count register
Timer 1 count register
Watchdog Timer Control register
Watchdog Timer Count register
Undefined
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
0xXXXXXX00
0x00000000
0x00000000
0x00000000
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFF00
0xFFFFFFFF
TCNT1
WDCON
WDCNT
MagIC Team
Page : 36
SAMSUNG ELECTRONICS
ELECTRONICS
S5N8947 (ADSL/Cable Modem MCU)
8. ELECTRIC CHARACTERISTICS
8.1. ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Units
Supply Voltage
DC input Voltage
VDD/VDDA 3.6
V
V
VIN
2.5 V I/O
3.6
6.5
5 V-tolerant
± 200
DC input current
Operating temperature
Storage temperature
IIN
mA
ºC
ºC
TOPR
TSTG
0 to 70
– 65 to 150
Table 4 Absolute Maximum Ratings
8.2. Recommended Operating Conditions
Parameter
Supply Voltage
Symbol
Rating
Units
VDD/VDDA 2.3 to 2.7
V
Oscillator frequency
fOSC
LF
12
MHz
pF
External Loop Filter Capacitance
Commercial temperature
820
TA
0 to 70
ºC
Table 5 Recommaended Operating Conditions
NOTES
ü
It is strongly recommended that all the supply pins (VDD/VDDA) be powered from the same source
to avoid power latch-up.
SAMSUNG ELECTRONICS
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MagIC Team
ELECTRONICS
S5N8947 (ADSL/Cable Modem MCU)
8.3. DC ELECTRICAL CHARACTERISTICS
VDD =2.5V+/-0.2V, VEXT = 5+/-0.25V, TA=-40 to 85 Centigrade (In case of 5V-tolerant I/O)
Parameter
High level input voltage
Symbol
Conditions
Min
1.7
Typ
Max
Unit
(1)
LVCMOS
interface
LVCMOS
interface
–
–
–
–
–
V
V
VIH
(1)
Low level input voltage
Switching threshold
–
0.7
VIL
VT
LVCMOS
LVCMOS
LVCMOS
VIN = VDD
–
0.5 VDD
–
V
–
Schmitt trigger positive-going threshold
Schmitt trigger negative-going threshold
VT+
VT–
–
–
1.9
–
0.6
– 10
10
–
–
High level input current
Low level input current
High level output voltage
Input buffer IIH
–
10
50
µA
Input buffer
with pull-up
25
Input buffer ILH
VIN = VSS
– 10
– 50
–
10
µA
V
Input buffer
with pull-up
Type B1 to VOH
B16(2)
– 25
– 10
IOH = –
A
VDD
– –
–
0.05
1.9
Type B1
Type B2
Type B4
Type B6
IOH = – 1 mA
IOH = – 2 mA
IOH = – 4 mA
IOH = – 6 mA
Low level output voltage
Type B1 to VOL
B16(2)
Type B1
IOL = –
A
0.05
0.5
V
IOL = – 1 mA
IOL = – 2 mA
IOL = – 4 mA
IOL = – 6 mA
Type B2
Type B4
Type B6
Tri-state output leakage current
IOZ
IDD
VOUT = VSS or – 10
VDD
10
55
µA
Maximum operating current
VDD = 3.6 V,
fMCLK = 50MHz
mA
Table 6 DC Electrical Characteristics
NOTES:
1. All 5V-tolerant input have less than 0.2V hysterisis.
2. Type B1 means 1mA output driver cells, and Type B6/B24 means 6mA/24mA output driver cells.
MagIC Team
Page : 38
SAMSUNG ELECTRONICS
ELECTRONICS
S5N8947 (ADSL/Cable Modem MCU)
8.4. A.C Electrical Characteristics
(Ta = -40 to +85 Centigrade, VDD = 2.3V to 2.7V)
Signal Name
tEMz
Description
Memory control signal High-Z time
ExtMREQ setup time
Min
5.1
Max
10.1
Unit
ns
tEMRs
tEMRh
tEMAr
tEMAf
0
ExtMREQ hold time
3.0
12.1
12.3
8.5
7.08
5.2
5.7
5.5
3.0
ExtMACK rising edge delay time
ExtMACK falling edge delay time
Address hold time
29.3
29.7
tADDRh
tADDRd
tNRCS
tNROE
tNWBE
tRDh
Address delay time
17.5
12.4
13.6
13.1
ROM/SRAM/Flash bank chip select delay time
ROM/SRAM or external I/O bank output enable delay
ROM/SRAM or external I/O bank write byte enable delay
Read data hold time
tWDd
Write data delay time (SRAM or external I/O)
Write data hold time (SRAM or external I/O)
DRAM row address strobe active delay
DRAM row address strobe release delay
DRAM column address strobe active delay
DRAM CAS signal release delay time
DRAM bank write enable delay time
DRAM bank out enable delay time
External I/O bank chip select delay time
DRAM write data delay time (DRAM)
DRAM write data hold time (DRAM)
External wait setup time
17.23
tWDh
9.4
5.6
4.3
5.5
4.36
5.8
5.7
5.3
5.9
7.4
0
tNRASf
tNRASr
tNCASf
tNCASr
tNDWE
tNDOE
tNECS
tWDDd
tWDDh
tWs
13.4
16.38
13.1
13.1
13.9
13.6
12.5
14.2
tWh
External wait hold time
3.0
TMCLKOd
External clock to MCLKO delay time when PLL power-down 5.0
12.45
Table 7 AC Electrical Characteristics
SAMSUNG ELECTRONICS
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MagIC Team
ELECTRONICS
S5N8947 (ADSL/Cable Modem MCU)
XCLK
tEMz
Address, Data,
nOE, nWBE, nDWE,
nRCS, nCAS, nRAS
tEMRs
tEMRh
ExtMREQ
ExtMACK
tEMAr
tEMRf
Figure 14 External Bus Request Timing
MagIC Team
Page : 40
SAMSUNG ELECTRONICS
ELECTRONICS
S5N8947 (ADSL/Cable Modem MCU)
XCLK
tADDRh
tADDRd
tCOH tNECS
tNROE
Address
nECS
tACS tNECS
tNROE
tACC
nOE
tCOS
nWBE
Data(R)
nEWAIT
tRDh
tWS
tWH
tCOH = 0
tCOH = 1
Data Fetch
(tCOH = 0)
Data Fetch
(tCOH = 1)
Figure 15 External I/O Read Timing with nEWAIT (tCOH = 1, tACC = 1, tCOS = 1, tACS = 1)
SAMSUNG ELECTRONICS
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ELECTRONICS
S5N8947 (ADSL/Cable Modem MCU)
XCLK
tADDRh
tADDRd
Address
tACS tNECS
tCOH tNECS
nECS
tNROE
tNROE
nWBE
tRDh
Data(W)
tWS
tWH
nEWAIT
tCOH = 0
tCOH = 1
Data Fetch
(tCOH = 0)
Data Fetch
(tCOH = 1)
Figure 16 External I/O Write Timing with nEWAIT (tCOH = 1, tACC = 1, tCOS = 1, tACS = 1)
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SAMSUNG ELECTRONICS
ELECTRONICS
S5N8947 (ADSL/Cable Modem MCU)
XCLK
tADDRh
tADDRd
Address
nRCS
tNRCS
tNROE
tNRCS
tNROE
tRDh
tACC
nOE
Data(R)
Figure 17 ROM/SRAM/Flash Read Access Timing
XCLK
Address
nRCS
tADDRh
tADDRd
tNRCS
tNRCS
tACC
tNRWE
tNRWE
nWBE
tWDd
tWDh
Data(W)
Figure 18 ROM/SRAM/Flash Write Access Timing
SAMSUNG ELECTRONICS
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MagIC Team
ELECTRONICS
S5N8947 (ADSL/Cable Modem MCU)
XCLK
tNRASr
tRP
tNRASf
tRC
nRAS
tCS
tCP
tCS
nCAS
tNCASf
tADDRd
tNCASw
tNCASr tNCASf
tNCASr
Address
nOE
Row Address
tNDOE
Column Address
Column Address
tNDWE
tADDRh
tWDDh
EDO
Data(R)
Fetch time
(EDO DRAM)
Fetch time
(EDO DRAM)
Figure 19 EDO/FP DRAM Bank Read Timing (Page Mode)
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SAMSUNG ELECTRONICS
ELECTRONICS
S5N8947 (ADSL/Cable Modem MCU)
XCLK
nRAS
nCAS
tNRASr
tRP
tNRASf
tRC
tCS
tCP
tCS
tNCASf
tADDRd
tNDWE
tNCASw
tNCAS tNCAS
tNCAS
r
r
f
Address
Row
Address
Column
Address
Column
Address
tNDWE
tADDR
h
nDWE
tWDDh
tWDDh
tWDDd
Data(W)
tWDDd
Figure 20 EDO/FP DRAM Bank Write Timing (Page Mode)
Timing Parameters for MII Transactions
The timing diagrams in this section conform to the guidelines described in the "Draft Supplement to ANSI/IEEE Std. 802.3,
Section 22.3, Signal Characteristics."
Tx_clk
0ns MIN, 25ns MAX
TxD[3:0]
Tx_en
Figure 21 Transmit Signal Timing Relationship at MII
Rx_clk
10ns MIN 10ns MIN
RxD[3:0],
Rx_DV,
Rx_er
INPUT VALID
Figure 22 Receive Signal Timing Relationship at MII
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SAMSUNG ELECTRONICS
MagIC Team
ELECTRONICS
S5N8947 (ADSL/Cable Modem MCU)
7 Cycles
7 Cycles
MDC
0ns MIN, 300ns MAX
MDIO
Figure 23 MDIO Sourced by PHY
MDC
10ns MIN 10ns MIN
INPUT VALID
MDIO
Figure 24 MDIO Sourced by STA
Timing Parameters for UTOPIA, An ATM-PHY Interface Specification
The AC characteristics are based on the timing specification for the receiver side pof a signal. The setup and hold times are
defined with regard to a positive clock edge (see Figure 25). Tacking the actual used clock frequency into account (e.g. up to
the max. frequency), the corresponding (min. and max.) transmit side “clock to output” propagation delay specifications can
be derived. The timing references (tT5 to tT12) are according to Table 8 and 9.
Clock
Signal
tT5, tT7
tT6, tT8
Input setup to clock
Input hold from clock
Figure 25 Aetup and hold time definition (single- and multi-PHY)
Figure 26 shows the tri-state timing for the multi-PHY application (multiple PHY devices, multiple output signals are
multiplexed together).
Clock
Signal going low
Signal going high
impedance to clock
impedance to clock
tT9
tT10
Signal
tT11
tT12
Signal going low
impedance from clock
Signal going high
impedance from clock
Figure 26 Tri-state timing (multi-PHY, multiple devices only)
In the following Tables, AÞ P (column DIR, direction) defines a signal from the ATM layer (transmitter, driver) to the PHY
layer (receiver), AÜ P defines a signal from the PHY layer (transmitter, driver) to the ATM layer (receiver).
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SAMSUNG ELECTRONICS
ELECTRONICS
S5N8947 (ADSL/Cable Modem MCU)
Signal Name
TxClk
DIR Item
Description
Min
0
Max
f1 TxClk frequency (nominal)
tT2 TxClk duty cycle
33MHz
AÞ P
40%
-
60%
tT3 TxClk peak-to-peak jitter
tT4 TxClk rise/fall time
5%
-
3ns
TxData[7:0], TxPrty, TxSOC,
TxEnb*, TxAddr[4:0]
tT5 Input setup to TxClk
8ns
1ns
8ns
1ns
8ns
0ns
1ns
1ns
-
-
-
-
-
-
-
-
AÞ P
AÜ P
tT6 Input hold from TxClk
TxFull*/TxClav[3:0]
tT7 Input setup to TxClk
tT8 Input hold from TxClk
tT9 Signal going low impedance to TxClk
tT10 Signal going high impedance to TxClk
tT11 Signal going low impedance from TxClk
tT12 Signal going high impedance from TxClk
Table 8 Transmit timing (8-bit data bus, N33MHz at cell interface, multi-PHY)
Signal Name
RxClk
DIR Item
Description
Min
0
Max
f1 RxClk frequency (nominal)
tT2 RxClk duty cycle
33MHz
AÞ P
40%
-
60%
tT3 RxClk peak-to-peak jitter
tT4 RxClk rise/fall time
5%
-
3ns
RxEnb*, RxAddr[4:0]
tT5 Input setup to RxClk
8ns
1ns
8ns
1ns
8ns
0ns
1ns
1ns
-
-
-
-
-
-
-
-
AÞ P
AÜ P
tT6 Input hold from RxClk
RxData[7:0], RxPrty, RxSOC,
RxEmpty*/RxClav[3:0]
tT7 Input setup to RxClk
tT8 Input hold from RxClk
tT9 Signal going low impedance to RxClk
tT10 Signal going high impedance to RxClk
tT11 Signal going low impedance from RxClk
tT12 Signal going high impedance from RxClk
Table 9 Receive timing (8-bit data bus, N33MHz at cell interface, multi-PHY)
SAMSUNG ELECTRONICS
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MagIC Team
ELECTRONICS
S5N8947 (ADSL/Cable Modem MCU)
9. PACKAGE DIMENSION
This section describes the mechanical data for the S5N8947 208-pin TQFP package.
208-TQFP-2828 PACKAGE DIMENSIONS
Figure 27 208-TQFP-2828 Package Dimensions
MagIC Team
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SAMSUNG ELECTRONICS
ELECTRONICS
S5N8947 (ADSL/Cable Modem MCU)
Revision History
Revision
No.
Date
Description
0.1
2000-05-23
S5N8947X (Rev.0.1) Released.
IMPORTANT NOTICE
The information furnished by Samsung Electronics in this document is belived to be accurate and
reliable. However, no resposibility is assumed by Samsung Electronics for its use, nor for any
infringements of patents or other rights of third parties resulting from its use. No license is granted
under any patents or patent rights of Samsung Electronics. Samsung Electronics reserves the right to
make changes to its products or to discontinue any semiconductor product or service without notice,
and advises its customers to obtain the latest version of relevant information to verify, before placing
orders, that the information being relied on is current and complete.
For More Information
Tel: (82)-(31)-209-8301, Fax: (82)-(31)-209-8309
E-mail: kimil@sec.samsung.com
http://www.intl.samsungsemi.com
Copyright ©2000 Samsung Electronics, Inc. All Rights Reserved
SAMSUNG ELECTRONICS
Page : 49
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