S5N8952X [SAMSUNG]
ADSL Transceiver for NIC; ADSL收发器网卡
| 型号： | S5N8952X |
| 厂家： | 
SAMSUNG |
| 描述： | ADSL Transceiver for NIC |
| 文件： | 总18页 (文件大小：214K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S5N8952X
ADSL Transceiver for NIC
Preliminary Information
(Revision 2.0)
September. 2000
SAMSUNG ELECTRONICS CONFIDENTIAL PROPRIETARY
Copyright ©1999-2000 Samsung Electronics, Inc. All Rights Reserved
S5N8952X
ADSL Transceiver for NIC
Contents
1. Features .......................................................................................................... 5
2. General Description........................................................................................... 5
3. Logical Symbol Diagram .................................................................................... 6
4. Pin Configuration .............................................................................................. 7
5. Pin Description ................................................................................................. 8
6. Functional Description ..................................................................................... 13
7. I/O Timing Description..................................................................................... 14
8. Electrical Characteristics .................................................................................. 16
9. Package Description........................................................................................ 17
Preliminary Information (Rev.2.0)
2
S5N8952X
ADSL Transceiver for NIC
List of Figures
Figure 1: General Block Diagram......................................................................... 5
Figure 2: Logical Symbol Diagram of the S5N8952X............................................. 6
Figure 3: Pin Configuration of the S5N8952X ...................................................... 7
Figure 4: Functional Block Diagram of the S5N8952X......................................... 13
Figure 5: AFE Data I/F Timing Diagram.............................................................. 14
Figure 6: AFE Control I/F Timing Diagram .......................................................... 14
Figure 7: PCI I/F Timing Diagram ...................................................................... 15
Figure 8: 208-LQFP Package Diagram ............................................................... 17
Preliminary Information (Rev.2.0)
3
S5N8952X
ADSL Transceiver for NIC
List of Tables
Table 1: Pin Description of the S5N8952X .......................................................... 8
Table 2: Absolute Maximum Ratings ................................................................. 16
Table 3: Recommended Operating Conditions .................................................... 16
Table 4: Pow er Dissipation .............................................................................. 16
Table 5: DC Characteristics ............................................................................. 16
Preliminary Information (Rev.2.0)
4
S5N8952X
ADSL Transceiver for NIC
1. Features
· Full Compliance w ith T1.413 Issue-2, ITU-T G.992.1 (G.dmt) and G.992.2 (G.lite).
· FDM and EC-based DMT Line Coding
· Data Rate: over 8Mbps for Dow nstream and 640 Kbps for Upstream.
· Reach: 6.7 Km (22Kft) w ith 24 AWG and 5.5 Km (18 Kft) w ith 26 AWG
· Supports Rate Adaptive Mode (steps of 32kbps)
· Reed-Solomon Forward Error Correction w ith(or w ithout) Interleaver
· Adaptive Frequency and Time Domain Equalizer.
· Trellis Coding and Echo Cancellation.
· Supports Normal or Reduced Overhead Framing Modes
· Supports Analog and Digital PLL.
· Compatible to PCI V2.2
· Handle ATM Cells (On-Chip SAR and Connection Memory)
· Supports Fast Retraining Function in G.lite Mode
· Supports Netw ork Management Function
· Supports Power Management Function
· 0.18mm, 1.8V CMOS Technology
· Operating Temperature: -40 °C to 85 °C
· Package Type: 208-LQFP
2. General Description
The S5N8952X is a complete ATM-based ADSL modem solution w ith associated F/W and
an Analog Front-End (S5N8951). The S5N8952X provides all the digital functions such as
PCI I/F, SAR, ATM framing, channel codec, DMT modulation, and DSP control.
There are tw o interfaces for external communications; PCI bus interface for NIC
applications and AD/DA interface. The S5N8952X is optimized for providing NIC solution
for CPE, and uses 17.664MHz Xtal oscillator as a master clock.
S5N8952
S5N8951
Phone
Analog
Front-
End
ATM
Framer
DMT
Processor
Hybrid
PCI
&
SAR
Line
Driver
PCI_BUS
ROM
DSP
Figure 1: General Block Diagram
Preliminary Information (Rev.2.0)
5
S5N8952X
ADSL Transceiver for NIC
3. Logical Symbol Diagram
S5N8952X
RESET_N
XTAL_IN
LD_TX_PWDN
LD_RX_PWDN
XTAL_OUT
EXT_CLK
AFE_RESET_N
AFE_SDI
PLL_FILT
TEST_MODE[3:0]
TEST_SCN_EN
TEST_IN
AFE_SDO
AFE_SCK
AFE_SEN_N
AFE_BUSY
AFE_PME
TEST_OUT
TX_SHOW
RX_SHOW
GP_OUT[1:0]
BT_MODE[1:0]
NTR
AFE_NOISE
AFE_DA_REF
AFE_DA_CLK
AFE_DA_DAT[6:0]
AFE_AD_REF
AFE_AD_CLK
PCI_AD[31:0]
PCI_CBE_N[3:0]
PCI_FRAME_N
PCI_IRDY_N
PCI_TRDY_N
PCI_DEVSEL_N
PCI_STOP_N
PCI_PERR_N
PCI_PAR
AFE_AD_DAT[6:0]
TL_TMS
TL_TCK
TL_TDI
TL_TDO
TL_TINTP
PCI_GNT_N
PCI_PME_N
PCI_REQ_N
PCI_SERR_N
PCI_INTA_N
PCI_RST_N
PCI_CLK
PCI_IDSEL
EPROM_CS_N
EPROM_SI
EPROM_SO
EPROM_CK
PWR_ON
AUX_PWR_ON
Figure 2: Logical Symbol Diagram of the S5N8952X
Preliminary Information (Rev.2.0)
6
S5N8952X
ADSL Transceiver for NIC
4. Pin Configuration
EXT_CLK
AFE_DA_CLK
VDD33
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
1
2
3
4
5
6
7
8
PCI_AD_25
PCI_AD_24
VDD1
GND37
GND1
TEST_MODE_3
AFE_DA_REF
TEST_MODE_2
GND36
VDD32
GND35
TEST_MODE_1
AFE_DA_DAT_6
TEST_MODE_0
GND34
VDD31
GND33
PCI_CBE_N_3
PCI_IDSEL
VDD2
GND2
9
PCI_AD_23
PCI_AD_22
VDD3
PCI_AD_21
PCI_AD_20
VDD4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
GND3
PCI_AD_19
PCI_AD_18
VDD5
AFE_DA_DAT_5
TEST_SCN_EN
VDD30
S5N8952X
GND4
GND32
PCI_AD_17
PCI_AD_16
VDD6
PCI_CBE_N_2
GND5
VDD7
GND6
PCI_FRAME_N
VDD8
GND7
PCI_IRDY_N
VDD9
PCI_TRDY_N
PCI_DEVSEL_N
VDD10
AFE_DA_DAT_4
AFE_AD_CLK
AFE_DA_DAT_3
VDD29
ADSL Transceiver for NIC
GND31
AFE_AD_REF
AFE_DA_DAT_2
AFE_AD_DAT_6
AFE_DA_DAT_1
VDD28
(208-LQFP)
GND30
AFE_AD_DAT_5
AFE_AD_DAT_3
AFE_AD_DAT_4
GND29
VDD27
GND28
AFE_AD_DAT_1
AFE_DA_DAT_0
AFE_SDI
GND8
PCI_STOP_N
PCI_PERR_N
VDD11
GND9
PCI_SERR_N
PCI_PAR
VDD12
PCI_CBE_N_1
PCI_AD_15
VDD13
AFE_SDO
AFE_AD_DAT_2
AFE_RESET_N
AFE_AD_DAT_0
AFE_SCK
GND27
VDD26
GND10
PCI_AD_14
PCI_AD_13
VDD14
GND11
PCI_AD_12
PCI_AD_11
GND26
AFE_BUSY
AFE_SEN_N
AFE_PME
AFE_NOISE
Figure 3: Pin Configuration of the S5N8952X
Preliminary Information (Rev.2.0)
7
S5N8952X
ADSL Transceiver for NIC
5. Pin Description
Table 1: Pin Description of the S5N8952X
No
Name
I/O
I
I
Description
178 RESET_N
168 XTAL_IN
169 XTAL_OUT
System master reset (Active low )
System master clock (17.664MHz)
O
External clock for test
(Float in normal mode)
PLL pump out
(A 320pF capacitor betw een the pin and GNDA)
156 EXT_CLK
172 PLL_FILT
I
O
152 TEST_MODE_3
150 TEST_MODE_2
146 TEST_MODE_1
144 TEST_MODE_0
139 TEST_SCN_EN
Chip test mode
[0] Normal mode, [1-15] Test mode
I
I
I
O
Scan enable (Set to ‘0’ in normal mode)
Test input (Float in normal mode)
Test output (Float in normal mode)
Tx show time indicator
(Active high. Connect to LED)
Rx show time indicator
(Active high. Connect to LED)
General purpose outputs
(Float if not needed)
93
92
TEST_IN
TEST_OUT
182 TX_SHOW
183 RX_SHOW
O
O
O
158 GP_OUT_1
157 GP_OUT_0
165 BT_MODE_1
Boot mode
I
[0] Reset, [1] Boot from host
[2] Boot from J TAG, [3] Self-booting
ATM netw ork timing reference (8KHz. Float if not
needed)
164 BT_MODE_0
161 NTR
B
200 PCI_AD_31
201 PCI_AD_30
203 PCI_AD_29
204 PCI_AD_28
207 PCI_AD_27
208 PCI_AD_26
1
2
9
PCI_AD_25
PCI_AD_24
PCI_AD_23
PCI_AD_22
PCI_AD_21
PCI_AD_20
PCI_AD_19
PCI_AD_18
PCI_AD_17
PCI_AD_16
PCI_AD_15
PCI_AD_14
PCI_AD_13
10
12
13
16
17
20
21
44
47
48
B
PCI address data [31:0]
Preliminary Information (Rev.2.0)
8
S5N8952X
ADSL Transceiver for NIC
51
52
53
54
55
58
61
65
66
70
71
74
75
PCI_AD_12
PCI_AD_11
PCI_AD_10
PCI_AD_9
PCI_AD_8
PCI_AD_7
PCI_AD_6
PCI_AD_5
PCI_AD_4
PCI_AD_3
PCI_AD_2
PCI_AD_1
PCI_AD_0
B
PCI address data [31:0]
5
PCI_CBE_N_3
PCI_CBE_N_2
PCI_CBE_N_1
PCI_CBE_N_0
PCI_FRAME_N
PCI_IRDY_N
PCI_TRDY_N
PCI_DEVSEL_N
PCI_STOP_N
PCI_PERR_N
PCI_PAR
B
B
B
B
B
B
B
B
B
B
B
I
23
43
60
27
30
32
33
36
37
41
PCI command byte enable [3:0]
PCI frame
PCI initiator ready
PCI target ready
PCI device select
PCI stop
PCI parity error
PCI parity bit
PCI grant
191 PCI_GNT_N
40
PCI_SERR_N
OZ PCI system error
OZ PCI interrupt A
OZ PCI pow er management event
OZ PCI request
I
I
I
186 PCI_INTA_N
196 PCI_PME_N
195 PCI_REQ_N
187 PCI_RST_N
190 PCI_CLK
PCI reset
PCI clock
PCI initialization device select
6
PCI_IDSEL
79
82
83
78
EPROM_SO
EPROM_SI
EPROM_CS_N
EPROM_CK
I
EPROM scan out
EPROM scan in
EPROM chip select
EPROM clock
O
87
88
AUX_PWR_ON
PWR_ON
I
I
Aux pow er detected (Active high)
Main pow er detected (Active high)
95
94
LD_TX_PWDN
LD_RX_PWDN
O
O
Tx line driver pow er-dow n (Active high)
Rx line driver pow er-dow n (Active high)
114 AFE_RESET_N
117 AFE_SDI
O
I
AFE reset (Active low )
AFE serial interface data in
116 AFE_SDO
112 AFE_SCK
107 AFE_SEN_N
108 AFE_BUSY
O
O
O
I
AFE serial interface data out
AFE serial interface clock
AFE serial interface data enable (Active low )
AFE serial interface busy (Active high. Float if not
Preliminary Information (Rev.2.0)
9
S5N8952X
ADSL Transceiver for NIC
needed)
AFE pow er management event (Active high. Float if
not needed)
Audible noise detection for pow er cutback (Active
high. Float if not needed)
106 AFE_PME
I
I
105 AFE_NOISE
155 AFE_DA_CLK
151 AFE_DA_REF
O
O
DAC sample reference 1 (8.832MHz)
DAC sample reference 0 (4.416MHz)
145 AFE_DA_DAT_6
140 AFE_DA_DAT_5
136 AFE_DA_DAT_4
134 AFE_DA_DAT_3
130 AFE_DA_DAT_2
128 AFE_DA_DAT_1
118 AFE_DA_DAT_0
O
DAC data [6:0]
135 AFE_AD_CLK
131 AFE_AD_REF
I
I
ADC sample reference 1 (Float in normal mode)
ADC sample reference 0 (Float in normal mode)
129 AFE_AD_DAT_6
125 AFE_AD_DAT_5
123 AFE_AD_DAT_4
124 AFE_AD_DAT_3
115 AFE_AD_DAT_2
119 AFE_AD_DAT_1
113 AFE_AD_DAT_0
I
ADC Data [6:0]
104 TL_TMS
103 TL_TCK
100 TL_TDI
I
I
I
J TAG test mode select (Float in normal mode)
J TAG test clock (Float in normal mode)
J TAG test input data (Float in normal mode)
99
98
TL_TDO
TL_TINTP
OZ J TAG test output data (Float in normal mode)
O
TJ AM interrupt to host (Float in normal mode)
11
22
31
42
59
77
85
97
VDD3
VDD6
VDD9
VDD12
VDD16
VDD20
VDD22
VDD24
P1
1.8V supply voltage
110 VDD26
127 VDD28
138 VDD30
148 VDD32
159 VDD34
162 VDD35
180 VDD40
202 VDD45
3
14
18
VDD1
VDD4
VDD5
P1
3.3V supply voltage
Preliminary Information (Rev.2.0)
10
S5N8952X
ADSL Transceiver for NIC
25
34
38
49
57
63
73
81
90
VDD7
VDD10
VDD11
VDD14
VDD15
VDD17
VDD19
VDD21
VDD23
102 VDD25
121 VDD27
133 VDD29
142 VDD31
154 VDD33
166 VDD36
184 VDD41
188 VDD42
198 VDD44
205 VDD46
P1
3.3V supply voltage
7
VDD2
28
45
68
VDD8
VDD13
VDD18
P1
3.3V or 5V supply voltage for PCI only
193 VDD43
4
GND1
8
GND2
15
19
24
26
29
35
39
46
50
56
62
64
67
69
72
76
80
84
86
89
91
96
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
P0
Ground
101 GND25
Preliminary Information (Rev.2.0)
11
S5N8952X
ADSL Transceiver for NIC
109 GND26
111 GND27
120 GND28
122 GND29
126 GND30
132 GND31
137 GND32
141 GND33
143 GND34
147 GND35
149 GND36
153 GND37
160 GND38
163 GND39
167 GND40
179 GND45
181 GND46
185 GND47
189 GND48
192 GND49
194 GND50
197 GND51
199 GND52
206 GND53
P0
Ground
170 VDDA37
174 VDDA38
176 VDDA39
P1
P0
1.8V analog supply voltage
Analog ground
171 GNDA41
173 GNDA42
175 GNDA43
177 GNDA44
I
= Input
O
= Output
OZ
B
P1
P0
= Tri-state output
= Bi-direction
= Pow er
= Ground
Preliminary Information (Rev.2.0)
12
S5N8952X
ADSL Transceiver for NIC
6. Functional Description
The ADSL modem for customer premises consists of tw o main chips; ADSL transceiver
chip (S5N8952) and analog front-end chip (S5N8951). The analog front-end provides an
analog interface w ith line drivers and hybrid components for connecting to the PSTN. The
ADSL Transceiver provides all the digital functions as depicted in Figure 4.
DMT inherently transmits an optimized time-variable spectrum. This spectrum is adjusted
according to the desired data rate and the transmission characteristics (transfer function
and noise spectrum) on each and every subchannel. For this, CO and CPE transmit 256
4kHz-w ide tone dow nstream and upstream respectively to each other during initialization.
They measure the quality of each of these received tones and then decide w hether a tone
has sufficient quality to be used for further transmission and, if so, how much data this
tone should carry relative to the other tones that are used. They inform the bit loading
informations to each other.
In FDM-based DMT (Discrete MultiTone) modulation, the frequency band, 0 to 1.104MHz,
is divided into 256 equi-spaced subchannels w ith 4.3125KHz tone spacing. The frequency
band, 26KHz (#6) to 134KHz (#31) is used for the upstream, and 142KHz (#33) to
1.1MHz (#255) for the dow nstream.
The S5N8952 provides PCI bus interface for NIC application and 14-bit AD/DA interface.
SAR (Segmentation and Reassembly) and ATM TC (Transmission Convergence) are
implemented for ATM cell handling and especially on-chip hardw are SAR provides more
processing pow er by reducing the PCI bus traffic than the softw are SAR. Reed-Solomon
error correction w ith/w ithout interleaver and Trellis coded modulation increase channel
noise immunity. Time/frequency-domain equalizers, echo canceller, and digital filters, of
w hich coefficients are adaptively updated according to the channel conditions, enhance
the performance of data recovery.
TCM/
TEQ/FEQ/
FRAMER/
FFT/IFFT/
ROTER
ANALOG
ATM
TC
SAR
VITERBI/
FILTER/
ECHO
RS CODEC
FRONT_END
QAM CODEC
PCI_BUS
PCI
TEAKLITE
DSP
HOST
I/F
RAM
ROM
Figure 4: Functional Block Diagram of the S5N8952X
Preliminary Information (Rev.2.0)
13
S5N8952X
ADSL Transceiver for NIC
7. I/O Timing Description
AFE_DA_CLK
(8.832MHz)
AFE_DA_REF
t1
t2
(4.416MHz)
AFE_DA_DAT
[6:0]
[6:0]
[13:7]
t3
t4
AFE_AD_DAT
[6:0]
[6:0]
[13:7]
Parameter
Description
Min
15
15
30
1
Max
Unit
ns
ns
ns
ns
t1
t2
t3
t4
AFE_DA_DAT setup to AFE_DA_CLK •
AFE_DA_DAT hold after AFE_DA_CLK •
AFE_AD_DAT setup to AFE_DA_CLK ¯
AFE_AD_DAT hold after AFE_DA_CLK ¯
Figure 5: AFE Data I/F Timing Diagram
t2
t3
AFE_SEN_N
AFE_SCK
(1.104MHz)
AFE_SDO
CS0
CS1
A4
A0
RW
t1
D15 D14
D0
D14
D15
D0
AFE_SDI
Parameter
Description
AFE_SDI setup to AFE_SCK•
AFE_SEN_N ¯ before AFE_SCK •
AFE_SEN_N • from AFE_SCK •
Min
30
30
Max
Unit
ns
ns
t1
t2
t3
15
ns
Figure 6: AFE Control I/F Timing Diagram
Preliminary Information (Rev.2.0)
14
S5N8952X
ADSL Transceiver for NIC
t3
t4
t5
PCI_CLK
(33MHz)
Inputs
t1
t2
t6
t7
Outputs
Tri-state
Outputs
t8
Parameter
Description
Min
3
0
30
6
6
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
t1
t2
t3
t4
t5
t6
t7
t8
Input setup to PCI_CLK •
Input hold after PCI_CLK •
PCI_CLK period
PCI_CLK low time
PCI_CLK high time
PCI_CLK • to signal valid delay
Float to active delay
Active to float delay
1
1
6
14
Figure 7: PCI I/F Timing Diagram
Preliminary Information (Rev.2.0)
15
S5N8952X
ADSL Transceiver for NIC
8. Electrical Characteristics
Table 2: Absolute Maximum Ratings
Symbol
ILATCH
TSTG
Parameter
Latch-up Current
Storage Temperature
Rating
Unit
mA
°C
±200
-65 to 150
Table 3: Recommended Operating Conditions
Symbol
Parameter
Rating
Unit
1.8V I/O
3.3V I/O
5V-tolerant I/O
(3.3V Interface)
1.65 to 1.95
3.0 to 3.6
DC Supply Voltage
VDD
V
3.0 to 3.6
1.8±5%
0 to 70
Analog Core DC Supply
Voltage
Operating Temperature
(Ambient)
1.8V Core
TA
Commercial
°C
Table 4: Pow er Dissipation
Symbol
Parameter
Min
Typ
Max
Unit
PD
Pow er Dissipation
-
0.3
-
W
Table 5: DC Characteristics
Symbol
VIH
VIL
VOH
VOL
Parameters
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Sw itching Threshold
Min
2.0
-
2.4
-
Typ
Max
Unit
-
-
-
-
0.8
-
0.4
-
-
V
VT
-
1.4
Schmitt Trigger, Positive-going
Threshold
Schmitt Trigger, Negative-
going Threshold
VT+
VT-
IIH
-
-
-
2.0
-
0.8
-10
10*
-10
-
33*
-
10
60*
10
Input High Current (VIN= VDD)
Input Low Current (VIN= VSS)
IIL
-60*
-33*
-10*
mA
Tri-state Output Leakage
Current
IOZ
-10
-
10
IDD
CIN
COUT
Quiescent Supply Current
Input Capacitance
Output Capacitance
-
-
-
-
-
-
100
4
4
pF
NOTES:
* - input buffer w ith pull-up(VIN= VSS) or pull-dow n(VIN= VDD).
Preliminary Information (Rev.2.0)
16
S5N8952X
ADSL Transceiver for NIC
9. Package Description
A
B
A: 30.00±0.30
B: 28.00±0.20
A
B
#208
#1
(1.25)
+ 0.10
0.50
0.20
- 0.05
0.08MAX
0~ 8°
0.10MAX
0.50±0.20
Figure 8: 208-LQFP Package Diagram
Preliminary Information (Rev.2.0)
17
S5N8952X
ADSL Transceiver for NIC
Revision History
Revision
No.
Date
Description
1.0
1.1
2000-09-15
2000-09-20
First released.
Pin configuration changed.
T1.413 issue-2 added.
2.0
2000-11-15
PCI version upgraded from 2.1 to 2.2
IMPORTANT NOTICE
The information furnished by Samsung Electronics in this document is belived to be
accurate and reliable. How ever, no resposibility is assumed by Samsung Electronics for its
use, nor for any infringements of patents or other rights of third parties resulting from its
use. No license is granted under any patents or patent rights of Samsung Electronics.
Samsung Electronics reserves the right to make changes to its products or to discontinue
any semiconductor product or service w ithout notice, and advises its customers to obtain
the latest version of relevant information to verify, before placing orders, that the
information being relied on is current and complete.
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Preliminary Information (Rev.2.0)
18
相关型号：
S5PMS-M3/86A
DIODE 1.8 A, 1000 V, SILICON, RECTIFIER DIODE, TO-277A, HALOGEN FREE AND ROHS COMPLIANT, PLASTIC, SMPC, 3 PIN, Rectifier Diode
VISHAY
S5PMS-M3/87A
DIODE 1.8 A, 1000 V, SILICON, RECTIFIER DIODE, TO-277A, HALOGEN FREE AND ROHS COMPLIANT, PLASTIC, SMPC, 3 PIN, Rectifier Diode
VISHAY
S5PV210AA0-LA40
RISC Microprocessor,S5PV210 is a 32-bit RISC cost-effective, low power, high performance microprocessor solution for mobile phones and general applications, and integrates an ARM Cortex-A8 which implements the ARM architecture V7-A with supporting numerous peripherals.
SAMSUNG
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