S5K3A1EA02-G0 [SAMSUNG]
CCD Sensor, 1280 Horiz pixels, 1024 Vert pixels, Surface Mount;
| 型号： | S5K3A1EA02-G0 |
| 厂家： | 
SAMSUNG |
| 描述： | CCD Sensor, 1280 Horiz pixels, 1024 Vert pixels, Surface Mount CD 传感器 换能器 |
| 文件： | 总34页 (文件大小：326K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1/3 INCH SXGA CMOS IMAGE SENSOR
S5K3A1EA
S5K3A1EA
(1/3” SXGA CMOS Image Sensor)
Preliminary Specification
Revision 0.4
Jun, 2004
1
S5K3A1EA
1/3” SXGA CMOS IMAGE SENSOR
DOCUMENT TITLE
1/3” Optical Size 1280x1024(SXGA) 2.8V / 1.8V CMOS Image Sensor
REVISION HISTORY
Revision No.
History
Draft Date
Remark
0.0
0.1
0.2
0.3
0.4
Initial Draft
Feb.03, 2004 Preliminary
Mar.29.2004
DC Characteristics Changed.
Register Map Updated.
Apr.09.2004
Imaging Characteristics Changed
Imaging Characteristics Changed
S5K3A1EA13 Product Added
AC Characteristics Changed
Ob_area Recommended Setting Changed
Jun.10.2004
Jun.11.2004
2
1/3 INCH SXGA CMOS IMAGE SENSOR
S5K3A1EA
INTRODUCTION
The S5K3A1EA is highly integrated single chip CMOS image sensor, fabricated by SAMSUNG
0.18um CMOS image sensor process technology. It is developed for image application to realize high
efficiency photo sensor. The sensor has 1280 x 1024 effective pixels with 1/3 inch optical format. The
sensor has on-chip 10-bit ADC blocks to digitize the pixel output and also on-chip CDS to reduce Fixed
Pattern Noise (FPN) drastically. With its few interface signals and 10-bit raw data directly connected to
the external devices, a camera system can be configured easily.
FEATURES
— Process Technology: 0.18µm Dual Gate Oxide SPQM CMOS
— Optical Size: 1/3 inch
— Unit Pixel: 3.8 µm X 3.8 µm
— Effective Resolution: 1280X1024, SXGA
— Line Progressive Read Out.
— 10-bit Raw Image Data Output
— Windowing and Panning
— Sub-Sampling (2X, 4X, 8X)
— Timing Generator for Frame Memoryless Scaler
— Timing Generator for Stepless Zooming
— Continuous and Single Frame Capture Mode
— Programmable Exposure Time and Gain Control
— Auto Dark Level Compensation
— Standby Mode for Power Saving
— Maximum 15 Frames per Second for Full Frame Readout with 24 MHz Output Data Rate
— Bad Pixel Replacement
— Dual Power Supply Voltage: 2.8V/1.8V (2.8V for analog, 1.8V for digital)
— Package Type: 48-CLCC/PLCC
PRODUCTS
Product Code
Power Supply
Backend Process
Description
S5K3A1EA01
2.8V / 1.8 V
None
Monochrome image sensor
High sensitivity monochrome
Image sensor
S5K3A1EA02
S5K3A1EA03
S5K3A1EA13
2.8V / 1.8 V
2.8V / 1.8 V
2.8V / 1.8 V
On-chip micro lens
On-chip color filter
and micro lens
On-chip color filter
and micro lens
RGB color image sensor
RGB color image sensor
3
S5K3A1EA
1/3” SXGA CMOS IMAGE SENSOR
BLOCK DIAGRAM
Main Clock
Divider
10-bit Column ADC
Odd Column CDS
MCLK
RSTN
STBYN
STRB
DATA9
DATA8
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
Timing
Generator
VSYNC
HSYNC
DCLK
Active Pixel
Sensor Array
Control
Registers
Even Column CDS
10-bit Column ADC
SCL
SDA
I2C Interface
4
1/3 INCH SXGA CMOS IMAGE SENSOR
S5K3A1EA
PIXEL ARRAY MAP
(TOP VIEW ON CHIP. DISPLAYED IMAGE WILL BE FLIPPED.)
Optical
Black Pixels
Active Pixels
10
4
Default Window of Interest
1280X1024
G B G B G B
R G R G R G
G B G B G B
R G R G R G
G B G B G B
R G R G R G
10
10
4
4
G B G B G B
R G R G R G
G B G B G B
R G R G R G
G B G B G B
R G R G R G
(14,14) read out start
point
4
10
(0,0)
5
S5K3A1EA
1/3” SXGA CMOS IMAGE SENSOR
PIN CONFIGURATION
MCLK
7
42
41
40
39
38
37
36
35
34
33
32
31
SDA
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DCLK
8
SCL
9
RSTN
STBYN
STRB
VDDA
10
11
12
13
14
15
16
17
18
VSSA
VREF
TEST2
TEST1
HSYNC
VSYNC
First Readout Pixel
6
1/3 INCH SXGA CMOS IMAGE SENSOR
S5K3A1EA
MAXIMUM ABSOLUTE RATINGS
Characteristic
Symbol
Value
Unit
Analog maximum absolute voltage
(VDDA supply relative to VSSA )
V
VDDH
-0.3 to 3.8
Digital and I/O maximum absolute voltage
(VDDIO supply relative to VSSIO
VDDD supply relative to VSSD)
VDDL
-0.3 to 2.7
VIN
Input voltage
-0.3 to 2.7
-20 to +60
-40 to +125(1)
-40 to +85(2)
TOPR
TSTG
Operating temperature
Storage temperature
°C
NOTES:
1. The maximum allowed storage temperature for S5K3A1EA01.
2. The maximum allowed storage temperature for S5K3A1EA02 and S5K3A1EA03.
7
S5K3A1EA
1/3” SXGA CMOS IMAGE SENSOR
ELECTRICAL CHARACTERISTICS
DC Characteristics
(TA = -20 to +60°C, CL = 15pF)
Characteristics
Symbol
Condition
Min
Typ
Max
Unit
VDDH
Operating voltage
applied to VDDA pins
2.6
2.8
3.0
V
VDDL
VIH
VIL
applied to VDDIO and VDDD pin
1.65
1.27
-
1.8
1.95
-
Input voltage(1)
-
-
-
-
-
0.57
10
IIL
VIN = VDDL
Input leakage
current(2)
-10
µA
IILD
VIN = VDDL
Input leakage current
5
18
-
40
-
with pull-down(3)
VOH
VDDL
0.05
-
High level output
voltage(4)
V
IOH = -1µA
I
OH = -4mA
1.2
-
-
-
-
-
-
VOL
Low level output
voltage(5)
0.05
0.45
10
IOL = 1µA
IOL = 4mA
-
IOZ
VOUT = VSS or VDDL
High-Z output leakage
current(6)
-10
µA
Input capacitance(1)
CIN
-
-
-
-
-
4
pF
ISTBL
Supply current
STBYN=Low(Active)
10
µA
All input clocks = Low
0 lux illumination
applied to VDDIO and VDDD pin
ISTBH
STBYN=Low(Active)
All input clocks = Low
0 lux illumination
-
-
10
µA
applied to VDDA pin
IDDL
fMCLK = 12MHz
-
-
10
20
15
25
mA
mA
0 lux illumination
applied to VDDIO and VDDD pin
IDDH
fMCLK = 12MHz
0 lux illumination
applied to VDDA pin
NOTES:
1. Applied to MCLK, RSTN, STBYN, STRB, SCL, SDA, TEST1, TEST2 pins.
2. Applied to MCLK, RSTN, STBYN, STRB, SCL, SDA pins
3. Applied to TEST1, TEST2 pin
4. Applied to DCLK, HSYNC, VSYNC, DATA0 to DATA9 pin. I
5. Applied to DCLK, HSYNC, VSYNC, DATA0 to DATA9, SCL, SDA pin. I : Low level output current
: High level output current
OH
OL
6. Applied to SDA pin when in High-Z output state
8
1/3 INCH SXGA CMOS IMAGE SENSOR
S5K3A1EA
9
S5K3A1EA
1/3” SXGA CMOS IMAGE SENSOR
Imaging Characteristics
(Light source with 3200K of color temperature and IR cut filter (CM-500S, 1mm thickness) is used. Electrical
operating conditions follow the recommended typical values. The control registers are set to the default values.
TA = 25°C if not specified.)
Characteristic
Saturation level(1)
Symbol
VSAT
Condition
Min
600
Typ
650
Max
-
Unit
mV
-
Sensitivity(2)
Dark level(3)
S
-
-
-
1500
4
-
mV/lux sec
mV/sec
VDARK
8
TA = 40°C
-
20
40
TA = 60°C
Dynamic range(4)
Signal to noise ratio(5)
Dark signal non-uniformity(6)
DR
S/N
-
-
-
-
60
40
-
-
-
dB
-
DSNU
40
mV/sec
%
TA = 60°C
Photo response non-
PRNU
-
-
4
8
uniformity(7)
Vertical fixed pattern noise(8)
Horizontal fixed pattern noise(9)
VFPN
HFPN
-
-
4
4
8
8
%
%
NOTES:
1. Measured minimum output level at 100 lux illumination for exposure time 1/30 sec. 7X7 rank filter is applied for the whole
pixel area to eliminate the values from defective pixels.
2. Measured average output at 25% of saturation level illumination for exposure time 1/30 sec. Green channel output values
are used for color version.
3. Measured average output at zero illumination without any offset compensation for exposure time 1/30 sec.
4. 20 log (saturation level/ dark level RMS noise excluding fixed pattern noise). 60dB is limited by 10-bit ADC.
5. 20 log (average output level / RMS noise excluding fixed pattern noise) at 25% of saturation level illumination for exposure
time 1/30 sec.
6. Difference between maximum and minimum pixel output levels at zero illumination for exposure time 1/30 sec. 7X7 median
filter is applied for the whole pixel area to eliminate the values from defective pixels.
7, Difference between maximum and minimum pixel output levels divided by average output level at 25% of saturation level
illumination for exposure time 1/30 sec. 7X7 median filter is applied for the whole pixel area to eliminate the values from
defective pixels.
8. For the column-averaged pixel output values, maximum relative deviation of values from 7-depth median filtered values for
neighboring 7 columns at 25% of saturation level illumination for exposure time 1/30 sec.
9. For the row-averaged pixel output values, maximum relative deviation of values from 7-depth median filtered values for
neighboring 7 rows at 25% of saturation level illumination for exposure time 1/30 sec.
10
1/3 INCH SXGA CMOS IMAGE SENSOR
AC Characteristics
S5K3A1EA
°
(VDDH = 2.8V ± 0.25V, VDDL = 1.8V ± 0.15V, TA = -20 to + 60 C, CL = 10pF)
Characteristic
Symbol
Condition
Min
Typ
Max
Unit
fMCLK
Main input clock frequency
Duty = 50%
6
12
48
MHz
fDCLK
tPDMV
tPDMH
tPDMD
tPDMO
tPDDV
tPDDH
tPDDO
tWRST
tWSTB
Data output clock frequency
-
6
-
12
-
30
10
10
6
Propagation delay time
from main input clock
VSYNC output
HSYNC output
DCLK output
ns
-
-
-
-
DATA output
-
-
10
4
Propagation delay time
from data output clock
VSYNC output
HSYNC output
DATA output
-
-
-
-
4
-
-
4
(1)
Reset input pulse width
RSTN=low(active)
STBYN=low(active)
5
4
-
-
TMCLK
Standby input pulse width
-
-
NOTES:
1. TMCLK is the period of the master input clock, MCLK.
0.5V
DD
PDMD
MCLK
t
t
PDMD
DCLK
DATA
t
PDDO
t
PDMO
t
t
PDDH
PDDH
HSYNC
VSYNC
t
PDMH
t
PDMH
t
t
PDDV
PDMV
11
S5K3A1EA
1/3” SXGA CMOS IMAGE SENSOR
MCLK
RSTN
t
WRST
t
WSTB
STBYN
system
reset
partial
complete
power down
power down
I2C Serial Interface Characteristics (1)
Characteristic
Clock frequency
Symbol
fSCL
Condition
Min
-
Typ
-
Max
400
Unit
kHz
-
tWH
tWL
Clock high pulse width
Clock low pulse width
Clock rise/fall time
SCL
SCL
0.6
1.3
-
-
-
-
-
-
-
-
µs
tR/tF
tDS
SCL, SDA
SDA to SCL
SCL to SDA
-
0.3
-
Data set-up time
0.1
-
tDH
Data hold time
0.9
(2)
tSTRS
tSTRH
tSTPS
tGSS
CPIN
CBUS
RPU
START condition setup time
START condition hold time
STOP condition setup time
STOP to new START gap
Capacitance for each pin
Capacitive bus load
Pull-up resistor
4
TMCLK
-
4
-
-
4
-
-
-
-
-
-
-
8
SCL, SDA
SCL, SDA
SCL, SDA to VDD
-
4
pF
-
200
10
1.5
kΩ
NOTES:
1. I2C is a proprietary Phillips interface bus.
2. TMCLK is the period of the master input clock, MCLK.
t
t
t
t
R
WL
WH
F
0.9V
DD
SCL
0.1V
DD
t
t
DS
STPS
t
t
DH
STRH
t
STRS
0.9V
SDA
DD
0.1V
DD
12
1/3 INCH SXGA CMOS IMAGE SENSOR
S5K3A1EA
PIN DESCRIPTION
Pin No
VDDD (6,25,48)
VDDIO (5)
I/O
Name
Function
)
For logical circuit (VDDL
Power Digital power supply
Power
For I/O circuit (VDDL
)
VSSD (19,26,47) Power
VSSIO (20) Power
0V (GND)
0V (GND)
For analog circuit (VDDH
)
VDDA(1,4,21,24, Power Analog power supply
28,29,37,44,45)
VSSA(2,3,22,23, Power
27,30,36,43,46)
0V (GND)
MCLK (7)
RSTN (40)
STBYN (39)
I
I
I
Master clock
Reset
Standby
Master clock pulse input for all timing generators.
Initializing all the device registers. (Active low)
Activating power saving mode.
( high=normal operation, low=power saving mode )
STRB (38)
I
Strobe
Triggering the integration start and stop when single
frame capture mode.
DATA0~DATA9
(8 ~ 17)
O
Image data output
10-bit image data outputs. When ADC resolution is
reduced, the unused lower bits are set to 0.
DCLK (18)
HSYNC (32)
O
O
Data clock
Horizontal sync clock
Image data output synchronizing pulse output.
Horizontal synchronizing pulse or data valid signal
output.
VSYNC (31)
SCL (41)
SDA (42)
O
I
I/O
Vertical sync clock
Serial interface clock
Serial interface data
Vertical synchronizing pulse or line valid signal output.
I2C serial interface clock input
I2C serial interface data bus
(external pull-up resistor required)
VREF (35)
TEST1 (33)
I/O
I
Reference voltage
Test input 1
For proper operation, the external capacitor larger than
0.1uF must be connected between VREF and VDDA.
Test input signal. Though it can be opened in normal
operation (internally pulled down), it is recommended to
ground the test pins.
TEST2 (34)
I
Test input 2
Test input signal. Though it can be opened in normal
operation (internally pulled down), it is recommended to
ground the test pins.
13
S5K3A1EA
1/3” SXGA CMOS IMAGE SENSOR
CONTROL REGISTERS
Address
(Hex)
Reset
Value
Bits
Mnemonic
Description
(Factory use only) CDS timing control
00h
01h
[7]
[6]
p2_r_con
bprm
Bad pixel replacement mode
0b: disabled (default), 1b: enabled
Color channel separation mode
[5]
ccsm
0b: not separated (default), 1b: separated
[4:2]
mcdiv
Main clock divider
000b: DCLK=MCLK(default), 001b: DCLK=MCLK÷2
010b: DCLK=MCLK÷4,
100b: DCLK=MCLK÷16,
111b: forbidden value
011b: DCLK=MCLK÷8
101b: DCLK=MCLK÷32
Electronic shutter mode
[1]
[0]
shutc
0b: disabled (default), 1b: enabled
ADC resolution
adcres
0b: 8-bit, 1b: 10-bit (default)
01h
00h
[7]
[6]
[5]
shut_err_cor
Not_use
mircv
Shutter error correction register
Vertical mirror control
0b: normal (default), 1b: mirrored
Horizontal mirror control
[4]
mirch
subsr
0b: normal (default), 1b: mirrored
Row sub-sampling mode
00b: disabled (default),
01b: 2X, 10b: 4X, 11b: 8X
[3:2]
Column sub-sampling mode
[1:0]
subsc
00b: disabled (default),
01b: 2X, 10b: 4X, 11b: 8X
Row start point for window of interest
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
00h
0Eh
00h
0Eh
04h
00h
05h
00h
80h
[2:0]
[7:0]
[2:0]
[7:0]
[2:0]
[7:0]
[2:0]
[7:0]
[7:0]
wrp_high
wrp_low
wcp_high
wcp_low
wrd_high
wrd_low
wcw_high
wcw_low
offsdef
wrp[10:0] = 14d(default)
Column start point for window of interest
wcp[10:0] = 14d(default)
Row depth for window of interest
wrd[10:0] = 1024d(default)
Column width for window of interest
wcw[10:0] = 1280d(default)
(Factory use only) Analog offset reference
offsdef[7:0] = 128d (default)
14
1/3 INCH SXGA CMOS IMAGE SENSOR
S5K3A1EA
Address
(Hex)
Reset
Value
Bits
Mnemonic
Description
Integration time in single frame capture mode
sint[15:0] = 1125d (default)
0Bh
0Ch
0Dh
0Eh
04h
65h
04h
65h
[7:0]
[7:0]
[7:0]
[7:0]
sint_high
sint_low
cintr_high
cintr_low
Row-step integration time in continuous frame
capture mode
cintr[15:0] = 1125d (default)
0Fh
10h
00h
00h
[7:0]
[7:0]
cintc_high
cintc_low
Column-step integration time in continuous frame
capture mode
cintc[15:0] = 0d (default)
HSYNC polarity
11h
00h
[7]
[6]
[5]
[4]
[3]
hspolar
hsdisp
0: active high (default), 1: active low
HSYNC display mode
0: sync mode (default), 1: data valid mode
VSYNC polarity
vspolar
0: active high (default), 1: active low
VSYNC display mode
vsdisp
0: sync mode (default), 1: data valid mode
global_mod
Single frame capture integration mode
Field shift shutter mode
Single frame capture integration mode
[2]
[1]
roll_mod
Rolling shutter mode
Single frame capture integration mode
simultaneous frame integration with mechanical
shutter
mech_mod
[0]
sfcen
vswd
Single frame capture mode enable
0b: disabled (default), 1b: enabled
VSYNC width
12h
01h
[7:0]
vswd[7:0] = 1d (default)
13h
14h
15h
16h
17h
00h
00h
00h
65h
20h
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
vsstrt_high
vsstrt_low
vblank_high
vblank_low
hswd
VSYNC start position
vsstrt[9:0] = 0d (default)
Vertical blank depth
vblank[12:0] = 101d (default)
HSYNC width
hswd[7:0] = 32d (default)
HSYNC start position
hsstrt[9:0] = 0d (default)
18h
19h
1Ah
1Bh
00h
00h
00h
8Eh
[7:0]
[7:0]
[7:0]
[7:0]
hsstrt_high
hsstrt_high
hblank_high
hblank_low
Horizontal blank depth
hblank[15:0] = 142d (default)
15
S5K3A1EA
1/3” SXGA CMOS IMAGE SENSOR
Description
Address
(Hex)
Reset
Value
Bits
[6:0]
[6:0]
Mnemonic
pgcr
1Ch
00h
Red channel gain
pgcr[6:0] = 0d (default)
1Dh
00h
pgcg1
Green(Red row) channel gain
or all channel gain (ccsm=0)
pgcg1[6:0] = 0d (default)
Green(Blue row) channel gain
pgcg2[6:0] = 0d (default)
Blue channel gain
1Eh
1Fh
00h
00h
[6:0]
[6:0]
pgcg2
pgcb
pgcb[6:0] = 0d (default)
20h
21h
0Fh
0Fh
[4:0]
[4:0]
sgg1
sgg2
1st quadrisectional global gain
sgg1[4:0] = 0F(default)
2nd quadrisectional global gain
sgg2[4:0] = 0F(default)
22h
23h
24h
25h
0Fh
0Fh
80h
80h
[4:0]
[4:0]
[7:0]
[7:0]
sgg3
sgg4
offsr
3rd quadrisectional global gain
sgg3[4:0] = 0F(default)
4th quadrisectional global gain
sgg4[4:0] = 0F(default)
Red channel analog offset
Offsr[7:0] = 128 (default)
offsg1
Green(Red row) channel analog offset or
all channel offset (ccsm=0) offsg1[7:0] = 128
(default)
26h
27h
28h
80h
80h
14h
[7:0]
[7:0]
offsg2
offsb
Green(Blue row) channel analog offset
offsg2[7:0] = 128 (default)
Blue channel analog offset
offsb[7:0] = 128 (default)
[7]
clipen
(Factory use only) Reset clipping enable
[6:0]
pthresh
Bad pixel threshold
pthresh[6:0] = 20d (default)
ADC offset (count delay register)
adcoffs[7:0] = 0d (default)
adcoffs
29h
00h
[7:0]
ADLC formula : Dfinal = D(n) + adcoffs
When adcoffs[7] is 1 , adc offset is +adcoffs[6:0],
else adc offset is - adcoffs[6:0]
16
1/3 INCH SXGA CMOS IMAGE SENSOR
S5K3A1EA
Address
(Hex)
Reset
Value
Bits
Mnemonic
Description
2Ah
40h
[7:5]
[4:0]
[7:0]
[7:0]
[7:6]
[5]
stbystrt
stbystp
rxstrt
blank
Not_use
id_inv
sck_inv
Not_use
i2ctest
(Factory use only) Stand-by start
(Factory use only) Stand-by stop
(Factory use only) Reset start control
Blank register for general purpose
2Bh
2Ch
2Dh
00h
00h
02h
(Factory use only) Line color inversion
(Factory use only) Column color inversion
[4]
[3:2]
[1]
(Factory use only) IIC test mode
[0]
nandtree
adlc_mod_d
(Factory use only) NAND tree test mode
2Eh
06h
[7]
Adlc mode always enable when this register is high.
0b: disabled (default), 1b: enabled
Adlc mode works when gain values are changed
[6]
[5]
adlc_mod_c
adlc_mod_b
0b: disabled (default), 1b: enabled
Adlc mode works when shutter values are changed
0b: disabled (default), 1b: enabled
Adlc mode works till adlc length value
[4]
adlc_mod_a
0b: disabled (default), 1b: enabled
Feedback gain value about ADLC
[3:2]
feedback_gain_B
00b : 0,
01b : 0.5(default),
10b : 0.75,
11b : 1
ADLC formula : Dfinal = D(n) + adcoffs
D(n) = A*(OB(n) + OB(n-1)) + B*D(n-1)
Feedback gain value about ADLC
[1:0]
feedback_gain_A
00b : 0,
01b : 0.5,
10b : 0.25(default), 11b : 0.125
17
S5K3A1EA
1/3” SXGA CMOS IMAGE SENSOR
Description
Address
(Hex)
Reset
Value
Bits
Mnemonic
dckout_en
2Fh
00h
[7]
DCK pad control
0b : output enable (default), 1b : stable value
I/O driver fan-out control register.
[6]
[5]
dfo
VSYNC always high at frame start point.
0b: disabled (default), 1b: enabled
fixvs
[4]
[3]
isp_sel
ob_sel
(Factory use only)
ADLC formula : D = D(n) + adcoff
D(n) = A*(OB(n) + OB(n-1)) + B*D(n-1)
0b : OB(n-1) = OB(n-1) (default)
1b : OB(n-1) = OB(n)
OB area selection
[2]
ob_area
0b:128*8 (default), 1b:512*2 (recommended)
[1:0]
adlc_length
ADLC function works only during this value when
adlc_mod_a enabled,
00b : 1 frame, 01b : 2 frames,
10b : 3 frames, 11b : 4 frames
30h
02h
[7:6]
[5]
Not_use
pwr_save2
(Factory use only)
rx & tx signals are enable only active area.
0b: disabled (default), 1b: enabled
[4]
[3]
pwr_save1
ggo_en
(Factory use only)
0b: disabled (default), 1b: enabled
(Factory use only)
0b: disabled (default), 1b: enabled
[2]
[1]
rsm_en
gbmod
(Factory use only)When this register is zero, H-sync
keeps same period in one frame.
Guardband mode
0b: disabled, 1b: enabled(default)
Stepless mode enable
[0]
stpless_mod
0b: disabled (default), 1b: enabled
Guardband start position
Guardband end position
Keep the same frame in zoom mode.
This register compensates remainder of frame.
31h
32h
33h
34h
35h
1Eh
32h
00h
00h
CCh
[7:0]
[7:0]
[5:0]
[7:0]
[7:4]
[3:0]
[7:4]
[3:0]
gb_start
gb_end
vs_postc_high
vs_postc_low
p12_stp
(Factory use only) CDS timing control
(Factory use only) CDS timing control
(Factory use only) CDS timing control
(Factory use only) CDS timing control
p11_stp
p2r_stp
p2_stp
36h
CCh
18
1/3 INCH SXGA CMOS IMAGE SENSOR
S5K3A1EA
Address
(Hex)
Reset
Value
Bits
Mnemonic
Description
37h
00h
[7:0]
holdline_high
holdline_low
Active output delay about its register value
38h
39h
3Ah
00h
0Ah
1Ah
[7:0]
[7:0]
[7]
vsend_ofset-high This register value is must larger than OB line.
Not use
(Factory use only)Add tg to reduce NIT.
[6]
tx_add
[5]
shutx_sel
(Factory use only)Enlarge shutter TX width to reduce
NIT.
[4]
cal_en
(Factory use only) calibration enable
[3:0]
cal_stp
(Factory use only) calibration signal control
19
S5K3A1EA
1/3” SXGA CMOS IMAGE SENSOR
OPERATION DESCRIPTION
1. Output Data Format
1-1. Main Clock Divider
All the data output and sync signals are synchronized to data clock output (DCLK). It is generated by dividing
the input main clock (MCLK). The dividing ratio is 1, 2, 4, 8, 16, and 32 according to main clock dividing control
register (mcdiv). For 10-bit ADC and SXGA resolution, dividing ratio of 1 is required. If dividing ratio of 1 is used,
the duty must be within 40% to 60%.
1-2. Synchronous Signal Output
The horizontal sync(HSYNC) and vertical sync(VSYNC) signals are also available. The sync pulse width,
polarity and position are programmable by control registers (ref. timing chart). When display mode is enabled, the
sync signal outputs indicate that the output data is valid (hsdisp=1) or the output rows are valid (vsdisp=1).
1-3. Window of Interest Control
Window of Interest (WOI) is defined as the pixel address range to be read out. The WOI can be assigned
anywhere on the pixel array. It is composed of four values: row start pointer(wrp), column start pointer(wcp), row
depth(wrd) and column width(wcw). Each value can be programmed by control registers. For convenience of
color signal processing, wcp is truncated to even numbers so that the starting data of each line is the red and
green column of Bayer pattern. Figure 1 refers to a pictorial representation of the WOI on the displayed pixel
image.
0
1307
0
(wcp,wrp)
wcw
Window Of Interest
1051
Figure 1. WOI definition.
1-4. Vertical Mirror and Horizontal Mirror Mode Control
The pixel data are read out from left to right in horizontal direction and from top to bottom in vertical direction
normally. By changing the mirror mode, the read-out sequence can be reversed and the resulting image can be
flipped like a mirror image. Pixel data are read out from right to left in horizontal mirror mode and from bottom to
top in vertical mirror mode. The horizontal and the vertical mirror mode can be programmed by Horizontal Mirror
Control Register (mirch) and Vertical Mirror Control Register (mircv).
1-5. Sub-sampling Control
The user can read out the pixel data in sub-sampling rate in both horizontal and vertical direction. Sub-sampling
can be done in four rates : full, 1/2, 1/4 and 1/8. The user controls the sub-sampling using the Sub-sampling
20
1/3 INCH SXGA CMOS IMAGE SENSOR
S5K3A1EA
Control Registers, subsr and subsc. The sub-sampling is performed only in the Bayer space. In Figure 2, the
Bayer space sub-sampling examples are shown.
R G R G R G R G R G R G R G R G
G B G B G B G B G B G B G B G B
R G R G R G R G R G R G R G R G
G B G B G B G B G B G B G B G B
R G R G R G R G R G R G R G R G
G B G B G B G B G B G B G B G B
R G R G R G R G R G R G R G R G
G B G B G B G B G B G B G B G B
R G R G R G R G R G R G R G R G
G B G B G B G B G B G B G B G B
R G R G R G R G R G R G R G R G
G B G B G B G B G B G B G B G B
R G R G R G R G R G R G R G R G
G B G B G B G B G B G B G B G B
R G R G R G R G R G R G R G R G
G B G B G B G B G B G B G B G B
subsr=01b, subsc=01b
R G R G R G R G R G R G R G R G
G B G B G B G B G B G B G B G B
R G R G R G R G R G R G R G R G
G B G B G B G B G B G B G B G B
R G R G R G R G R G R G R G R G
G B G B G B G B G B G B G B G B
R G R G R G R G R G R G R G R G
G B G B G B G B G B G B G B G B
R G R G R G R G R G R G R G R G
G B G B G B G B G B G B G B G B
R G R G R G R G R G R G R G R G
G B G B G B G B G B G B G B G B
R G R G R G R G R G R G R G R G
G B G B G B G B G B G B G B G B
R G R G R G R G R G R G R G R G
G B G B G B G B G B G B G B G B
subsr=00b, subsc=10b
Figure 2. Bayer Space Sub-Sampling Examples
1-6. Line Rate and Frame Rate Control (Virtual Frame)
The line rate and the frame rate can be changed by varying the size of virtual frame. The virtual frame’s width
and depth are controlled by effective WOI and blank depths. The effective WOI is scaled by the subsampling
factors from WOI set by register values. For CDS and ADC function, the virtual column width must be larger than
(adcres+1)*256/(2^mcdiv)+264, where adcres is the ADC resolution control register value. The horizontal and
vertical blanking time (hblank, vblank) should be over 60 and 4, respectively. The detailed restriction of h-blank
period is shown in table 1.
Table 1. Restriction of h-blank period (minimum 1H-period(dck)
minimum 1H-period(dck)
mcdiv[2:0]
adcres = 1
1412
836
adcres = 0
548
0
1
2
3
4
5
404
332
300
278
548
404
332
300
270
Setting procedure of hblank, vblank and vs_postc is as follows.
Frame cycle = ((wcw>>subsc) + hblank) x ((wrd>>subsr) + vblank) + vs_postc
vblank >= 4 (isp_sel=1)
vs_postc < 1H ( (wcw>>subsc) + hblank) )
1-7. Continuous Frame Capture Mode(CFCM) Integration Time Control (Electronic Shutter Control)
21
S5K3A1EA
1/3” SXGA CMOS IMAGE SENSOR
In CFCM operation, the integration time is controlled by shutter operation. The shutter operation is done when
shutter control register (shutc) is set to “1”. In shutter operation, the integration time is determined by the Row
Step Integration Time Control Register(cintr) and Column Step Integration Time Control Register(cintc)
In CFCM integration time control. There are two different modes. One is normal shutter mode. The other is
shutter TX wide mode to reduce nonlinear integration time. The effective integration time(EIT) formulas of each
mode are as follows.
1) normal mode (00h[2] = 1, 01h[7] = 1, 3Ah[5] = 1)
EIT = (cintr - 1) x ( (wcw>>subsc) + hblank ) + cintc + 145 (dck)
restriction of cintr?
1 <= cintr <= (wrd>>subsr) + vblankr –1
restriction of cintc?
0 <= cintc <= (wcw>>subsc) + hblank - 7
2) shutter TX wide mode (00h[2] = 1, 01h[7] = 0, 3Ah[5] = 1)
EIT = (cintr - 1) x ( (wcw>>subsc) + hblank ) + cintc + 145 (dck)
restriction of cintr?
1 <= cintr <= (wrd>>subsr) + vblankr - 1
restriction of cintr?
case of (1 <= cintr <= (wrd>>subsr) + vblankr - 2)
0 <= cintc <= (wcw>>subsc) + hblank - 7
case of (cintr = (wrd>>subsr) + vblankr - 1)
0 <= cintc <= (wcw>>subsc) + hblank - 195
1-8. Single Frame Capture Mode(SFCM) Integration Time Control
To capture a still image, SFCM can be set by Single Frame Capture Enable Register(sfcen). There are two
types of integration mode implemented. In the rolling shutter mode (sfcim=0), the integration time is controlled by
SFCM Integration Time Register (sint). The light integration period for each rows progresses with reading rows.
The integration time is expressed as :
Integration Time = sint * (1 line time)
In the mechanical shutter mode (sfcim=1), the integration time for all rows is the period during the external input
signal, STRB is active. After STRB goes to be inactive, the external mechanical shutter should shut off incident
lignt on image sensor and the data readout sequence starts.
2. Analog to Digital Converter ( ADC)
The image sensor has on-chip ADC. Two-channel column parallel ADC scheme is used for separated color
channel gain and offset control.
2-1. ADC resolution
The default value of ADC resolution is 10bit and can be changed to 8bit or 9bit by control the ADC Resolution
Control Register (adcres). Lowering ADC resolution reduces the required minimum line time. When the number of
effective output bits is reduced, upper n-bits of output ports are valid and lower bits always have values of “0”.
2-2. Correlated Double Sampling ( CDS )
The analog output signal of each pixel includes some temporal random noise caused by the pixel reset action
22
1/3 INCH SXGA CMOS IMAGE SENSOR
S5K3A1EA
and some fixed pattern noise by the in-pixel amplifier offset deviation. To eliminate those noise components, a
correlated double sampling(CDS) circuit is used before converting to digital. The output signal of each pixel is
sampled twice, once for the reset level and once for the actual signal level.
2-3. Programmable Gain and Offset Control
The user can controls the gain of individual color channel by the Programmable Gain
R G1 R G1
Control Registers (pgcr, pgcg1, pgcg2, pgcb) and offset by Offset Control Registers
G2 B G2 B
R G1 R G1
G2 B G2 B
(offsr, offsg1, offsg2, offsb). If the Color Channel Separation Mode is disabled
(ccsm=0), pgcg1 and offsg1 change the gains and offsets for all channels. As increasing
the gain control register, the ADC conversion input range decreases and the gain
increases as following equation and the relative channel gain is shown in figure 3
Channel Gain = 128 / (128 – Programmable Gain Control Register Value[6:0])
10
9
8
7
6
5
4
3
2
1
45
40
35
30
25
20
15
10
5
0
0
16
32
48
64
80
96
112 128
0
16
32
48
64
80
96
112 128
Programmable Gain Control
Programmable Gain Control
Figure 3. Relative Channel Gain
2-4. Quadrisectional Global Gain Control
The user can controls the global gain to change the gain for all color channels by the Global Gain Control
Registers (sgg1, sgg2, sgg3, sgg4). The global gain control register is composed of four register groups and
each register value decides the gain for each quarter section of output code level. At MCLK=12MHz and
ggo_en=L, the global gain is determined by the following formula.
Global Gain = (sgg[4:0]+1) / 16
23
S5K3A1EA
1/3” SXGA CMOS IMAGE SENSOR
10
5
2.2
2
1.8
1.6
1.4
1.2
1
0
-5
-10
-15
-20
-25
0.8
0.6
0.4
0.2
0
0
4
8
12
16
20
24
28
32
0
4
8
12
16
20
24
28
32
Programmable Gain Control
Programmable Gain Control
Figure 4. Relative Global Gain
The ADC gain is dependent on MCLK frequency (not on DCLK frequency) and ADC resolution. The default
global gain is set for typical MCLK frequency (12MHz) and 10-bit ADC. When the frequency and ADC resolution
is changed, the global gain should be changed to maintain the resulting gain over unity for assuring appropriate
ADC conversion range. The recommended minimum global gain setting depending on ggo_en and adcres is
shown in figure 5 and table 2.
30
28
26
24
22
20
18
16
14
12
10
10-bit ADC resolution
8
6
8-bit ADC resolution
4
2
0
0
2
4
6
8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48
MCLK Frequency (MHz)
Figure 5. Recommended Minimum Global Gain Control Value (ggo_en = L)
24
1/3 INCH SXGA CMOS IMAGE SENSOR
S5K3A1EA
Table 2. Recommended Minimum Global Gain Setting (adcres = H)
MCLK
[MHz]
6
ggo_en = L
ggo_en=H
Decimal
Hexadecimal
1F
1B
17
Decimal
Hexadecimal
31
27
23
21
19
17
15
14
13
12
11
11
10
10
9
9
8
8
7
7
7
7
6
6
6
6
6
5
5
5
5
5
5
5
4
-
-
-
-
-
-
-
-
-
-
-
-
7
8
9
15
13
11
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
30
31
32
33
34
35
36
37
38
39
0F
0E
0D
0C
0B
0B
0A
0A
09
09
08
08
07
07
07
07
06
06
06
06
06
31
29
27
25
23
22
21
20
19
18
17
16
15
15
14
14
13
13
13
13
12
11
11
11
10
10
10
10
9
1F
1D
1B
19
17
16
15
14
13
12
11
10
0F
0F
0E
0E
0D
0D
0C
0D
0C
0B
0B
0B
0A
0A
0A
0A
09
05
05
05
05
05
05
05
04
25
S5K3A1EA
1/3” SXGA CMOS IMAGE SENSOR
40
41
42
43
44
45
46
47
48
4
4
4
4
4
4
4
4
3
04
04
04
04
04
04
04
04
03
9
9
9
8
8
8
8
8
7
09
09
09
08
08
08
08
08
07
By appropriately programming these four register values, the different output resolution according to the
signal can be achieved and the intra-scene dynamic range can be increased by 16 times. In another application,
the sectional global gain control can be used as a rough gamma correction with four sectional linear
approximation curve as shown in Figure 6.
sgg1
sgg2
sgg3
sgg4
sgg1=11111b
sgg2=01111b
sgg3=00111b
sgg4=00011b
sgg1=01111b
sgg2=01111b
sgg3=01111b
sgg4=01111b
0
255
511
767
1023
ADC output code at 10-bit resolution
Figure 6. Quadrisectional Glabal Gain Control
26
1/3 INCH SXGA CMOS IMAGE SENSOR
S5K3A1EA
3. Post Processing
3-1. Dark Level Compensation
The dark level of Image sensor is defined as average output level without illumination. It includes pixel ouput
caused by leakage current of the photodiodes and ADC offset. To compensate the dark level, the output level of
optical black(OB) pixels can be a good reference value. When Auto Dark Level Compensation Register (dlcm) is
set, the image sensor detects the OB pixel level at the start of every frame and anglog-to-digital conversion range
is shifted to compensate the dark level for that frame. So, the resulting output data of that frame will be almost
zero under dark state. If user wants the dark level which is not zero, the ADC Offset Register (adcoffs) can be
used. The lower 7-bit value represent the offset value in outout code for compensation and the MSB is the sign to
define whether the offset is positive (adcoffs[7]=0) or negative (adcoffs[7]=1). When not in auto dark level
compensation mode, the adcoffs[7:0] act as a output code value to subtract the output image data. Please notify
that the all the 8-bit data are used for an offset value without sign bit.
ADLC formula : Dfinal = D(n) + adcoffs
D(n) = (feed_gain_a)*(OB(n) + OB(n-1)) + (feed_gain_b)*D(n-1)
3-2. Bad Pixel Replacement
When the Bad Pixel Replacement Register (bprm) is enabled, the image sensor check that the image data is
less or greater than horizontally neighboring pixels in same color channel by the preset threshold value (pthresh).
If satisfied, the output of the pixel is replaced by the averaged value of the neighboring two pixels. The detectable
defected pixels are rare and the bad pixel replacement action can remove defected image effectively. But it
reduces the line resolution in horizontal direction.
4. I2C Serial Interface
The I2C is an industry standard serial interface. The I2C contains a serial two-wire half duplex interface that
features bi-directional operation, master or slave mode. The general SDA and SCL are the bi-directional data and
clock pins, respectively. These pins are open-drain type ports and will require a pull-up resistor to VDD. The
image sensor operates in salve mode only and the SCL is input only. The I2C bus interface is composed of
following parts : START signal, 7-bit slave device address (0010001b) transmission followed by a read/write bit,
an acknowledgement signal from the slave, 8-bit data transfer followed by an acknowledgement signal and STOP
signal. The SDA bus line may only be changed while SCL is low. The data on the SDA bus line is valid on the
high-to-low transition of SCL.
27
S5K3A1EA
1/3” SXGA CMOS IMAGE SENSOR
SCL
SDA
D
7
D
6
D
D
D
D
D
D
“0” “0” “1” “0” “0” “0” “1”
I2C Bus Address
Ack
Start
Write Ack
I2C Register Address
SCL
SDA
D
D
6
D
D
D
D
D
D
7
Data to Write
Ack Stop
Figure 7. I2C Bus Write Cycle
SCL
SDA
D
7
D
6
D
D
D
D
D
D
D
“0” “0” “1” “0” “0” “0” “1”
I2C Bus Address
Start
SCL
Write Ack
Read Ack
I2C Register Address
Ack
D
7
D
6
D
D
D
D
D
SDA
“0” “0” “1” “0” “0” “0” “1”
I2C Bus Address
Re-Start
Data to be Read
Ack Stop
Figure 8. I2C Bus Read Cycle
28
1/3 INCH SXGA CMOS IMAGE SENSOR
S5K3A1EA
TIMING CHART
VERTICAL TIMING DIAGRAM
Continuous Frame Capture Mode
( Default Case )
1 frame = wrd + vblank ( 1125 rows )
VSYNC
vswd (1row)
10 rows = vsend_ofset
HSYNC
DATA
wrp(14th row)
wrd (1024 rows)
vblank (101 rows)
( Delayed Vertical Sync Case)
1 frame = wrd + vblank ( 1125 rows )
vswd
VSYNC
vsstrt
10 rows = vsend_ofset
HSYNC
DATA
wrp(14th row)
2rows
2rows
( Vertical Data Valid Mode Case) vsdisp=1
VSYNC
10 rows = vsend_ofset
HSYNC
(hsdisp=0)
HSYNC
(hsdisp=1)
DATA
wrp(14th row)
wrd (1024 rows)
vblank (101 rows)
29
S5K3A1EA
1/3” SXGA CMOS IMAGE SENSOR
VERTICAL TIMING DIAGRAM (continued)
( Short OB Line & Fixed Vertical Sync mode) isp_sel = 1& fix_vs = 1
1 frame = wrd + vblank ( 1125 rows )
Normal frame output
VSYNC
vswd (1row)
4 rows = vsend_ofset
HSYNC
DATA
wrp(14th row)
wrp(14th row)
wrd (1024 rows)
vblank (101 rows)
( Short OB Line & Normal Sync mode) isp_sel = 1, vsstrt = 1117d, vswd = 2d
1 frame = wrd + vblank ( 1125 rows )
DEFAULT
VSYNC
Normal frame output
vsstrt (1117 rows)
VSYNC
vswd (2rows)
4 rows = vsend_ofset
HSYNC
DATA
wrp(14th row)
wrd (1024 rows)
wrp(14th row)
vblank (101 rows)
30
1/3 INCH SXGA CMOS IMAGE SENSOR
S5K3A1EA
VERTICAL TIMING DIAGRAM (continued)
Single Frame Capture Mode
( Rolling Shutter Case, sfcen = 1 & roll_mod = 1 )
Normal frame output
STRB
Integration time for 1st readout row
Integration time for 2nd readout row
Integration time for 3rd readout row
Integration time for 4th readout row
sint X (1 row time) = integration time
VSYNC
HSYNC
DATA
wrp(14th row)
wrd (1024 rows)
( Mechanical Shutter Case, sfcen=1 & mech_mod = 1 )
Normal frame output
STRB
Integration time for all pixels
VSYNC
HSYNC
DATA
wrp(14th row)
wrd (1024 rows)
External
Mechanical
Shutter
Should be closed
Can be opened
31
S5K3A1EA
1/3” SXGA CMOS IMAGE SENSOR
( Global Shutter Case, sfcen=1 & global_mod = 1 )
Normal frame output
STRB
VSYNC
HSYNC
DATA
Integration time for all pixels
wrp(14th row)
wrd (1024 rows)
32
1/3 INCH SXGA CMOS IMAGE SENSOR
S5K3A1EA
HORIZONTAL TIMING DIAGRAM
( Default Case )
1 row = wcw + hblank ( 1422 columns )
VSYNC
HSYNC
hswd
10 DCLK
DCLK
DATA
wcp
( 14th column)
wcw ( 1280 columns )
1 row = wcw + hblank
hblank ( 142 columns )
( Delayed Horizontal Sync Case )
VSYNC
HSYNC
hswd
hsstrt
DCLK
DATA
wcw
( Horizontal Data Valid Mode Case ) hsdisp=1
VSYNC
HSYNC
DCLK
DATA
hblank
wcw
33
S5K3A1EA
1/3” SXGA CMOS IMAGE SENSOR
PACKAGE DIMENSION
48pin CLCC
14.22SQ +0.30/-0.13
1 48
(unit = mm)
6
43
7
42
TOP VIEW
Center of Image Area
(X=+0.088 ± 0.15, Y=0.002± 0.15
from package center)
Max. Chip Rotation = ±1.5 degree
Max. Chip Tilt = 0.05mm
18
31
19
30
Glass
0.55 ± 0.05
1.65 ± 0.18
SIDE VIEW
11.176 ± 0.13
1.016 ± 0.08
48
1
BOTTOM VIEW
R 0.15
4 Corners
0.51 ± 0.08
1.016 ± 0.18
34
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