S5K433CA01_技术文档

1/4 INCH VGA CMOS IMAGE SENSOR

S5K433CA, S5K433LA

(1/4” VGA CMOS Image Sensor)

Preliminary Specification

Revision 0.3.1

July 2002

1

S5K433CA, S5K433LA

1/4” VGA CMOS IMAGE SENSOR

DOCUMENT TITLE

1/4” Optical Size 640x480(VGA) 3.3V/2.8V CMOS Image Sensor

REVISION HISTORY

Revision No.

History

Draft Date

Remark

0.0

0.1

Initial Draft

Feb. 16, 2002 Preliminary

Feb. 21, 2002 Preliminary

Pin description error corrected (LHOLD polarity).

Timing chart added.

0.2

0.3

STRB signal polarity error corrected

SFCM timing diagram corrected

Operation description added.

Apr. 10, 2002 Preliminary

DC timing characteristics specification changed

AC timing characteristics specification changed

STRB and LHOLD pins are deleted

July 8, 2002

Preliminary

0.3.1

Minor description error corrected

July 15, 2002 Preliminary

2

1/4 INCH VGA CMOS IMAGE SENSOR

S5K433CA, S5K433LA

INTRODUCTION

The S5K433CA and S5K433LA are highly integrated single chip CMOS image sensors fabricated by

SAMSUNG 0.35mm CMOS image sensor process technology. It is developed for imaging application to realize

high-efficiency and low-power photo sensor. The sensor has 640 x 480 effective pixels with 1/4 inch optical

format. The sensor has on-chip 10-bit ADC blocks to digitize the pixel output and also on-chip CDS to reduce

Fixed Pattern Noise (FPN) drastically. With its few interface signals and 10-bit raw data directly connected to the

external devices, a camera system can be configured easily. S5K433CA is suitable for a camera system with

standard 3.3V logic operation and S5K433LA is suitable for low power camera module with 2.8V power supply.

FEATURES

— Process Technology: 0.35mm DPTM CMOS

— Optical Size: 1/4 inch

— Unit Pixel: 5.6 mm X 5.6 mm

— Effective Resolution: 640X480, VGA

— Line Progressive Read Out.

—

10-bit Raw Image Data Output

Programmable Exposure Time

Programmable Gain Control

Auto Dark Level Compensation

Windowing and Panning

Sub-Sampling (2X, 3X, 4X)

Standby-Mode for Power Saving

Maximum 36 Frame per Second

Bad Pixel Replacement

Single Power Supply Voltage: 3.3V or 2.8V

Package Type: 48-CLCC/PLCC

PRODUCTS

Product Code

Power Supply

3.3 V

Backend Process

Description

S5K433CA01

S5K433LA01

S5K433CA02

S5K433LA02

S5K433CA03

S5K433LA03

None

Monochrome image sensor

2.8 V

3.3 V

High sensitivity monochrome

Image sensor

On-chip micro lens

2.8 V

3.3 V

On-chip color filter

and micro lens

RGB color image sensor

2.8 V

3

S5K433CA, S5K433LA

1/4” VGA CMOS IMAGE SENSOR

BLOCK DIAGRAM

Main Clock

Divider

10-bit Column ADC

Odd Column CDS

MCLK

RSTN

DATA9

DATA8

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

STBYN

Timing

Generator

VSYNC

HSYNC

DCLK

Active Pixel

Sensor Array

Control

Registers

Even Column CDS

10-bit Column ADC

SCL

SDA

I²C Interface

Figure 1. Block Diagram

4

1/4 INCH VGA CMOS IMAGE SENSOR

S5K433CA, S5K433LA

PIXEL ARRAY

(TOP VIEW ON CHIP. DISPLAYED IMAGE WILL BE FLIPPED.)

Optical

Black Pixels

Active Pixels

8

6

Default Window of Interest

640X480

G B G B G B

R G R G R G

G B G B G B

R G R G R G

G B G B G B

R G R G R G

10

4

30

R G R G R G

G B G B G B

R G R G R G

G B G B G B

R G R G R G

G B G B G B

R G R G R G

G B G B G B

R G R G R G

(14,14) read out start point

6

8

(0,0)

Figure 2. Pixel Array Configuration

5

S5K433CA, S5K433LA

1/4” VGA CMOS IMAGE SENSOR

PIN CONFIGURATION

(NC)

7

42

41

40

39

38

37

36

35

34

33

32

31

STBYN

VBBA

VSSA

VDDA

VSSIO

(NC)

8

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

DATA8

(NC)

9

10

11

12

13

14

15

16

17

18

(NC)

VDDIO

VDDA

VSSA

VBBA

TEST2

First Readout Pixel

(NC)

Figure 3. Pin Configuration

6

1/4 INCH VGA CMOS IMAGE SENSOR

S5K433CA, S5K433LA

MAXIMUM ABSOLUTE LIMIT

Characteristic

Symbol

Value

Unit

Operating voltage

V_DD

(VDDD, VDDIO, VDDA supply

-0.3 to 3.8

V

relative to VSSD, VSSIO, VSSA, VBBA)

V_IN

-0.3 to V_DD+0.3 (Max. 3.8)

-20 to +60

Input voltage

T_OPR

T_STG

Operating temperature

Storage temperature

-40 to +125⁽¹⁾

°C

-40 to +85⁽²⁾

NOTES:

1. The maximum allowed storage temperature for S5K433C(L)X01.

2. The maximum allowed storage temperature for S5K433C(L)X02 and S5K433C(L)X03.

7

S5K433CA, S5K433LA

1/4” VGA CMOS IMAGE SENSOR

ELECTRICAL CHARACTERISTICS

DC Characteristics

(T_A= -20 to +60°C, C_L= 15pF)

Characteristics

Symbol

Condition

Min

Typ

Max

Unit

V_DD

Operating voltage

VDDD, VDDIO,

S5K433CA

S5K433LA

3.0

3.3

3.6

V

VDDA

2.55

2.8

-

3.05

-

Input voltage ⁽¹⁾

-

V_IH

V_IL

I_IL

0.8V_DD

0.2V_DD

0

-

V_IN= V_DDto V_SS

V_IN= V_DD

Input leakage

current⁽²⁾

-10

10

mA

I_ILD

Input leakage current

with pull-down⁽³⁾

10

30

60

V_OH

V_DD-0.05

2.4

High Level Output

voltage ⁽⁴⁾

I_OH= -1mA

-

V

I_OH= -4mA

S5K433CA

S5K433LA

1.9

-

V_OL

Low Level Output

voltage ⁽⁵⁾

I_OL= 1mA

I_OL= 4mA

V_OUT= V_DD

0.05

-

0.4

10

I_OZ

I_STB

I_DD

High-Z output leakage

current ⁽⁶⁾

mA

Supply current

STBYN=Low(Active)

All input clocks = Low

-

10

V_DD= 3.3V ⁽⁷⁾

-

27

18

-

mA

f_MCLK= 24.54MHz

0 lux illumination V_DD= 2.8V ⁽⁸⁾

NOTES:

1. Applied to MCLK, RSTN, STBYN, SCL, SDA, TEST1, TEST2 pin.

2. MCLK, RSTN, STBYN, SCL, SDA pin

3. TEST1, TEST2 pin

4. DCLK, HSYNC, VSYNC, DATA0 to DATA9 pin

5. DCLK, HSYNC, VSYNC, DATA0 to DATA9, SCL, SDA pin

6. SDA pin when in High-Z output state

7. S5K433CA

8. S5K433LA

8

1/4 INCH VGA CMOS IMAGE SENSOR

Imaging Characteristics

S5K433CA, S5K433LA

(Light source with 3200K of color temperature and IR cut filter (CM-500S, 1mm thickness) is used. Electrical

operating conditions follow the recommended typical values. The control registers are set to the default values. T_A

= 25°C if not specified.)

Characteristic

Saturation level⁽¹⁾

Symbol

Condition

Min

Typ

Max

Unit

V_SAT

S5K433CA

950

1000

-

mV

S5K433LA

S5K433(C,L)X01

S5K433(C,L)X02

S5K433(C,L)X03

T_A= 40°C

850

900

1500

4000

1500

9

-

Sensitivity⁽²⁾

Dark level⁽³⁾

S

-

mV/lux sec

-

V_DARK

18

mV/sec

dB

T_A= 60°C

-

50

100

Dynamic range⁽⁴⁾

DR

S/N

-

60

40

-

Signal to noise ratio⁽⁵⁾

Dark signal non-uniformity⁽⁶⁾

T_A= 60°C

DSNU

100

mV/sec

%

Photo response non-

uniformity⁽⁷⁾

PRNU

-

4

8

Vertical fixed pattern noise⁽⁸⁾

VFPN

HFPN

4

8

%

Horizontal fixed pattern noise⁽⁹⁾

NOTES:

1. Measured minimum output level at 100 lux illumination for exposure time 1/30 sec. 7X7 rank filter is applied for the whole

pixel area to eliminate the values from defective pixels.

2. Measured average output at 25% of saturation level illumination for exposure time 1/30 sec. Green channel output values

are used for color version.

3. Measured average output at zero illumination without any offset compensation for exposure time 1/30 sec.

4. 20 log (saturation level/ dark level rms noise excluding fixed pattern noise). 60dB is limited by 10-bit ADC.

5. 20 log (average output level/rms noise excluding fixed pattern noise) at 25% of saturation level illumination for exposure

time 1/30 sec.

6. Difference between maximum and minimum pixel output levels at zero illumination for exposure time 1/30 sec. 7X7

median filter is applied for the whole pixel area to eliminate the values from defective pixels.

7, Difference between maximum and minimum pixel output levels divided by average output level at 25% of saturation level

illumination for exposure time 1/30 sec. 7X7 median filter is applied for the whole pixel area to eliminate the values from

defective pixels.

8. For the column-averaged pixel output values, maximum relative deviation of values from 7-depth median filtered values for

neighboring 7 columns at 25% of saturation level illumination for exposure time 1/30 sec.

9. For the row-averaged pixel output values, maximum relative deviation of values from 7-depth median filtered values for

neighboring 7 columns at 25% of saturation level illumination for exposure time 1/30 sec.

9

S5K433CA, S5K433LA

AC Characteristics

1/4” VGA CMOS IMAGE SENSOR

(V_DD= 3.0V to 3.6V for S5K433CA, V_DD= 2.55V to 3.05V for S5K433LA, Ta = -20 to + 60^°C, C_L= 50pF)

Characteristic

Symbol

Condition

Min

3⁽¹⁾

Typ

Max

Unit

f_MCLK

Main input clock frequency

Duty = 50%

24.54

30

MHz

f_DCLK

t_PDMD

t_PDMO

t_PDMH

t_PDMV

t_PDDO

t_PDDH

t_PDDV

t_WRST

t_WSTB

Data output clock frequency

Propagation delay time

from main input clock

-

2

-

12.27

15

20

25

10

-

DCLK output

-

ns

DATA output

-

HSYNC output

VSYNC output

DATA output

-

Propagation delay time

from data output clock

-

HSYNC output

VSYNC output

RSTN=low(active)

STBYN=low(active)

-

(2)

Reset input pulse width

5

4

T_MCLK

Standby input pulse width

-

NOTES:

1. 8-bit ADC resolution case. If 10-bit ADC resolution is used, the frequency should be over 12MHz.

2. The period time of main input clock, MCLK.

0.5V

DD

MCLK

t

PDMD

DCLK

DATA

t

PDDO

t

PDMO

t

PDDH

HSYNC

t

PDMH

t

PDMH

t

PDDV

VSYNC

t

PDMV

10

1/4 INCH VGA CMOS IMAGE SENSOR

S5K433CA, S5K433LA

MCLK

t

WRST

RSTN

t

WSTB

STBYN

system

reset

partial

power down

complete

power down

2

I C Serial Interface Characteristics

Characteristic

Clock frequency

Symbol

f_SCK

t_WH

Condition

Min

Typ

Max

Unit

-

400

kHz

Clock high pulse width

Clock low pulse width

Clock rise/fall time

SCL

800

-

ns

t_WL

SCL

SCL, SDA

SDA to SCL

-

1000

-

t_R/t_F

t_DS

-

300

1200

4

300

Data set-up time

-

t_DH

Data hold time

t_STH

t_STS

t_GSS

C_PIN

C_BUS

R_PU

T_MCLK

START condition hold time

STOP condition setup time

STOP to new START gap

Capacitance for each pin

Capacitive bus load

Pull-up resistor

-

4

-

8

SCL, SDA

SCL, SDA to V_DD

-

4

pF

-

200

10

1.5

kW

t

R

WL

WH

F

0.9V

DD

SCL

SDA

0.1V

DD

t

DS

STPS

t

STRH

DH

t

STRS

0.9V

DD

0.1V

DD

11

S5K433CA, S5K433LA

1/4” VGA CMOS IMAGE SENSOR

PIN DESCRIPTION

Pin No

I/O

Name

Function

For logical circuit ( V_DD± 10% )

VDDD (24)

Power Digital power supply

VSSD (1)

Power

0V (GND)

For I/O circuit ( V_DD± 10% )

VDDIO (26, 35)

Power I/O power supply

VSSIO (47, 38)

Power

0V (GND)

For analog circuit ( V_DD± 10% )

VDDA

Power Analog power supply

(4, 21, 34, 39)

VSSA

(3, 22, 33, 40)

Power

0V (GND)

VBBA

For analog circuit bulk bias ( 0V)

(2, 23, 32, 41)

MCLK (46)

RSTN (43)

STBYN (42)

I

Master clock

Reset

Master clock pulse input for all timing generators.

Initializing all the device registers. (Active low)

Standby

Activating power saving mode.

( high=normal operation, low=power saving mode )

DATA0~DATA9

(6, 9~16, 19)

O

Image data output

10-bit image data outputs. When ADC resolution is

reduced, the unused lower bits are set to 0.

DCLK (27)

HSYNC (28)

VSYNC (29)

SCL (45)

O

I

Data clock

Image data output synchronizing pulse output.

Horizontal synchronizing pulse or data valid signal output.

Vertical synchronizing pulse or line valid signal output.

I2C serial interface clock input

Horizontal sync clock

Vertical sync clock

Serial interface clock

Serial interface data

SDA (44)

I/O

I2C serial interface data bus

(external pull-up resistor required)

TEST1 (30)

TEST2 (31)

I

Test input 1

Test input 2

Test input signal. Though it can be opened in normal

operation (internally pulled down), it is recommended to

ground the test pins.

Test input signal. Though it can be opened in normal

operation (internally pulled down), it is recommended to

ground the test pins.

12

1/4 INCH VGA CMOS IMAGE SENSOR

S5K433CA, S5K433LA

CONTROL REGISTERS

Address

(Hex)

Reset

Value

Bits

[5]

Mnemonic

bprm

Description

Bad pixel replacement mode

00h

02h

0b: disabled (default), 1b: enabled

Dark level compensation mode

0b: manual (default), 1b: auto

Color channel separation mode

0b: not separated (default), 1b: separated

Electronic shutter mode

[4]

dlcm

[3]

ccsm

[2]

shutc

0b: disabled (default), 1b: enabled

ADC resolution

[1:0]

[7]

adcres

mircv

00b: 8-bit, 01b: 9-bit, 10b: 10-bit (default)

Vertical mirror control

01h

10h

0b: normal (default), 1b: mirrored

[6]

mirch

mcdiv

Horizontal mirror control

0b: normal (default), 1b: mirrored

[5:4]

Main clock divider

00b: DCLK=MCLK, 01b: DCLK=MCLK¸ 2 (default)

10b: DCLK=MCLK¸ 4, 11b: DCLK=MCLK¸ 8

[3:2]

[1:0]

subsr

subsc

Row subsampling mode

00b: disabled (default),

01b: 2X, 10b: 3X, 11b: 4X

Column subsampling mode

00b: disabled (default),

01b: 2X, 10b: 3X, 11b: 4X

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

00h

0Eh

00h

0Eh

01h

E0h

02h

80h

[0]

wrp_high

wrp_low

wcp_high

wcp_low

wrd_high

wrd_low

wcw_high

wcw_low

Row start point for window of interest

wrp[8:0] = 14d(default)

[7:0]

[0]

Column start point for window of interest

wcp[8:0] = 14d(default)

[7:0]

[0]

Row depth for window of interest

wrd[8:0] = 480d(default)

[7:0]

[1:0]

[7:0]

Column width for window of interest

wcw[9:0] = 640d(default)

(Factory use only))

13

S5K433CA, S5K433LA

1/4” VGA CMOS IMAGE SENSOR

Address

(Hex)

Reset

Value

Bits

Mnemonic

Description

(factory use only)

0Bh

02h

[4]

[3]

[2:0]

[7:0]

[4:0]

[7:0]

0Ch

0Dh

0Eh

0Dh

01h

06h

cintr_high

cintr_low

Row-step integration time in continuous frame

capture mode

cintr[12:0] = 262d (default)

0Fh

10h

00h

[5:0]

[7:0]

cintc_high

cintc_low

Column-step integration time in continuous frame

capture mode

cintc[13:0] = 0d (default)

VSYNC width

11h

12h

01h

00h

[7:0]

[5]

vswd

vspolar

vsdisp

vswd[7:0] = 1d (default)

VSYNC polarity

0: active high (default), 1: active low

VSYNC display mode

[4]

0: sync mode (default), 1: data valid mode

VSYNC start position

[1:0]

[7:0]

[4:0]

[7:0]

vsstrt_high

vsstrt_low

vblank_high

vblank_low

hswd

vsstrt[9:0] = 0d (default)

13h

14h

15h

16h

00h

2Dh

20h

Vertical blank depth

vblank[12:0] = 45d (default)

HSYNC width

hswd[7:0] = 32d (default)

HSYNC polarity

17h

00h

[5]

[4]

hspolar

hsdisp

0: active high (default), 1: active low

HSYNC display mode

0: sync mode (default), 1: data valid mode

HSYNC start position

[1:0]

[7:0]

[5:0]

[7:0]

hsstart_high

hsstart_low

hblank_high

hblank_low

hsstrt[9:0] = 0d (default)

18h

19h

1Ah

00h

8Ch

Horizontal blank depth

hblank[13:0] = 140d (default)

14

1/4 INCH VGA CMOS IMAGE SENSOR

S5K433CA, S5K433LA

Address

(Hex)

Reset

Value

Bits

[3:0]

[7:4]

Mnemonic

sgg1

Description

1^stquadrisectional global gain

1Bh

77h

sgg1[3:0] = 7d (default)

2^ndquadrisectional global gain

sgg2[3:0] = 7d (default)

sgg2

1Ch

77h

[3:0]

[7:4]

sgg3

sgg4

3^rdquadrisectional global gain

sgg3[3:0] = 7d (default)

4^thquadrisectional global gain

sgg4[3:0] = 7d (default)

1Dh

1Eh

00h

[6:0]

pgcr

Red channel gain

pgcr[6:0] = 0d (default)

pgcg1

Green(Red row) channel gain

or all channel gain (ccsm=0)

pgcg1[6:0] = 0d (default)

1Fh

20h

21h

22h

00h

80h

[6:0]

[7:0]

pgcg2

pgcb

Green(Blue row) channel gain

pgcg2[6:0] = 0d (default)

Blue channel gain

pgcb[6:0] = 0d (default)

offsr

Red channel analog offset

offsr[7:0] = 128 (default)

Green(Red row) channel analog offset

offsg1

or all channel offset (ccsm=0)

offsg1[7:0] = 128 (default)

Green(Blue row) channel analog offset

offsg2[7:0] = 128 (default)

23h

24h

80h

[7:0]

offsg2

offsb

Blue channel analog offset

offsb[7:0] = 128 (default)

25h

26h

14h

00h

[6:0]

[7:0]

pthresh

adcoffs

Bad pixel threshold

pthresh[6:0] = 20d (default)

ADC offset

adcoffs[7:0] = 0d (default)

27h

01h

[5]

[4]

-

(Factory use only)

-

(Factory use only)

[3:0]

p12stp

(Factory use only) P12 start control

15

S5K433CA, S5K433LA

1/4” VGA CMOS IMAGE SENSOR

Address

(Hex)

Reset

Value

Bits

Mnemonic

Description

28h

40h

[7:5]

[4:0]

[7:0]

[5]

-

(Factory use only) -

-

29h

2Ah

2Bh

00h

02h

-

blank

Blank register for general purpose

(Factory use only)

-

[4]

(Factory use only)

[3]

(Factory use only)

[2]

(Factory use only)

[1]

(Factory use only)

[0]

(Factory use only)

16

1/4 INCH VGA CMOS IMAGE SENSOR

S5K433CA, S5K433LA

OPERATION DESCRIPTION

1. Output Data Format

1-1. Main Clock Divider

All the data output and sync signals are synchronized to data clock output (DCLK). It is generated by dividing the

input main clock (MCLK). The dividing ratio is 1, 2, 4, and 8 according to main clock dividing control register

(mcdiv). For 10-bit ADC and VGA resolution, dividing ratio of more than 2 is required. If ratio of 1 is used, the duty

must be within 40% to 60%.

1-2. Synchronous Signal Output

The horizontal sync(HSYNC) and vertical sync(VSYNC) signals are also available. The sync pulse width, polarity

and position are programmable by control registers (ref. timing chart). When display mode is enabled, the sync

signal outputs indicate that the output data is valid (hsdisp=1) or the output rows are valid (vsdisp=1).

1-3. Window of Interest Control

Window of Interest (WOI) is defined as the pixel address range to be read out. The WOI can be assigned

anywhere on the pixel array. It is composed of four values: row start pointer(wrp), column start pointer(wcp), row

depth(wrd) and column width(wcw). Each value can be programmed by control registers. For convenience of

color signal processing, wcp is truncated to even numbers so that the starting data of each line is the red and

green column of Bayer pattern. Figure 4 refers to a pictorial representation of the WOI on the displayed pixel

image.

0

687

0

(wcp,wrp)

wcw

Window Of Interest

507

Figure 4. WOI definition.

1-4. Vertical Mirror and Horizontal Mirror Mode Control

The pixel data are read out from left to right in horizontal direction and from top to bottom in vertical direction

normally. By changing the mirror mode, the read-out sequence can be reversed and the resulting image can be

flipped like a mirror image. Pixel data are read out from right to left in horizontal mirror mode and from bottom to

top in vertical mirror mode. The horizontal and the vertical mirror mode can programmed by Horizontal Mirror

Control Register (mirch) and Vertical Mirror Control Register (mircv).

1-5. Sub-sampling Control

The user can read out the pixel data in sub-sampling rate in both horizontal and vertical direction. Sub-sampling

can be done in four rates : full, 1/2, 1/3 and 1/4. The user controls the sub-sampling using the Sub-sampling

Control Registers, subsr and subsc. The sub-sampling is performed only in the Bayer space.

17

S5K433CA, S5K433LA

1/4” VGA CMOS IMAGE SENSOR

R G R G R G R G R G R G R G R G