S5D0127X01_技术文档

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

MULTISTANDARD VIDEO DECODER/SCALER

The S5D0127X01 converts analog NTSC, PAL or SECAM

video in composite, S-video, or component format to

digitized component video. Output data can be selected for

CCIR 601 or square pixel sample rates in either YCbCr or

RGB formats. The digital video can be scaled down in both

the horizontal and vertical directions. The S5D0127X01

also decodes Intercast, Teletext, Closed Caption, and WSS

data with a built-in bit data slicer. Digitized CVBS data can

be output directly during VBI for external processing.

100 PQFP

FEATURES

• Accepts NTSC-M/N/4.43, PAL-M/N/B/G/H/I/D/K/L and

SECAM formats with auto detection

• 6 analog inputs: 3 S-video, 6 composite, or 1 3-wire

YCbCr component video

ORDERING INFORMATION

• 2-line luma and chroma comb filters including adaptive

luma comb for NTSC

Device

Package

Temperature Range

• Programmable luma bandwidth, contrast, brightness,

and edge enhancement

S5D0127X01-

Q0R0

-20°~+70°C

100 PQFP

• Programmable chroma bandwidth, hue, and saturation

• High quality horizontal and vertical down scaler

• Intercast, Teletext and Closed Caption decoding with

built-in bit slicer

• Digital Video

• Direct output of digitized CVBS during VBI for Intercast

application

• Video Capture/Editing

• Analog square pixel or CCIR 601 sample rates

RELATED PRODUCTS

• Output in 4:4:4, 4:2:2, or 4:1:1 YCbCr component, or

24-bit or 16-bit RGB formats with dithering

• S5D0123X01

ENCODER

MULTISTANDARD

VIDEO

• YCbCr 4:2:2 output can be 8 or 16 bits wide with

embedded timing reference code support for 8-bit mode

• Simultaneous scaled and non-scaled digital output ports

outputs for 8-bit mode.

• Direct access to scaler via bi-directional digital port.

• Programmable Gamma correction table

• Programmable timing signals

• Industry standard IIC interface

APPLICATIONS

• Multimedia

Modified on May/04/2000

PAGE 1 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

BLOCK DIAGRAM

MULTIMEDIA VIDEO

Modified on May/04/2000

PAGE 2 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

PIN ASSIGNMENT - 100 PQFP

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

NCP

81

82

NCP

Y3

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

83 VSS

AY0

84

Y2

VDDA

Y1

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

AY1

Y0

VSS

AY2

C7

VDD3

VSS

VDDA

AC0

VSS

AC1

VSS

C6

S5D0127X01

VDDA

AC2

VSS

TEST

C5

C4

C3

C2

COMP2

VDDA

C1 34

C0 33

NCP

32

31

NCP

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

Modified on May/04/2000

PAGE 3 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

PIN DESCRIPTION

MULTIMEDIA VIDEO

Pin Name

INPUT

Pin #

Type

Description

AY0

AY1

AY2

84

86

88

I

1 of 6 analog CVBS or 1of 3 S-video Y inputs.

1 of 6 analog CVBS input or 1 of 3 S-video Y inputs or Y input for 3

wire component input

AC0

AC1

90

92

I

1 of 6 analog CVBS or 1 of 3 S-video C inputs.

1 of 6 analog CVBS or 1 of 3 S-video C inputs or Cb input for 3 wire

component input

AC2

94

I

1 of 6 analog CVBS or 1 of 3 S-video C inputs or Cr input for 3 wire

component input

XTALI

XTALO

RST

8

I

O

I

Pin 1 for an external crystal or TTL clock input.

Pin 2 for an external crystal.

7

10

Chip reset. Active low signal.

OUTPUT (All output pins can be selectively three-stated)

Y0 - Y7, C0 - C7 45-48,53-56,33-

39,44

O

Digital video outputs.

EXV0 - EXV7

16,27,28,61-63,

68,71

I/O Expanded digital video I/O port. Can be configured as an additional

8-bit output port (no scaling), or additional outputs of the main digital

output stream for 24 bit output modes, as an 8-bit input for direct

digital access of the down scaler.

HS1

26

76

23

I/O Programmable horizontal timing signal. One pulse every video line.

When the EXV port is configured as an input, this pin can be

programmed as an input.

HS2(IIC)

VS

I/O Programmable horizontal timing signal. One pulse every video line.

At power up, this pin needs a 10 kW pull-down resistor to configure

the chip to operate in IIC mode.

I/O Programmable vertical timing signal. When the EXV port is

configured as an input, this pin can be programmed as an input.

HAV

25

3

O

Programmable horizontal active video flag.

VAV(OENC0)

I/O Programmable vertical active video flag.

During reset, the pin is an input and the logic state of this pin is

latched into the OENC[0] register bit. Use a 10 kW resistor for pull-up

or pull-down.

EHAV

5

O

Valid pixel data flag. Polarity is programmable. Active when output

video data is valid.

Modified on May/04/2000

PAGE 4 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

PIN DESCRIPTION (Continued)

Pin Name

Pin #

Type

Description

EVAV(OENC1)

4

I/O Valid line flag. Polarity is programmable. Active when output video

line is valid. During reset, the pin is an input and the logic state of

this pin is latched into the OENC[1]register bit. Use a 10 kW resistor

for pull-up or pull-down.

ODD

PID

22

17

15

18

O

I

Odd field flag. Polarity is programmable. Active for fields 1 and 3.

PAL ID flag. High for phase alternating line.

OEN

CK

Digital video data, timing and clock output 3-state control.

I/O Pixel clock. In normal decoding mode, this is an output. When the

EXV port is used as an input, this can be programmed as an input

pixel clock.

CK2

21

73

O

Pixel output clock (rate is one half of CK) aligned to HAV signal.

CCDAT

Sliced VBI data output. Data can be from Closed Caption, Teletext,

Intercast, or WSS type encoded data.

CCEN

74

O

When high, this pin indicates that valid VBI data is being clocked out

at the CCDAT pin or at the digital video output.

MULTI-PURPOSE I/O PORTS AND TEST ENABLE

PORTA

58

24

57

I/O Multi-purpose I/O port.

SCH(PORTB)

TESTEN

I

When tied to VDD, the chip is put into the test mode. For normal use,

this pin should be connected to VSS.

TEST

96

I

When tied to VDD, the chip is put into the test mode. For normal use,

this pin should be connected to VSS.

REFERENCE AND COMPENSATION

VRT

77

78

97

I/O ADC VRT compensation (requires an external 0.1 mF capacitor

connected to VSS).

VRB

I/O ADC VRB compensation (requires an external 0.1 mF capacitor

connected to VSS).

COMP2

I/O Internal 1.3 V reference (requires an external 0.1 mF capacitor

connected to VSS).

HOST INTERFACE

SCLK

75

I

Serial clock for IIC host interface.

SDAT

72

I/O Serial data for IIC host interface.

AEX0 - AEX1

69 - 70

I

Device ID selection for IIC host interface.

Modified on May/04/2000

PAGE 5 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

PIN DESCRIPTION (Continued)

Pin Name

Pin #

Type

Description

POWER AND GROUND

VDD

20,59

PWR Digital power supply for output buffers. The voltage can be +5V or

3.3V depending on interface requirement.

VDD3

11,12,42,43,66, +3.3V Digital power supply for internal logic.

67

VDDA

VDDA1

VSS

85,89,93,98

9

+5V Analog power supply for ADC, AGC and reference circuits.

+5V Analog power supply for clock generation circuitry.

GND Common ground.

6,13,14,19,40,

41,60,64,65,83,

87,91,95

NC

NCP

1,2,29-32,49-52,

79-82,99,100

-

These pins are directly connected to the die substrate. If electrical

connect is desired (not required) only connection to VSS is allowed.

Modified on May/04/2000

PAGE 6 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

PIN CROSS REFERENCE: NUMERICAL ORDER BY PIN NUMBER

Pin #

1

Pin Name

NCP

Pin #

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

Pin Name

HS1

EXV1

EXV2

NCP

C0

Pin #

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

Pin Name

NCP

Pin #

Pin Name

HS2(IIC)

VRT

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

2

NCP

3

VAV(OENC0)

EVAV(OENC1)

EHAV

VSS

Y4

VRB

4

Y5

NCP

5

Y6

NCP

6

Y7

NCP

7

XTALO

XTALI

VDDA1

RST

TESTEN

PORTA

VDD

NCP

8

VSS

9

C1

AY0

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

C2

VSS

VDDA

AY1

VDD3

VSS

C3

EXV3

EXV4

EXV5

VSS

C4

VSS

C5

AY2

VSS

C6

VDDA

AC0

OEN

VSS

VDD3

C7

VSS

EXV0

VDD3

EXV6

AEX0

AEX1

EXV7

SDAT

CCDAT

CCEN

SCLK

VSS

PID

AC1

CK

VDDA

AC2

VSS

VDD

Y0

VSS

CK2

Y1

TEST

COMP2

VDDA

NCP

ODD

Y2

VS

Y3

SCH(PORTB)

HAV

NCP

Modified on May/04/2000

PAGE 7 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

1. FUNCTIONAL DESCRIPTION

1.1. VIDEO INPUT

The S5D0127X01 supports complete video decoding of many analog video standards. In addition, the chip can

support direct 8-bit YCbCr input for high quality video scaling and other processing.

1.1.1. Analog Video Input

Figure 1 shows the detailed block diagram of the analog front end. Up to six composite video sources, three

S-video sources, one 3-wire YCbCr component video source, or any combination can be selected. The allowed

inputs are selected using the INSEL[3:0] bits in the CMDB register. Table 1 lists all possible input selections. The

front end has two paths each containing an analog gain control, a clamping control, and an 8-bit ADC. Composite

video input uses only the luma path. S-video and analog component YCbCr inputs utilize both the luma and

chroma paths. The ADC digital data is used to calculate the correct gain and clamp values. The data is feedback to

the analog clamping and gain control. This architecture eliminates any offset and gain mismatch in the analog front

end.

OFFSET

LPF

AC0

AC1

To Chroma Processing

8 Bit ADC

AGC

AC2

VRT

VRB

COMP1

AY0

AY1

AY2

To Luma Processing

To Timing Generation

8 Bit ADC

AGC

LPF

8-bit

Digital

Input

GAIN

OFFSET

Figure 1. Analog Front End

The analog inputs must be AC coupled through an external 0.1 mF capacitor clamp. Due to the high sampling rate

of the ADC’s inside the S5D0127X01, most video sources will not require a low-pass filter for alias reduction. For

those video sources with harmonics above 13 MHz, a simple single order pole at 6 MHz will provide sufficient high

frequency signal reduction. This can be implemented with a 400 pF capacitor in parallel with the 75 W load.

Analog

Video

S5D0127X01

0.1 mF

75 W

Figure 2. Typical Analog Video Input

Modified on May/04/2000

PAGE 8 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

Table 1: Analog Video Input selections

INSEL[3:0](hex)

Selected Input(s)

Video Type

0

1

2

4

5

6

8

9

A

F

AY0

Composite

S-Video

AY1

AY2

AC0

AC1

AC2

AY0, AC0

AY1, AC1

S-Video

AY2, AC2

S-Video

AY2(Y), AC1(Cb), AC2(Cr)

YCbCr component video

1.1.2. Digital AGC Control

The AGC normally references to the ADC code difference between sync tip and back porch. Two sets of sync

tip-back porch ADC values are available for different AGC gain requirements: if AGCGN = 0, the sync tip locks to

code 2, and the back porch locks to code 70; when AGCGN = 1, the sync tip locks to 16, and the back porch locks

to code 70. Video signal with abnormal sync tip or very bright saturated colors may cause the ADC to limit the

maximum value. This situation can be corrected by enabling the AGCOVF bit in the CMDB register to force the

gain tracking loop to reduce AGC when maximum limiting conditions occur. The AGC may also be programmed to

freeze the AGC at the current value by setting the AGCFRZ bit in the CMDB register. Once the AGC is frozen, the

gain can be manually adjusted with the AGC register. The tracking time constant for the AGC can be controlled

with the AGC_LPG[1:0] bits in the TRACKB register. In addition, the AGC tracking time constant can be configured

as 2X faster during acquisition via the AGC_LKG.

1.1.3. Digital Video Input

The high quality digital video down scaler in the S5D0127X01 can be directly accessed via the EXV bi-directional

port. The S5D0127X01 accepts CCIR 656 compliant 8-bit YCbCr digital video input with embedded or external

timing. Video timing may also be generated by the S5D0127X01. Data path for 8-bit YCbCr input is shown in

Figure 3. Selection of analog video input or digital CCIR 656 data is with the INPSL[1:0] register bits. The

S5D0127X01 can operate in master or slave timing mode when the chip is programmed for digital video input.

1.1.4. Pixel Clock and Timing Mode Selection for Digital Video Input

Pixel clock and synchronization timing can be individually selected to either come from an external generator or be

generated internally. In addition, if synchronization is provided by an external source, the S5D0127X01 supports

embedded syncs as defined in CCIR 656, or TTL HS and VS inputs. Selection of pixel clock is via CKDIR bit in

Modified on May/04/2000

PAGE 9 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

CMDD register. Timing selection is through either SYNDIR or EAV bit.

HS1

VS

Timing

Control

Luma

Processing

To Luma Scaler

Y

C

EXV[7:0]

Data

Demux

Chroma

Processing

To Chroma Scaler

From Luma ADC

From Chroma ADC

Figure 3. 8-bit YCbCr Input Data Path

By using an external pixel clock, the reference clock input at XTALI is no longer required. Additional register bits

have to be programmed for different selections of pixel clock and timing, which are detailed in Table 2. The

following register/bit-settings are required for digital video input:

INSEL[3:0] = 8, 9, A, or F.

TSTCGN = 1.

DMCTL[1:0] = 2 or 3.

UGAIN = 238.

BRT = 34.

SAT = 229.

RGBH = UNIT = PED = 1.

Table 2: Digital Video Input Pixel Clock and Timing Selection

Embedded

Timing

Pixel Clock TTL Timing

Additional Register Programming

*1

*2

*3

CKDIR

SYNDIR

EAV

VMEN TSTGPH TSTGEN TSTGFR PIXSEL MNFMT

IFMT

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

3

1

3

1

0 if input

data is at

square

pixel

rate.

1 if input

is at

1

0 if input

is 50 Hz

video.

1 if input

is 60 Hz

video.

CCIR

601 rate.

*1

*2

*3

: CKDIR = 0 - CK is output and is internally generated. CKDIR = 1 - CK is input from an external source.

: SYNDIR = 0 - HS1 and VS are output. SYNDIR = 1 - HS1 and VS are inputs from external sources.

: EAV = 0 - chip will not sync to embedded timing. EAV = 1 - chip will sync to embedded timing.

Note: the combination X11 for CKDIR, SYNDIR, EAV is not valid.

Modified on May/04/2000

PAGE 10 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

When in digital input mode, all programmable timing registers (such as HAVB,HAVE, HS2B etc.) are still functional.

If HS1 and VS are programmed as inputs, the associated output timing controls such as HS1B,E will have no

effect. An example of horizontal timing for digital input is shown in Figure 4.

HS1

Programmable, when an

This HS1 location can also come

From a 656 SAV code

output - Any input phase

is acceptable

Constant to internal counter reference

EXV[7:0]

80 10 80 10 80 10 U₀Y₀V₀Y₁U₂Y₂V₂Y₃U₄Y₄V₄Y₅U₆Y₆V₆Y₇U_xY_xV_xY_xU_xY_xV_xY_xV_x

Data group delay through chip --

Y[7:0]

80 10 80 10 80 10 U₀Y₀V₀Y₁U₂Y₂V₂Y₃U₄Y₄V₄Y₅U₆Y₆V₆Y₇U_xY_xV_xY_xU_x

Y output for OFMT=2 is

shown, any 8 or 16 bit

output format is allowed.

Fully programmable HAVB location

based on internal counter

HAV -- fully programmable,

Defines location of first, last pixel

and defines Cb,Y,Cr data location

Fully programmable

HAVE location

HAV

CK

CK2

CK can be input or output

The CK2 output clock phasing

is aligned to the HAV leading

edge

Figure 4. Horizontal Timing for EXV Port as Digital Input

1.1.5. Additional Information for Analog Component Video Input

For the S5D0127X01 to correctly set the V component phase in analog component video input mode, PID (pin 17)

and PORTA (pin 58) need to be connected together. PORTA has to be configured as input (DIRA = 0) and

connected to the internal CBG signal (DATAA[2:0] = 3).

It is also recommended that external clamp circuit be used for Cb and Cr inputs (before the coupling caps) and the

internal chroma clamp be disabled (COFFENB = 1) due to slight Cb/Cr leakage.

Modified on May/04/2000

PAGE 11 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

1.2. VIDEO TRACKING AND TIMING GENERATION

When the S5D0127X01 is configured for analog video input, the chip tracks the video input and generates a

sampling clock that is line locked to the input video. The S5D0127X01 requires an external reference clock for

video tracking. This reference can be supplied via a crystal using the on chip crystal interface or any TTL

compatible source. These configurations are shown in Figure 5

1.2.1. Clock Input Timing Reference

The S5D0127X01 can use either a 24.576 MHz or a 26.8 MHz reference. However, it is recommended that the

24.576 MHz reference be used for CCIR 601 operation, and the 26.8 MHz reference be used for square pixel or

dual mode operation. Other specifications for the crystal are:

• Fundamental or third overtone

• Load capacitance of ~20 pF

• Series resistance of 40 W or less

• Frequency deviation of 50 ppm or less over operating temperature range

22 pF

8

7

8

7

24.576 MHz

TTL Clock

XTALI

S5D0127X01

XTALO

XTALI

S5D0127X01

XTALO

24.576 MHz

22 pF

N. C.

5.7 mH

Using a Clock

Optional for 3rd

harmonic crystal

Using a Crystal

391 pF

Figure 5. Standard Clock Configurations

1.2.2. The Sampling Clock

The sampling clock is generated by multiplying the line rate by N. This ensures that samples are aligned

horizontally, vertically and in time. The required N factor for the S5D0127X01 is based upon the field rate (60 Hz or

50 Hz) and the desired sampling rates (CCIR 601 or square pixel). Field rate can be automatically detected and

can be monitored with the FFRDET bit in the STAT register. Manual control of the field rate can be controlled with

the MNFMT and IFMT bits. The PIXSEL bit in register CMDA selects CCIR 601 or square pixel. Table 3 shows the

constants for the various combinations of input formats and output pixel rates.

Modified on May/04/2000

PAGE 12 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

Table 3: Timing for Different Pixel Rates

CCIR 601 Data Rates

Square Pixel Data Rates

Units

M

N,B,G,H,I,D,K,K1,L

M

N,B,G,H,I,D,K,K1,L

50

Field Rate

60

858

720

480

13.5

27

50

864

720

580

13.5

27

60

780

Hz

Pixels/Line (N)

Active Pixels/Line

Active Lines/Frame

Pixel Rate

944

768

Pixels

Lines

MHz

640

480

580

12.27

24.54

14.75

29.5

ADC Sampling Rate

MHz

The time constants for the pixel clock tracking loop can be adjusted with the HFSEL[1:0] bits.

In addition to providing the pixel clock, the S5D0127X01 also outputs various timing signals to indicate the

beginning of a line, a field, and for field and frame identification. All the timing and clock pins may be optionally put

into high impedance state. Three-state of these pins are software controlled and initial state of these pins at power

up is controlled via two configuration pins: 3 and 4.

The S5D0127X01 can generate all the video timing without video input. This enables the S5D0127X01 to be used

as a video timing generator for a system that contains both the S5D0127X01 for live video input and a MPEG

decoder which requires a video timing generator.

1.2.3. Horizontal Timing

The S5D0127X01 creates many internal timing signals aligned to the horizontal sync tip (mid-way of the falling

edge of horizontal sync, typically ADC code 36). These include locations of color burst (CBG, CBGW) used in

chrominance processing, back porch (BPG), and sync tip timing signals (SLICE, FS_PULSE) used for AGC and

clamp functions. SLICE is low whenever the input is below half way level of horizontal sync (typically ADC code

36). FS_PULSE is a single clock pulse coincide with the start of SLICE. One of these internal signals can be made

available at the PORTA or PORTB pin at any time.

The chip outputs two horizontal synchronization signals: HS1 and HS2. The start and stop locations for these

signals are fully programmable. Offset programmed to HSxB, HSxE, and HSxBE0 are added to the default edge

locations as shown in Table 4. Note that there are different modulo numbers for different input video standards and

output pixel rates.

Modified on May/04/2000

PAGE 13 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

Table 4: Horizontal Timing Signal Edge Locations (in # of CK)

60 Hz

Square Pixel

50 Hz

CCIR 601 Square Pixel

Description

Signal

CCIR 601

(modulo 1716) (modulo 1560) (modulo 1728) (modulo 1888)

Chip delay

120

72

120

72

120

72

120

72

Sync gate (1-CK pulse)

Back porch gate

SYG

BPG

[147 222]

222

[129 204]

204

[154 234]

234

[168 254]

254

Color burst gate (1-CK pulse)

Wide color burst gate

CBG

CBGW

FH2

[159 254]

42, 900

[147 233]

42, 822

[173 254]

42, 906

[186 277]

42, 986

Two pulses per line (1-CK each

pulse)

Default one pulse per line

Default horizontal cropping

HS1

HS2

HAV

[65 238]

[351 75]

[45 220]

[334 58]

[69 250]

[379 91]

[65 270]

[415 59]

An additional signal, HAV, is provided for horizontal video cropping. This signal has programmable polarity, start

and stop locations. Two 11-bit registers, HAVB and HAVE, are used to define the first and last pixel locations of the

horizontal portion of the cropped video. Numbers programmed into these registers are used as offset to the default

locations as shown in Table 4. Note that even though HAVB and HAVE have 1-CK resolution, the difference

between them should be maintained at multiple of 4 CKs for correct output.

Table 4 shows the default edge locations relative to the midway of the falling edge of the analog horizontal sync.

Note the numbers shown are in multiple of CK clocks. Figure 6 shows the approximate locations for the horizontal

timing signals. Horizontal timing signals used for scaling will be described in Section 1.6.1.

Modified on May/04/2000

PAGE 14 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

Analog video input

Digital video output

Active video

Blank

HAVB

Active video

Chip delay

HAVE

HAV

HSE

HSB

HS1,2

FS_PULSE

SLICE

SYG

BPG

CBG

CBGW

FH2

Figure 6. Approximate Locations for the Horizontal Timing Signals

1.2.4. Vertical Timing

The vertical timing signals include VS, VAV, ODD, SCH, and PID.

The VS is used for identifying the first line of video in the vertical position. The VS leading edge can be

programmed to either track the incoming video’s serration pulses or to be aligned to the beginning of the video line

or half way, as shown in Figure 36 and Figure 37. If VALIGN = 0, the VS leading edge is based on the output of an

internal low pass filter, and its location is dependent on the noise conditions of the video input. The trailing edge of

VS is locked to either the beginning of the video line or half way. The half way location relative to the beginning of

the video line changes depending on current input standard and output format. If VALIGN = 1, the leading edge of

the VS is aligned to the beginning of the video line or half way. The trailing edge is always aligned to the beginning

of the video line. The VSE bit in the CMDA register can be programmed to shorten the VS falling edge by one

horizontal line.

The VAV signal is used for vertical cropping. The start and stop lines for VAV are programmable through the VAVB

and VAVE registers, respectively.

The ODD signal signifies the current field number. When ODD is active, the current field is 1 or 3 (or 5 or 7 if in PAL

mode). The leading and trailing edges of ODD can be aligned to either the leading edge of VS (VALIGN = 1) or the

trailing edge of VS (VALIGN = 0). The signal may be used in conjunction with SCH and PID to exactly identify the

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current field. To distinguish between fields 1, 2 verse fields 3, 4 (or fields 1, 2, 3, 4 verse fields 5, 6, 7, 8 for PAL) the

phase of the color burst relative to the sync tip must be measured. That information is provided by the SCH pin.

The S5D0127X01 provides the output of a comparator that measures whether the current color burst phase

relative to the falling edge of the sync is greater or less than a predetermined constant. This constant is controlled

with SCHCMP[3:0]. The polarity of the SCH output pin depends on the current SCHCMP[3:0] value. The SCH

signal changes every video line. The SCH for line 260 is held for the entire vertical blanking period. By using the

SCH signal for the same line from each field, proper field identification can be determined. Figure 8 shows field

identification values for SCHCMP[3:0]=0. It is important to note that the SCH value is only valid for video signals

that have a constant sync tip to color burst relationship. This is not the case with consumer VCRs.

.

HS1

(default)

ODD FIELD and VALIGN = 0

VS

60 Hz - CCIR 601 = 885, Square = 708

50 Hz - CCIR 601 = 891, Square = 971

0, except 60 Hz Square = 2

ODD

EVEN FIELD or VALIGN = 1

27, except 60 Hz Square = 28

VS

0, except 60 Hz Square = 2

ODD

15, except 60 Hz Square = 14

VAV

HAV

default width for each input standard and output mode

60 Hz - 261

50 Hz - CCIR 601 = 273, Square = 341

EVAV

Note: Numbers shown are in CK. Active high polarities are used. Timing shown for VAV and EVAV are with qualifier off.

Figure 7. Short Term Vertical Timing

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VS

2

ODD

1

3

4

SCH

Truth Table

Note:

FIELD

ODD

SCH

3

4

L

1

2

L

ODD and SCH are

measured at the trailing

edge of VS.

H

L

H

Figure 8. NTSC Vertical Timing Signals

The PID pin is used to identify whether the current V-axis is inverted in PAL mode. This signal changes at the color

burst. By noting this value at the same line of each field, a determination of whether a field is from {1-4} or {5-8} can

be made. As with the SCH pin, the S5D0127X01 is designed to hold the line 260 PID measurement for the entire

vertical blank period. This allows easy sampling of the PID or current field identification.

The ODD, SCH and PID signals change at different times and more than once within the video fields. Proper data

for field identification is determined by latching all three signals at the trailing edge of VS. Figure 9 shows the VS,

ODD, SCH, and PID signals and their latched values for each of the 8 possible fields. Figure 10 is the line to line

timing diagram for these signals in PAL mode.

VS

2

6

8

3

4

5

1

7

ODD

SCH

PID

Truth Table

FIELD

ODD

SCH

PID

3

4

7

H

L

8

L

H

1

2

L

5

6

L

Note:

ODD, SCH and PID are

measured at the trailing

edge of VS (VALIGN = 0).

H

L

H

L

H

L

H

Figure 9. PAL Vertical Timing Signals

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SCH

ODD

PID

VS

HS

Figure 10. Line to Line VS, SCH and PID Timing (PAL input)

1.3. HORIZONTAL LUMA PROCESSING

A simplified block diagram for the luma path is shown in Figure 11.

Programmable

Low Pass Filter

Decimation

Filter

Horizontal

Peaking

Contrast

Control

Chroma

Trap

Brightness

Control

FROM ADC

HYLPF

HYBWR

HYBWI

CTRAP

CONT

HYPK

BRT

Figure 11. Horizontal Luma Processing Unit

1.3.1. Luminance DC Gain

The S5D0127X01 can accommodate CCIR 624 M/N/H/G standards, which fall into categories of -40 or -43 sync tip

and inclusion or exclusion of 7.5 setup. The S5D0127X01 can produce correct CCIR 601 luminance output levels

by controlling the gain and offset in the luminance path via PED. This register should be set for the appropriate

input standard. The programmable CONT and BRT registers provide the user with additional flexibility to create

non-standard luminance gain and offset values.

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Max Input

Peak White

Black Level

Blanking Level

Sync Tip

Figure 12. Luminance Signal

Luminance levels produced by the S5D0127X01 for different broadcast standards (assuming AGCGN=0, CONT=0

and BRT=0) are summarized in Table 5.

Table 5: Luminance Digital Level Code

M/N PED=1

M/N PED=0

B/G/H PED=1

Level ADC

Level

ADC

(IRE) (CVBS)

Level

ADC

(IRE) (CVBS)

Signal

Y[7:0]

(IRE) (CVBS)

Max Input

Peak White

Black

109

100

7.5

0

255

240

83

255

235

16

1

109

100

0

255

240

70

255

235

16

117

100

0

255

229

70

255

235

16

Blank

70

0

70

16

0

70

Sync

-40

2

1

-40

2

1

-43

2

KS0127B Data

Path Equation

C_Y= 1.37CVBS–80

C_Y= 1.288CVBS–74

C_Y= 1.37CVBS–100

When digital component output is desired in RGB mode, the RGBH register can be programmed to increase the

0-100% values from standard CCIR 601 levels to full range levels.The gain variations are shown in Table 6.

Table 6: RGB Output Range

RGB normal gain (RGBH=0)

RGB high gain (RGBH=1)

Signal

Cy

RGB (U,V=0)

Cy

RGB (U,V=0)

Peak White

Black

235

16

235

16

255

0

255

0

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For CCIR 601 digital video input (INPSL[1:0] = 1), register UNIT must be set to 1 to produce unit gain.

1.3.2. Horizontal Luma Frequency Shaping

The luma path contains many programmable filters for different purposes. The combination of these filters will give

different frequency characteristics.

The over sampled video data from the ADC pass through a decimation filter. The decimation filter has user

programmable bandwidth. Three registers are used to control the decimation filter characteristics and each is

designed for certain purposes. The HYBWI, when set to “1”, provides extra bandwidth for very high quality video

source. The HYBWR, when set to “1”, reduces the bandwidth so high frequency noise can be eliminated. The 3-bit

register HYLPF[2:0] provides the necessary bandwidth reduction for horizontal scaling. When all three registers

are programmed to “0”, the decimation filter has the bandwidth of the normal video. The S5D0127X01 provides the

option of bypassing the decimation filter. This option should be used only when the input video is band limited and

with low high frequency noise.

For composite video input, the notch filter can be enabled (CTRAP set to “1”) to extract the luminance. The notch

filter has different center frequencies for different input video format. User selectable peaking function is included

for edge enhancement. The notch filter should be bypassed for S-video and component video input, or if luma

comb filter is enabled.

The luminance filter characteristics have been designed to be very similar for all combinations of 60/50 Hz video

and CCIR 601/square pixel sampling rates. Figure 13 and Figure 14 show the output characteristics of the

luminance path with different filter combinations for the supported input standards and output pixel rates.

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Figure 13. Medium to High Frequency Luma Filter Characteristics (CTRAP=0)

Figure 14. Medium to Low Frequency Luma Filter Characteristics (NTSC, CTRAP=1)

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Figure 15. Medium to Low Frequency Luma Filter Characteristic (PAL, CTRAP=1)

Figure 16. Luma Filter Characteristic with Peaking On (NTSC, CTRAP=1)

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1.4. HORIZONTAL CHROMA PROCESSING

A simplified block diagram for the horizontal chroma processing unit is shown in Figure 17.

COS

SIN

Frequency

Tracking

RTCO

Control

CFTC

HUE, TSTCFR

Low

Pass

RTC_DTO

RTC_PID

V

Gain / PAL

Control

Saturation

Control

SECAM

Frequency

Differentiator

Color

Killer

CBW,FSEC

Low

Pass

UGAIN

VGAIN

FROM ADC

U

CKILL

CBW,FSEC

Auto

Offset

Control

Coring

Control

Detect

Gain

Tracking

SAT

UOFFST

VOFFST

CGTC

CORE

CKILL

TSTCGN

Figure 17. Horizontal Chroma Processing Unit

The S5D0127X01 supports chroma input in NTSC, PAL, SECAM and component formats. The color standard is

automatically detected and the various chroma processing blocks are enabled as required for the given chroma

standard. Details of the various chroma processing blocks follow.

1.4.1. IF Compensation

For improved chroma demodulation when the input video is from a mis-tuned IF source, an IF compensation filter

is included that has variable gain for the upper chroma side band. This is controlled by the CIFCMP[1:0] bits at

location CDEM. The frequency response is shown in Figure 18. For convenience, all plots are normalized to the

NTSC modulation frequency.

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Figure 18. Chroma IF Compensation Frequency Response

1.4.2. Demodulation Gain

The demodulation gain block is controlled by feedback from the gain tracking block. For NTSC and PAL type

inputs, the gain constant is derived from a programmable reference compared against the U component of the

input video. This reference is controlled by the SAT register. The default value “0” is the correct gain (saturation for

nominal output). For SECAM type input, the feedback is calculated such that proper frequency demodulation is

obtained. When external calibration is desired, the gain feed back loop can be “opened” by setting TSTCGN=1.

The SAT then controls bits 8 through 1 of a 10 bit multiplier.

For standard auto tracking applications, it is recommended that the SAT register be used as an end user saturation

control. This register is 2’s compliment.

1.4.3. Demodulation Low Pass Filter

The demodulation circuit also contains a programmable low pass filter and a coring function for noise reduction.

The chroma low pass filter frequency response for the demodulation circuit for the various video standards are

shown in Figure 19

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Figure 19. Chroma Low Pass Filter Frequency Response

1.4.4. SECAM Demodulation

SECAM processing includes a frequency differentiator, a Cloche and a de-emphasis filter. Frequency response for

the filters are shown in Figure 20 and Figure 21.

Figure 20. Cloche Filter Frequency Characteristic

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Figure 21. De-emphasis Filter Frequency Response

1.4.5. Additional Chroma Functions

S5D0127X01 has many built in auto detection circuits. These allow S5D0127X01 to track any type of video

standard input automatically.

For analog component video input, the demodulation function is not enabled. The low pass filter provides a group

delay for Cb and Cr alignment. This enables the two components to be sampled by one ADC.

An RTCO serial output is provided that encodes the current chroma and pixel frequency of the decoder. This

information can be used by an Encoder running off of the decoder clock to produce proper color output. The

horizontal position of the serial signal is controlled by the HS2 location. The phasing of the DTO and the Encoder

can be reset using the RTC_DTO bit. For PAL mode, the PID polarity can be controlled with the RTC_PID bit.

1.5. COMB FILTER

Comb filters provide superior Y/C separation for composite NTSC and PAL than simple chroma trap filter. The

S5D0127X01 contains on-chip separate 2-line stored luma and chroma comb filters. An internal signal COMB

controls for what lines the comb function is enabled. This signal is available through the PORTB pin. Combing is

part of the vertical processing which also includes vertical scaling, which is discussed in Section 1.6. A block

diagram for the vertical processing section is shown in Figure 22.

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Luma

Vertical

Scaler

Vertical

BW

Retention

Horizontal

Scaler

Y

Luma

Adaptive

Comb

Chroma

Vertical

Scaler

Horizontal

Scaler

Chroma

Sum

C

Chroma

Comb

Figure 22. Vertical Processing

1.5.1. Luma Comb Filter

The luma comb filter reduces high frequency chroma leakage into the luminance path. The S5D0127X01 uses

2-line stored luma data for combing. Filter coefficients for different video input standards are provided and can be

selected automatically based on the video input. Filter coefficients may also be set manually.

An optional active comb is employed for NTSC video. Selection of luma comb coefficients is based on line-to-line

chroma correlation.

Provision is made to disable luma comb for S-video, component, or digital video input. This is achieved by

programming the luma comb control register MNYCMB to “1”, and by choosing the value 3 or 4 for YCMBCO[2:0].

This will result either a 1-line or 2-line luma delay. Care must be exercised when disabling the luma comb so that

luma line delay matches the chroma path line delay.

Special filtering is applied to ensure that high vertical bandwidth is retained for the luma path.

1.5.2. Chroma Comb Filter

The chroma comb filter provides further color separation from the composite video. Filter coefficients can be

automatically selected based on the input video standard or manually set using NMCCMB and CCMBCO[2:0].

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1.6. SCALING

The S5D0127X01 includes a high quality down scaler. The video images can be down scaled in both horizontal

and vertical direction to an arbitrary size.

1.6.1. Horizontal Scaler

The horizontal scaler uses a 5-tap 32-phase interpolation filter for luma, and a 3-tap 8-phase interpolation filter for

chroma. Scaled pixel data are stored in an on-chip FIFO so they can be sent out in a continuous stream.

Horizontal scaling ratio is programmed via the 15-bit register HSCL. The timing signal EHAV is used to indicate

when scaled pixel data is available at the video output port. EHAV can be programmed so that it is active for every

line regardless of vertical cropping and scaling. Or it can be programmed to be active only for valid video lines. For

example, Figure 23 shows the timing for CIF output assuming HAV is programmed to be active for 720 pixels. The

HSCL register is programmed with the value 4000 (hex). The trailing edge of EHAV is either aligned with the trailing

edge of HAV if the total number of scaled pixels is even, or is one pixel clock earlier if the number is odd.

CK2

720

HAV

360

EHAV

-

Y₀

U₀

Y₃₅₆

U₃₅₆

Y₁

V₀

Y₂

U₂

Y₃

V₂

Y₃₅₇Y₃₅₈Y₃₅₉

V₃₅₆U₃₅₈V₃₅₈

Y[7:0]

C[7:0]

-

Figure 23. Horizontal Scaler Timing for CIF Output (CCIR 601 Pixel Rate)

Frequency response and group delay for the luma scaler are shown in Figure 24 and Figure 25, respectively. The

luma interpolation filter is designed to achieve relatively flat frequency response and minimal group delay up to the

normal video bandwidth. A flat full data path frequency response may be obtained with the help of the luma

peaking control register HYPK[1:0]. The high quality filter ensures minimal artifacts for any scaling ratio.

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Figure 24. Horizontal Luma Scaler Interpolation Filter Frequency Response

3

2.5

2

1.5

1

Figure 25. Horizontal Luma Scaler Interpolation Filter Group Delay

Because of the limited bandwidth of the chroma data, a simpler interpolation filter is used for the horizontal chroma

scaler. The frequency response and group delay for this filter are shown in Figure 26 and Figure 27, respectively.

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Figure 26. Horizontal Chroma Scaler Interpolation Filter Frequency Response

1.5

1.0

0.5

Figure 27. Horizontal Chroma Scaler Interpolation Filter Group Delay

1.6.2. Luma Vertical Scaler

Vertical luma scaling uses either a 3-tap or 5-tap 8-phase interpolation filter depending on the horizontal scaling

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ratio.

Vertical scaling ratio is programmed via the 14-bit register VSCL. A valid scaled line is indicated by the timing

signal EVAV being active. The EVAV can be programmed to be internally gated by the VAV signal so it can only be

valid within the vertically cropped region.

Luma horizontal scaling can use either a 3-tap or a 5-tap interpolation filter depending on the horizontal scaling

ration. If the scaled horizontal line has less than or equal to 384 pixels, the 5-tap luma interpolation filter can be

turned on by programming the VRT2X bit to a “1”. Otherwise, the VRT2X bit should be set to “0” and the 3-tap filter

be used.

The VYBW bit provides additional vertical bandwidth control for vertical scaling. Typically, when the vertical scaling

ratio is less than 1/2, this bit should be set to “1” to eliminate any aliasing effect.

Luma vertical scaler interpolation filter frequency response is shown in Figure 28.

Figure 28. Luma Vertical Scaler Interpolation Filter Frequency Response

In vertical scaling, the start of signal VAV controls the phase of the vertical scaler interpolation filter. If VAVB, VAVE,

VAVOD0, VAVEV0, and VSCL are programmed such that the vertical interpolation filter has the same phase and

scaling ratio as that of a memory controller (most memory controller has simple line dropping vertical scaling), it is

possible to interface the S5D0127X01 to the memory controller without using EVAV.

1.6.3. Chroma Vertical Scaling

Chroma vertical scaling uses different algorithms depending on video input standard and horizontal scaling ratio. If

horizontal scaling results in line with less than or equal to 384 pixels, and the VRT2X is set to a “1”, a 5-tap

interpolation filter will be used for all video inputs. Otherwise, for NTSC, a 3-tap interpolation filter will be used for

NTSC input, and decimation (line dropping without filtering) will be used for PAL and SECAM. Filter characteristics

for the 3-tap and 5-tap filters are shown in Figure 29.

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Figure 29. Chroma Vertical Scaler Interpolation Filter Frequency Response

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1.7. VBI DATA PROCESSING

The S5D0127X01 VBI data processing is very flexible in that it supports VBI data formats of:

• Closed Caption Line 21 Data Service (EIA-608)

• 525 line / 60Hz Teletext systems B,C,D (ITU-R BT.653-2)

• 625 line / 50Hz Teletext systems A,B,C,D (ITU-R BT.653-2)

• Copy Generation Management System (EIA/IS-702)

• Wide Screen Signalling (WSS ETS 300 294).

Note that the SMPTE data slicing is removed for the S5D0127X01 and replaced with the WSS / CGMS processing.

This data can be accessed from the part via four different methods:

• Enabling the “Raw un-processed 27MHz” Y ADC samples to be output for the appropriate lines in place of the

normal YUV data.

• Slicing the data (creating a clock and comparing the data to a threshold at the clock) and bursting this data out

on Y output.

• Reading the sliced data from two internal registers via the IIC bus.

• Via 2 external pins that output the sliced VBI data and the time at which the slice is valid.

A simplified block diagram for the VBI section is shown in Figure 30.

Normal

Decoded Y Data

MUX /

VBI

8

Y[7:0]

Format

From Y ADC

FRAME

ALIGNMENT

SLICER

TTFRAM

FIFO

VYFMT

VBINSRT

CCEN

ODD

MODE

CTRL

LOGIC

ODDEN

EVENEN

ODDOS

VBIL

CLOCK

GENERATOR

PIXSEL

IFMT

SECAM

CCDATA

Figure 30. VBI Decoder Block Diagram

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Table 7 lists all the video standards that the VBI data slicer supports. Some of these modes are auto detected

based on the current video input standard,

Table 7: Video Standards Supported by VBI Decoder

Value of Chip Detec- Required Values of Characteristics of the Stan-

tion Bits

Registers to enable

Standard

dard

Mode

Format

SECAM VBIL0-15 TT_SYS Data Rate

(MHz)

Number of

Bits (bytes)

60Hz Teletext system C

(NTSC / Intercast)

1

0

1

2

0

5.727272

272 (34)

344 (43)

304 (38)

50Hz Teletext system B

(PAL)

6.9375

50Hz Teletext system A

(SECAM)

6.203125

60Hz Teletext system B

50Hz Teletext system C

50Hz Teletext system D

60Hz Teletext system D

Closed Caption NTSC 601

CGMS (NTSC 60Hz)

WSS (PAL 50Hz)

0

1

2

1

3

1

2

5.727272

5.734375

5.6457875

5.727272

0.5035

280 (35)

272 (34)

280 (35)

16 (2)

0

1

3

0

1

3

N/A

1

N/A

0.447443

5.0000

20 (3)

0

84

Configuring the VBI processing consists of many different steps which are individually explained below.

1.7.1. Enabling the VBI Processor

The VBI processor can be enabled independently for the ODD or EVEN fields with the ODDEN and EVENEN bits.

Some VBI data is only present on line in 1 of the 2 fields, These independent field enables allow control of the total

VBI data output from the chip. These controls apply to all VBI Lines, Thus it is not possible to enable Closed

caption line 21 for the Even field and line 19 Teletext for both the odd and even field.

1.7.2. Selecting the Type of Output Data

As previously mentioned, there are 4 different ways the VBI data can be extracted. Three of these are selected as

shown in the table, the fourth method (CCEN and CCDAT pins) is always available if VBI processing is enabled.

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Table 8: VBI Data Output Mode (VBILn != 0)

VBCVBS

VBINSRT

Output Mode

0

The VBI data is available via the internal registers CCDAT1 and

CCDAT2. Only the last 2 extracted bytes are stored in these

registers. Thus, this mode is only useful for extraction of Closed

Caption data.

0

1

0

1

This mode enables output of the sliced VBI data.

This mode enables output of direct data from the ADC.

This mode is invalid.

The S5D0127X01 adds an additional output mode and flexibility to vary the modes from line to line. If VBCVBS=0

and VBINSRT=1 S5D0127X01 will output sliced data on enabled lines. By setting VBIMID to 1, any line for which

VBIL=3 will output raw ADC data instead of WSS or CGMS. This mode allows a mixture of sliced and raw data.

This can be used to output raw data from a teletext line and sliced data from a closed caption line.

1.7.3. Select Individual Lines Enabled for VBI Processing

The S5D0127X01 allows programmable selection of processing for the various video lines. For example

Teletext/Intercast data can be sliced for lines 14 - 17, and closed caption for line 21.

Each 2-bit register VBIL0 through VBIL15 defines how a specific VBI line is processed. As can be seen in Figure

36 for 60 Hz and Figure 37 for 50 Hz video, the following alignments exist:

Table 9: VBI Line(s) Selection

Line Number That the VBIL Processing command applies to

(Assuming ODDOS=1)

VBIL

number

Odd Field

60 Hz

Even Field

60 Hz

Odd Field

50 Hz

Even Field

50Hz

VBIL0

All Lines

Except 10-24 Except

273-287

All Lines

All lines

Except 7-21

All lines Except

320 - 334

VBIL1

VBIL2

VBIL3

VBIL4

VBIL5

VBIL6

VBIL7

VBIL8

VBIL9

VBIL10

VBIL11

VBIL12

VBIL13

VBIL14

VBIL15

9&10

11

272&273

6&7

8

319&320

321

274

275

12

9

322

13

276

10

323

14

277

11

324

15

278

12

325

16

279

13

326

17

280

14

327

18

281

15

328

19

282

16

329

20

283

17

330

21

284

18

331

22

285

19

332

23

286

20

333

24&25

287&288

21&22

334&335

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The ODDOS[1:0] bits allow offset between the odd and even fields. Thus VBIL9 can be lines 17,18 or 19 for ODD

fields while VBIL9 is still line 281 for EVEN fields. This extra controls account for variations of VBI data locations

from ODD and EVEN fields.

When Intercast or Teletext data is selected, an 8-bit user programmable register (TTFRAM) is provided for the

framing byte. The frame alignment processor uses this information to properly locate the first data bit on each line

1.7.4. Raw CVBS Data Output Format

When raw ADC data is selected as output in place of the normal YUV or RGB data. The following rules apply:

• For 656 type 8 bit outputs, The ADC data outputs with successive data points in place of the Cb, Y, Cr, Y data

stream.

• For 16 bit or 24 bit outputs, The ADC data is output on the Y[7:0] and C[7:0] output pins. At any CK2 clock 2

bytes of ADC data are output. The Y[7:0] bus represents data N while C[7:0] is data N+1.

• ADC data is only output during the region that HAV is active.

• All ADC outputs are limited to the range 1-254, thus a 0 or 255 value will not be output.

For the line selected mode described above using VBCVBS and VBIL, data is from the luma ADC only. If C ADC

data or the entire video line is required, configure OFMT bits.

1.7.5. Sliced Data Output Formats

While sliced data is available for many of the output formats, the target application is 656 output format. The

description of data format is limited to this mode. The S5D0127X01 allows this data to be output during active

video.

Figure 31 shows the timing diagram for VYFMT[1:0]=3.

Video input

HAV

CCEN -VBINSRT=0

CCEN -VBINSRT=1

10h

Y[7:0] -- VYFMT=3

VBINSRT=1

Zoom In - Random data

Y[7:0] -- VYFMT=3

VBINSRT=1

10h 10h 10h

85h

45h

10h

A4h

E4h

45h 2Dh

54h

10h 84h

23h

Figure 31. VBI Insertion Timing for VYFMT[1:0]=3

Digitized CVBS data can also be output on the video output port (except for output format 1, 5 and 7). CVBS is

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always digitized at the CK clock rate. CVBS data is available when HAV is active. Raw CVBS data is output in a

similar fashion as decoded video. For 8-bit output format, data is output at CK rate using the same 8-bit port as the

decoded video. For 16-bit and 24-bit output format, data is output at CK2 rate using Y and C ports. The sequence

of data output is CVBS on Y, and CVBS

on C (note that EXV port is not used in 24-bit format for outputting

2n

2n+1

raw CVBS data).

For Closed Caption data, two read-only registers, CCDAT1 and CCDAT2, are provided so the Closed Caption data

can be read via the host interface. The VBIFLG bit can be polled to see if data captured in the two registers can be

safely read.

1.8. COLOR SPACE CONVERTER

The color space converter processes the video data as YCbCr 4:4:4 when converting to RGB. A programmable

limiter (YCRANG) can be imposed on the Y/C data to limit the ranges. One can choose to limit the Y/C to 1 - 254,

or Y to 16 - 235 and C to 16 - 240.

When selected, YCbCr 4:4:4 is converted to 24 bit RGB according to the following equations:

R = C_Y+ 1.375C_R

G = C_Y– 0.703C_R– 0.328C_B

B = C_Y+ 1.734C_B

For 16-bit RGB output, truncation with dithering is used to convert the data from 24 bit to 16 bit.

1.9. GAMMA CORRECTION

The S5D0127X01 programmable gamma tables allows the customer to apply many different type of corrections.

These corrections can be a standard 2.2 factor for NTSC or 2.8 for PAL. These factors can be applied in the RGB

or YUV domains.

A basic standard gamma equation of

R = R'^2.2

when applied to the R, G, or B signals, generates the response shown as the upper curve below. It is the inverse of

the monitor response and thus compensates to produce a linear response.

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Gamma correction

Effective output

TV tube characteristic

Figure 32. RGB Gamma Correction

1.9.1. Programming the S5D0127X01

The previous response is easily programmed into the S5D0127X01 loading the 0, 8, 16, 24 etc. values into the

GAMMA0,1,2,3 locations. Thus every 8th value is stored. The S5D0127X01 will use linear interpolation to generate

the values between every 8th points. This is shown in the following figure.

Output

GAMMA7

GAMMA6

GAMMA5

GAMMA4

GAMMA3

GAMMAD2

GAMMA2

GAMMAD1

GAMMA1

GAMMAD0

GAMMA0

0

8

16 24 32 40 48 56 64

192 200 208 216 224 232 240 248

Input

Figure 33. Gamma LUT Programming

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For ease of design, the difference between adjacent points must also be loaded. The complete data values for the

previous gamma factor of 1/2.2 is shown in the table below.

Table 10: RGB Gamma LUT Values

GAMMA

program at index Offset+40h

GAMMAD

program at index Offset+60h

Offset

0

1

0

53

20

14

12

11

10

8

53

2

73

3

87

4

99

5

110

120

128

136

144

151

158

164

170

176

181

187

192

197

202

207

211

216

220

225

229

233

237

241

245

249

252

6

7

8

9

7

A

7

B

6

C

6

D

6

E

5

F

6

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

5

4

5

4

5

4

3

4

The flexibility of this architecture is shown in the following example. Here it is assumed that the S5D0127X01 is

operating in a YUV output mode but some form of Gamma correction is required. By converting the RGB gamma

correction function back to the YUV color space, the following function can be applied to the U and V signals for

improved color performance. This flexibility can be extended in software to produce many type of customer defined

transfer functions.

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Figure 34. Gamma Correction for Cb and Cr

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1.10. DIGITAL VIDEO OUTPUT

The S5D0127X01 can output digital video data in various formats, which are tabulated in Table 11. All 8-bit output

Table 11: Digital Video Output Format

Clock

CK2

CK

OFMT

0

1

4

5

6

7

2, 3

YCbCr

4:2:2

YCbCr RGB RGB RGB

4:4:4 565 888 888

Type

YCbCr 4:1:1

+1 +2

YCbCr 4:2:2

C0

2N

+1

4N

+3

N

Cb0

Cb1

Cb2

Cb3

N

B0

B1

B2

B3

B4

N

B0

B1

B2

B3

B4

N

B3

B4

B5

B6

B7

G2

G3

G4

4N

+1

+2

+3

Cb0 Cr0

Cb1 Cr1

Cb2 Cr2

Cb3 Cr3

C1

C2

C3

C4

Cb4 Cr4 Cr6 Cr4 Cr2 Cr0 Cb4

Cb5 Cr5 Cr7 Cr5 Cr3 Cr1 Cb5

Cb6 Cr6 Cb6 Cb4 Cb2 Cb0 Cb6

Cb7 Cr7 Cb7 Cb5 Cb3 Cb1 Cb7

C5

G0 B5

G1 B6

G2 B7

C6

C7

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

Y0

G3 G0 G5 Cb0 Y0

G4 G1 G6 Cb1 Y1

G5 G2 G7 Cb2 Y2

R0 G3 R3 Cb3 Y3

R1 G4 R4 Cb4 Y4

R2 G5 R5 Cb5 Y5

R3 G6 R6 Cb6 Y6

R4 G7 R7 Cb7 Y7

R0 B0

Cr0 Y0

Cr1 Y1

Cr2 Y2

Cr3 Y3

Cr4 Y4

Cr5 Y5

Cr6 Y6

Cr7 Y7

Y1

Y2

Y3

Y4

Y5

Y6

Y7

EXV0

EXV1

EXV2

EXV3

EXV4

EXV5

EXV6

EXV7

Cr0

Cr1

Cr2

Cr3

Cr4

Cr5

Cr6

Cr7

R1 B1

R2 B2

R3 G0

R4 G1

R5 R0

R6 R1

R7 R2

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formats use CK as pixel clock; the other formats use CK2 as pixel clock. The first pixel is always aligned to the

leading edge of the HAV signal.

1.10.1. Validation Code Insertion

S5D0127X01 inserts validation codes during inactive video (HAV is inactive), and invalid video (HAV is active but

EHAV is inactive) to assist in recognition of scaled data and VBI data. Table 12 lists the available codes, when they

are inserted, and related programming registers.

Table 12: Invalid and Unused Code Insertion

Code

Description

INVALY This user programmed code is inserted in the Y or G output stream in scaling operation when

HAV is active while EHAV is inactive. Insertion of this code is independent of the output

format. Related register is INVALY.

INVALU This user programmed code is inserted in the U or B output stream in scaling operation when

HAV is active while EHAV is inactive. Insertion of this code is independent of the output

format. Related register is INVALU.

INVALV This user programmed code is inserted in the V or R output stream in scaling operation when

HAV is active while EHAV is inactive. Insertion of this code is independent of the output

format. Related register is INVALV.

UNUSEY This user programmed code is inserted in the Y or G output stream when HAV is inactive and

no other reference code is inserted. Insertion of this code is independent of the output format.

Related register is UNUSEY.

UNUSEU This user programmed code is inserted in the U or B output stream when HAV is inactive and

no other reference code is inserted. Insertion of this code is independent of the output format.

Related register is UNUSEU.

UNUSEV This user programmed code is inserted in the V or R output stream when HAV is inactive and

no other reference code is inserted. Insertion of this code is independent of the output format.

Related register is UNUSEV.

An example timing diagram for some of the programmable modes is shown in Figure 35. In this diagram, The field

rate is 60 Hz, A CCIR 601 sampling rate has been selected thus giving 720 active pixels. The horizontal scaling

ratio has been selected for an output of 718 out of 720 pixels.

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Legend

Y₀

U₀

Luma Data with pixel number

Chroma (Cb) Data with pixel number

Chroma (Cr) Data with pixel number

V₀

Y_I

U_I

Programmable INVALY data (index 0x32)

Programmable INVALU data (index 0x33)

V_I

Programmable INVALV data (index 0x34)

Y_U

U_U

Programmable UNUSEY data (index 0x35)

Programmable UNUSEU data (index 0x36)

V_U

Programmable UNUSEV data (index 0x37)

Invalid data (During

Active Video but Scaling

Has made picture smaller

and right justified)

If Horizontal Scaling is

disabled, EHAV will be the same

as HAV and there will be no

Invalid data. For this Example,

Unused Data

the last Data would be

Y₇₁₉

HAV

EHAV

CK

CK2

OFMT=0 (16 bits @ 13.5 Mhz 4:2:2 - 601)

Y_U

Y_I

V_I

Y_I

U_I

Y_I

V_I

Y₀

U₀

Y₁

V₀

Y₂

U₂

Y₃

V₂

Y₀

Y₇₁₄

Y₇₁₅

Y_U

U_U

Y_U

V_U

Y[7:0]

C[7:0]

V_U

U_U

V_U

U_I

U₇₁₄

V₇₁₄

OFMT=2 (8 bits @ 27 Mhz 656 data no SAV EAV)

Y[7:0] V_UY_UU_UY_UV_UY_UU_IY_IV_IY_IU_IY_IV_IY_IU₀Y₀V₀Y₁U₂Y₂V₂Y₃Y₀Y₀U_xY_xV_xY_xU_UY_UV_U

OFMT= 3

SAV -- see Table 12 for details

EAV -- see table for details

Same Format as OFMT=2

A

B

C

D

A

B

C

D

OFMT=4 (24 bits @ 13.5 Mhz YUV 4:4:4)

Y[7:0]

Y_U

U_U

V_U

Y_U

U_U

V_U

Y_U

U_U

V_U

Y_I

U_I

V_I

Y_I

U_I

V_I

Y_I

U_I

V_I

Y_I

U_I

V_I

Y₀

U₀

V₀

Y₁

U₁

V₁

Y₂

U₂

V₂

Y₃

U₃

V₃

Y₀

Y_T714Y_Y715

U₇₁₄Y₇₁₅

V₇₁₄V₇₁₅

Y_U

C[7:0]

U_U

V_U

U_U

V_U

EXV[7:0]

V_0-

Figure 35. Horizontal Data Timing for Various Output Modes

1.10.2. 656 Op Codes

The S5D0127X01 supports timing synchronization through embedded (656) timing reference codes in the output

video data stream. This mode is available for output format 3 (OFMT[3:0] = 3). The 656 Op Codes follow the CCIR

656 standard. An optional set of 656 Op Codes can be enabled to identify VBI data using the TASKB bit.

The (A,B,C,D) inserted codes for 656 output modes are explained below. Locations in the data stream are shown

in Figure 35. The D’ data is substituted for the standard codes shown in column D if TASKB bit is set and the

current line is processing VBI data (sliced or raw ADC data format).

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Fields

1,3

60 Hz ODD FIELD

24

23

22

21

2

3

2

4

3

5

6

7

6

8

7

9

10

20

21

1

525

Analog

Input

525

524

4

5

8

9

10

20

1

Digital

output

VSE=0

VSE=1

VALIGN=0

VALIGN=1

VALIGN=0

VS

VSE=1

VSE=0

VSE=1

VS

VSE=1

ODD

VSE=0

VSE=1

VSE=0

VALIGN=1

ODD

EAV

SAV

656 SAV EAV Codes for VSE=0, VALIGN=1

Y[0..7]

9D80

F1EC F1EC F1EC B6AB B6AB B6AB B6AB B6AB B6AB 9D80 9D80 9D80 9D80

9D80

DAC7

TASK B VIP 656 SAV EAV Codes for VSE=0, VALIGN=1, VBIL12-VBIL1=1, TASKB=1

Y[0..7]

1380

F1EC F1EC F1EC B6AB B6AB B6AB B6AB B6AB B624 130E 130E 13 0E 13 80

9D80 9D80

15

13

DAC7

VBIL[N]

0

1

-

11

12

14

0

Fields

2,4

60 Hz EVEN FIELD

286

284

287

285

283

264

265 266

267

268

269

270 271 272

273

263

262

Analog

Input

285

283

286

284

263 264

265 266

267

268

269

270 271 272

273

Digital

Output

VSE=0

VALIGN=0

VALIGN=1

VS

VSE=1

VSE=0

VSE=1

VALIGN=0

VALIGN=1

VSE=1

ODD

VSE=0

VSE=1

EAV

SAV

656 SAV EAV Codes for VSE=0, VALIGN=1

DAC7 DAC7 DAC7

Y[0..7]

B6AB B6AB F1EC F1EC F1EC F1EC F1EC F1EC F1EC F1C7 DAC7 DAC7 DAC7

9D80

TASK B VIP 656 SAV EAV Codes for VSE=0, VALIGN=1, VBIL12-VBIL1=1, TASKB=1

B6AB B6AB F1EC F1EC F1EC F1EC F1EC F1EC F162 7F62 7F62 7F62 7F62

7FC7 DAC7 DAC7

15

Y[0..7]

9D80

0

1

-

11

12

13

14

0

VBIL[N]

Figure 36. Vertical Timing for 60 Hz Video

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Fields

1,3

50 Hz ODD FIELD

25

24

622

621

623

622

624

625

624

1

2

3

4

3

5

4

6

7

6

20

21

20

22

21

23

22

24

23

Analog

Input

623

625

1

2

5

7

Digital

Output

VS

VSE=0

VALIGN=0

VSE=1

VSE=0

VALIGN=1

VSE=0, ALT656=1

VSE=1

VSE=0, ALT656=0

VALIGN=0

ODD

VSE=0

VALIGN=1

VSE=1

EAV

SAV

656 SAV EAV Codes for VSE=0, VALIGN=1

Y[0..7]

9D

B6AB B6AB B6AB B6AB B6AB B6AB B6AB B6AB B6 AB 9D 80 9D 80

DAC7 DAC7 DAC7 F1EC F1EC

B6AB B6AB

TASK B VIP 656 SAV EAV Codes for VSE=0, VALIGN=1, ALT656=1, VBIL15-VBIL1=1, TASKB=1

Y[0..7]

DAC7 DAC7 DAC7 DAC7 DAC7 F1EC F1EC B6AB B6AB B6AB B6AB B624 130E 130E 130E 130E 13 80 9D 80

VBIL[N]

0

1

-

14

15

0

15

Fields

2,4

50 Hz EVEN FIELD

333 334 335

336

337

310 311

312 313

314 315

316

317 318 319

320

Analog

Input

310 311

312 313

314 315

316

317 318 319

320

333 334 335

336

Digital

Output

VALIGN=0

VSE=0

VS

VSE=0

VSE=1

VALIGN=1

VSE=0, ALT656=0

VSE=1

VSE=0, ALT656=1

VSE=0

ODD

VALIGN=0

VSE=-0

VALIGN=1

VSE=1

EAV

SAV

656 SAV EAV Codes for VSE=0, VALIGN=1

Y[0..7]

D

9D80 9D80 B6AB B6AB F1EC F1EC F1EC F1EC F1EC F1EC F1EC F1EC F1EC F1EC F1EC F1 EC DAC7 DAC7

TASK B VIP 656 SAV EAV Codes for VSE=0, VALIGN=1, ALT656=1, VBIL15-VBIL1=1, TASKB=1

Y[0..7]

9D80 9D80 B6AB B6AB F1EC F1EC F1EC F1EC F1EC F1EC F162 5449 5449 5449 5449 54 49 54 C7 DA C7

VBIL[N]

0

1

-

14

15

0

15

Figure 37. Vertical Timing For 50 Hz Video

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Table 13: 656 and TASKB 656 Op Codes

SAV / EAV Output Sequence --

Reference Output timing pic-

tures

Condition

656 FVH values

Field

Vertical

Horizontal

A

B

C

D

D’

F

V

H

Field 2

Field 1

Vertical Blank

Vertical Active

Vertical Blank

Vertical Active

End Active Video

FFh

00h

F1h

ECh

DAh

C7h

B6h

ABh

9Dh

80h

7Fh

62h

54h

49h

38h

24h

13h

0Eh

1

Start Active Video FFh

End Active Video FFh

Start Active Video FFh

End Active Video FFh

Start Active Video FFh

End Active Video FFh

Start Active Video FFh

1

0

1

0

1

0

1

0

1

0

1

0

1.10.3. 656 Op Code Vertical Transitions

The vertical transition locations of the various 656 Op Codes are shown in Figure 36 and Figure 37. Note that for

proper transition locations of the SAV and EAV Op Codes VSE=0 and VALIGN=1.

1.11. HOST INTERFACE

The S5D0127X01 supports the IIC serial interface for programming the chip registers.

1.11.1. IIC Interface

The two wire interface consists of the SCLK and SDAT signals. Data can be written to or read from the

S5D0127X01. For both read and write, each byte is transferred MSB first, and the data bit is valid when the SCLK

is high.

To write to the slave device, the host initiates a transfer cycle with a START signal. The START signal is HIGH to

LOW transition on the SDAT while the SCLK is high. The host then sends a byte consisting of the 7-bit slave device

ID and a 0 in the R/W bit. The arrangement for the slave device ID and the R/W bit is depicted in Figure 38. AEX1

and AEX0 are configuration pins used to configure the S5D0127X01 to use one of the four addresses. Up to four

S5D0127X01’s can be used in one system each with a unique address.

msb

1

lsb

1

0

1

AEX1

AEX0

R/W

slave device ID

Figure 38. IIC Slave Device ID and R/W Byte

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The second byte the host sends is the base register index. The host then sends the data. The S5D0127X01

increments the index automatically after each byte of data is sent. Therefore, the host can write multiple bytes to

the slave if they are in sequential order. The host completes the transfer cycle with a STOP signal which is a LOW

to HIGH transition when the SCLK is high.

Each byte transfer consists of 9 clocks. When writing to the S5D0127X01, an acknowledge signal is asserted by

the salve device during the 9th clock.

SCLK

data

device ID

index

data

SDAT

STOP

ACK

START

ACK

Figure 39. IIC Data Write

A read cycle takes two START-STOP phases. The first phase is a write to the index register. The second phase is

the read from the data register.

The host initiates the first phase by sending the START signal. It then sends the slave device ID along with a 0 in

the R/W position. The index is then sent followed by the STOP signal.

The second phase also starts with the START signal. It then sends the slave device ID but with a 1 in the R/W

position to indicate data is to be read from the slave device. The host uses the SCLK to shift data out from the

S5D0127X01. A typical second phase in a read transaction is depicted in Figure 40. Auto index increment is

supported in Read mode.

SCLK

index

device ID

SDAT

STOP

START

ACK

SCLK

SDAT

data

device ID

STOP

START

NACK

Figure 40. IIC Data Read

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2. CONTROL REGISTER DESCRIPTION

This section contains information concerning the programmable control registers. Table 14 provides the default

power up values for each index, and a bit map for each register. The following pages describe each register in

detail and the possible programing values (an * indicates the power-on default). Gamma correction registers are

write only. When the index register points to any of the Gamma correction register, the Gamma look-up table is put

into a program mode. Normal operation resumes when the index is outside the range from 0x40 to 0xFF.

Table 14: Register Summary

Bit Map

Index Mnemonic Default

7

6

5

4

3

2

1

0

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

STAT

RO

CHIPID VBIFLG NOVID FFRDET PALDET CDET

POWDN VSE HFSEL[1:0] XT24 PIXSEL MNFMT

AGCGN VALIGN AGCOVF AGCFRZ

HLOCK CLOCK

CMDA

CMDB

CMDC

CMDD

HAVB

2C

IFMT

20

INSEL[3:0]

00

VMEN TSTGE1

0

TSTGPK TSTGPH

INPSL[1:0]

HAVB[7:0]

HAVE[7:0]

HS1B[8:1]

HS1E[8:1]

HS2B[8:1]

HS2E[8:1]

AGC[7:0]

TSTGFR[1:0]

TSTGEN

00

EAV

0

CKDIR

SYNDIR Y1MHZ GPPORT

00

HAVE

00

HS1B

00

HS1E

00

HS2B

00

HS2E

00

AGC

50

HXTRA

CDEM

PORTAB

LUMA

CON

00

HAVB[10:8]

FSEC

HAVE[10:8]

CIFCMP[1:0]

DIRA

HS1BE0 HS2BE0

00

OUTHIZ

DIRB

0

00

DATAB[2:0]

RGBH

DATAA[2:0]

00

UNIT

PED

CONT[7:0]

BRT[7:0]

CBW

HYBWR CTRAP

HYPK[1:0]

00

BRT

00

CHROMA

CHROMB

DEMOD

SAT

08

ACCFRZ PALM

PALN

CORE[1:0]

CKILL[1:0]

00

CDLY[3:0]

FSCDET SECDET CDMLPF CTRACK

SAT[7:0]

HUE[7:0]

VRT2X

HYBWI HYDEC

SCHCMP[3:0]

00

MNFSC[1:0]

MNSECAM[1:0]

00

HUE

00

VERTIA

VERTIB

VERTIC

HSCLL

HSCLH

VSCLL

VSCLH

OFMTA

OFMTB

00 MNYCMB

YCMBCO[2:0]

HYLPF[2:0]

CCMBCO[2:0]

HSCL[6:0]

VCTRL[2:0]

VSCLEN[1:0]

00

0

03 MNCCMB

ACMBEN VYBW EVAVEV EVAVOD

CMBMOD

00

FC

FF

HSCL[14:7]

VSCL[5:0]

VSCL[13:6]

OENC[1:0]

EVAND[1:0] EVHS1 EVHAV EVEHAV EVAVG EVANDL

ACMBCO ACMBRE

-

GAMEN[1:0]

VSVAV

OFMT[3:0]

00

Modified on May/04/2000

PAGE 48 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

Table 14: Register Summary

Bit Map

Index Mnemonic Default

7

6

5

4

3

2

1

0

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x30

0x31

0x32

0x33

0x34

0x35

0x36

0x37

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

0x40-5F

0x60-7F

0xC0-DF

0xE0-FF

VBICTL

CCDAT1

CCDAT2

VBIL30

00

RO

00

33

00

23

82

00

10

80

10

80

00

VBCVBS

VYFMT[1:0]

VBINSRT ODDEN EVENEN

ODDOS[1:0]

b0

b1

b2

b3

b4

b5

b6

P1

P2

VBIL3

VBIL2

VBIL6

VBIL1

VBIL5

VBIL9

VBIL13

VBIL0

VBIL4

VBIL8

VBIL12

VBIL74

VBIL7

VBIL11

VBIL15

VBIL118

VBIL1512

TTFRAM

TESTA

VBIL10

VBIL14

TTFRAM[7:0]

0

UVOFFH

UVOFFL

UGAIN

TSTCLC TSTCGN

TSTCFR

UOFFST[5:4]

VOFFST[5:4]

UOFFST[3:0]

VOFFST[3:0]

UGAIN[7:0]

VGAIN

VGAIN[7:0]

VAVB

VAVB[6:1]

VAVOD0 VAVEV0

CFTC[1:0]

VAVE

VAVE[8:1]

CTRACK

POLCTL

REFCOD

INVALY

INVALU

INVALV

UNUSEY

UNUSEU

UNUSEV

EXCTRL

TRACKA

VBICTLB

TRACKB

RTC

0

VSPL

0

DMCTL[1:0]

ODDPL HAVPL EHAVPL HS2PL

0 0

CGTC[1:0]

EVAVPL

YCRANG

VAVPL

0

HS1PL

0

INVALY[7:0]

INVALU[7:0]

INVALV[7:0]

UNUSEY[7:0]

UNUSEU[7:0]

UNUSEV[7:0]

0

ENINCST

MAC_DET

0

-

AUCPWD

0

CLEVEL

STCTRL

VCR_DET VCR_LEV[1:0] ATCTRAP VCTRAP AGCLSB

YOFFENB COFFENB

00 VBISWAP

TT_SYS[1:0]

VBIMID NEW_CC CC_OVFL

AGC_LPG[1:0]

AGC_LKG

0

00

09

00

-

ALT656 VBI_PH VBI_FR PH_CTRL VNOISCT

RTC_DTO RTC_PID

0

TDMOD

0

CMDE

ODFST VSALG

TR_MS NOVIDC

CTRAPFSC

HCORE[1:0]

CHIPREVID

VSDEC[5:0]

VSDEL

CMDF

VIPMODE EVAVY UVDLEN UVDLSL REGUD TASKB

GAMMA0[7:0] - GAMMA31[7:0]

CBWI

GAMMA

GAMMAD

GAMUV

GAMUVD

-

GAMMAD0[5:0] - GAMMAD31[5:0]

GAMUV0[7:0] - GAMUV31[7:0]

GAMUVD0[5:0] - GAMUVD31[5:0]

-

Modified on May/04/2000

PAGE 49 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

Read Only Status Bits

Index

00h

Mnemonic

STAT

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

CHIPID

VBIFLG

NOVID

FFRDET PALDET

CDET

HLOCK

CLOCK

HLOCK

CDET

Status for color lock.

0

1

Not locked.

Color lock achieved.

Status for current line tracking mode.

0

1

Chip is in initial tracking mode.

Chip is in steady state tracking mode.

Status for detection of color.

0

1

No color signal is detected.

Color signal is detected.

PALDET

Status for current detected color format. Information contained in this bit is valid only if

CLOCK is 1.

0

1

NTSC color format.

PAL color format.

FFRDET

NOVID

Status for current detected field frequency.

0

1

50 Hz field frequency, i.e. N,B,G,H,I,D,K,K1,L system.

60 Hz field frequency, i.e. M system.

Video detect flag. This bit should not be used for detecting the presence of a TV channel

from the output of a TV tuner.

0

1

Sync has been detected for the last 32 lines.

No sync has been detected.

VBIFLG

CHIPID

Vertical blanking interval flag.

0

1

Video is in active region.

Video is in vertical blanking region.

Chip version ID. Please refer to the CHIPREVID bits for additional information

0

1

KS0122S.

S5D0124D01.

Modified on May/04/2000

PAGE 50 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

Control Register A

bit 5 bit 4

HFSEL[1:0]

Index

01h

Mnemonic

CMDA

bit 7

bit 6

bit 3

bit 2

bit 1

bit 0

POWDN

VSE

XT24

PIXSEL

MNFMT

IFMT

Manual video input standard select. Standard selection can be controlled automatically if

MNFMT=0.

0

1

Chip is forced to assume input is 50 Hz.*

Chip is forced to assume input is 60 Hz.

MNFMT

Manual input format control override. When this bit is 1 the IFMT bit is enabled.

0

The chip determines the input video standard based on the detected field rate:*

NTSC if 60 Hz.

PAL/SECAM if 50 Hz.

1

Input video standard is selected with the IFMT bit.

PIXSEL

XT24

Select pixel sampling rate.

0

1

Output data is at square pixel rate.

Output data is at CCIR 601 rate.*

Select the external clock reference frequency.

0

1

External clock is 26.8 MHz.

External clock is 24.576 MHz.*

HFSEL[1:0]

Horizontal tracking loop frequency select.

0

1

2

3

Force loop to very fast.

Force loop to fast.

Force loop to VCR time constant.*

Force loop to TV time constant.

VSE

Change the vertical end location of the VS.

0

1

Line 10/10.5.*

Line 9/9.5.

POWDN

Power down mode.

0

1

Normal operation.*

All chip functions except microprocessor interface and CK/CK2 generation are

disabled. The output of the CK/CK2 pins retains the most recent frequency when

the power down mode is enabled.

Modified on May/04/2000

PAGE 51 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

Control Register B

bit 5 bit 4

Index

02h

Mnemonic

CMDB

bit 7

bit 6

bit 3

bit 2

bit 1

bit 0

AGCGN VALIGN AGCOVF AGCFRZ

INSEL[3:0]

Analog input channel select.

0

1

2

4

5

6

8

9

A

F

AY0 is composite input.*

AY1 is composite input.

AY2 is composite input.

AC0 is composite input.

AC1 is composite input.

AC2 is composite input.

AY0 is luminance input, AC0 is chrominance input.

AY1 is luminance input, AC1 is chrominance input.

AY2 is luminance input, AC2 is chrominance input.

AY2 is luminance input, AC1 is Cb input, AC2 is Cr input.

AGCFRZ

AGCOVF

Freeze the analog AGC for the Y and C paths at their current values.

0

1

AGC is running. Reading AGC register returns the current AGC gain.*

AGC is frozen. Gain can be changed or read with AGC register.

AGC gain control mode.

0

1

AGC gain tracks to sync tip and back porch delta.

If ADC overflows, AGC gain will be reduced (this has higher priority over normal

sync tip - back porch tracking).*

VALIGN

AGCGN

VS edge alignment control.

0

VS leading edge occurs during serration pulses (typically within the first serration

pulse). VS trailing edge is aligned to half line or beginning of the line depending on

the field.*

1

VS leading edge is aligned to half line or beginning of the line depending on the

field. VS trailing edge is always aligned to beginning of the line.

AGC gain calculation.

0

Normal mode. AGC gain calculation is based on sync tip to back porch difference

equal to 68 ADC code.*

1

AGC gain calculation is base on sync tip to back porch difference equal to 54 ADC

code. This will reduce the AGC gain by a factor of 1/1.25 compare to normal mode.

When used in conjunction with PED and RGBH, this effectively increases the input

dynamic range.

Modified on May/04/2000

PAGE 52 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

Control register C

Index

03h

Mnemonic

CMDC

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

VMEN

TSTGE1

0

TSTGPK TSTGPH

TSTGFR[1:0]

TSTGEN

Enable manual control of horizontal phase and frequency tracking.

0

1

Auto phase and frequency tracking.*

Enable manual control of horizontal phase and frequency with TSTGFR[1:0] and

TSTGPH.

TSTGFR[1:0]

When TSTGEN == 1, these two bits control the horizontal frequency tracking.

00

01

1X

Stop frequency tracking and freeze the frequency at the current value.*

Horizontal frequency tracks the input.

Horizontal frequency tracking ignores video input and runs at nominal value based

on the field rate and output pixel rate selected by IFMT and PIXEL bits.

TSTGPH

TSTGPK

TSTGE1

VMEN

When TSTGEN == 1, this bit controls the horizontal phase tracking.

0

1

No phase tracking.*

Horizontal phase tracks the input video or HS1 input if in slave mode.

If TSTGE1 == 1, this bit controls AGC.

0

1

AGC clamps to back porch and gain is set based on sync tip-back porch difference.*

AGC clamps to sync tip and gain is set based on peak-valley difference.

Enables the function of TSTGPK.

0

1

Disables TSTGPK.*

Enables TSTGPK.

Vertical master mode.

0

1

Normal vertical sync operation.*

Vertical sync ignores input and free runs at 50 Hz or 60 Hz. This mode can be used

to generate video timing for a slave device.

Modified on May/04/2000

PAGE 53 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

Control Register D

Index

04h

Mnemonic

CMDD

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

EAV

0

CKDIR

INPSL[1:0]

SYNDIR Y1MHZ GPPORT

GPPORT

Y1MHZ

General purpose port. This register is useful only if DATAA[2:0] == 7. If DIRA == 0, this bit is

read only and reflects the logic state at PORTA pin. If DIRA == 1, any value written to this bit will

appear at PORTA pin.

Luma bandwidth control.

0

1

Luma bandwidth is controlled by other luma filters in the luma path.*

Luma data is low pass filtered to 1MHz bandwidth.

SYNDIR

HS1 and VS pin direction control.

0

1

HS1 and VS are output.*

HS1 and VS are input.

INPSL[1:0]

Video input and clock source select.

0

Video source is analog and connected to the chip’s analog input. Clock is internally

generated.*

1

3

Video source is 8-bit digital CbYCr and connected to EXV0 through EXV7 pins.

Video source is 8-bit digitized CVBS and connected to EXV0 through EXV7 pins.

CKDIR

EAV

Clock select.

0

1

Clock is from internal clock generator. A reference clock at XTALI pin is required.*

Clock is from CK pin. When this is selected, the CK pin automatically becomes an

input.

In 8-bit digital CbYCr input mode, this bit selects the sync source.

0

1

Horizontal and vertical syncs are from HS1 and VS pins, respectively.*

Syncs are embedded in the 8-bit digital data stream (CCIR 656 compatible).

Modified on May/04/2000

PAGE 54 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

HAV Start Control

bit 5 bit 4

HAVB[7:0]

HAVE[10:8]

Index

Mnemonic

bit 7

bit 6

bit 3

bit 2

bit 1

bit 0

05h

0Ch

HAVB

HXTRA

HAVB[10:8]

HS1BE0 HS2BE0

HAVB[10:0]

This 11-bit register is used to define the start location of the HAV signal relative to the sync tip

(for CVBS input, this is the composite video sync tip. For 8-bit CbYCr input, this is the leading

edge of the HS1 or EAV). The content of this register is a 2’s complement number which is

used as an offset to the default. The resolution for this register is 1 CK clock.

HAV End Control

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

HAVE[7:0]

HAVE[10:8]

bit 3

bit 2

bit 1

bit 0

06h

0Ch

HAVE

HXTRA

HAVB[10:8]

HS1BE0 HS2BE0

HAVE[10:0]

This 11-bit register is used to define the end location of the HAV signal relative to the sync tip.

The content of this register is a 2’s complement number which is used as an offset to the

default The resolution for this register is 1 CK clock.

HS1 Start Control

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

HS1B[8:1]

HAVE[10:8]

bit 3

bit 2

bit 1

bit 0

07h

0Ch

HS1B

HXTRA

HAVB[10:8]

HS1BE0 HS2BE0

HS1B[8:1] -

HS1BE0

If HS1 is programmed as an output, this 9-bit register defines the start location of the HS1

signal. The content of this register is a 2’s complement number which is used as an offset to the

default. The resolution for this register is 1 CK clock.

Modified on May/04/2000

PAGE 55 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

HS1 End Control

bit 5 bit 4

HS1E[8:1]

HAVE[10:8]

Index

Mnemonic

bit 7

bit 6

bit 3

bit 2

bit 1

bit 0

08h

0Ch

HS1E

HXTRA

HAVB[10:8]

HS1BE0 HS2BE0

HS1E[8:1] -

HS1BE0

If HS1 is programmed as an output, this 9-bit register defines the end location of the HS1

signal. The content of this register is a 2’s complement number which is used as an offset to the

default. The resolution for this register is 1 CK clock.

HS2 Start Control

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

HS2B[8:1]

HAVE[10:8]

bit 3

bit 2

bit 1

bit 0

09h

0Ch

HS2B

HXTRA

HAVB[10:8]

HS1BE0 HS2BE0

HS2B[8:1] -

HS2BE0

This 9-bit register defines the start location of the HS2 signal. The content of this register is a

2’s complement number which is used as an offset to the default HS2B location. The resolution

for this register is 1 CK clock.

HS2 End Control

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

HS2E[8:1]

HAVE[10:8]

bit 3

bit 2

bit 1

bit 0

0Ah

0Ch

HS2E

HXTRA

HAVB[10:8]

HS1BE0 HS2BE0

HS2E[8:1] -

HS2BE0

This 9-bit register defines the end location of the HS2 signal. The content of this register is a 2’s

complement number which is used as an offset to the default HS2E location. The resolution for

this register is 1 CK clock.

Modified on May/04/2000

PAGE 56 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

AGC Control

bit 5 bit 4

AGC[7:0]

Index

0x0B

Mnemonic

AGC

bit 7

bit 6

bit 3

bit 2

bit 1

bit 0

AGC[7:0]

This register is used to manually set AGC when AGCFRZ is set to “1”. The content in the

register is unsigned.

Chroma Demodulation Control

Index

0Dh

Mnemonic

CDEM

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

OUTHIZ

FSEC

0

CIFCMP[1:0]

0

CIFCMP[1:0]

IF compensation for the chroma path.

0

1

2

3

No compensation.*

Upper chroma side band is 1 dB higher than lower side band.

Upper chroma side band is 3 dB higher than lower side band.

Upper chroma side band is 6 dB higher than lower side band.

FSEC

Chroma frequency demodulation filter select for SECAM video.

0

1

Select SECAM chroma frequency demodulation filter if SECAM video is detected.*

Always use SECAM chroma frequency demodulation filter.

OUTHIZ

This is the software output three-state control bit. If this bit is set to a “1”, or the OEN pin is at a

logic LOW level, output pins can be selectively put in the high impedance state using the

additional software control bits OENC[1:0].

0

1

This is default setting.*

This will enable the output pins to be three-stated regardless the state of the OEN

pin.

Modified on May/04/2000

PAGE 57 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

Port A and B Control

Index

0Eh

Mnemonic

PORTAB

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

DIRB

DATAB[2:0]

DIRA

DATAA[2:0]

Port A data select. For internal gate signal locations.

0

1

2

3

4

Port A is disconnected from the internal signal path.*

Port A is connected to the BPG (back porch gate) signal.

Port A is connected to the SYG (sync tip gate) signal.

Port A is connected to the CBG (color burst gate) signal.

Port A is connected to the CBGW (color burst gate wide) signal. The CBGW is high

for the entire color burst period.

5

6

7

Port A is connected to the SLICE (mid way of the sync tip) signal.

Port A is connected to the VBI (vertical blanking interval) signal.

Port A is connect to the GPPORT bit.

DIRA

Port A direction control.

0

Port A is configured as input. The input is connected directly to the signal path

selected by DATAA[2:0]. The internally generated gate signal is disconnected from

the signal path.*

1

Port A is an output and is driven by the internally generated signal as selected by

DATAA[2:0].

DATAB[2:0]

Port B data select. For internal gate signal locations.

0

1

2

3

4

Port B is disconnected from the internal signal path.*

Port B is connected to the SCH (sync tip to color burst phase) signal.

Port B is connected to the FH2 (twice per line pulses) signal.

Port B is connected to the FS_PULSE (falling edge of the sync tip) signal.

Port B is connected to the VBI_CVBS (VBI raw ADC) signal. This signal is high for

those lines that output data directly from the ADC (not YUV or RGB data).

5

Port B is connected to the VBI_PROC (VBI sliced) signal. This signal is high for

those video lines that output sliced VBI data.

6

7

Port B is connected to the VS (Vertical Sync) signal.

Port B is configured as the RTCO (Real Time Control Output). This single pin serial

interface transmits phase and frequency information to a video encoder so that it

may operate directly from the S5D0127X01 output clock.

DIRB

Port B direction control.

0

Port B is configured as input. The input is connected directly to the signal path

selected by DATAB[2:0]. The internally generated gate signal is disconnected from

the signal path.*

1

Port B is an output and is driven by the internally generated signal as selected by

DATAB[2:0].

Modified on May/04/2000

PAGE 58 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

Luma Control Register

Index

0x0F

Mnemonic

LUMA

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0

UNIT

RGBH

PED

HYBWR

CTRAP

HYPK[1:0]

Luminance horizontal peaking control around 3 MHz.

0

1

2

3

Less than nominal peaking.*

Nominal peaking.

Increased peaking.

Maximum peaking.

CTRAP

HYBWR

PED

Chroma trap (notch filter) in the luma path.

0

1

No chroma trap. This mode is recommended for S-video or component video input.*

Chroma trap is enabled.

Luminance horizontal bandwidth reduction control.

0

1

Full bandwidth.*

Reduced bandwidth.

Enable gain correction for 7.5 blank-to-black setup (pedestal).

0

1

No pedestal. 0% = Y code 16. 100% = Y code 235.*

Gain adjusted for 7.5% blank-to-black setup (pedestal). 7.5% = Y code 16. 7.5% -

100% input produce Y code 16 - 235.

RGBH

UNIT

High gain to produce full range Y for 0% (or 7.5% if PED = 1) to 100% input.

0

1

Black (0% or 7.5%) to peak white(100%) input produce Y code 16 to 235.*.

Black (0% or 7.5%) to peak white(100%) input produce Y code 0 to 255.

When PED and RGBH are both set to a “1”, setting this bit to a “1” produces a unit gain for

CCIR 601 digital input (INPSL[1:0] = 1).

0

1

Luma DC gain is controlled by PED and RGBH as described for each bit.*

Luma DC gain is unity for CCIR 601 digital input.

Modified on May/04/2000

PAGE 59 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

Contrast Control

bit 5 bit 4

CON[7:0]

Index

0x10

Mnemonic

CON

bit 7

bit 6

bit 3

bit 2

bit 1

bit 0

CON[7:0]

This 8-bit register contains a 2’s compliment number for contrast control.

Brightness Control

Index

0x11

Mnemonic

BRT

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

BRT[7:0]

Brightness control register. The number contained in the register is 2’s compliment.

Modified on May/04/2000

PAGE 60 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

Chroma Control Register A

Index

0x12

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

CHROMA ACCFRZ

PALM

PALN

CBW

CORE[1:0]

CKILL[1:0]

CORE[1:0]

Color kill.

0

Auto detect mode. If color burst is too low or no color burst, chroma data is forced to

code 128.*

2

3

Chroma is always ON.

Chroma data is always forced to code 128.

Chroma data coring.

0

1

2

3

No coring.

Chroma data within the range 128+/-1, inclusive, will be force to 128.

Chroma data within the range 128+/-3, inclusive, will be force to 128.*

Chroma data within the range 128+/-7, inclusive, will be force to 128.

CBW

Chroma bandwidth control.

0

1

Chroma 3 dB bandwidth is 850 kHz.*

Chroma 3 dB bandwidth is 550 kHz.

PALN

Select color tracking for PAL-N, or NTSC-N when input field rate is 50 Hz and Fsc is 3.58 MHz.

0

1

Select NTSC-N.*

Select PAL-N.

PALM

ACCFRZ

Select color tracking for PAL-M or NTSC-M when input field rate is 60 Hz.

0

1

Select color tracking for NTSC-M.*

Select color tracking for PAL-M.

Chroma gain tracking freeze control.

0

1

Chroma gain tracks the input. Color saturation can be adjusted with SAT.*

Chroma gain freezes at the current saturation level.

Modified on May/04/2000

PAGE 61 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

Chroma Control Register B

bit 5 bit 4

CDLY[3:0]

Index

0x13

Mnemonic

CHROMB

bit 7

bit 6

bit 3

bit 2

bit 1

bit 0

SCHCMP[3:0]

CDLY[3:0]

Phase constant compare value for color burst phase relative to sync tip. Each step is 22.5

degrees with the value of 0 equal to 0 degree.

Chroma path group delay relative to the luma path (in unit of CK):

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

No delay.*

-0.5

1

0.5

2

1.5

3

2.5

-4

-4.5

-3

-3.5

-2

-2.5

-1

-1.5

Modified on May/04/2000

PAGE 62 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

Chroma Demodulation Control and Status

bit 6 bit 5 bit 4 bit 3

FSCDET SECDET CDMLPF CTRACK

Index

0x14

Mnemonic

DEMOD

bit 7

bit 2

bit 1

bit 0

MNFSC[1:0]

MNSECAM[1:0]

MNSECAM[1:0] Enable manual SECAM input detection.

0

2

3

Detection of SECAM input is automatic.*

Force the chip to assume input is not SECAM.

Force the chip to assume input is SECAM.

MNFSC[1:0]

Enable manual Fsc detection.

0

2

3

Detection of Fsc frequency is automatic.*

Force chip to assume input Fsc is 4.43 MHz or 4.286 MHz.

Force chip to assume input Fsc is 3.58 MHz.

CTRACK

CDMLPF

SECDET

FSCDET

Chroma frequency tracking mode.

0

1

Chroma frequency tracking is based on the field rate and Fsc.*

Chroma frequency tracking is based on field rate only.

Bypass the LPF in the chroma demodulator.

0

1

Chroma data pass through the LPF for color demodulation.*

Chroma data bypass the LPF. This setting is used for component video input.

SECAM detection (read only).

0

1

Chip did not detect SECAM input.

Chip detected SECAM input.

Color subcarrier detection (read only).

0

1

Chip detected 4.43 MHz or 4.286 MHz Fsc.

Chip detected 3.58 MHz Fsc.

Modified on May/04/2000

PAGE 63 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

Color Saturation Control

bit 5 bit 4

SAT[7:0]

Index

0x15

Mnemonic

SAT

bit 7

bit 6

bit 3

bit 2

bit 1

bit 0

SAT[7:0]

Color saturation control register. Register content is in 2’s compliment if TSTCGN=0. 0 value

corresponds to nominal saturation.

Hue Control

Index

0x16

Mnemonic

HUE

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

HUE[7:0]

Hue control register. The register content is in 2’s compliment format. It covers the range from

-180° to +178.59° degree. The resolution is 1.41°/LSB.

Modified on May/04/2000

PAGE 64 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

Vertical Processing Control A

Index

0x17

Mnemonic

VERTIA

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

MNYCMB

YCMBCO[2:0]

VRT2X

VCTRL[2:0]

Luminance vertical filter control.

0

1

2

3

4

Scaler uses LPF path, comb uses HPF.*

Scaler uses full bandwidth, comb is disabled.

Scaler is disabled, comb uses full bandwidth.

Scaler uses LPF, comb is disabled.

Scaler is disabled, comb uses HPF.

VRT2X

3/5-tap vertical scaler filter select.

0

1

Select 3-tap vertical scaler filter.*

Select 5-tap vertical scaler filter. This option can be used only if horizontally cropped

line is less than or equal to 384 pixels.

YCMBCO[2:0]

Luma comb filter coefficients selection when the MNYCMB is set to “1”.

0

1

2

3

4

5

6

7

[1/4 1/2 1/4].*

[3/8 1/2 1/8].

[1/2 1/2 0].

[1 0 0].

[0 1 0].

[1/2 0 1/2].

[0 1/2 1/2].

[1/8 1/2 3/8].

MNYCMB

Select between auto and manual luma comb filter coefficients.

0

Luma comb filter coefficients are automatically selected based on input video

standard.*

1

Luma comb filter coefficients are selected with YCMBCO[2:0].

Modified on May/04/2000

PAGE 65 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

Vertical Processing Control B

Index

0x18

Mnemonic

VERTIB

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

HYLPF[2:0]

HYBWI

HYDEC

VSCLEN[1:0]

0

VSCLEN[1:0]

Vertical scaling enable.

0

1

2

3

Vertical scaling is enabled.*

Vertical scaling is disabled.

Vertical scaling is disabled. Video is 1-line delayed.

Vertical scaling is disabled. Video is 2-line delayed.

HYDEC

Luma path decimation filter enable.

0

1

Luma path decimation is enabled.*

Luma path decimation is disabled.

HYBWI

Luma path decimation filter bandwidth select.

0

1

Normal bandwidth.*

Bandwidth is 1 MHz higher.

HYLPF[2:0]

Horizontal luma LPF bandwidth control.

0

1

2

3

4

Full bandwidth.*

4.5 MHz bandwidth.

3.5 MHz bandwidth.

2.5 MHz bandwidth.

1.5 MHz bandwidth.

Modified on May/04/2000

PAGE 66 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

Vertical Processing Control C

Index

0x19

Mnemonic

VERTIC

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

MNCCMB

CCMBCO[2:0]

ACMBEN VYBW

EVAVEV EVAVOD

EVAVOD

EVAVEV

Enable VAV signal output during ODD field.

0

1

VAV signal is disabled (always inactive) during ODD field.

VAV signal is enabled during ODD field.*

Enable VAV signal output during EVEN field.

0

1

VAV signal is disabled (always inactive) during EVEN field.

VAV signal is enabled during EVEN field.*

VYBW

Luma vertical bandwidth control.

0

1

Full bandwidth.*

Reduced bandwidth.

ACMBEN

CCMBCO[2:0]

Enable luma active comb for NTSC.

0

1

Active comb is disabled.*

Active comb is enabled.

Manual chorma comb filter coefficients select.

0

1

2

3

4

5

6

7

Select the coefficient set [1/2 1/2 0] (if VRT2X = 0).*

Select the coefficient set [1/4 1/2 1/4] (if VRT2X = 0).

Select the coefficient set [0 1/2 1/2 0 0] (if VRT2X = 1).

Select the coefficient set [0 1/4 1/2 1/4 0] (if VRT2X = 1).

Select the coefficient set [1 0 0].

Select the coefficient set [0 1 0].

Select the coefficient set [0 0 1].

No output (disabled).

MNCCMB

Chroma comb filter coefficients are selected automatically or manually.

0

Filter coefficients are automatically selected based on the selected video input

standard. SECAM must use this value.*

1

Filter coefficients are selected manually with CCMBCO[2:0].

Modified on May/04/2000

PAGE 67 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

Horizontal Scaling Ratio

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x1A

0x1B

HSCLL

HSCLH

HSCL[6:0]

CMBMOD

HSCL[14:7]

CMBMOD

This bit controls when comb is enabled internally.

0

1

Comb is enabled by the internal signal COMB_EN.*

Comb is enabled when VAV is active.

15

HSCL[14:0]

The 15-bit register defines a horizontal scaling ratio of HSCL[14:0]/2 . Any change to this

value will become effective during the next vertical sync.

Vertical Scaling Ratio

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x1C

0x1D

VSCLL

VSCLH

VSCL[5:0]

ACMBCO ACMBRE

VSCL[13:6]

ACMBRE

ACMBCO

VSCL[13:0]

Active comb filter threshold select.

0

1

High threshold.*

Low threshold.

Active comb filter coefficient set select.

0

1

Use the set of coefficients for 100% comb.*

Use the set of coefficients for 75% comb.

14

The 14-bit register defines a vertical scaling ratio of VSCL[13:0]/2 . Any change to this value

will become effective during the next vertical sync.

Modified on May/04/2000

PAGE 68 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

Output Control A

bit 5 bit 4

OENC[1:0]

Index

0x1E

Mnemonic

OFMTA

bit 7

bit 6

bit 3

bit 2

bit 1

bit 0

GAMEN[1:0]

OFMT[3:0]

Digital video output format select. 16 and 24 bit data are output at CK2 clock rate. 8 bit data are

output at CK clock rate.

0

1

2

3

4

5

6

7

8

16-bit YCbCr 4:2:2 output on the Y and C output ports.*

12-bit YCbCr 4:1:1 output on the Y and C output ports.

8-bit YCbCr 4:2:2 without embedded timing reference codes.

8-bit YCbCr 4:2:2 with embedded timing reference codes.

24-bit YCbCr 4:4:4.

16-bit RGB 565.

24-bit RGB 888 with linear bit ordering.

24-bit RGB 888, bit ordering is an extension of the 16-bit RGB 565 format.

Same as mode 2 with the additional of 8-bit YCbCr 4:2:2 data output on the EXV

port. While the Y port can be scaled down, the EXV port will always be a full size

picture.

9

Same as 8 with the addition of SAV and EAV codes.

A

output Y ADC data all the time (including syncs) on the Y port, C port is non-scaled

656 data with no timing codes.

B

Output Y ADC data all the time (including syncs) on the Y port,

Output C ADC data all the time (including syncs) on the C port,

OENC[1:0]

When either the OEN pin is low or the OUTHIZ is a “1”, these two bits will determine which

output pins are three-stated.

0

1

All video pins are three-stated.

All video pins, plus HAV, VAV, EVAV, EHAV, PID, ODD, HS1, HS2, VS, and SCH are

three-stated.

2

3

All pins listed above, plus CK and CK2 are three-stated.

Always output data.

GAMEN[1:0]

Gamma correction enable.

0

1

2

3

No gamma correction.*

Gamma correction is applied to Y/G data.

Gamma correction is applied to U/B and V/R data.

Gamma correction is applied to Y/G, U/B, and V/R data.

Modified on May/04/2000

PAGE 69 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

Output Control B

Index

0x1F

Mnemonic

OFMTB

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

VSVAV

EVAND[1:0]

EVHS1

EVHAV EVEHAV EVAVG EVANDL

EVAVG

EVEHAV

EVHAV

EVHS1

Gate EVAV with VAV before sending to output.

0

1

EVAV is not gated with VAV. EVAV may be active outside of active VAV region.*

EVAV is gated with VAV. EVAV can be active only when VAV is active.

Additional qualifier for EHAV.

0

1

No additional qualifier.*

EHAV uses qualifier from EVAND[1:0].

Additional qualifier for HAV.

0

1

No additional qualifier.*

HAV uses qualifier from EVAND[1:0].

Additional qualifier for HS1.

0

1

No additional qualifier.*

HS1 uses qualifier from EVAND[1:0].

EVAND[1:0],

EVANDL

Qualifier signal that defines active video lines. This control enables 656 codes, HAV, EHAV and

HS1.

EVANDL is the EVAND LSB. These three bits are grouped together and explained below

0

1

2

Qualifier is active for all lines.*

Qualifier is EVAV. -- Any line during vertical active or blank will be output.

Qualifier is EVAV and VAV -- All lines during vertical blank (VAV==0) and all lines

when EVAV is active during vertical active will be output.

3

4

Qualifier is VAV -- All lines during vertical active will be output.

Qualifier is EVAV and VAV -- All lines that EVAV is active during vertical active will

be output.

5

6

7

Qualifier is EVAV, VAV and VBI_RAW_EN -- All lines as in option 4 plus the VBI

RAW ADC lines.

Qualifier is EVAV, VAV, VBI_RAW_EN and VBI_SLC_EN-- All lines as in option 5

plus the VBI Sliced Lines.

All VBI sliced and VBI RAW Lines only.

VSVAV

Enable VAV to be output to VS.

0

1

Output normal VS.*

VS has the same output as VAV

Modified on May/04/2000

PAGE 70 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

VBI Decoder Control

bit 5 bit 4

VYFMT[1:0] VBINSRT ODDEN EVENEN

Index

0x20

Mnemonic

VBICTL

bit 7

bit 6

bit 3

bit 2

bit 1

bit 0

VBCVBS

ODDOS[1:0]

Line offset for ODD field. See also VBIL[15:0].

0

1

2

3

ODD field line offset is -1 compared to EVEN field.*

No offset.

ODD field line offset is 1 compared to EVEN field.

ODD field line offset is 2 compared to EVEN field.

EVENEN

ODDEN

VBI data processing for EVEN field.

0

1

No processing.*

VBI processing is enabled for EVEN field.

VBI data processing for ODD field.

0

1

No processing.*

VBI processing is enabled for ODD field.

VBINSRT

VYFMT[1:0]

Enable VBI data to be output on the Y bus.

0

1

VBI data is not output on the Y bus.*

VBI data is output on the Y bus.

When VBINSRT = 1, these bits control how VBI data are output on the Y bus.

0

1

2

3

1 bit on Y7 per CK2 clock.*

1 bit on Y7 plus a “1” on Y3 per CK2 clock.

4 bits on Y7..Y4, with first bit on Y7, last bit on Y4, plus a “1” on Y3 per CK2 clock.

8 bits on Y7..Y0, with first bit on Y7, last bit on Y0, per CK2 clock.

VBCVBS

Enable digitized CVBS data from ADC to be output for the selected VBI line instead of sliced

VBI data. The new VBIMID bit allows simultaneous output (line by line bases) of sliced data

and raw ADC data.

0

1

Output sliced VBI data for any line whose VBIL value ~= 0.*

Output digitized CVBS data for any line whose VBIL value ~=0.

Modified on May/04/2000

PAGE 71 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

First Decoded Close-Caption Data Byte (Read Only)

Index

0x21

Mnemonic

CCDAT1

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

b0

b1

b2

b3

b4

b5

b6

P1

CCDAT1

This byte contains the first byte of the decoded close-caption data as defined in EIA-608. In

order for this register to receive the CC data, VBINSRT must be programmed to a “1”, and

VYFMT[1:0] must be programmed with the value 3. The same applies to CCDAT2. For normal

NTSC Closed Caption decoding, ODDEN should be set to a “1”, VBIL12 should be

programmed with the value 1.

Second Decoded Close-Caption Data Byte (Read Only)

Index

0x22

Mnemonic

CCDAT2

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

b0

b1

b2

b3

b4

b5

b6

P2

CCDAT2

This byte contains the second byte of the decoded close-caption data as defined in EIA-608.

VBI Data Decoding

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x23

0x24

0x25

0x26

VBIL30

VBIL74

VBIL3

VBIL7

VBIL2

VBIL6

VBIL1

VBIL5

VBIL9

VBIL13

VBIL0

VBIL4

VBIL8

VBIL118

VBIL1512

VBIL11

VBIL15

VBIL10

VBIL14

VBIL12

VBIL0..VBLI15

These 16 2-bit numbers select how the chip should decode the VBI data for each VBI line. For

60 Hz video, VBIL1 through VBIL15 correspond to lines 10 through 24 in the ODD field, and

lines 273 through 286 in the EVEN filed for NTSC (refer to NTSC line numbering convention).

For 50 Hz video, VBIL1 corresponds to line 7 in the ODD field, and line 320 in the EVEN field.

VBIL0 is used for all other lines not covered by VBIL1 through VBIL15.

0

1

2

3

Decode normal video.*

Decode Closed Caption data.

Decode Teletext data.

Decode WSS data.

Modified on May/04/2000

PAGE 72 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

Teletext Frame Alignment Pattern

bit 6 bit 5 bit 4 bit 3

TTFRAM[7:0]

Index

0x27

Mnemonic

TTFRAM

bit 7

bit 2

bit 1

bit 0

TTFRAM[7:0]

User programmable Teletext frame alignment pattern.

UV Offset Adjustment

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

UOFFST[5:4]

VOFFST[3:0]

bit 2

bit 1

bit 0

0x29

0x2A

UVOFFH

UVOFFL

TSTCLC TSTCGN

0

TSTCFR

VOFFST[5:4]

UOFFST[3:0]

VOFFST[5:0],

UOFFST[5:0]

These two 6-bit 2’s compliment values are for offset adjustment to the U and V components of

the chroma data. The resolution is 1/4 LSB of the 8-bit U and V.

TSTCFR

TSTCGN

TSTCLC

Chroma frequency tracking control.

0

1

Chroma frequency tracking is enabled.*

Chroma frequency tracking is open loop.

Chroma gain control.

0

1

Chroma gain tracks input.*

Chroma gain is controlled by SAT only.

Cloche filter bypass.

0

1

Cloche filter is enabled for SECAM input.*

DC bypass of the cloche filter.

Modified on May/04/2000

PAGE 73 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

U Component Gain Adjustment

bit 6 bit 5 bit 4 bit 3

UGAIN[7:0]

Index

0x2B

Mnemonic

UGAIN

bit 7

bit 2

bit 1

bit 0

UGAIN[7:0]

U component gain adjustment. The nominal value is 0.

V Component Gain Adjustment

Index

0x2C

Mnemonic

VGAIN

bit 7

bit 6

bit 5

bit 4

bit 3

VGAIN[7:0]

V component gain adjustment. The nominal value is 0.

VAV Begin

Index

0x2D

Mnemonic

VAVB

bit 7

bit 6

bit 5

bit 4

bit 3

VAVB[6:1]

VAVOD0 VAVEV0

VAVEV0

VAVOD0

VAVB[6:1]

The LSB for VAVB and VAVE for the even field.

The LSB for VAVB and VAVE for the odd field.

The 6 MSB’s of a 7-bit unsigned number which defines the start of VAV. The value “0”

corresponds to line 4.

VAV End

Index

0x2E

Mnemonic

VAVE

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

VAVE[8:1]

The 8 MSB’s of a 9-bit unsigned number which defines the end of VAV. The value “0”

corresponds to line 4.

Modified on May/04/2000

PAGE 74 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

Chroma Tracking Control Register

Index

0x2F

Mnemonic

CTRACK

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0

DMCTL[1:0]

CGTC[1:0]

CFTC[1:0]

CGTC[1:0]

DMCTL[1:0]

Chroma frequency tracking time constant.

0

1

2

3

Slower.*

Slow.

Fast.

Faster.

Chroma gain tracking time constant.

0

1

2

3

Slower.*

Slow.

Fast.

Faster.

Chroma demodulation bypass mode.

0

1

2

Chroma demodulation is enabled.*

Chroma demodulation is bypassed for digital YCbCr input.

Chroma demodulation is bypassed for analog YCbCr input. Cb path is phase

delayed by one half of CK2 clock period.

3

Chroma demodulation is bypassed for analog YCbCr input. Cr path is phase

delayed by one half of CK2 clock period.

Modified on May/04/2000

PAGE 75 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

Timing Signal Polarity Control

Index

0x30

Mnemonic

POLCTL

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

EVAVPL

VSPL

ODDPL

HAVPL EHAVPL

HS2PL

VAVPL

HS1PL

VAVPL

HS2PL

EHAVPL

HAVPL

ODDPL

VSPL

HS1 polarity.

0

1

Active high.*

Active low.

VAV polarity.

0

1

Active high.*

Active low.

HS2 polarity.

0

1

Active high.*

Active low.*

EHAV polarity.

0

1

Active high.*

Active low.

HAV polarity.

0

1

Active high.*

Active low.

ODD polarity (this also affects the F bit in 656 code).

0

1

Active high.*

Active low.

VS polarity (this also affect the V bit in 656 code).

0

1

Active high.*

Active low.

EVAVPL

EVAV polarity.

0

1

Active high.*

Active low.

Modified on May/04/2000

PAGE 76 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

Reference Code Insertion Control

Index

0x31

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

REFCOD YCRANG

0

YCRANG

Digital video output range control.

0

1

Y and C ranges are limited to 1 - 254; R, G, and B ranges are limited to 1 - 254.*

Y range is limited to 16 - 235; C range is limited to 16 - 240; R, G, and B ranges are

limited to 16 - 240.

Invalid Y Code

Index

0x32

Mnemonic

INVALY

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

INVALY[7:0]

User programmed code to be output for Y data when HAV is active but EHAV is inactive.

Invalid U Code

Index

0x33

Mnemonic

INVALU

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

INVALU[7:0]

User programmed code to be output for U data when HAV is active but EHAV is inactive.

Invalid V Code

Index

0x34

Mnemonic

INVALV

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

INVALV[7:0]

User programmed code to be output for V data when HAV is active but EHAV is inactive.

Modified on May/04/2000

PAGE 77 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

Unused Y Code

bit 5 bit 4

UNUSEY[7:0]

Index

0x35

Mnemonic

UNUSEY

bit 7

bit 6

bit 3

bit 2

bit 1

bit 0

UNUSEY[7:0]

User programmed code to be output for Y data when HAV is inactive.

Unused U Code

Index

0x36

Mnemonic

UNUSEU

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

UNUSEU[7:0]

User programmed code to be output for U data when HAV is inactive.

Unused V Code

Index

0x37

Mnemonic

UNUSEV

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

UNUSEV[7:0]

User programmed code to be output for V data when HAV is inactive.

Modified on May/04/2000

PAGE 78 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

Extra Control Bits for the S5D0127X01 Version

Index

0x38

Mnemonic

EXCTRL

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0

ENINCST

0

-

AUCPWD

0

CLEVEL

Programmable CKILL burst level select bit.

0

1

Burst peak level is 11 IRE.*

Burst peak level is 5.5 IRE.

AUCPWD

ENINCST

Auto chroma ADC power down mode enabled when appropriate input format is selected.

0

1

Chroma ADC powered down only during entire chip power down mode.*

Chroma ADC is power downed when CVBS input or case ‘0’ condition.

Scaler enable control bit during VBI.

0

1

Scaler on during VBI interval (defined by VAV).*

Scaler off during VBI interval.

Modified on May/04/2000

PAGE 79 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

Tracking Configuration Controls A

bit 6 bit 5 bit 4 bit 3

STCTRL MAC_DET VCR_DET VCR_LEV[1:0]

Index

0x39

Mnemonic

TRACKA

bit 7

bit 2

bit 1

bit 0

ATCTRAP VBCTRAP AGCLSB

AGCLSB

AGC LSB for control of the 9 bit AGC gain value. This bit only write to AGC when AGCFRZ is

1.

0

1

Write ‘0’ to AGC 9 bit control LSB if AGCFRZ = 1.*

Write ‘1’ to AGC 9 bit control LSB if AGCFRZ = 1.

VBCTRAP

ATCTRAP

VCR_LEV

Chroma trap enabled during the VBI.

0

1

Chroma trap is controlled by CTRAP only.*

Chroma trap enabled during VBI.

Auto Chroma Trap on luma path when VCR input is detected.

0

1

Chroma trap is controlled by CTRAP only.*

If VCR type input is detected, then CTRAP is enabled.

Set the Fh variation from nominal for detection of VCR type input.

0

1

2

3

50 PPM.*

100 PPM.

200 PPM.

400 PPM.

VCR_DET

MAC_DET

STCTRL

Status bit. Detect input that is not SCH locked such as consumer type VCR (Read only).

0

1

SCH locked video.

Color burst not locked to Fh (VCR).

Status bit. Macrovision Encoded Data detected as input video source (Read only).

0

1

Standard video detected.

Macrovision Encoded data detected.

State machine transition control.

0

1

Normal state machine transitions.*

Steady state sync level removed as condition for lock.

Modified on May/04/2000

PAGE 80 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

VBI Control Register B

bit 5 bit 4

TT_SYS[1:0] VBIMID NEW_CC CC_OVFL YOFFENB COFFENB

Index

0x3A

Mnemonic

bit 7

bit 6

bit 3

bit 2

bit 1

bit 0

VBICTLB VBISWAP

COFFENB

YOFFENB

CC_OVFL

Disable control for the C-path clamp control.

0

1

C-path clamp works as normal.*

C-path clamp disabled.

Disable control for the Y-path clamp control.*

0

1

Y-path clamp works as normal.*

Y-path clamp disabled.

Defines when the current CCDAT1,2 data has over written previous data that was not read.

(Read Only)

0

1

Current data has not generated an overflow condition.

Current data as written over data that was not read.

NEW_CC

Defines when new Closed Caption data is ready for reading from the CCDAT1,2 bytes. (Read

Only)

0

1

Current data in CCDAT1,2 has already been read.

Current data in CCDAT1,2 is new.

VBIMID

TT_SYS

Changes function of WSS enable (per line bases during VBI) to a raw CVBS enable.

0

1

When VBIL(0-15) = 3, current line is enabled for WSS slicing.*

When VBIL(0-15) = 3, current line is enabled for raw ADC output.

Select Teletext input system when auto detect is not possible.

0

1

2

3

Auto Teletext Select.*

Teletext System B.

Teletext System C.

Teletext System D.

VBISWAP

Reverse the bit order for data output from the closed caption or Teletext slicer.

0

1

Same as S5D0124D01 -- First bit sliced is located in MSB position.*

First bit sliced (in time) is located in LSB position.

Modified on May/04/2000

PAGE 81 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

Tracking Configuration Controls B

Index

0x3B

Mnemonic

TRACKB

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

ALT656

VBI_PH

VBI_FR PH_CTRL VNOISCT

AGC_LPG[1:0]

AGC_LKG

AGC_LPG

AGC gain tracking loop time constant for initial tracking mode.

0

1

Same as steady state time constant.*

2X faster than selected steady state time constant.

AGC gain steady state tracking loop time constant.

0

1

2

3

Fastest.*

Fast.

Slow.

Slowest.

VNOISCT

PH_CTRL

VBI_FR

Vertical sync noise control enable.

0

1

Vertical sync adjusts with all sync phase changes.*

Vertical sync large phase errors must occur for 4 lines to activate a phase change.

Controls phase detector response.

0

1

Syncs after the “0” point reference have priority.*

Syncs prior to “0” point reference have priority.

Disables frequency compensation for VCR head switch lines only.

0

1

Frequency tracking independent of this control.*

Frequency tracking disabled for VCR head switch lines.

VBI_PH

ALT656

Enables phase compensation for VCR head switch lines only.

0

1

Phase tracking independent of this control.*

Phase tracking enabled for VCR head switch lines only.

Alternate 656 Vertical blank location for 50 Hz video.

0

1

Vertical blank size per the ITU 656 Specification (ends at 656 digital line 23).*

Vertical blank size same as 60 Hz (ends at 656 digital line (50 Hz) 6).

Modified on May/04/2000

PAGE 82 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

RTC Genlock output signal control

Index

0x3C

Mnemonic

RTC

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

RTC_DTO RTC_PID

0

TDMOD

0

TDMOD

Test bit for chroma demodulation mode.

0

1

Normal operation.*

Test mode.

RTC_PID

RTC_DTO

Polarity control for PAL ID transferred within the RTC data stream.

0

1

Same polarity as default PID pin.*

Inverted polarity.

Enables a DTO reset inside the S5D0127X01 and sends a DTO reset within the RTC data

stream. Function is activated on the rising edge of RTC_DTO.

0

1

Function disabled.*

Function enabled one time when set to 1.

Modified on May/04/2000

PAGE 83 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

Command Register E

bit 5 bit 4

HCORE[1:0]

Index

0x3D

Mnemonic

CMDE

bit 7

bit 6

bit 3

bit 2

bit 1

bit 0

ODFST

VSALG

CHIPREVID

HCORE

Four additional bits for determination of current Revision and differentiation from the

S5D0124D01.

0

9

S5D0124D01.

S5D0127X01 Revision A.*

Luma path horizontal coring. Noise limiter for high frequency portion of luma.

0

1

2

3

Coring function is disabled.*

1 bit of coring.

2 bits of coring.

4 bits of coring.

VSALG

ODFST

Vertical scaling line dropping algorithm.

0

Vertical scaling drops the same lines in the Odd and Even fields -- good for fast

motion video.*

1

Vertical scaling drops lines based on the final de-interlaced video. This is a better

vertical scaling but may be sensitive to fast motion video.

Alternate the first scaling line between Odd and Even fields.

0

1

Even field is the first scaled field.*

Odd field is the first scaled field.

Modified on May/04/2000

PAGE 84 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

VS Delay Control

bit 5 bit 4

Index

0x3E

Mnemonic

VSDEL

bit 7

bit 6

bit 3

bit 2

bit 1

bit 0

TR_MS NOVIDC

VSDEL[5:0]

NOVIDC

When the chip is programmed for digital video input operation, this register provides an offset

for the internal line counter to align with input video (VS can be either from the VS pin or from

embedded timing code). The register content is unsigned.

Allows NOVID bit to be output to PORTB (pin 24).

0

1

Normal operation.*

The NOVID bit is output to PORTB if DATAB[2:0]=1 and DIRB=1.

TR_MS

Enable alternative initial tracking mode state machine.

0

1

Normal operation - Horizontal tracking mode is controlled by the HFSEL[1:0] bits.*

Variable tracking modes during locking time.

Modified on May/04/2000

PAGE 85 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

Command Register F

bit 5 bit 4

VIPMODE EVAVY UVDLEN UVDLSL REGUD

Index

0x3F

Mnemonic

CMDF

bit 7

bit 6

bit 3

bit 2

bit 1

bit 0

CTRAPFSC

TASKB

CBWI

Chroma bandwidth increase. This function should be used for digital video input mode only.

0

1

Normal chroma bandwidth.*

Increased chroma bandwidth.

TASKB

Select between task A and B as described in “VIP Specification V. 1.0”.

0

1

Select CCIR 656 timing codes (T-bit is always 1).*

Select between task A and B when VBI data is output. If active video is output, T-bit

is set to 1(task A). If VBI data is output, T-bit is set to 0 (task B).

REGUD

Control register update control.

0

1

Registers are updated immediately after being written to.*

The following registers and register bits are updated only during the start of vertical

sync after they are written to:

Index 0x02, indices 0x17 through 0x1D, bit 0 of index 0x04, bits [2:0] and [6:4] of

index 0x0E.

UVDLSL

UVDLEN

EVAVY

U or V delay control when UVDLEN is set to 1.

0

1

V is delayed by 1 CK period.*

U is delayed by 1 CK period.

Enable the function of UVDLSL.

0

1

UVDLSL is disabled.*

UVDLSL is enabled.

Control the output of INVALY, INVALU, and INVALV codes when EVAV is inactive.

0

1

Output of these codes are not affected by EVAV.*

These codes are output when EVAV is inactive (line is being dropped by the vertical

scaler).

VIPMODE

Allows transfer of hardware sliced VBI data as ancillary data during the following line’s

horizontal blanking period.

0

1

Standard S5D0124D01 original sliced VBI data transfer.*

Optional ancillary sliced VBI data transfer.

CTRAPFSC

Enable chroma trap location based on Fsc frequency instead of field rate.

0

1

Chroma trap based on field rate (same as S5D0124D01).*

Chroma trap based on detected Fsc frequency.

Modified on May/04/2000

PAGE 86 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

Gamma Base

bit 5 bit 4

Index

Mnemonic

bit 7

bit 6

bit 3

bit 2

bit 1

bit 0

0x40

0x41

:

GAMMA0

GAMMA0[7:0]

GAMMA1

GAMMA1[7:0]

:

0x5F

GAMMA31

GAMMA31[7:0]

GAMMA0

-GAMMA31

Gamma correction base. The desired output for 8*N, where N = 0, .., 31, is programmed into

GAMMAN. Note that data written into these addresses are simultaneously written into

addresses 0xC0 through 0xDF.

Gamma Correction Delta

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0x60

GAMMAD0

-

:

-

:

GAMMAD0[5:0]

0x61

GAMMAD1

GAMMAD1[5:0]

:

0x7F GAMMAD31

-

GAMMAD31[5:0]

GAMMAD0

..GAMMAD31

The Nth location of the 32 locations is programmed with a 6-bit unsigned number which

represents the gamma correction delta for the gamma bases N and N + 1. The last location

will contain the gamma correction delta for gamma base 31 and presumed base 32 which has

the value of 256. Note that data written into these addresses are simultaneously written into

addresses 0xE0 through 0xFF.

Modified on May/04/2000

PAGE 87 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

U/V Gamma Base

bit 5 bit 4

Index

Mnemonic

bit 7

bit 6

bit 3

bit 2

bit 1

bit 0

0xC0

0xC1

:

GAMUV0

GAMUV0[7:0]

GAMUV1

GAMUV1[7:0]

:

0xDF

GAMUV31

GAMUV31[7:0]

GAMUV0

U and V gamma correction base. The desired output for 8*N, where N = 0, .., 31, is

-GAMUV31

programmed into GAMUVN.

U/V Gamma Correction Delta

Index

Mnemonic

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0xE0

GAMUVD0

-

:

-

:

GAMUVD0[5:0]

0xE1

GAMUVD1

GAMUVD1[5:0]

:

0xFF GAMUVD31

-

GAMUVD31[5:0]

GAMUVD0

..GAMUVD31

U and V gamma correction delta. The Nth location of the 32 locations is programmed with a

6-bit unsigned number which represents the gamma correction delta for the gamma bases N

and N + 1. The last location will contain the gamma correction delta for gamma base 31 and

presumed base 32 which has the value of 256.

Modified on May/04/2000

PAGE 88 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Characteristics

MULTIMEDIA VIDEO

Symbol

Value

Units

5-V supply voltage (measured to VSS)

3.3-V supply voltage (measured to VSS)

Voltage on any digital pin

V

-0.5 to + 7.0

-0.5 to + 4.5

V

DD

V

DD3

V

-0.5 to (V +0.5)

V

DD

Ambient operating temperature (case)

Storage temperature

T

-35 to + 100

-65 to + 150

150

°C

A

T

S

Junction temperature

T

J

Vapor phase soldering (1 min.)

Tvsol

220

Notes: 1.Absolute maximum ratings are limiting values applied individually while all other parameters are within

specified operating conditions.

2.Functional operation under any of these conditions is not implied.

3.Applied voltage must be current limited to a specified range.

OPERATING CONDITIONS

Characteristics

Symbol

Min

Typ

Max

Units

5-V supply voltage (measured to VSS)

3.3-V supply voltage (measured to VSS)

Ambient operating temperature, still air

V

4.75

3.0

5.0

3.3

5.25

3.6

70

V

DD5

DD3

T

-20

°C

A

Modified on May/04/2000

PAGE 89 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

ELECTRICAL CHARACTERISTICS

Characteristics

MULTIMEDIA VIDEO

Symbol

Min

Typ

Max

Units

Supply

+5V (VDD, VDDA, VDDA1), normal operation

+3.3V (VDD3), normal operation

I

150

141

90

mA

DD5

DD3

DD5

DD3

+5V (VDD, VDDA, VDDA1), power down mode I

+3.3V (VDD3), power down mode

Analog Characteristics

I

5

Integral linearity error (AGC/ADC only)

Differential linearity error (AGC/ADC only)

Total harmonic distortion (4 MHz full scale)

Signal to noise ratio (4 MHz full scale)

Analog bandwidth (50 IRE to 3 dB point)

Input voltage range (peak-peak) 100 IRE input

Input resistance AY0-AY2,AC0-AC2

Input capacitance for analog video inputs

Charge current for offset control

E

1.0

0.5

54

3.0

1.5

lsb

I-ADC

D-ADC

THD

SNR

BW

V

dB

42

dB

4

MHz

0.5

200

1.5

-50

V

pp

I(PP)

R

kW

pF

mA

dB

IN

C

10

±4

I

OFF

Cross talk between analog inputs

Video Performance

a

-42

Luminance frequency response (maximum

variation to 4.2 MHz - multi burst)

F

1.5

dB

%

LUMA

Differential gain - complete chip (Modulated 40

IRE ramp)

D

G

Differential phase - complete chip (Modulated

40 IRE ramp)

1.0

degree

kHz

P

Chrominance frequency response (3 dB point) - F

CBWR=0/1

800/500

1

CHROMA

Chroma nonlinear gain distortion (NTC-7

Combination)

C

%

NGD

NPD

LI

Chroma nonlinear phase distortion (NTC-7

Combination)

C

1.25

1

degree

IRE

Chroma to luma intermodulation (NTC-7

Combination)

Chroma luma gain equality (NTC-7 Composite) DEL

±20

98-101

-58

ns

%

CL

Chroma luma delay equality (NTC-7 Composite) AMP

CL

Noise level for unified weighting 10 kHz-5 MHz N

(100 IRE unmodulated ramp)

dB

LUMA

Chroma AM noise (red field)

Chroma PM noise (red field)

N

-60

-54

dB

CAM

CPM

Modified on May/04/2000

PAGE 90 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

Characteristics

Symbol

Min

Typ

Max

Units

Digital I/O Characteristics

Input low voltage (other digital I/O)

Input high voltage (other digital I/O)

Input low voltage (SCLK,SDAT,RST)

Input high voltage (SCLK,SDAT,RST)

V

VSS-0.5

2.0

0.8

VDD+0.5

0.3VDD

VDD+0.5

-1

V

IL

IH

VSS-0.5

0.7VDD

V

ILI2C

IHI2C

V

Input low current (V = 0.4 V)

I

mA

V

IN

IL

IH

Input high current(VIN=2.4)

-1

Digital output low voltage (I =3.2mA)

V

0.4

OL

Digital output high voltage (IOH=400mA)

Digital three-state current

2.4

V

OH

I

50

7

mA

pF

OZ

Digital output capacitance

C

OUT

Maximum capacitance load for digital data pins C

30

60

L-DATA

C

L-CK

Maximum capacitance load for CK and CK2

outputs

Timing Characteristics - Digital Inputs

XTALI input pulse width low

t

15

20

ns

pwlX

XTALI input pulse width high

pwhX

Clock and Data Timing

Analog video input to digital video output delay

t

120

CK

ns

dCHIP

Pulse width high for CK (KS0112 operates at

frequencies from 24.5 MHz to 29 MHz)

15

30

18.5

22

44

pwhCK

Pulse width high for CK2

t

37

4

ns

pwhCK2

Delay from rising edge of CK to CK2

CK2

Delay from rising edge CK to data change

(including pins Y0-Y7, C0-C7, HAV, VAV, EHAV,

EVAV, HS1, HS2, VS, ODD, PID, SCH)

16

23

21

dD

(CK is output)

t

14

ns

dD

(CK is input)

Minimum hold time from rising edge of CK for

data output)

t

7

hD

Delay from falling edge of OEN to data bits in

3-state

20

18

zD

Delay from rising edge OEN to data bits

enabled

enD

Timing Characteristics -IIC Host Interface

SCLK clock frequency

r

0

400

kHz

pF

ms

SCLK

Capacitive load for each bus line

Hold time for START condition

Setup time for STOP condition

Rise and fall times for SCLK and SDAT

C

b

t

0.6

20

hSTA

sSTO

ms

t , t

300

ns

R

F

Modified on May/04/2000

PAGE 91 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

Characteristics

Symbol

Min

Typ

Max

Units

SCLK minimum pulse width low

t

1.3

0.6

100

0

ms

ns

pwlSCLK

SCLK minimum pulse width high

pwhSCLK

SDAT setup time to rising edge of SCLK

SDAT hold time from rising edge of SCLK

SDAT

s

hSDAT

Note: AC/DC characteristics provided are per design specifications.

Modified on May/04/2000

PAGE 92 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

t_pwhCK

CK

t_pwhCK2

CK2

t_CK2

OEN

t_hD

Y,C,AV

VS,HS,ODD

SCH,PID

t_dD

t_zD

t_enD

Figure 41. Data Output

Analog Video

Input

Digital Video

Active video

Blank

Active video

Output

t_dCHIP

Figure 42. Analog Video Input to Digital Video Output Delay

SDAT

SCLK

t_BUF

t_hSDAT

t_sSTO

t_R

t_pwhSCLK

t_F

t_hSDA

t_sSDAT

t_pwlSCLK

Figure 43. IIC Host Interface Detailed Timing

Modified on May/04/2000

PAGE 93 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

VCC

FE. BEAD

0.1 mF

3.3V

10 mF

84

AY0

AY1

56

55

54

53

48

47

86

88

Y7

Y6

Y5

Y4

Y3

Y2

AY2

90

92

AC0

AC1

46

45

Y1

Y0

44

39

38

37

36

35

C7

C6

C5

C4

C3

C2

94

AC2

0.1 mF

75

34

33

C1

C0

77

VRT

78

96

97

S5D0127X01

VRB

26

76

23

25

5

3

4

22

17

24

15

18

21

HS1

HS2

VS

HAV

EHAV

VAV

EVAV

ODD

PID

SCH

OEN

TEST

COMP2

0.1 mF

8

7

XTALI

24.576 MHz

XTALO

22 pF

CK

CK2

75

72

69

70

SCLK

SDAT

AEX0

AEX1

57

TESTEN

HS2

20 k

Modified on May/04/2000

PAGE 94 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

Package Dimension

MULTIMEDIA VIDEO

100-QFP-1420D

23.90±0.30

20.00±0.20

0.10MAX

#100

#1

0.30±0.10

0.10MAX

(0.58)

0.00MIN

3.00MAX

0.65

2.65±0.10

0.80±0.20

Dimensions are in Millimeters

Modified on May/04/2000

PAGE 95 OF 96

ELECTRONICS

S5D0127X01 Data Sheet

MULTIMEDIA VIDEO

SAMSUNG SEMICONDUCTOR WORLDWIDE OFFICES

HEAD OFFICE

SAMSUNG ELECTRONICS JAPAN CO., LTD.

8/11FL., SAMUNG MAIN BLDG.

250, 2-KA, TAEPYUNG-RO,

CHUNG-KU, SEOUL, KOREA

TEL: 2-727-7114

HAMACHO CENTER BLDG.

31-1, NIHONBASHI-HAMACHO, 2-CHOME

CHUO-KU, TOKYO 103, JAPAN

TEL: 3-5641-9850

FAX: 2-753-0967

FAX: 3-5641-9851

SEMICONDUCTOR BUSINESS

SALES & MARKETING DIVISION

SAMSUNG ELECTRONICS HONG KONG CO., LTD.

65TH FL., CENTRAL PLAZA

18 HARBOUR ROAD

WANCHAI, HONG KONG

TEL: 852-2862-6900

15/16FL., SEVERANCE BLDG.

84-11, 5-KA, NAMDAEMOON-RO

CHUNG-KU, SEOUL, KOREA

TEL: 2-259-1114

FAX: 852-2866-1343

FAX: 2-259-2468

SAMSUNG ELECTRONICS TAIWAN CO., LTD.

SAMSUNG SEMICONDUCTOR INC.

30FL., NO.333 KEELUNG RD.

SEC 1, TAIPEI, TAIWAN, R.O.C

TEL: 886-2-757-9292

3655 NORTH FIRST STREET

SAN JOSE, CA 95134, U.S.A.

TEL: 408-954-7000

FAX: 886-2-757-7311

FAX: 408-954-7873

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SAMSUNG SEMICONDUCTOR EUROPE GMBH

80 ROBINSON RD., #20-01

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TEL: 65-535-2808

SAMSUNG HOUSE

AM KRONBERGER HANG 6

65824, SCHWALBACH/TS

TEL: 49-6196-663300

FAX: 49-6196-663311

FAX: 65-227-2792

SAMSUNG ELECTRONICS CO., LTD.

SHANGHAI OFFICE

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9F, SHANGHAI INTERNATIONAL TRADE CENTRE

NO.2200 YANAN(W) RD.

SHANGHAI, P.R.C. 200335

TEL: 8621-6270-4168

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GREAT WEST ROAD, BRENTFORD

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TEL: 181-380-7132

FAX: 8621-6275-2975

FAX: 181-380-7220

SAMSUNG ELECTRONICS CO., LTD.

SEMICONDUCTOR BUSINESS BEIJING OFFICE

15FL., BRIGHT CHINA CHANG AN BLDG.,

NO.7, JIANGUOMEN, NEI AVENUE

BEIJING, CHINA 100005

TEL: 8610-6510-1234(0)

.

Circuit diagrams utilizing SAMSUNG and/or SAMSUNG ELECTRONICS products are included as a means of illustrating typical

semiconductor applications; consequently, complete information sufficient for construction purposes is not necessarily given.

The information has been carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for

inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor devices described herein

any license under the patent rights of SAMSUNG and/or SAMSUNG ELECTRONICS, or others. SAMSUNG and/or SAMSUNG

ELECTRONICS, reserve the right to change device specifications.

LIFE SUPPORT APPLICATIONS

SAMSUNG and/or SAMSUNG ELECTRONICS products are not designed for use in life support applications, devices, or

systems where malfunction of a SAMSUNG product can reasonably be expected to result in a personal injury. SAMSUNG

and/or SAMSUNG ELECTRONICS’ customers using or selling SAMSUNG and/or SAMSUNG ELECTRONICS products for use

in such applications do so at their own risk and agree to fully indemnify SAMSUNG and/or SAMSUNG ELECTRONICS for any

damages resulting from such improper use or sale.

Modified on May/04/2000

PAGE 96 OF 96

ELECTRONICS


型号：	S5D0127X01
厂家：	SAMSUNG
描述：	MULTISTANDARD VIDEO DECODER/SCALER 多标准视频解码器/ SCALER 解码器
文件：	总96页 (文件大小：1508K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

S5D0127X01 [SAMSUNG]

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