S5D2400XXX-T0 [SAMSUNG]
Consumer Circuit, MOS, PQFP100;
| 型号： | S5D2400XXX-T0 |
| 厂家： | 
SAMSUNG |
| 描述： | Consumer Circuit, MOS, PQFP100 商用集成电路 |
| 文件： | 总92页 (文件大小：3008K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S5D2400X
Data Sheet
Revision 1.0
RECORD OF REVISIONS
Rev. No
0.0
Date
Page
Description of Change
2003/10
2004/09
First Release
1.0
39
5.12 Display Region Masking Control block addition
42,43
Register Map addition (0x0007~0x0009, 0x000E~0x000F)
Table of Contents
1 Overview .......................................................................................................................................7
1.1 Overview.................................................................................................................................7
1.2 Applications ...........................................................................................................................7
1.3 Features ................................................................................................................................7
2 Pin Information ..............................................................................................................................9
2.1 Pin Configuration.....................................................................................................................9
2.2 Pin Description..................................................................................................................... 10
3 Functional Block Diagram............................................................................................................. 12
3.1 System Block Diagram.......................................................................................................... 13
3.2 Functional Block Diagram...................................................................................................... 17
4 Solution Circuit for Application ...................................................................................................... 18
5 Functional Description................................................................................................................... 19
5.1 Clock Systems and System Operation Modes......................................................................... 19
5.2 De-Interlace.......................................................................................................................... 21
5.3 Timing Generator .................................................................................................................. 22
5.4 Scaler.................................................................................................................................. 23
5.5 Boost-Up.............................................................................................................................. 23
5.6 OSD (On-Screen Display)...................................................................................................... 24
5.7 Gamma................................................................................................................................ 33
5.8 Contrast Control.................................................................................................................... 34
5.9 Dither................................................................................................................................... 34
5.10 Test Pattern Generator (TPG)............................................................................................... 35
5.11 I2C Host Interface Protocol................................................................................................... 37
5.12 Display Region Masking Control........................................................................................... 39
6 Register Map............................................................................................................................... 40
6.1 Global Control Registers........................................................................................................ 40
6.2 Timing Generator Control Registers ........................................................................................ 44
6.3 De-Interlace Control Registers................................................................................................ 50
6.4 Image Scaling Control Registers............................................................................................. 53
6.5 Advanced Color Contrast Enhancement (ACE) Control Registers............................................... 55
6.6 Global Image Gain & Offset Control Register ........................................................................... 62
6.7 OSD Control Registers .......................................................................................................... 66
6.8 Gamma Correction Control Register........................................................................................ 76
6.9 OSD RAM Control Registers.................................................................................................. 79
Table of Contents (Continued)
7 Electrical Specification................................................................................................................. 80
7.1 Absolute Maximum Ratings ................................................................................................... 80
7.2 Recommended Operation Conditions ...................................................................................... 80
7.3 DC Electrical Characteristics ................................................................................................. 81
7.4 AC Electrical Characteristics ................................................................................................. 82
8 Package Dimension..................................................................................................................... 84
8.1 100-TQFP-1414 .................................................................................................................... 84
9 Fonts ...................................................................................................................................... 85
Figure of Contents
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
S5D2400X Pin Configuration...................................................................................9
S5D2400X System Block Diagram (ITU-R BT.656 Input to Single RGB Output)......... 13
S5D2400X System Block Diagram (ITU-R BT.656 Input to Dual RGB Output)............ 14
S5D2400X System Block Diagram (ITU-R BT.601 Input to Single RGB Output)......... 15
S5D2400X System Block Diagram (DVI Input to Single RGB Output)....................... 16
S5D2400X Functional Block Diagram .................................................................... 17
S5D2400X Solution Circuit for Application.............................................................. 18
Internal Clock System Diagram............................................................................. 19
OSD Font RAM................................................................................................... 25
OSD Display RAM............................................................................................... 26
OSD FONT Structure........................................................................................... 28
OSD Display RAM Structure ................................................................................ 28
OSD Position...................................................................................................... 29
OSD Multi Color Font Structure ............................................................................ 31
OSD Row Space................................................................................................. 32
Half Tone Block................................................................................................... 33
R-Channel Gamma Correction .............................................................................. 33
Error Diffusion Architecture................................................................................... 34
TPG Sync Signals............................................................................................... 35
Test Pattern Generation Method ........................................................................... 35
Built-in Test Patterns ........................................................................................... 36
PRELIMINARY DATASHEET
S5D2400X
1 OVERVIEW
1.1 OVERVIEW
S5D2400X scaling image processor is a display SOC designed for TFT-LCD monitors and TV systems. This chip
consists of Scaler, Deinterlace and ACE block. The chip receives the signal of digital RGB 24-bit or ITU-R
BT.656/601 format, deinterlaces the signal and sends the single or dual channel digital data (24-bit or 48-bit). The
chip provides the ACCE (Adaptive Color & Contrast Enhancement) function that minimizes color change and
improves brightness function, and has the built-in filter that improves sharpness.
The built-in OSD supports 512 ROM fonts of 12*18 matrix, and processes 28 RAM fonts.
1.2 APPLICATIONS
·
·
·
·
·
Multimedia LCD Monitors/TVs
Digital TVs
CRTs and Rear Projection TVs
Plasma Displays
Projection Displays
1.3 FEATURES
·
·
·
High-Quality Advanced Scaling
–
–
Fully Programmable Scale-Up Ratios
Scale-up or down for Horizontal and Vertical
Built-in OSD for LCD Monitor
–
–
512 ROM Fonts
28 RAM Fonts
Economic Output Clock Source
–
–
Built-In PLL Core
External X-tal Device
·
·
·
Supports I2C Bus Host Interface
R/G/B Gamma look-up table
Dithering
–
8 to 6 Dithering
7
PRELIMINARY DATASHEET
S5D2400X
·
Color & Contrast Management
–
–
–
–
–
Adaptive Contrast Control
Adaptive Brightness Control
Image Sharpness Control
Color Compensation
Boost Up Sub Zone
·
·
Digital RGB input
Video De-interlacing
–
–
–
ITU-R BT.656 Interfacing
ITU-R BT.601 Interfacing
Spatial Interpolation Filter
·
·
PKG Information
PKG: 100-TQFP-1414 (100TQFP)
–
Operating Conditions
–
–
1.8 Volts Core
3.3 Volts I/O
8
PRELIMINARY DATASHEET
S5D2400X
2 PIN INFORMATION
2.1 PIN CONFIGURATION
75
70
60
51
VDD3OP
BO7
76
80
50
BIO1
BIO0
VSS3OP
GIO7
GIO6
GIO5
GIO4
GIO3
GIO2
GIO1
GIO0
VDD3OP
RIO7
RIO6
RIO5
RIO4
RIO3
RIO2
RIO1
RIO0
VSS2I
VI7
BO6
BO5
BO4
BO3
BO2
BO1
BO0
VSS3OP
GO7
GO6
GO5
GO4
GO3
GO2
GO1
GO0
VDD2I
RO7
40
S5D2400X
TFT-LCD Image Navigator
90
RO6
RO5
RO4
RO3
30
26
VI6
VI5
VI4
RO2
100
1
10
20
25
Figure 1. S5D2400X Pin Configuration
9
PRELIMINARY DATASHEET
S5D2400X
2.2 PIN DESCRIPTION
I/O Legend : I = Input
O = Output
P = Power
G = Ground
Table 1. MCU Interface Pins
Pin Name
MIFSEL
I2CEN
SCSN
SCL
I/O
I
Pin No
Description
MCU I/F Logic Selection (Always High)
I2C Enable Signal (Always High)
Chip Select Signal. (Always High)
Serial Bus Clock
4
5
I
I
6
I
7
SDA
I/O
O
O
O
8
Serial Bus Data (I: Input Data, O: Output Data)
General Purpose Output 0
GPO0
GPO1
GPO2
58
59
60
General Purpose Output 1
General Purpose Output 2
Table 2. PLL Interface Pins
Pin Name
I/O
I
Pin No
11
Description
X1
X2
X-tal Input (Max 30 MHz)
X-tal Output
O
O
12
FILT
17
PLL External Loop Filter (Refer to the circuit diagram on Page
14.)
Table 3. Video Input Interface Pins
Pin No Description
Pin Name
VCK
I/O
I
I
20
Input Clock for Video Mode (De-Interlace)
VI[7:0]
22~29
ITU-R BT.656: Video Data Input Port
ITU-R BT.601: Y Data Input Port
Pull down by internal 70kW resistors
GVS
GHS
FLD
I
I
I
61
62
63
ITU-R BT.601: V-SYNC Input from Decoder
ITU-R BT.601: H-SYNC Input from Decoder
ITU-R BT.601: External FIELD Signal Input
10
PRELIMINARY DATASHEET
S5D2400X
Table 4. DVI Interface Pins
Pin No
Pin Name
RSTN
I/O
I
Description
9
System Reset (Low Active)
RIO[7:0]
I/O
31 ~ 38
Input or Dual Output Port RED[7:0]
ITU-R BT.601: UV Data Input Port
Pull down resistors
GIO[7:0]
BIO[7:0]
I/O
I/O
40 ~ 47
49 ~ 56
Input or Dual Output Port GREEN[7:0]
Pull down resistors
Input or Dual Output Port BLUE[7:0]
Pull down resistors
DVS
DHS
I
I
I
I
64
65
67
68
V-SYNC Input
H-SYNC Input
DCK
Input Clock
DDEN
Input Data Enable (Digital Input Mode)
Table 5. Panel Interface Pins
Pin Name
I/O
Pin No
Description
RO[7:0]
O
1~2
Single Output Port RED[7:0]
95~100
PCKO
PDEN
PVSO
PHSO
BO[7:0]
GO[7:0]
O
O
O
O
O
O
72
73
Output Clock
Output Data Enable
V-SYNC Output
74
75
H-SYNC Output
77~84
86~93
Single Output Port BLUE[7:0]
Single Output Port GREEN[7:0]
Table 6. Test Pins
Description
Pin Name
I/O
Pin No
SCAN
I
69
Scan Enable Signal for test. Not use normal condition
(Always Low)
TMD0
TMD1
I
I
70
71
Test Mode Selection 0 (Always Low)
Test Mode Selection 1 (Always Low)
11
PRELIMINARY DATASHEET
S5D2400X
Table 7. Supply Voltage and Ground Pins: 3.3 / 1.8 Volt
Pin Name
VSS2I
Pin Number
3, 30, 66
10, 39, 76
13, 48, 85
14
Description
Internal ground
VDD3OP
VSS3OP
VSSDP
VDDDP
VBBP
3.3V Output-Driver and Pre-Driver supply voltage
Output-Driver and Pre-Driver ground
PLL Digital ground
15
1.8V PLL Digital supply voltage
PLL Bulk-Bias ground
16
VSSAP
VDDAP
VDD2I
18
PLL Analog ground
19
1.8V PLL Analog supply voltage
1.8V Internal Supply voltage
21, 57, 94
Total Supply Voltage : 8 Pin (3.3V: 3 Pin, 1.8V: 3 Pin, PLL (1.8V): 2 Pin)
Ground : 9 Pin (3.3V: 3 Pin, 1.8V: 3 Pin, PLL (1.8V): 2 Pin, Analog (Bulk-Bias 1.8V): 1 Pin)
12
PRELIMINARY DATASHEET
S5D2400X
3 FUNCTIONAL BLOCK DIAGRAM
3.1 SYSTEM BLOCK DIAGRAM
ITU-R BT.656 Input to Single RGB Output System
RGB Output
18 24
LVDS
DISPLAY
PORT
or
PANNEL
PHSO/PVSO/
PDEN/PCKO
S5D2400X
* RGB Output
18-bit: RO2 - RO7
GO2 - GO7
BO2 - BO7
VCK
8
24-bit: RO0 - RO7
GO0 - GO7
Video
Decoder
Deinterlacer
BO0 - BO7
VI
OSC
PORT
HOST I/F
PORT
(ITU-R BT.656)
Video Input
X1
X2
SCL
SDA
X-tal
MCU
Figure 2. S5D2400X System Block Diagram (ITU-R BT.656 Input to Single RGB Output)
13
PRELIMINARY DATASHEET
S5D2400X
ITU-R BT.656 Input to Dual RGB Output System
RGB Output
48
LVDS
DISPLAY
PORT
or
PANNEL
PHSO/PVSO/
PDEN/PCKO
* RGB Output
S5D2400X
A Channel: RO0 - RO7
GO0 - GO7
BO0 - BO7
VCK
8
B Channel: RIO0 - RIO7
GIO0 - GIO7
Video
Decoder
Deinterlacer
BIO0 - BIO7
VI
OSC
PORT
HOST I/F
PORT
(ITU-R BT.656)
Video Input
X1
X2
SCL
SDA
X-tal
MCU
Figure 3. S5D2400X System Block Diagram (ITU-R BT.656 Input to Dual RGB Output)
14
PRELIMINARY DATASHEET
S5D2400X
ITU-R BT.601 Input to Single RGB Output System
RGB Output
18 24
LVDS
or
DISPLAY
PORT
PANNEL
PHSO/PVSO/
PDEN/PCKO
S5D2400X
* RGB Output
VCK/FLD
GVS/GHS
18-bit: RO2 - RO7
GO2 - GO7
BO2 - BO7
8
Video
Decoder
Deinterlacer
24-bit: RO0 - RO7
GO0 - GO7
UV
BO0 - BO7
8
Y
OSC
PORT
HOST I/F
PORT
(ITU-R BT.601)
* UV Data Input
Video
Input
X1
X2
SCL
SDA
8-bit: RIO0 - RIO7
* Y Data Input
8-bit: VI0 - VI7
X-tal
MCU
Figure 4. S5D2400X System Block Diagram (ITU-R BT.601 Input to Single RGB Output)
15
PRELIMINARY DATASHEET
S5D2400X
DVI Input to Single RGB Output System
* RGB Input
RGB Output
24
RIO0 - RIO7
GIO0 - GIO7
BIO0 - BIO7
LVDS
or
DISPLAY
PORT
PANNEL
PHSO/PVSO/
PDEN/PCKO
RGB Input
24
S5D2400X
TMDS
* RGB Output
DCK/DDEN/
DHS/DVS
RO0 - RO7
GO0 - GO7
BO0 - BO7
DVI Graphic
Input
OSC
PORT
HOST I/F
PORT
X1
X2
SCL
SDA
X-tal
MCU
Figure 5. S5D2400X System Block Diagram (DVI Input to Single RGB Output)
16
PRELIMINARY DATASHEET
S5D2400X
3.2 FUNCTIONAL BLOCK DIAGRAM
0
1
Boost-up
&
Sharpness
Control
RIO7-RIO0
GIO7-GIO0
BIO7-BIO0
0
1
0
1
Input data
Formatter
Scaling
Engine
SFC
BU_ON
SC_ON
VIDEO_ON
Adaptive
Coeff. gen
De-
interlacer
VI7-VI0
Scaling Controller
ITU-R.656
RO7-RO0
GO7-GO0
BO7-BO0
RGB
Gamma
Correction
Output
Data
Formatter
Contrast
Control
OSD
MIX
8 to 6-bit
Dither
PHSO
PVSO
PDEN
PCKO
OSD_ON
DCK
VCK
0
1
CKI
OSD
VIDEO_ON
Timing
Generator
RAM ROM
Fonts Fonts
X1
X2
Host Interface
CKO
PLL
Sync Delay Match
Hardware Reset
CKOSC
Int.OSC
FILT
RSTN
MIFSEL I2CEN SCL SDA
Figure 6. S5D2400X Functional Block Diagram
17
PRELIMINARY DATASHEET
S5D2400X
4 SOLUTION CIRCUIT FOR APPLICATION
OUT_CK
OUT_DE
OUT_VS
OUT_HS
I/O_BLUE7
I/O_BLUE6
I/O_BLUE5
I/O_BLUE4
I/O_BLUE3
I/O_BLUE2
I/O_BLUE1
I/O_BLUE0
I/O_BLUE[0...7]
+1.8VD1
+3.3VD2
76
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VDD3OP
BIO1
BIO0
O_BLUE7
O_BLUE6
O_BLUE5
O_BLUE4
O_BLUE3
O_BLUE2
O_BLUE1
O_BLUE0
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
BO7
BO6
BO5
BO4
BO3
BO2
BO1
BO0
VSS3OP
GO7
GO6
GO5
GO4
GO3
GO2
GO1
GO0
VDD2I
RO7
RO6
RO5
RO4
RO3
RO2
O_BLUE[0...7]
O_GREEN[0...7]
O_RED[0...7]
VSS3OP
GIO7
GIO6
GIO5
GIO4
GIO3
GIO2
GIO1
GIO0
VDD3OP
RIO7
RIO6
RIO5
RIO4
RIO3
RIO2
RIO1
RIO0
VSS2I
VI7
I/O_GREEN7
I/O_GREEN6
I/O_GREEN5
I/O_GREEN4
I/O_GREEN3
I/O_GREEN2
I/O_GREEN1
I/O_GREEN0
I/O_GREEN[0...7]
O_GREEN7
O_GREEN6
O_GREEN5
O_GREEN4
O_GREEN3
O_GREEN2
O_GREEN1
O_GREEN0
S5D2400X
I/O_RED7
I/O_RED6
I/O_RED5
I/O_RED4
I/O_RED3
I/O_RED2
I/O_RED1
I/O_RED0
I/O_RED[0...7]
100-TQFP-1414 (AN)
O_RED7
O_RED6
O_RED5
O_RED4
O_RED3
O_RED2
O_RED1
O_RED0
I_VIDEO7
I_VIDEO6
I_VIDEO5
I_VIDEO4
I_VIDEO3
I_VIDEO2
I_VIDEO1
I_VIDEO0
I_VIDEO[0...7]
VI6
VI5
VI4
D_GND
+3.3VD2
3.3K
3.3K
3.3K
100
100
100
VIDEO_CLK
SCL
SDA
4.7K
47nF
- ITU-R BT.656 Input Port
VI[0:7]: Video Data Input Port
VCK: Video Clock Input Port.
RSTN
3.9nF
+1.8VP
- ITU-R BT.601 Input Port
VI[0:7]: V Data Input Port
RIO[0:7]:UV Data Input Port
VCK: Video Clock Input Port
FLD: Field Signal Input Port
GHS: H-Sync Input Port
22pF
22pF
25MHz
1M
1.5uH
100nF
D_GND
GVS: V-Sync Input Port
D_GND
D_GND
Figure 7. S5D2400X Solution Circuit for Application
18
PRELIMINARY DATASHEET
S5D2400X
5. FUNCTIONAL DESCRIPTION
5.1 CLOCK SYSTEMS AND SYSTEM OPERATION MODES
5.1.1 Clock Systems
The chip supports switching of Separate-RGB signal or ITU-R BT.656/601 protocol video signal data. The Separate-
RGB data input clock is DCK, and the ITU-R BT.656/601 format video signal input clock is VCK. The external X-tal
oscillation clock X1 is a Free-Run Clock (Recommended 25MHz) which is used as the source clock of PLL in
creating data fetch and output clock for host interface. The external clock is created by internal PLL based on the X1
frequency input in accordance with the scaling factor, and is sent to the scaling output terminal and the Panel
Display Clock (PCKO). In other words, the clock system selects DCK/VCK as the external clock, uses the free-run
clock X1 as the source of output clock and for host I/F, and creates the output clock based on the scaling factor in
the internal PLL.
In order to reduce power consumption, it is possible to control the clock system to selectively enable/disable Scaler,
OSD, De-Interlacer, Boost-Up and other blocks. In the DPMS Mode, input and output clock is disabled, and only the
free-run X1 clock is enabled.
SFC (sampling Freq. Conversion)
Data-path
Input Domain
Output Domain
RIO7 - RIO0
GIO7 - GIO0
BIO7 - BIO0
RO7 - RO0
GO7 - GO0
BO7 - BO0
VI7 - VI0
Host I/F & Register
Control
DCK
VCK
CKI (Input Clock)
CKO (Output clock)
Internal Oscillator
CKOSC (Free-Run Clock)
X1
X2
Freq. Synthesis
PLL
Pre-divider
PCKO
Note: CKI, CKO, CKOSC: Internal clock Name
Figure 8. Internal Clock System Diagram
19
PRELIMINARY DATASHEET
S5D2400X
5.1.2 System Operation Modes
The operation mode is divided, depending on the application system, into separate RGB signal input so that the
signal can be used in the flat panel display, and processing of video signal entered to ITU-R BT.656/601. The built-in
auto tuning function and the de-interlace function may operate against each other. In this way, power consumption
can be minimized through management of the functional block.
The table below shows the example of On/Off operation sets. In the DPMS mode, all the functional blocks are off,
and only the host interface function works by X-tal clock X1. In the separate RGB input mode, only the BASIC_ON
register must be ON for simple 1:1 action. It is possible to expand, in the system level, the operation mode set which
is not described in the table.
Mode
ITU-R BT.656
Common
BU_ON OSD_ON BASIC_ON
Remark
VIDEO_ON
SC_ON
DPMS (No Sync)
Bypass 1
X
X
X
X
X
X
X
X
X
X
X
X
O
O
Standby (X1 Clock)
Sep. RGB (No Scale)
Bypass 2
O
Sep. RGB
No Scale + OSD
Bypass 3
X
X
X
O
O
O
O
O
O
X
X
O
O
X
O
O
O
O
O
Sep. RGB
No Scale + BU
Scale Up/Down 1
Scale Up/Down 2
Scale Up/Down 3
Scale Up/Down 4
Sep. RGB
All Operation
O
O
O
ITU-R BT.656
Scale + OSD
O
O
ITU-R BT.656
Scale + BU
O
ITU-R BT.656
All Operation
NOTES:
1. Ref. Register Map (0x0001[6:0])
2. "O " ® ON (Logical "H"), "X" ® OFF (Logical "L")
3. Description
¨ VIDEO_ON : De-Interlace ON / OFF for ITU-R BT.656/601 Video Mode
(separate-RGB or ITU-R BT.656/601 Mode Selection)
¨ SC_ON : Scaler ON / OFF
¨ BU_ON : Boost-Up ON / OFF for Image Enhancement
¨ OSD_ON : ON-Screen Display ON / OFF for User Control Mode
¨ BASIC_ON : Basic Logic Path ON / OFF (Always ON except DPMS Mode)
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PRELIMINARY DATASHEET
S5D2400X
5.2 DE-INTERLACE
The De-Interlace block receives the ITU-R BT.656/601 format data, and converts the luminance data and
chrominance data from interlace scan mode to progressive scan mode. The luminance data and chrominance data in
progressive scan are converted into Red/Green/Blue (RGB) data. The ITU-R BT.656 format data are separated into
horizontal sync, vertical sync, field information, luminance data and chrominance data, and ITU-R BT.601 format data
are separated into luminance data and chrominance data with horizontal sync, vertical sync and field information
received through the other pin.
5.2.1 Functions
·
·
·
·
·
·
·
Horizontal Sync Separation from ITU-R BT.656 Format Data
Vertical Sync Separation from ITU-R BT.656 Format Data
Field Information Separation from ITU-R BT.656 Format Data
Luminance Data Separation from ITU-R BT.656 Format Data
Chrominance Data Separation from ITU-R BT.656 Format Data
Interlace to Progressive Scan Conversion for Luminance and Chrominance Data
Red / Green / Blue (RGB) Data Conversion from Luminance / Cb / Cr (YCbCr) Data
5.2.2 ITU-R BT.656 Format Data Separation
The ITU-R BT.656 format data separation block separates horizontal sync, vertical sync, field information, luminance
data and chrominance data from the ITU-R BT.656 format data input.
Horizontal sync is in low state in blanking interval, and in high state in active interval. Vertical sync is in low state in
blanking interval and in high state in active interval. F is in high state in odd field, and in low state in even field. The
active data are a set of Cb/Y/Cr/Y.
5.2.3 Interlace to Progressive Scan Conversion
The Interlace to Progressive Scan Conversion (IPC) block converts the field structure of interlace scan into the frame
structure of progressive scan. In other words, 60 Hz / 30 frame (60 field) interlace scan is changed into 60 Hz / 60
frame progressive scan. In interlace to progressive scan conversion, the progressive scan line of 1 frame becomes
double of the interlace scan line. In S5D2400X, you can select whether to double the line or maintain the line as it is
when converting scan.
5.2.4 YCbCr to RGB Conversion
The YCbCr to RGB conversion block converts the Y / Cb / Cr data into the Red / Green / Blue data.
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PRELIMINARY DATASHEET
5.3 TIMING GENERATOR
S5D2400X
The timing generator makes timing for S5D2400X, and delivers the value required to make PCKO (output clock).
Using the input HS and VS, the block generates PHSO, PVSO and PDEN for output sync, and the signals made
with the optimum timing for each block are sent to other blocks. TG also delivers the value required for PCKO. It
sends the MCU setting value to internal PLL.
5.3.1 Output Timing Generation
Using input HS and VS, TG generates the output sync (PHSO, PVSO and PDEN). The active data area must be set
in input HS and VS. As shown in the following figure, set HIA_STR (0x0012, 0x0013), HIA_END (0x0014, 0x0015),
VIA_STR (0x0016, 0x0017), VIA_END (0x0018, 0x0019), HIAS (0x0020, 0x0021) and VIAS (0x0022, 0x0023).
H_Input_Total
HSW
HBP
H_Active Data_Area
HFP
Horizontal
Sync Input
H_Start_Point
H_End_Point
V_Input_Total
V_Active Data_Area
VSW
VBP
VFP
Vertical
Sync Input
V_Start_Point
V_End_Point
Figure 9 Output Timing Generation
The output signal can be set in HOFP (0x001A), HOSW (0x001B), HOBP (0x001C, 0x001D), VOFP (0x001E),
VOSW (0x001F), HOAS (0x0024, 0x0025), VOAS (0x0026, 0x0027).
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5.4 SCALER
The scaler of S5D2400X operates in the following three modes (Scale-Up, Scale-Down, Bypass).
5.4.1 Scale-Up
The scaler can perform scale-up from VGA to XGA (VGA ® SVGA, VGA ® XGA, SVGA ® XGA) in the DVI mode,
and from VGA to 100MHz (VGA ® SVGA, VGA ® XGA, VGA ® 100 MHz, SVGA ® XGA, SVGA ® 100 MHz,
XGA ® 100 MHz) in the ITU-R BT.656/601 mode. Different scaling ratio may be applied to H/V (Horizontal/Vertical)
direction.
5.4.2 Scale-Down
The scaler can perform scale-down from XGA to VGA (XGA ® SVGA, XGA ® VGA, SVGA ® VGA), and different
scaling ratio may be applied to H/V directions.
5.4.3 Bypass
In the bypass mode, the ratio between input and output image is 1:1. In this case, power consumption is decreased
if the scaler is OFF (0x001[1]). The bypass mode can be used together with the scale-up mode. In order to use the
two modes together, set Bypass (1:1) to horizontal direction and Scale-Up (VGP ® XGA) to the vertical direction.
5.5 BOOST-UP
The boost-up block provides you a clear screen.
5.5.1 Adaptive Contrast Control
This function provides a clearer view of a part of or the entire screen by sorting the color to find the maximum,
minimum and average value and perform the contrast control processing, and replacing the color with the adaptively
calculated color.
5.5.2 Adaptive Brightness Control
This function provides a brighter screen based on a given LUT value. LUT is 0 ~ 255, and is mapping by 1:1.
5.5.3 Image Sharpness Control
The image sharpness control processing provides a more distinctive view of each color by increasing sharpness of
boundary of each color.
5.5.4 Color Compensation
A color can be distorted on the screen and may look like a completely different color. The color compensation circuit
corrects this problem and maintains the original color.
5.5.5 Boost Up Sub Zone
Boost Up function recognizes the current status of the screen, and reflects the result on the screen. The screen area
to be recognized is called "sub zone". Setting the sub zone is necessary because the screen may be affected by
other data than the actual video image.
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5.6 OSD (ON-SCREEN DISPLAY)
OSD function provides outward GUI between TFT_LCD Monitor and End-User, enabling the user to easily control the
environment of TFT-LCD monitor.
OSD supports up to 512 ROM fonts; 16 MCF (Multi-Colored Font) and 464 SF (Standard Font). OSD can be set on
certain area of the screen with certain size.
5.6.1 OSD Fonts
1) ROM Font
·
·
·
7 languages
464 Standard Fonts (SF)
16 Multi-Colored Font (MCF)
2) RAM Font
·
·
User Definable Font
Max. 28 SF, Max. 9 MCF
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3) Font RAM Structure
S5D2400X
Font RAM is assigned of 1008 addresses (from 0x3FFF to 0x43EE). Where, 1008 is (8 row * 28 fonts) * 2 = 504 * 2.
1008/28 = 36, and therefore, 36 addresses are assigned to a font. Because the host interface transports data in the
unit of 8 bits, in order to configure a font of 12*18 as shown in Figure 10, the upper 4 bits and the lower 8 bits of 1line
(12 bits) are assigned as an address. The upper 4 bits are transported as the even address and the lower 8 bits are
transported as the odd address to Font RAM, respectively.
Even address
odd address
FONT RAM
1
2
0x3FFF
0x4000
0x4001
0x4002
0x4003
0x4004
0x4005
0x4006
0x4007
0x4008
0x4009
0x400A
0x400B
0x400C
0x400D
0x400E
0x400F
0x4010
0x4011
0x4012
0x4013
0x4014
0x4015
0x4016
0x4017
0x4018
0x4019
0x401A
0x401B
0x401C
0x401D
0x401E
0x401F
0x4020
0x4021
0x4022
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Figure 10. OSD Font RAM
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4) Display RAM Structure
S5D2400X
Display RAM is assigned of 900 addresses (0x2000 ~ 0x2383). As 900/450 = 2, 2 addresses are assigned to a
display Ram cell. Because the host interface transports data in the unit of 8 bits, in order to form the display RAM
cell that uses 16 bits as a cell, 2 addresses must be transported. Figure 11 shows the structure of display RAM cell.
Font RAM
12
Display RAM
Font
Number
0x2000
3
2
0x2001
0x2002
0x2003
0x2004
0x2005
0x2006
0x2007
0x2008
0x2009
0x200A
0x200B
0x200C
0x200D
0x200E
0x200F
0x2010
0x2011
0x2012
0
1
2
3
18
3
0
A
B
C
5
13
11
10
27
15
0x2013
...
. . .
0x2382
0x2383
1
Boder/
shadow
Font
Color (FC)
Ram/Rom
Select
BLINK
Even Address
Odd Address
27
&
Font Number
Display RAM Cell
Figure 11. OSD Display RAM
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5) Font RAM Clear
S5D2400X
This function clears the font RAM based on rising edge detect. The font RAM is cleared by power on reset or
FTRAM_CLRN Register. The operation time is 1 Clock, and no delay is made.
The refresh region indicates that "0" value will be given to the entire memory.
Down load or clear works only when OSD_ON Register is On.
In basic operation the font RAM clear function is not required. Using the function in basic mode may cause data loss
or other critical problems.
6) Display RAM Clear
This function clears display RAM based on the rising edge detect. The RAM is cleared by power on reset or
DSRAM_CLRN Register.
The operation time is 1 Clock, and no delay is made.
5.6.2 OSD Windows
1. Flexible OSD Size:
·
·
Displays up to 64 fonts in horizontal within the range of 450 fonts
Displays up to 64 fonts in vertical within the range of 450 fonts
2. Up to 4 multiple Windows (1 Main Window + 4 Multiple Windows)
3. Up to 32 Windows color including intensity
4. Programmable multiple Windows shadow color/size
5. Fine Windows bordering
6. Pop up / down-able multiple Windows
7. Font position mapping based multiple Windows horizontal/vertical start / end point adjustment
8. Transparency: Input image / OSD image mix.
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5.6.3 System Description
S5D2400X
OSD stores ROM and font RAM address and features on the display RAM, displays the font and its features at the
designated position, and displays on the screen the features designated in OSD register.
1) FONT
OSD font consists of 12 ´ 18 (width ´ length) pixels, and is divided into character and raster when displayed on the
screen.
12
Raster
Font
Character
18
A
Figure 12. OSD FONT Structure
Font color can be controlled by FC of display RAM. Each font can have 16 character colors and 16 raster colors. FC
value is used as a reference of LUT to control character color and raster color.
2) User Definable OSD area
OSD area is defined with the number of OSD horizontal fonts and the number of OSD vertical fonts to be displayed
on the screen by OSD_HFONT[5:0] and OSD_VFONT[5:0]. OSD_HFONT and OSD_VFONT are assigned of 6 bits
each, generating 64 horizontal/vertical fonts respectively. Because the maximum size of display RAM is limited to
450, it must meet OSD_HFONT*OSD_VFONT £ 450. (RAM Address 0 ~ 449) If OSD_HFONT is set to 30 and
OSD_VFONT to 10, OSD area is displayed as shown below. In this case, Addresses 0~299 of the display RAM are
used for display.
Display RAM
Address 0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
1
2
A
L
P
H
A
Display RAM
Address 30
3
4
5
6
7
8
9
10
Figure 13. OSD Display RAM Structure
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5.6.4. Functions
1) OSD Position
Start position of OSD can be changed via OSD_HSP and OSD_VSP of the OSD register.
Horizontal Active Area
(1, 1)
(OSD_HSP, OSD_VSP)
OSD Window Border Component
(LUO, LUI, RLI, RLO, TK, TN)
LUO
LUI
TK
OSD Area
TN
RLI
RLO
Vertical Active Area
Figure 14. OSD Position
2) Font size control
OSD fonts are saved in FontRAM or ROM in the unit of 12 bits, displayed as a 12*18 font through No. 18 access and
display. The horizontal and vertical size of a font can be 1x, 2x, 3x and 4x through adjustment of CH_HSZ and
CH_VSZ.
3) Character Border/Shadow
Character Border/Shadow of a font can be implemented through CH_BDSH_EN setting in OSD register, and with 1or
0 (1: Border, 0: Shadow) selection of CH_BDSH of display RAM.
4) Blink Control
OSD blink can be controlled by font. Font blinking function is enabled through BL_NTRA (BLink or NoToneRAster)
setting and display RAM blink setting.
BLNK_SEL is used to adjust blink duty as the blink function is enabled.
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BLNK_SEL
Blink OFF
0.5 sec
1 sec
Blink ON
0.5 sec
0.5 sec
1 sec
0
1
2
3
4
5
6
7
0.5 sec
1 sec
1 sec
1.5 sec
2 sec
1.5 sec
1 sec
1 sec
2 sec
2 sec
2 sec
BLNK_C supports the color inversion of the blinking character. If BLNK_C is enabled, the complementary color of the
font raster color is displayed in the character area during blink-off. If BLINK_C is reset, the raster color is displayed in
the character area during blink-off.
5) Intensity control
OSD intensity can be controlled by frame. It is possible to control 16 colors by character / raster in reference to LUT
of Display RAM FC (Font Color), or 32 colors by frame by toggling INTENSITY bit.
6) Multi-Colored font control
OSD provides 512 ROM fonts to display the icon, generating Multi-language OSD icon. Out of 512 ROM fonts, 464
fonts are the standard fonts (Single-Color) and 16 (16*3 = 48) fonts are multi-colored fonts. Each multi-colored font
consists of three color attribute ROM fonts. The three fonts make a multi-colored font with OR operation. In order to
access a multi-colored font, the R-color attribute font is addressed. For example, 1D0h, 1E0h and 1F0h address
indicate R, G and B-color attribute fonts respectively. By addressing 1D0h, a multi-colored font can be accessed
through OR operation of 1D0h, 1E0h and 1F0h color attribute fonts.
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1
0
R
Y
G
C
B
1D0h : Red
1E0h : Green
1F0h : Blue
Masked data of multi-color font: 1D0h
Displayed font: 1D0h
Figure 15. OSD Multi Color Font Structure
The multi-colored font (MCF) of the RAM font is made in the same way as the Standard Font (SF) is formed. MCF
count can be adjusted through the N_MCF value, and 28 fonts except MCF are used as SF.
7) External OSD control
If the external OSD is enabled (EXT_OSD_SEL == 1), the external OSD expresses the color in reference to LUT of
S5D2400X_OSD. For color mapping, refer to 4-3. Receiving R, G, B, I, EN input from the external OSD,
S5D2400X_OSD decodes the 4 inputs except EN, and displays each color value. External OSD input is delayed by
2Pixel clock before displayed. Even if external OSD is used, S5D2400X_OSD supports half tone. In order to apply
half tone to font raster and not to apply half tone to the character, the values between 0000b and 1011b shall be
assigned to R, G, B, I.
(OSD_TONE == 0, CH_TONE == 0)
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8) Blank font control
S5D2400X
By accessing and displaying 000h address of ROM, it is possible to display only input image within the OSD area.
This ROM 000h address called a blank font has several useful functions. For example, multiple Windows can be
displayed on the OSD area only. The function can be used to display multiple Windows without the OSD area.
9) Row Space
A row space indicates the space in vertical direction between the fonts displayed on OSD. S5D2400X_OSD assigns
0-15 to ROW_SP to implement the row space.
A row space is displayed on the screen via interworking with Character Vertical Size (CH_VSZ).
In other words, if CH_VSZ is 1 and ROW_SP is 3, the row space actually displayed is 6 pixels. The maximum
number of vertical pixels of a row space to be displayed is 4*15 (CH_VSZ == 3, when ROW_SP == 15).
If row space is enabled, the raster is extended as many as the row space pixels on the top or bottom of a font.
Figure 18 shows the details. (when ROW_SP == 1, and CH_VSZ == 0).
If row space is applied, the multi color Ram font has extended row on the top and bottom of the font.
A
B
Row Space
Row Space
20
18
18
Figure 16. OSD Row Space
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10) Half Tone (Transparency) Control
Half tone of S5D2400X_OSD is made via mixing of input image and OSD image.
Where, OSD_TONE[1:0] is used as a weight for mixing of image and OSD image.
w
Input Image
Half Tone Image
OSD Image
1-w
Figure 17. Half Tone Block
5.7 GAMMA
The gamma correction block performs gamma compensation to complement the TFT-LCD panel features. The block
divides the input signal level to various sections, makes non-linear feature curve for each section, and by linear
interpolation of each section, performs gamma compensation. In other words, the block divides the input into
sections, and changes the output value of each section to deform specific curves for gamma compensation. An input
signal has 8 bits digital level, it is evenly divided into 32 sections with the space of 8.
The block receives output value for each evenly spaced level from MCU, performs non-linear gamma compensation,
and performs linear interpolation for the values between the levels. Gamma compensation is applied to each of RGB
data in the same way, but the output values can be changed respectively.
Y
RYAV32
RYAV31
RYAV30
RYAV4
RYAV3
RYAV2
RYAV1
X
0
8
16 24 32
240, 248, 255,
. . . .
Figure 18. R-Channel Gamma Correction
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5.8 CONTRAST CONTROL
S5D2400X
Contrast block is applied to all pixels, and can control the boost-up area and other areas respectively. Blacklevel and
brightness play the role of offset, and contrast works as gain.
Each pixel value is acquired in the following process.
Rout = [Rin - Blacklevel(Red)] * Contrast(Red) + Brightness(Red)
Gout = [Gin - Blacklevel(Green)] * Contrast(Green) + Brightness(Green)
Bout = [Bin - Blacklevel(Blue)] * Contrast(Blue) + Brightness(Blue)
5.9 DITHER
5.9.1 Enable Dither
The dithering block supports the following 4 modes.
Table 8. Dither Mode
DTH_MODE[1:0]
Operation mode (I/O and RGB data valid bit count)
Bypass mode (8-bit RGB input, 8-bit RGB output)
ED mode (8-bit RGB input, 6-bit RGB output)
000
101
5.9.2 Error Diffusion (ED) Method
The following figure illustrates the block diagram of error diffusion dithering. The block diagram is made for R, but can
be applied to G and B in the same manner.
R
THRESHOLD
R_D
ERROR FILTER
Figure 19. Error Diffusion Architecture
The threshold block cuts off the lower 2 bits. Therefore the cut 2 bits are used as the input to the error filter.
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5.10 TEST PATTERN GENERATOR (TPG)
TPG internally generates a pattern for sync and test without input sync and data. In order to enable TPG,
TEST_PAT_ON (0x0001[7]) must be High.
5.10.1 TPG Sync Signals
Figure 20 illustrates the internally generated sync.
64
3
120
16
16
1
Active Data Area
Active Line Area
HS
VS
Figure 20. TPG Sync Signals
The active data area and the active line area in Figure 20 are determined by TP_RESOLUTION (0x0006 [7:6]).
Table 9. Active Pattern Areas
PATTERN_SIZE
0
1
2
ACTIVE AREA (H*V)
VGA (640*480)
SVGA (800*600)
XGA (1024*768)
5.10.2 Test Patterns
The pattern to be used as input data to scaler is selected by TP_TYPE(0x0006[5:0]). For Bit [5], 0 is pass and 1
inverts image. For Bit [4], 0 sends normal pattern and 1 sends H/V ramp waveform. Other bits are described in
Figure 21.(a) and (b). Figure 21.(a) illustrates the ramp waveform selection in H/V direction when Bit [4] is 1. Figure
22 (a) shows the example. Figure 21.(b) shows the example when bit [4] is 0. If the lower 4bits are 0~5, the screen
pattern is as displayed in Figure 22.(b). The other values from 6~15 display the white screen.
[5] [4] [3] [2] [1] [0]
1
[5] [4] [3] [2] [1] [0]
0
0 - 5
INV.
0~7:Ramp wavelength interval
INV.
PATTERN INDEX
(b)
H/V SEL
(a)
Figure 21. Test Pattern Generation Method
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1
1
1 0 0 0
1
1
1 0 0 1
1
1
0 0 0 0
1 1 0 0 0 1
0
1
1 0 0 0
0
1
1 0 0 1
0
1
0 0 0 0
0 1 0 0 0 1
(a)
0 : Boundary
1 : Diagonal
Ramp
2 : ON/OFF
3 : H-Line
4 : V-Line
5 : BLACK
(b)
Figure 22. Built-in Test Patterns
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5.11 I2C HOST INTERFACE PROTOCOL
S5D2400X supports data communication through I2C protocol based host interface. The slave address for a device ID
is 7 bits (binary "0000101"). The address is made with 15 bits with 8 bits data depth. Therefore, in order to access an
address, 2 bytes (Address MSB, Address LSB) are indexed with 1 byte data depth. Because the address bits are 15
bits, the 1 byte of the address MSB is Binary "X A
A
A
A
A
A A ", and the 1 byte of the address LSB is
14 13 12 11 10 9 8
Binary "A A A A A A A A ".
7
6
5
4
3
2
1
0
5.11.1 Timing Chart (Data sequence for register write/read of n registers)
Write Data Sequence
SDA
SCL
Device ID
W
Address MSB
Start
ACK
ACK
SDA
SCL
Address LSB
Data 1
ACK
ACK
SDA
SCL
Data 2
Data n
ACK Stop
Read Data Sequence
SDA
Device ID
Address LSB
Data 2
Address MSB
R
SCL
Start
ACK
ACK
SDA
SCL
Data 1
ACK
ACK
SDA
SCL
Data n
ACK Stop
The figure below shows the device ID and read/write byte for the slave address in the above timing chart.
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0
0
0
0
1
0
1
R/W
DEVICE ID
(R = 1, W = 0)
Because an address is 15 bits, the 1 bit of the address MSB is remained. Set 0 or 1 (Don't Care : X) for the 1 bit.
5.11.2 Example
Write to one register
·
·
·
·
·
·
Send Start Signal
Send Device ID Byte (R/W Bit = LOW)
Send Address MSB
Send Address LSB
Send Data to Address
Send Stop Signal
Write to four consecutive register
·
·
·
·
·
·
·
·
·
Send Start Signal
Send Device ID Byte (R/W Bit = LOW)
Send Address MSB
Send Address LSB
Send Data 1 to Address
Send Data 2 to (Address + 1)
Send Data 3 to (Address + 2)
Send Data 4 to (Address + 3)
Send Stop Signal
Read from one register
·
·
·
·
·
·
Send Start Signal
Send Device ID Byte (R/W Bit = HIGH)
Send Address MSB
Send Address LSB
Receive Data from Address
Send Stop Signal
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Read form four consecutive control registers
·
·
·
·
·
·
·
·
·
Send Start Signal
Send Device ID Byte (R/W Bit = HIGH)
Send Address MSB
Send Address LSB
Receive Data 1 from Address
Receive Data 2 from (Address + 1)
Receive Data 3 from (Address + 2)
Receive Data 4 from (Address + 3)
Send Stop Signal
5.12 DISPLAY REGION MASKING CONTROL
As shown in the following figure, HMIN set the left boundary, HMAX set the right boundary, VMIN set the upper
boundary and VMAX set the lower boundary.
HMAX is assigned of both address 0X007[0] and 0X0009[7:0], Position of HMIN, HMAX, VMIN and VMAX has the
setting value of 4 times.
VMIN
VMAX
Actual Image Display Region
HMAX
Display Region
HMIN
In this way, Actual image display region can be selected flexibly, and the other display region is displayed black
level.
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6 REGISTER MAP
6.1 GLOBAL CONTROL REGISTERS
Bits
Register Name
0x0000
Function
GLOBAL_RESET (Default: 0 x 01)
R/W
7:2
1
Reserved
FREE_RUN
Pseudo sync RUN mode (1: ON, 0: OFF (Default))
- When to use : Power on, mode switch, and recovery from Over
Sync/Under Sync DPMS
0
SOFT_RSTN
Resets the chip in software level except User Register (The register defined
in the spec data sheet). (Low Active)
- When to use: Power ON and mode switch
- How to use: Set the chip to 0, reset, and then to 1.
(Reset time must be 1uS or higher (1 Clock) without delay.)
The last "N" of the Register Name indicates Active Low Soft Reset.
0x0001
GLOBAL_BLOCK_CONTROL (Default: 0 x 03)
R/W
7
6
TEST_PAT_ON
Blocks input regardless of external data input status, and displays the
internal test pattern.
Test Pattern (1: ON, 0: OFF (Default))
VIDEO Mode & DVI Mode
VIDEO_ON
(1: VIDEO Mode, 0: DVI Mode (Default))
Reserved
5
4
3
2
1
BU_ON
Boost Up (1: ON, 0: OFF (Default)). Do not use in the DVI mode.
OSD (1: ON, 0: OFF (Default))
OSD_ON
Reserved
SC_ON
- Up to 10x for Scaling-Up and up to 1/2x for Scaling-Down
- The screen size is not changed when switching OFF SC_ON
when the target resolution and the input resolution are the same
(1x Scaling).
- In bypass status, only scaling is bypassed. Therefore, PMS setting
must be performed.
(1: Scaler ON, 0: Scaler OFF (Default))
0
BASIC_ON
In the Normal operation status, Basic logic must be always On.
(1: Basic Logic ON (Default), 0: Basic Logic OFF)
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0x0002
GLOBAL_IO_CONTROL (Default: 0 x 00)
Reserved
Pulse Width Modulation1
R/W
7:4
3
PWM1_ON
1: ON (PWM_DATA1(0x000D 7:0h) signal is sent through GP01 Pin)
0: OFF(GPO1(Ox000B 1h) signal is sent through GP01 Pin)
Pulse Width Modulation0
2
PWM0_ON
1: ON (PWM_DATA0 (0x000C 7:0h) signal is sent through GPO0 Pin)
0: OFF(GPO0(0x000B 0h) signal is sent through GPO0 Pin)
Reserved
1
0
PLL_PWR_SAVE
Scaler PLL Power Down Mode for system CLK generation (CKO)
(1: PLL Power Down Mode, 0: Normal Mode)
0x0003
GLOBAL_OUTPUT_CONTROL (Default: 0 x 38)
Reserved
R/W
7:6
5
ROUT_EN
GOUT_EN
BOUT_EN
RIN/OUT_EN
RO (R-channel Output) Enable of PIN NO 1~2, 95~100 ROUT
(1: Enable (Default), 0: Disable)
4
3
2
GO (G-channel Output) Enable of PIN NO 86~93 GOUT
(1: Enable (Default), 0: Disable)
BO (B-channel Output) Enable of PIN NO 77~84 BOUT
(1: Enable (Default), 0: Disable)
Determines whether to use RIO of PIN NO 31~38 as output or input.
If the OCHMD bit is 0, RIO is used as input regardless of RIN/OUT_EN bit
control.
If the OCHMO bit is 1, RIO is used as input or output depending on
RIN/OUT_EN bit control. (1: Output, 0: Input (Default))
1
0
GIN/OUT_EN
BIN/OUT_EN
Determines whether to use GIO of PIN NO 40~47 as output or input
If the OCHMD bit is 0, GIO is used as input regardless of GIN/OUT_EN bit
control.
If the OCHMO bit is 1, GIO is used as input or output depending on
GIN/OUT_EN bit control. (1: Output, 0: Input (Default))
Determines whether to use BIO of PIN NO 49~56 as output or input.
If the OCHMD bit is 0, BIO is used as input regardless of BIN/OUT_EN bit
control.
If the OCHMO bit is 1, BIO is used as input or output depending on
BIN/OUT_EN bit control. (1: Output, 0: Input (Default))
41
PRELIMINARY DATASHEET
S5D2400X
0x0004
GLOBAL_PHASE_CONTROL ((Default: 0 x 00)
Reserved
R/W
7:6
5
CKI2_PHASE
Changeable 2-Times Input Clock Phase (1: Phase Inverse, 0: Normal)
Reserved
4:0
0x0005
GLOBAL_CKO_CONTROL (Default: 0 x 00)
Reserved
R/W
7:6
5:4
CKO_SEL
CKO Clock source Select (Always 00)
(00: PLL Output is used 01,10,11: Not used)
3
CKO2_PHASE
PCKO_PHASE
Changeable 2-Times Scaler Output Clock Phase
(1: Phase Reverse, 0: Normal)
2:0
Scaler Output Clock(PCKO) Time Delay
- PCKO_PHASE[2] : PCKO Phase Inverse.
- PCKO_PHASE[1:0] : X ns Delay (X = PCKO_PHASE[1:0])
0x0006
GLOBAL_PATTERN_CONTROL (Default: 0 x 80)
R/W
R/W
7:6
5:0
PATTERN_SIZE
Pattern Size select
(00: VGA, 01: SVGA, 10: XGA (Default), 11: Unused)
PATTERN_SEL
Selecting Test Pattern Type (Default: 0)
0x0007
HMAX[8]
GLOBAL_H_MASKING_CONTROL (Default: 0 x 00)
0
Horizontal Masking Max Number
(The MSB of HMAX [address 0x0009])
0x0008
GLOBAL_H_MASKING_CONTROL (Default: 0 x 00)
R/W
R/W
7:0
7:0
HMIN
Horizontal Masking Min Number
0x0009
HMAX[7:0]
GLOBAL_H_MASKING_CONTROL (Default: 0 x 00)
Horizontal Masking Max Number
(The LSB of HMAX)
42
PRELIMINARY DATASHEET
S5D2400X
0x000A
DITHER_MODE
GLOBAL_IO_MODE_DEFINE (Default: 0 x 00)
R/W
7:5
Selecting Dither mode type to change from 8 bits to 6 bits on the Scaler
out.
000 : Bypass
101 : Error Diffusion
Other values should not be used.
4:3
2
Reserved
ICHMD
OCHMD
OCHSEL
Scaler Input Channel Mode ( 0: Single Input (Always Low))
Scaler Output Channel Mode Select (1: Dual Output, 0: Single Output)
Select A or B channel from Scaler Output Dual Channel.
- This bit is enabled when ADDR (0x000A[1]) is Dual.
0: In the Dual mode, data are sent from Channel A.
1: In the Dual mode, data are sent from Channel B.
1
0
0x000B
GLOBAL_GPO_DATA (Default: 0 x 00)
R/W
7:6
5
PWM_PRE_
SCALE
When pulse width modulation is used, this bit determines, based on the
oscillation clock, the level of PWM duty level to be divided.
(00: Oscillation, 01: 2_Divided, 10: 4_Divided, 11: 8_Divided)
Pulse Width Modulation Enable
(1: Enable, 0: Disable)
PWM_EN
4:3
2
Reserved
GPO2
GPO1
GPO0
General Purpose Output 2
1
General Purpose Output 1
0
General Purpose Output 0
0x000C
PWM_DATA0
GLOBAL_PWM_DATA1 (Default: 0 x 00)
R/W
R/W
R/W
R/W
7:0
7:0
7:0
7:0
Pulse Width Modulation 0. Controls duty in the High section.
0x000D
PWM_DATA1
GLOBAL_PWM_DATA2 (Default: 0 x 00)
Pulse Width Modulation1. Controls duty in the High section.
0x000E
GLOBAL_V_MASKING_CONTROL (Default: 0 x 00)
VMIN
Vertical Masking Min Number
0x000F
GLOBAL_V_MASKING_CONTROL (Default: 0 x 00)
VMAX
Vertical Masking Max Number
43
PRELIMINARY DATASHEET
S5D2400X
6.2 TIMING GENERATOR CONTROL REGISTERS
Bits
Register Name
0x0010
Function
TG_MODE_SEL (Default: 0 x 18)
R/W
7
6
HVSO_DET_ON
HVSO_DET
Must be always 1. If the bit is "0", HVSO_DET is not controlled.
- In Invert, the bit initializes TG Sync, and detects again to create output
sync.
Event Driven PHSO and PVSO Detect (Low to High, High to Low) by Write
Value Change Operation
5
Reserved
4:3
DET_FRAME
TG Detection Start Frame (1 ~ 4 Frame): (Default: 3)
: The number of frames required to detect sync after the HVSO_DET
value is changed.
2
PREDIV_CKSEL
PLL_FIN_SEL
Pre-Divider clock Select
(1: CKI, 0: CKOSC (X1, Default))
PLL FIN Signal Select
1:0
(0: PRE_CK ® XGA (Default), 1: Not used,
2, 3: HS ® when scaling rate is small)
If HS is used in MCU Control, select PRE_CK to stabilize CLK, and then,
select HS.
0x0012
TG_HIA_STR_h (Default: 0 x 01)
R/W
7:3
2:0
Reserved
HIA_STR[10:8]
Manual Horizontal Input Active Start Point
(Horizontal Input sync Width + Back Porch)
0x0013
HIA_STR[7:0]
TG_HIA_STR_l (Default: 0 x 10)
R/W
R/W
7:0
Manual Horizontal Input Active Start Point
0x0014
TG_HIA_END_h (Default: 0 x 05)
Reserved
7:3
2:0
HIA_END[10:8]
Manual Horizontal Input Active End Point
(Horizontal Input sync Width + Back Porch + Active Size)
44
PRELIMINARY DATASHEET
S5D2400X
0x0015
HIA_END[7:0]
TG_HIA_END_l (Default: 0 x 0F)
R/W
R/W
7:0
Manual Horizontal Input Active End Point
0x0016
TG_VIA_STR_h (Default: 0 x 00)
Reserved
7:3
2:0
VIA_STR[10:8]
Manual Vertical Input Active Start Point
(Vertical Input sync Width + Back Porch)
0x0017
VIA_STR[7:0]
TG_VIA_STR_l (Default: 0 x 1F)
R/W
R/W
7:0
Manual Vertical Input Active Start Point
0x0018
TG_VIA_END_h (Default: 0 x 03)
Reserved
7:3
2:0
VIA_END[10:8]
Manual Vertical Input Active End Point
(Vertical Input sync Width + Back Porch + Active Size)
0x0019
VIA_END[7:0]
TG_VIA_END_l (Default: 0 x 1E)
R/W
7:0
Manual Vertical Input Active End Point
- H/V_Start/end Point is changed when VIA_END[7:0] is controlled.
0x001A
TG_HOFP (Default: 0 x 10)
Horizontal Output Front Porch
R/W
7:0
7:0
HOFP
0x001B
TG_HOSW (Default: 0 x 60)
Horizontal Output Sync Width
R/W
R/W
HOSW
0x001C
TG_HOBP_h (Default: 0 x 00)
7:3
2:0
Reserved
Horizontal Output Back Porch
HOBP[10:8]
0x001D
HOBP[7:0]
TG_HOBP_l (Default: 0 x B0)
Horizontal Output Back Porch
R/W
7:0
45
PRELIMINARY DATASHEET
S5D2400X
0x001E
TG_VOFP (Default: 0 x 01)
R/W
7
Reserved
Vertical Output Front Porch
6:0
VOFP
0x001F
VOSW
TG_VOSW (Default: 0 x 03)
Vertical Output Sync Width
R/W
R/W
7:0
0x0020
TG_HIAS_h (Default: 0 x 04)
7:3
2:0
Reserved
HIAS[10:8]
Horizontal Input Active Size
0x0021
TG_HIAS_l (Default: 0 x 00)
Horizontal Input Active Size
R/W
R/W
7:0
HIAS[7:0]
0x0022
TG_VIAS_h (Default: 0 x 03)
7:3
2:0
Reserved
VIAS[10:8]
Vertical Input Active Size
0x0023
VIAS[7:0]
TG_VIAS_l (Default: 0 x 00)
Vertical Input Active Size
R/W
R/W
7:0
0x0024
TG_HOAS_h (Default: 0 x 04)
7:3
2:0
Reserved
HOAS[10:8]
Horizontal Output Active Size
0x0025
HOAS[7:0]
TG_HOAS_l (Default: 0 x 00)
Horizontal Output Active Size
R/W
R/W
7:0
0x0026
TG_VOAS_h (Default: 0 x 03)
7:3
2:0
Reserved
VOAS[10:8]
Vertical Output Active Size
46
PRELIMINARY DATASHEET
S5D2400X
0x0027
VOAS[7:0]
TG_VOAS_l (Default: 0 x 00)
Vertical Output Active Size
R/W
R/W
R/W
R/W
7:0
7:0
7:0
0x0028
PLL_P[15:8]
TG_PLL_P_h (Default: 0 x 03)
PLL Programmable Pre-Divider
0x0029
PLL_P[7:0]
TG_PLL_P_l (Default: 0 x E8)
PLL Programmable Pre-Divider
0x002A
TG_PLL_M_h (Default: 0 x 18)
7:6
5:0
Reserved
PLL Programmable Main-Divider
PLL_M[13:8]
0x002B
PLL_M[7:0]
TG_PLL_M_l (Default: 0 x 9B)
PLL Programmable Main-Divider
R/W
R/W
7:0
0x002C
TG_PLL_S (Default: 0 x 01)
7:2
1:0
Reserved
PLL_S
PLL Programmable Post Scaler
0x002D
PLL_M_FRACT
TG_PLL_M_FRACT (Default: 0 x 00)
R/W
R/W
7:0
TG's PLL_M register Fraction bits
0x0032
TG_A_HACTO_OFFSET_h (Default: 0 x 02)
Reserved
7:6
5:0
A_HACTO_OFFSET
[13:8]
Automatic Horizontal Output Active Point OFFset Delay
- Up Mode: A_HACTO_OFFSET = HItotal * VSTR_OFFSET * Vratio *
HTOTratio / 32
- Down Mode: A_HACTO_OFFSET = 29 * HTOTratio * Vratio +
HITotal * VSTR_OFFSET * Vratio * HTOTratio/32 – 2
47
PRELIMINARY DATASHEET
S5D2400X
0x0033
A_HACTO_OFFSET
[7:0]
TG_A_HACTO_OFFSET_l (Default: 0 x 90)
R/W
7:0
Automatic Horizontal Output Active Point OFFset Delay
0x01BO
TG_SYNC_DVI (Default: 0 x 0A)
Reserved
R/W
7:5
4
D_STOP_SIZE
DHS_POL_SEL
DHS_POL_EXT
DVS_POL_SEL
DVS_POL_EXT
Size Detection Update Enable
(1: Previous Frame Data, 0: Frame Update)
TMDS Output DHS Polarity Detection Priority
(1: MCU Detection, 0: Internal Detection)
3
2
1
0
TMDS Output DHS Polarity Selection by MCU (DHS_POL_SEL = 1)
(1: Positive Type, 0: Negative Type)
TMDS Output DVS Polarity Detection Priority
(1: MCU Detection, 0: Internal Detection)
TMDS Output DVS Polarity Selection by MCU (DVS_POL_SEL = 1)
(1: Positive Type, 0: Negative Type)
0x01B2
TG_DHS_TOTAL_h
RO
7:3
2:0
Reserved
DHS Horizontal Input Total Size
DHS_HITS[10:8]
0x01B3
DHS_HITS[7:0]
TG_DHS_TOTAL_l
DHS Horizontal Input Total Size
RO
RO
7:0
0x01B4
TG_DVS_TOTAL_h
7:3
2:0
Reserved
DVS_VITS[10:8]
DVS Vertical Input Total Size
0x01B5
DVS_VITS[7:0]
TG_DVS_TOTAL_l
DVS Vertical Input Total Size
RO
7:0
48
PRELIMINARY DATASHEET
S5D2400X
0x01B6
TG_DDEN_HIA_STR_h
RO
7:3
Reserved
2:0
DD_HIA_STR[10:8]
DDEN Horizontal Input Active Start Point
0x01B7
TG_DDEN_HIA_STR_l
RO
RO
7:0
DD_HIA_STR[7:0]
DDEN Horizontal Input Active Start Point
0x01B8
TG_DDEN_HIA_END_h
Reserved
7:3
2:0
DD_HIA_END[10:8]
DDEN Horizontal Input Active End Point
0x01B9
TG_DDEN_HIA_END_l
RO
RO
7:0
DD_HIA_END[7:0]
DDEN Horizontal Input Active End Point
0x01BA
TG_DDEN_VIA_STR_h
Reserved
7:3
2:0
DD_VIA_STR[10:8]
DDEN Vertical Input Active Start Point
0x01BB
TG_DDEN_VIA_STR_h
RO
RO
7:0
DD_VIA_STR[7:0]
DDEN Vertical Input Active Start Point
0x01BC
TG_DDEN_VIA_END_h
Reserved
7:3
2:0
DD_VIA_END[10:8]
DDEN Vertical Input Active End Point
0x01BD
TG_DDEN_VIA_END_l
RO
7:0
DD_VIA_END[7:0]
DDEN Vertical Input Active End Point
49
PRELIMINARY DATASHEET
S5D2400X
6.3 DE-INTERLACE CONTROL REGISTERS
Bits
Register Name
0x0040
Function
DI_ SYNC_DEFINE (Default: 0 x 38)
R/W
7:6
5
Reserved
FIELD Signal Polarity
DI_FIELD_POL
DI_HACT_POL
DI_VACT_POL
1: Odd Field (Field 1) High, Even Field (Field 2) Low - Required Design
0: Even Field (Field 2) High, Odd Field (Field 1) Low - 656 SPEC
HACT Signal Polarity
4
3
1: Active High - Required Design
0: Active Low - 656 SPEC
VACT Signal Polarity
1: Active High - Required Design
0: Active Low - 656 SPEC
2
1
DI_SYNC_GEN
DI_C_SIGN
Sync Generation Block Selection
0: Required Design
Chroma Sign Bit Determination
1: 2's Complementary - Non SPEC
0: Positive Number - SPEC (Required Design)
Cb / Cr Signal Input Type Selection
1: CR Y CB Y CR Y ... - NON_SPEC
0: CB Y CR Y CB Y ... - SPEC (Required Design)
0
DI_CBCR_SEL
0x0041
DI_SYNC_POLARITY (Default: 0 x 00)
Reserved
R/W
7
6
5
4
3
2
1
ITU-R BT.656
1: ITU-R BT.601,
1: Half_Rate ON,
0: ITU-R BT.656
0: Half_Rate OFF
DI_HALF_RATE
HALF_YC_POL_INV
HALF_VS_POL_INV
HALF_HS_POL_INV
Half_Rate Y/C Polarity Inversion
Half_Rate V-Sync Polarity Inversion
Half_Rate H-Sync Polarity Inversion
HALF_HACTO_POL_ Half_Rate HACTO Polarity Inversion
INV
0
HALF_FIELD_POL_
INV
Half_Rate Field Polarity Inversion
50
PRELIMINARY DATASHEET
S5D2400X
0x0042
VSO_ODD_SEL
VSO_EVEN_SEL
DI_VSO_SEL (Default: 0 x 00)
Odd Field V-Sync Select
Even Field V-Sync Select
R/W
7:4
3:0
0x0043
DI_HOFP
DI_HOFP (Default: 0 x 0A)
Horizontal Output Front Porch
R/W
R/W
R/W
R/W
R/W
R/W
7:0
7:0
7:0
7:0
7:0
0x0044
DI_HOSW
DI_HOSW (Default: 0 x 1E)
Horizontal Output Sync Width
0x0045
DI_VOFP
DI_VOFP (Default: 0 x 04)
Vertical Output Front Porch
0x0046
DI_VOSW
DI_VOSW (Default: 0 x 06)
Vertical Output Sync Width
0x0047
DI_LINE_START
DI_LINE_START (Default: 0 x 03)
Vertical Line Start Point Included Active Vertical Area
0x0048
DI_LINE_WIDTH_h (Default: 0 x 01)
7:2
1:0
Reserved
DI_LINE_WIDTH[9:8] Vertical Line Width Included Active Vertical Area
0x0049
DI_LINE_WIDTH_l (Default: 0 x E2)
R/W
R/W
7:0
DI_LINE_WIDTH[7:0] Vertical Line Width Included Active Vertical Area
0x004A
DI_DEINTERLACE_TYPE (Default: 0x 0F)
Reserved
7:4
3:2
DI_DI_YTYPE
Y Interpolation Type (Trade Off of screen blurring and zagging)
0 : Screen blurring < -- > 3 : Noise
0 : Strong Zagging < -- > 3 : Weak Zagging
Recommended Value : 1
1:0
DI_DI_CTYPE
C Interpolation Type (The same value with Y Interpolation Type)
51
PRELIMINARY DATASHEET
S5D2400X
0x004B
DI_HACTO_ST_MG
DI_HACTO_MG (Default: 0 x FF)
R/W
7:4
3:0
HACTO Signal Start Point Margin (-8 ~ +7)
: DI_MIN_H = HACTO Start + DI_HACTO_ST_MG
DI_HACTO_ED_MG
HACTO Signal End Point Margin (-8 ~ +7)
: DI_MAX_H = HACTO End + DI_HACTO_ED_MG
0x004C
DI_601CLK_PHASE (Default: 0 x 00)
Unused
R/W
R/W
7:3
2:0
DCLK_PHASE
ITU-R BT.601 format Clock Phase
0x004D
DI_601HV_SEL (Default: 0 x 00)
Unused
7
6
EXT_FLD_SEL
HS601_INV
VS601_INV
V601_ODD
1: External Field Select, 0: Internal Field Select
ITU-R BT.601 H-Sync Inversion
5
4
ITU-R BT.601 V-Sync Inversion
3:2
1:0
ITU-R BT.601 Odd Field Active Line Select
ITU-R BT.601 Even Field Active Line Select
V601_EVEN
0x004E
DI_601HIA_STR_h (Default: 0 x 00)
Unused
R/W
7:1
0
DI_601HIA_STR[8]
ITU-R BT.601 Horizontal Input Active Start Point
0x004F
DI_601HIA_STR_l (Default: 0 x EF)
R/W
R/W
R/W
7:0
7:0
DI_601HIA_STR[7:0]
ITU-R BT.601 Horizontal Input Active Start Point
0x0050
DI_601VIA_STR (Default: 0 x 11)
DI_601VIA_STR
ITU-R BT.601 Vertical Input Active Start Point
0x0051
DI_601_VIAS_h (Default: 0 x 00)
Unused
7:2
1:0
DI_601_VIAS[9:8]
ITU-R BT.601 Vertical Input Active Size
52
PRELIMINARY DATASHEET
S5D2400X
0x0052
DI_601_VIAS[7:0]
DI_601_VIAS_l (Default: 0 x F1)
R/W
R/W
RO
7:0
7:0
ITU-R BT.601 Vertical Input Active Size
0x0053
FIELD601_TH
DI_FIELD601_TH (Default: 0 x 46)
ITU-R BT.601 Internal Field Threshold
0x01C0
DI_H_TOTAL_h
Reserved
7:3
2:0
DI_HOTS[10:8]
Horizontal Output Total Size
0x01C1
DI_HOTS[7:0]
DI_H_TOTAL_l
RO
RO
7:0
Horizontal Output Total Size
0x01C2
DI_V_TOTAL_h
Reserved
7:3
2:0
DI_VOTS[10:8]
Vertical Output Total Size
0x01C3
DI_VOTS[7:0]
DI_V_TOTAL_l
RO
RO
7:0
Vertical Output Total Size
0x01C4
DI_HOA_STR_h
Reserved
7:3
2:0
DI_HOA_STR[10:8]
Horizontal Output Active Start Point
0x01C5
DI_ HOA_STR _l
RO
RO
7:0
DI_HOA_STR[7:0]
Horizontal Output Active Start Point
0x01C6
DI_HOA_END_h
Reserved
7:3
2:0
DI_HOA_END[10:8]
Horizontal Output Active End Point
0x01C7
DI_HOA_END_l
RO
7:0
DI_HOA_END[7:0]
Horizontal Output Active End Point
53
PRELIMINARY DATASHEET
S5D2400X
0x01C8
DI_VOA_STR_h
RO
7:3
Reserved
2:0
DI_VOA_STR[10:8]
Vertical Output Active Start Point
0x01C9
DI_VOA_STR_l
RO
RO
7:0
DI_VOA_STR[7:0]
Vertical Output Active Start Point
0x01CA
DI_VOA_END_h
Reserved
7:3
2:0
DI_VOA_END[10:8]
Vertical Output Active End Point
0x01CB
DI_VOA_END_l
RO
7:0
DI_VOA_END[7:0]
Vertical Output Active End Point
54
PRELIMINARY DATASHEET
S5D2400X
6.4 IMAGE SCALING CONTROL REGISTERS
Bits
Register Name
0x0061
Function
SCALER_IVZOOM_h (Default: 0 x 02)
R/W
7:4
3:0
Reserved
IVZOOM[19:16]
Inversed Vertical Zoom Ratio ( = VIAS/VOAS )
0x0062
IVZOOM[15:8]
SCALER_IVZOOM_m (Default: 0 x 00)
R/W
R/W
R/W
7:0
7:0
Inversed Vertical Zoom Ratio ( = VIAS/VOAS )
0x0063
IVZOOM[7:0]
SCALER_IVZOOM_l (Default: 0 x 00)
Inversed Vertical Zoom Ratio ( = VIAS/VOAS )
0x0065
SCALER_IHZOOM_h (Default: 0 x 02)
Reserved
7:4
3:0
IHZOOM[19:16]
Inversed Horizontal Zoom Ratio ( = HIAS/HOAS )
0x0066
IHZOOM[15:8]
SCALER_IHZOOM_m (Default: 0 x 00)
R/W
R/W
R/W
7:0
7:0
Inversed Horizontal Zoom Ratio ( = HIAS/HOAS )
0x0067
IHZOOM[7:0]
SCALER_IHZOOM_l (Default: 0 x 00)
Inversed Horizontal Zoom Ratio ( = HIAS/HOAS )
0x0068
SCALER_HSTR_OFFSET (Default: 0 x 00)
Reserved
7:6
5:0
HSTR_OFFSET
Sub-Pixel Horizontal Starting Point OFFset for Scaling
- For Scale Down
: HSTR_OFFSET = [ (HIAS-1) – (HOAS – 1) / Hratio ] * 16
- For Scale Up
: HSTR_OFFSET = 32 – [16 * {(2 * é 3*HOAS/HIAS ù + HOAS – 1) /
Hratio – HIAS – 1}] %32
55
PRELIMINARY DATASHEET
S5D2400X
0x0069
SCALER_VSTR_OFFSET (Default: 0 x 00)
Reserved
R/W
7:6
5:0
VSTR_OFFSET
Sub-Pixel Vertical Starting Point OFFset for Scaling
- For Scale Down
: VSTR_OFFSET = [ (VIAS-1) – (VOAS – 1) / Vratio ] * 16
- For Scale Up
: VSTR_OFFSET = 32 – [16 * {(2 * é 3*VOAS/VIAS – 1 ù + VOAS –1) /
Vratio – VIAS – 1}] %32
56
PRELIMINARY DATASHEET
S5D2400X
6.5 ADVANCED COLOR CONTRAST ENHANCEMENT (ACE) CONTROL REGISTERS
Bits
Register Name
0x0070
Function
BU_H_START_h (Default: 0 x 00)
R/W
7:3
2:0
Reserved
BU_HSP[10:8]
BOOST UP AREA : Horizontal Start Point
0x0071
BU_HSP[7:0]
BU_H_START_l (Default: 0 x 00)
R/W
R/W
7:0
BOOST UP AREA : Horizontal Start Point
0x0072
BU_V_START_h (Default: 0 x 00)
Reserved
7:3
2:0
BU_VSP [10:8]
BOOST UP AREA : Vertical Start Point
0x0073
BU_VSP[7:0]
BU_V_START_l (Default: 0 x 00)
R/W
R/W
7:0
BOOST UP AREA : Vertical Start Point
0x0074
BU_H_END_h (Default: 0 x 00)
Reserved
7:3
2:0
BU_HEP[10:8]
BOOST UP AREA : Horizontal End Point
0x0075
BU_HEP[7:0]
BU_H_END_l (Default: 0 x 00)
R/W
R/W
7:0
BOOST UP AREA : Horizontal End Point
0x0076
BU_V_END_h (Default: 0 x 00)
Reserved
7:3
2:0
BU_VEP[10:8]
BOOST UP AREA : Vertical End Point
0x0077
BU_VEP[7:0]
BU_V_END_l (Default: 0 x 00)
R/W
7:0
BOOST UP AREA : Vertical End Point
- BU_H/V_Start/End Point is changed when BU_VEP[7:0] is controlled.
57
PRELIMINARY DATASHEET
S5D2400X
0x0078
SUB_ZONESEL
BU_SUB_H_START_h (Default: 0 x 00)
R/W
7
if (SUB_ZONESEL == 1) then BU_SUB_HSP = BU_HSP, BU_SUB_VSP
= BU_VSP, BU_SUB_HEP = BU_HEP, BU_SUB_VEP = BU_VEP;
6:3
2:0
Reserved
BU_SUB_HSP[10:8]
BOOST UP Calculating AREA : Horizontal Start Point
0x0079
BU_SUB_H_START_l (Default: 0 x 00)
R/W
R/W
7:0
BU_SUB_HSP [7:0]
BOOST UP Calculating AREA : Horizontal Start Point
0x007A
BU_SUB_V_START_h (Default: 0 x 00)
7:3
2:0
Reserved
BU_SUB_VSP [10:8] BOOST UP Calculating AREA : Vertical Start Point
0x007B
BU_SUB_V_START_l (Default: 0 x 00)
R/W
R/W
7:0
BU_SUB_VSP [7:0]
BOOST UP Calculating AREA : Vertical Start Point
0x007C
BU_SUB_H_END_h (Default: 0 x 00)
Reserved
7:3
2:0
BU_SUB_HEP [10:8]
BOOST UP Calculating AREA : Horizontal End Point
0x007D
BU_SUB_H_END_l (Default: 0 x 00)
R/W
R/W
7:0
BU_SUB_HEP [7:0]
BOOST UP Calculating AREA : Horizontal End Point
0x007E
BU_SUB_V_END_h (Default: 0 x 00)
Reserved
7:3
2:0
BU_SUB_VEP [10:8]
BOOST UP Calculating AREA : Vertical End Point
0x007F
BU_SUB_V_END_l (Default: 0 x 00)
R/W
7:0
BU_SUB_VEP [7:0]
BOOST UP Calculating AREA : Vertical End Point
- BU_SUB_H/V_Start/End Point is changed when BU_SUB_VEP[7:0] is
controlled
58
PRELIMINARY DATASHEET
S5D2400X
0x0080
MAX_coeff
BU_MAX_COEF (Default: 0 x 00)
Response time to MAX
R/W
R/W
R/W
R/W
R/W
7:0
7:0
7:0
7:0
0x0081
MIN_coeff
BU_MIN_COEF (Default: 0 x 00)
Response time to MIN
0x0082
AVR_L1_coeff
BU_AVR_L1_COEF (Default: 0 x 00)
AVR Response time before stretching
0x0083
AVR_coeff
BU_AVR_COEF (Default: 0 x 00)
AVR Response time after stretching
0x0084
Ymax_HIGH_int
BU_MAX_THRESHOLD (Default: 0 x 00)
Upper threshold for MAX
7:4
3:0
: Ymax_HIGH_TH >= MAX >= Ymax_LOW_TH
Lower threshold for MAX
Ymax_LOW_int
0x0085
BU_MIN_THRESHOLD (Default: 0 x 00)
Upper threshold for MIN
R/W
7:4
3:0
Ymin_HIGH_int
: Ymin_HIGH_TH >= MIN >= Ymin_LOW_TH
Lower threshold for MIN
Ymin_LOW_int
0x0086
Ymax_1st_base
BU_MAX_1ST (Default: 0 x 00)
R/W
R/W
R/W
7:0
7:0
7:0
The number of pixels considered as the biggest value in MAX
0x0086
Ymax_1st_base
BU_MAX_1ST (Default: 0 x 00)
The number of pixels considered as the biggest value in MAX
0x0087
Ymax_2nd_ base
BU_MAX_2ND (Default: 0 x 00)
The number of pixels considered as the next biggest value in MAX
When Ymax_1st_base condition is not met.
59
PRELIMINARY DATASHEET
S5D2400X
0x0088
Ymin_1st_base
BU_MIN_1ST (Default: 0 x 00)
R/W
R/W
7:0
7:0
The number of pixels considered as the smallest value in MIN
0x0089
BU_MIN_2ND (Default: 0 x 00)
Ymin_2nd_ base
The number of pixels considered as the next smallest value in MIN
When Ymin_1st_base condition is not met.
0x008A
BU_AVR_L1_H (Default: 0 x 00)
Adjusts the MAX value.
R/W
7:0
7:0
AVR_L1_H
0x008B
BU_AVR_L1_L (Default: 0 x 00)
Adjusts the MIN value.
R/W
R/W
AVR_L1_L
0x008C
BU_LEVEL (Default: 0 x 00)
ON / OFF (1: ON) of stretching and boost
Reserved
7
6:1
0
BOOST_ON
ST_LEVEL
Stretching Level (0: Low Stretch, 1: High Stretch)
0x008D
BU_MINMAX_CONTROL (Default: 0 x 00)
Reserved
R/W
7:5
4
Ymax_Ctrl
The method of modifying MAX : (M_MAX)
0 : Not Stretching
1 : M_MAX = 1/8 * MAX
3:1
0
Reserved
Ymin_Ctrl
The method of modifying Min : (M_MIN)
0 : Not Stretching
1 : M_MIN = 1/8 * MIN
0x008E
BU_AVR_LUT_GAIN (Default: 0 x 00)
Reserved
R/W
7:2
1:0
AVR_LUT_Gain
Boost gain control by AVR and LUT
60
PRELIMINARY DATASHEET
S5D2400X
0x0090
BU_COLOR_CONTROL (Default: 0 x 00)
Reserved
R/W
7:6
5
ITU-R.SEL
ITU-R BT.656 OFFset correction ON / OFF (1: ON)
4:2
RGBrate
Color correction rate
(0.5625, 0.625, 0.6875, 0.75, 0.8125, 0.875, 0.9375, 1)
1:0
SEL_div
Selects the color correction method
0 : OFF
1 : Color correction coefficient determining filter 1
2 : Color correction coefficient determining filter 2
3 : Color correction coefficient determining filter 3
0x0091
BU_APERTURE_GAIN (Default: 0 x 00)
Reserved
R/W
R/W
7:4
3:0
AP_GAIN
Sharpness Gain Control
0x0094
BU_GRAPH_CONTROL (Default: 0 x 00)
Reserved
7:2
1
GR_MODE
GR_STYLE
BOOST UP LUT Graph ON / OFF (1: ON)
BOOST UP LUT Graph Style Select (1: Bar, 0: Line)
0
0x0095
BU_AVR_RATE_h (Default: 0 x 00)
Reserved
R/W
R/W
7:1
0
AVRrate[8]
Adjusts boost rate (No boost if the bit is 0.)
0x0096
AVRrate[7:0]
BU_AVR_RATE_l (Default: 0 x 00)
7:0
Adjusts boost rate (No boost if the bit is 0.)
AVRrate[8:0] binary number. Only the first 1 bit is constant.
For example, 9bits is expressed as X.xxxxxxxx. The minimum must be
0.5.
0x0097
BU_FILTER_CONTROL (Default: 0 x 00)
Reserved
R/W
7:6
5
AREA_ON
Boost border line including screen outer line (1: ON, 0: OFF)
Reserved
4:0
61
PRELIMINARY DATASHEET
S5D2400X
6.6 GLOBAL IMAGE GAIN & OFFSET CONTROL REGISTER
Bits
Register Name
0x00D0
Function
CONTRAST_CONTROL_TYPE (Default: 0 x 01F)
R/W
7:6
5:4
Reserved
CONT_TYPE
ZONE_CT
Determines magnification of the contrast control area
00: 0 ~ 0.99609375, 01: 0.5 ~ 1.49609375 (Default)
10: 0 ~ 1.9921875, 11: 0 ~ 3.984375
Zone area control type
3
2
1
0
1: Adjusts global/zone together based on global (Default)
0: Adjusts global/zone separately
Black level control type
BLACK_CT
CONT_CT
1: Adjusts R/G/B together based on R (Default)
0: Adjusts R/G/B separately
Contrast control type
1: Adjusts R/G/B together based on R (Default)
0: Adjusts R/G/B separately
BRIGHT_CT
Brightness control type
1: Adjusts R/G/B together based on R (Default)
0: Adjusts R/G/B separately
0x00D1
CONTRAST_R_BLACK_global (Default: 0 x 00)
Reserved
R/W
7:6
5:0
R_BLACK_global
Adjusts R channel Black level.
R/G/B are adjusted separately if BLACK_CT (ADDR 0x00D0[2]) is 0, and
are adjusted together based on R if it is 1.
0x00D2
CONTRAST_G_BLACK_global (Default: 0 x 00)
Reserved
Adjusts G channel Black level.
R/W
7:6
5:0
G_BLACK_global
R/G/B are adjusted separately if BLACK_CT (ADDR 0x00D0[2]) is 0, and
are adjusted together based on R if it is 1.
0x00D3
CONTRAST_B_BLACK_global (Default: 0 x 00)
Reserved
Adjusts B channel Black level.
R/W
7:6
5:0
B_BLACK_global
R/G/B are adjusted separately if BLACK_CT(ADDR 0x00D0[2]) is 0, and
are adjusted together based on R if it is 1.
62
PRELIMINARY DATASHEET
S5D2400X
0x00D4
R_CONT_global
CONTRAST_R_CONT_global (Default: 0 x 80)
R/W
7:0
7:0
7:0
7:0
7:0
7:0
Adjusts R channel Contrast.
R/G/B are adjusted separately if CONT_CT(ADDR 0x00D0[1]) is 0, and are
adjusted together based on R if it is 1.
0x00D5
G_CONT_global
CONTRAST_G_CONT_global (Default: 0 x 80)
R/W
Adjusts G channel Contrast.
R/G/B are adjusted separately if CONT_CT(ADDR 0x00D0[1]) is 0, and are
adjusted together based on R if it is 1.
0x00D6
B_CONT_global
CONTRAST_B_CONT_global (Default: 0 x 80)
R/W
Adjusts B channel Contrast.
R/G/B are adjusted separately if CONT_CT(ADDR 0x00D0[1]) is 0, and are
adjusted together based on R if it is 1.
0x00D7
CONTRAST_R_BRIGHT_global (Default: 0 x 00)
R/W
R_BRIGHT_global
Adjusts R channel Brightness.
R/G/B are adjusted separately if BRIGHT_CT(ADDR 0x00D0[0]) is 0, and
are adjusted together based on R if it is 1.
0x00D8
CONTRAST_G_BRIGHT_global (Default: 0 x 00)
R/W
G_BRIGHT_global
Adjusts G channel Brightness.
R/G/B are adjusted separately if BRIGHT_CT (ADDR 0x00D0[0]) is 0, and
are adjusted together based on R if it is 1.
0x00D9
CONTRAST_B_BRIGHT_global (Default: 0 x 00)
R/W
B_BRIGHT_global
Adjusts B channel Brightness.
R/G/B are adjusted separately if BRIGHT_CT (ADDR 0x00D0[0]) is 0, and
are adjusted together based on R if it is 1.
0x00DA
CONTRAST_B_BLACK_ZONE (Default: 0 x 00)
Reserved
Adjusts R channel Black level in the boot area
R/W
7:6
5:0
R_BLACK_ZONE
63
PRELIMINARY DATASHEET
S5D2400X
0x00DB
CONTRAST_B_BLACK_ZONE (Default: 0 x 00)
Reserved
R/W
7:6
5:0
G_BLACK_ZONE
Adjusts G channel Black level in the boot area
0x00DC
CONTRAST_B_BLACK_ZONE (Default: 0 x 00)
Reserved
R/W
7:6
5:0
B_BLACK_ZONE
Adjusts B channel Black level in the boot area
0x00DD
R_CONT_ZONE
CONTRAST_R_CONT_ZONE (Default: 0 x 80)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7:0
7:0
7:0
7:0
7:0
7:0
Adjusts R channel Contrast in the boot area
0x00DE
G_CONT_ZONE
CONTRAST_G_CONT_ZONE (Default: 0 x 80)
Adjusts G channel Contrast in the boot area
0x00DF
B_CONT_ZONE
CONTRAST_B_CONT_ZONE (Default: 0 x 80)
Adjusts B channel Contrast in the boot area
0x00E0
CONTRAST_R_BRIGHT_ZONE (Default: 0 x 00)
R_BRIGHT_ZONE
Adjusts R channel Brightness in the boot area
0x00E1
CONTRAST_G_BRIGHT_ZONE (Default: 0 x 00)
G_BRIGHT_ZONE
Adjusts G channel Brightness in the boot area
0x00E2
CONTRAST_B_BRIGHT_ZONE (Default: 0 x 00)
B_BRIGHT_ZONE
Adjusts B channel Brightness in the boot area
0x00E3
CONTRAST_BG_COLOR_R (Default: 0 x 00)
Reserved
7:6
5
BG_COLOR
Enable Background Color (1: ON, 0: OFF)
- Background Color correspond to BG_COLOR_R,G,B color pallet
- Highest priority in color control.
4:0
BG_COLOR_R
R Channel Background Color
64
PRELIMINARY DATASHEET
S5D2400X
0x00E4
CONTRAST_BG_COLOR_G (Default: 0 x 00)
Reserved
R/W
7:5
4:0
BG_COLOR_G
G Channel Background Color
0x00E5
CONTRAST_BG_COLOR_B (Default: 0 x 10)
Reserved
R/W
7:5
4:0
BG_COLOR_B
B Channel Background Color
65
PRELIMINARY DATASHEET
S5D2400X
6.7 OSD CONTROL REGISTERS
Bits
Register Name
0x0100
Function
OSD_CHAR_TONE (Default: 0 x 60)
OSD Output Enable (1: Enable, 0: Disable)
DSRAM Clear (1: No Operation, 0: Active)
FONT RAM Clear (1: No Operation, 0: Active)
INTENSITY Select
R/W
7
6
5
4
3
OSD_EN
DSRAM_CLRN
FTRAM_CLRN
ITENSITY
CH_TONE
Character half Toning :
if (OSD_TONE[2] == 0 && OSD_TONE[1:0] != 0 && CH_TONE == 1) then
If Half Tone (Transparency) is enabled, it is applied to the font area.
2:0
OSD_TONE
OSD half Toning :
0: OSD bypass and input image are expressed. (Default)
1: Input Image and OSD are mixed at the rate of 0.25.
2: Input Image and OSD are mixed at the rate of 0.5.
3: Input Image and OSD are mixed at the rate of 0.75.
4 or higher : Only OSD is expressed without mixing with the input image.
0x0101
OSD_FONT_SIZE (Default: 0 x 00)
R/W
7:6
5:4
3:0
CH_HSZ
CH_VSZ
ROW_SP
Determines, based on the font size (12 ´ 18), the magnifying rate of the
character horizontal size.
- For example, if CH_HSZ is set to 1, the horizontal size of the character
becomes 12 ´ 2 Pixel.
(00: 12 ´ 1, 01: 12 ´ 2, 10: 12 ´ 3, 11: 12 ´ 4)
Determines, based on the font size (12 ´ 18), the magnifying rate of the
character vertical size.
- For example, if CH_VSZ is set to 3, the vertical size of the character
becomes 18 ´ 4 Pixel.
(00: 18 ´ 1, 01: 18 ´ 2, 10: 18 ´ 3, 11: 18 ´ 4)
Controls the number of row spaces between the upper and lower fonts.
The row space is expressed in interworking with vertical pixels in
accordance with the character vertical size.
- For example, if ROW_SP is 2 and CH_VSZ is 2, the row space is 6
lines.
66
PRELIMINARY DATASHEET
S5D2400X
0x0102
OSD_HFONT (Default: 0 x 00)
R/W
7:6
Reserved
The number of horizontal fonts of OSD
- If OSD_HFONT is 30, the number of horizontal fonts of OSD is 30.
5:0
OSD_HFONT
0x0103
OSD_VFONT (Default: 0 x 00)
R/W
7:6
5:0
Reserved
OSD_VFONT
The number of vertical fonts of OSD.
- If OSD_VFONT is 15, the number of vertical fonts of OSD is 15.
0x0104
OSD_HSP_h (Default: 0 x 00)
Reserved
R/W
7:3
2:0
OSD_HSP[10:8]
Sets the horizontal start point of OSD.
- If W_BDSH_EN is 1, and if OSD_HSP is lower than 6 as W_BDSH is 1,
OSD_HSP is 6.
0x0105
OSD_HSP[7:0]
OSD_HSP_l (Default: 0 x 00)
R/W
R/W
7:0
Sets the horizontal start point of OSD.
0x0106
OSD_VSP_h (Default: 0 x 00)
Reserved
7:3
2:0
OSD_VSP[10:8]
Sets Vertical Start Point of OSD.
- If W_BDSH_EN is 1, and OSD_VSP is lower than 6 as W_BDSH is 1,
OSD_VSP is 6.
0x0107
OSD_VSP[7:0]
OSD_VSP_l (Default: 0 x 00)
Sets the vertical start point of OSD.
R/W
7:0
67
PRELIMINARY DATASHEET
S5D2400X
0x0108
OSD_BORDER_SHADOW (Default: 0 x 00)
Reserved
R/W
7:5
4
W_BDSH_EN
Controls OSD Main Window Border / Shadow Enable
1: Enables OSD Main Window Border / shadow
0: OSD Main Window Border / shadow is disappeared regardless of
W_BDSH
3
2
W_BDSH
Border and shadow of OSD window is determined by setting W_BDSH to o
or 1 as W_BDSH_EN(ADDR 0x0108[4]) is 1.
(1: OSD Main Window Bordering, 0: OSD Main Window Shadow)
Controls border / shadow enable of multiple windows.
MW_BDSH_EN
1: Enables OSD Multiple Windows Border / shadow
0: Multiple Window Border / shadow is disappeared regardless of
MW_BDSH
1
0
MW_BDSH
Border and shadow of OSD window is determined by setting MW_BDSH to
0 or 1 as MW_BDSH_EN(ADDR 0x0108[2]) is 1.
(1: OSD Multiple Window Bordering, 0: OSD Multiple Window Shadow)
Controls Character Border/Shadow Enable
CH_BDSH_EN
1: Character border if DSRAM[15] is 1, and Character shadow if 0
0: Border / Shadow are disabled regardless of DSRAM[15].
0x0109
OSD_MW_ENABLE (Default: 0 x 00)
R/W
7:4
3
Reserved
W1_EN
W2_EN
W3_EN
W4_EN
Multiple Windows 1 Enable Control
1: LUT color of W1C is expressed in Multiple Windows 1
0: Multiple windows 1 is disabled.
2
1
0
Multiple Windows 2 Enable Control.
1: LUT color of W2C is expressed in Multiple Windows 2
0: Multiple windows 2 is disabled.
Multiple Windows 3 Enable Control.
1: LUT color of W3C is expressed in Multiple Windows 3
0: Multiple windows 3 is disabled.
Multiple Windows 4 Enable Control.
1: LUT color of W4C is expressed in Multiple Windows 4
0: Multiple windows 4 is disabled.
68
PRELIMINARY DATASHEET
S5D2400X
0x010A
W1_PRT
OSD_MW_PRIORITY (Default: 0 x 00)
R/W
7:6
5:4
3:2
1:0
Sets priority of W1 in 4 Multiple Windows
- The priority order is W1, W2, W3 and W4 if the same priority is given.
(0: Highest Priority, 1: 2nd Priority, 2: 3rd Priority, 2: 4th Priority)
Sets priority of W2 in 4 Multiple Windows
W2_PRT
W3_PRT
W4_PRT
- The priority order is W1, W2, W3 and W4 if the same priority is given.
(0: Highest Priority, 1: 2nd Priority, 2: 3rd Priority, 2: 4th Priority)
Sets priority of W3 in 4 Multiple Windows
- The priority order is W1, W2, W3 and W4 if the same priority is given.
(0: Highest Priority, 1: 2nd Priority, 2: 3rd Priority, 2: 4th Priority)
Sets priority of W4 in 4 Multiple Windows
- The priority order is W1, W2, W3 and W4 if the same priority is given.
(0: Highest Priority, 1: 2nd Priority, 2: 3rd Priority, 2: 4th Priority)
0x010B
OSD_BDSH_COLOR (Default: 0 x 00)
R/W
7:6
5:4
Reserved
WSH_C
Selects shadow color of OSD Main/ Multiple windows
0: LUT12[3:0] is applied to Windows Shadow Color
1: LUT13[3:0] is applied to Windows Shadow Color
2: LUT14[3:0] is applied to Windows Shadow Color
3: LUT15[3:0] is applied to Windows Shadow Color
3:0
CH_BSC
Selects Character Border / Shadow Color as CH_BDSH_EN (ADDR
0x0108[0] is 1. You can select from LUT0 to LUT15 in this way.
0: LUT0[7:4] is used as the Border / Shadow Color of the character
1: LUT1[7:4] is used as Border / Shadow Color of the character
2: LUT2[7:4] is used as Border / Shadow Color of the character
3: LUT3[7:4] is used as Border / Shadow Color of the character
69
PRELIMINARY DATASHEET
S5D2400X
0x010C
OSD_SHADOW_SIZE_MCF (Default: 0 x 00)
Reserved
R/W
7:6
Controls the window shadow size as W_BDSH_EN (ADDR 0x0108[4]) is 1
and W_BDSH(ADDR 0x0108[3]) is 0.
5:4
WSH_SZ
0. Horizontal/vertical shadow size of the OSD main window is 1 pixel in
both horizontal and vertical.
1. Horizontal/vertical shadow size of the OSD main window is 2 pixel in
both horizontal and vertical.
2. Horizontal/vertical shadow size of the OSD main window is 3 pixel in
both horizontal and vertical.
3. Horizontal/vertical shadow size of the OSD main window is 4 pixel in
both horizontal and vertical.
Controls the window shadow size as MW_BDSH_EN (ADDR 0x0108[2]) is
1 and MW_BDSH(ADDR 0x0108[1]) is 0.
Horizontal/vertical shadow size of the multiple windows are the same as
OSD main window.
Number of Multi-Colored RAM Font
3:0
N_MCF
- Up to 9 multi color fonts are available out of 28 RAM fonts. When
considering R/G/B, Up to 27 fonts (9x3) are available, and single color font
is used for the remaining 1 font. If 4 MCFs are used, 4*3 = 12 fonts out of
28 RAM fonts are used for MCF, and remaining 16 fonts can be used for
SF.
0x010D
OSD_BLINK_CONTROL (Default: 0 x 00)
Reserved
R/W
7:5
4:2
BLNK_SEL
Blink duty Select:
0: OFF 32 Frame (about 0.5sec) / ON 32 Frame (about 0.5sec)
1: OFF 64 Frame (about 1sec) / ON 32 Frame (about 0.5sec)
2: OFF 32 Frame (about 0.5sec) / ON 64 Frame (about 1sec)
3: OFF 64Frame (about 1sec) / ON 64 Frame (about 1sec)
4: OFF 96 Frame (about 1.5sec) / ON 96Frame (about 1.5sec)
5: OFF 128 Frame (about 2sec) / ON 64 Frame (about 1sec)
6: OFF 64 Frame (about 1sec) / ON 128 Frame (about 2sec)
7: OFF 128 Frame (about 2sec) / ON 128 Frame (about 2sec)
1
0
BL_NTRA
BLNK_C
Blink or No_Tone_Raster:
1: If Display RAM[14] is 1, Blink according to BLNK_SEL
0: If Display RAM[14] is 0, half tone is not applied to the raster part.
In this case, border/shadow of character is disabled.
Blink Color inversion:
1: If Blink is OFF, the complementary color of Raster is displayed in
the character part.
0: If Blink is OFF, the Raster color is displayed in the character part.
70
PRELIMINARY DATASHEET
S5D2400X
0x010E
OSD_W1_W2_COLOR (Default: 0 x 00)
Multiple Windows 1 Color.
R/W
7:4
3:0
W1C
- If W1_EN (ADDR 0x0109[3]) is 1 and n(0~15) is selected for W1C,
LUTn[3:0] is assigned for Multiple Windows 1.
For example, if W1C is 7 then LUT7[3:0] is assigned for the color of
windows multiple windows 1.
W2C
Multiple Windows 2 Color.
- If W2_EN (ADDR 0x0109[2]) is 1 and n(0~15) is selected for W2C,
LUTn[3:0] is assigned for Multiple Windows 2.
0x010F
OSD_W3_W4_COLOR (Default: 0 x 00)
Multiple Windows 3 Color.
R/W
7:4
3:0
W3C
W4C
- If W3_EN (ADDR 0x0109[1]) is 1 and n(0~15) is selected for W3C,
LUTn[3:0] is assigned for Multiple Windows 3.
Multiple Windows 4 Color.
- If W4_EN (ADDR 0x0109[0]) is 1 and n(0~15) is selected for W4C,
LUTn[3:0] is assigned for Multiple Windows 4.
0x0110
OSD_W1_ROW_STR (Default: 0 x 00)
Reserved
R/W
7:5
4:0
W1R_STR
Row Start position (1(not 0) ~ 31) of Multiple Windows 1
- If the bit is 1, y of the start (x, y) of Multiple Windows 1 is 1
0x0111
OSD_W1_ROW_END (Default: 0 x 00)
Reserved
R/W
7:5
4:0
W1R_END
Row End position (1(not 0) ~ 31) of Multiple Windows 1
- If the bit is 2, y of the end (x, y) of Multiple Windows 1 is 2
0x0112
OSD_W1_COLUMN_STR (Default: 0 x 00)
R/W
R/W
7:6
5:0
Reserved
W1C_STR
Column Start position (1(not 0) ~ 63) of Multiple Windows 1
- If the bit is 1, x of the start (x, y) of Multiple Windows 1 is 1
0x0113
OSD_W1_COLUMN_END (Default: 0 x 00)
Reserved
7:6
5:0
W1C_END
Column End position (1(not 0) ~ 63) of Multiple Windows 1
- If the bit is 2, x of the end (x, y) of Multiple Windows 1 is 2
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0x0114
OSD_W2_ROW_STR (Default: 0 x 00)
Reserved
R/W
7:5
4:0
W2R_STR
Row Start position (1(not 0) ~ 31) of Multiple Windows 2
- If the bit is 1, y of the start (x, y) of Multiple Windows 2 is 1
0x0115
OSD_W2_ROW_END (Default: 0 x 00)
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
7:5
4:0
W2R_END
Row End position (1(not 0) ~ 31) of Multiple Windows 2
- If the bit is 2, y of the end (x, y) of Multiple Windows 2 is 2
0x0116
OSD_W2_COLUMN_STR (Default: 0 x 00)
Reserved
7:6
5:0
W2C_STR
Column Start position (1(not 0) ~ 63) of Multiple Windows 2
- If the bit is 1, x of the start (x, y) of Multiple Windows 2 is 1
0x0117
OSD_W2_COLUMN_END (Default: 0 x 00)
Reserved
7:6
5:0
W2C_END
Column End position (1(not 0) ~ 63) of Multiple Windows 2
- If the bit is 2, x of the end (x, y) of Multiple Windows 2 is 2
0x0118
OSD_W3_ROW_STR (Default: 0 x 00)
Reserved
7:5
4:0
W3R_STR
Row Start position (1(not 0) ~ 31) of Multiple Windows 3
- If the bit is 1, y of the start (x, y) of Multiple Windows 3 is 1
0x0119
OSD_W3_ROW_END (Default: 0 x 00)
Reserved
7:5
4:0
W3R_END
Row End position (1(not 0) ~ 31) of Multiple Windows 3
- If the bit is 2, y of the end (x, y) of Multiple Windows 3 is 2
0x011A
OSD_W3_COLUMN_STR (Default: 0 x 00)
Reserved
7:6
5:0
W3C_STR
Column Start position (1(not 0) ~ 63) of Multiple Windows 3
- If the bit is 1, x of the start (x, y) of Multiple Windows 3 is 1
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0x011B
OSD_W3_COLUMN_END (Default: 0 x 00)
Reserved
R/W
7:6
5:0
W3C_END
Column End position (1(not 0) ~ 63) of Multiple Windows 3
- If the bit is 2, x of the start (x, y) of Multiple Windows 3 is 2
0x011C
OSD_W4_ROW_STR (Default: 0 x 00)
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
7:5
4:0
W4R_STR
Row Start position (1(not 0) ~ 31) of Multiple Windows 4
- If the bit is 1, y of the start (x, y) of Multiple Windows 4 is 1
0x011D
OSD_W4_ROW_END (Default: 0 x 00)
Reserved
7:5
4:0
W4R_END
Row End position (1(not 0) ~ 31) of Multiple Windows 4
- If the bit is 2, y of the end (x, y) of Multiple Windows 4 is 2
0x011E
OSD_W4_COLUMN_STR (Default: 0 x 00)
Reserved
7:6
5:0
W4C_STR
Column Start position (1(not 0) ~ 63) of Multiple Windows 4
- If the bit is 1, x of the start (x, y) of Multiple Windows 4 is 1
0x011F
OSD_W4_COLUMN_END (Default: 0 x 00)
Reserved
7:6
5:0
W4C_END
Column End position (1(not 0) ~ 63) of Multiple Windows 4
- If the bit is 2, x of the end (x, y) of Multiple Windows 4 is 2
0x0120
0x0121
OSD_LUT0 (Default: 0 x 00)
Look Up Table 0
7:0
7:0
LUT0
LUT1
(LUT0[7:4]: Font Character Color (7: R, 6: G, 5: G, 4: B)
LUT0[3:0]: Raster Font Color (3: R, 2: G, 1: G, 0: B))
OSD_LUT1 (Default: 0 x 00)
Look Up Table 1
(LUT1[7:4]: Font Character Color, LUT1[3:0]: Font Raster Color)
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0x0122
OSD_LUT2 (Default: 0 x 00)
Look Up Table 2
R/W
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
LUT2
(LUT2[7:4]: Font Character Color, LUT2[3:0]: Font Raster Color)
0x0123
0x0124
0x0125
0x0126
0x0127
0x0128
0x0129
OSD_LUT3 (Default: 0 x 00)
Look Up Table 3
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LUT3
LUT4
LUT5
LUT6
LUT7
LUT8
LUT9
(LUT3[7:4]: Font Character Color, LUT3[3:0]: Font Raster Color)
OSD_LUT4 (Default: 0 x 00)
Look Up Table 4
(LUT4[7:4]: Font Character Color, LUT4[3:0]: Font Raster Color)
OSD_LUT5 (Default: 0 x 00)
Look Up Table 5
(LUT5[7:4]: Font Character Color, LUT5[3:0]: Font Raster Color)
OSD_LUT6 (Default: 0 x 00)
Look Up Table 6
(LUT6[7:4]: Font Character Color, LUT6[3:0]: Font Raster Color)
OSD_LUT7 (Default: 0 x 00)
Look Up Table 7
(LUT7[7:4]: Font Character Color, LUT7[3:0]: Font Raster Color)
OSD_LUT8 (Default: 0 x 00)
Look Up Table 8
(LUT8[7:4]: Font Character Color, LUT8[3:0]: Font Raster Color)
OSD_LUT9 (Default: 0 x 00)
Look Up Table 9
(LUT9[7:4]: Font Character Color, LUT9[3:0]: Font Raster Color)
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0x012A
LUT10
OSD_LUT10 (Default: 0 x 00)
Look Up Table 10
(LUT10[7:4]: Font Character Color, LUT10[3:0]: Font Raster Color)
R/W
7:0
7:0
7:0
7:0
7:0
7:0
0x012B
LUT11
OSD_LUT11 (Default: 0 x 00)
Look Up Table 11
(LUT11[7:4]: Font Character Color, LUT11[3:0]: Font Raster Color)
R/W
0x012C
LUT12
OSD_LUT12 (Default: 0 x 00)
Look Up Table 12
(LUT12[7:4]: Font Character Color, LUT12[3:0]: Font Raster Color)
R/W
0x012D
LUT13
OSD_LUT13 (Default: 0 x 00)
Look Up Table 13
(LUT13[7:4]: Font Character Color, LUT13[3:0]: Font Raster Color)
R/W
0x012E
0x012F
0x43EF
OSD_LUT14 (Default: 0 x 00)
Look Up Table 14
(LUT14[7:4]: Font Character Color, LUT14[3:0]: Font Raster Color)
R/W
LUT14
LUT15
OSD_LUT15 (Default: 0 x 00)
Look Up Table 15
(LUT15[7:4]: Font Character Color, LUT15[3:0]: Font Raster Color)
R/W
FONT_RAM_EN
R/W
7:6
0
Reserved
FTRAM_EN
FONT RAM Enable (1: Enable, 0: Disable)
Writes data on the FONT RAM, and enables it.
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6.8 GAMMA CORRECTION CONTROL REGISTER
Bits
Register Name
0x0150
:
Function
GAM_R_LUT_1_2
Default
R/W
:
:
0x016F
RYAV1
RYAV2
RYAV3
RYAV4
RYAV5
RYAV6
RYAV7
RYAV8
RYAV9
RYAV10
RYAV11
RYAV12
GAM_R_LUT_31_32
R/W
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
RED Output (Y) Axis Value for Input (X) Axis
Value 8, 16, 24, 32, . . . , 240, 248, 255
8'h08
8'h10
8'h18
8'h20
8'h28
8'h30
8'h38
8'h40
8'h48
8'h50
8'h58
8'h60
Y
RYAV32
RYAV31
RYAV30
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
RYAV13
RYAV14
RYAV15
RYAV16
RYAV17
RYAV18
RYAV19
RYAV20
RYAV21
RYAV22
RYAV23
RYAV24
RYAV25
RYAV26
RYAV27
RYAV28
RYAV29
RYAV30
RYAV31
RYAV32
8'h68
8'h70
8'h78
8'h80
8'h88
8'h90
8'h98
8'hA0
8'hA8
8'hB0
8'hB8
8'hC0
8'hC8
8'hD0
8'hD8
8'hE0
8'hE8
8'hF0
8'hF8
8'hFF
RYAV4
RYAV3
RYAV2
RYAV1
X
0
8
16 24 32
. . . . . . . . . . 240, 248, 255
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Bits
Register Name
0x0170
Function
GAM_G_LUT_1_2
Default
R/W
:
:
:
0x018F
GAM_G_LUT_31_32
R/W
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
GYAV1
GREEN Output (Y) Axis Value for Input (X) Axis
Value 8, 16, 24, 32, . . . , 240, 248, 255
8'h08
8'h10
8'h18
8'h20
8'h28
8'h30
8'h38
8'h40
8'h48
8'h50
8'h58
8'h60
8'h68
8'h70
8'h78
8'h80
8'h88
8'h90
8'h98
8'hA0
8'hA8
8'hB0
8'hB8
8'hC0
8'hC8
8'hD0
8'hD8
8'hE0
8'hE8
8'hF0
8'hF8
8'hFF
GYAV2
GYAV3
GYAV4
Y
GYAV32
GYAV31
GYAV30
GYAV5
GYAV6
GYAV7
GYAV8
GYAV9
GYAV10
GYAV11
GYAV12
GYAV13
GYAV14
GYAV15
GYAV16
GYAV17
GYAV18
GYAV19
GYAV20
GYAV21
GYAV22
GYAV23
GYAV24
GYAV25
GYAV26
GYAV27
GYAV28
GYAV29
GYAV300
GYAV31
GYAV32
GYAV4
GYAV3
GYAV2
GYAV1
X
0
8
16 24 32
. . . . . . . . . . 240, 248, 255
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Bits
Register Name
0x0190
Function
GAM_B_LUT_1_2
Default
R/W
:
:
:
0x01AF
BYAV1
GAM_B_LUT_31_32
R/W
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
BLUE Output (Y) Axis Value for Input (X) Axis
Value 8, 16, 24, 32, . . . , 240, 248, 255
8'h08
8'h10
8'h18
8'h20
8'h28
8'h30
8'h38
8'h40
8'h48
8'h50
8'h58
8'h60
8'h68
8'h70
8'h78
8'h80
8'h88
8'h90
8'h98
8'hA0
8'hA8
8'hB0
8'hB8
8'hC0
8'hC8
8'hD0
8'hD8
8'hE0
8'hE8
8'hF0
8'hF8
8'hFF
BYAV2
BYAV3
BYAV4
Y
BYAV32
BYAV31
BYAV30
BYAV5
BYAV6
BYAV7
BYAV8
BYAV9
BYAV10
BYAV11
BYAV12
BYAV13
BYAV14
BYAV15
BYAV16
BYAV17
BYAV18
BYAV19
BYAV20
BYAV21
BYAV22
BYAV23
BYAV24
BYAV25
BYAV26
BYAV27
BYAV28
BYAV29
BYAV30
BYAV31
BYAV32
BYAV4
BYAV3
BYAV2
BYAV1
X
0
8
16 24 32
. . . . . . . . . . 240, 248, 255
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6.9 OSD RAM CONTROL REGISTERS
Address
Bits
Register Name
BU_LUT
Function
0x1000
~
7:0
ACCE Look Up Table
0x10FF
0x2000
~
0x2383
15:0
11:0
0
OSD_DSPRAM
OSD_FONTRAM
FTRAM_EN
Display RAM ( 450 ´ 16 bits ) for OSD
0x3FFF
~
0x43EE
Font RAM for OSD, 28 Fonts ( 1Fonts = 18 ´ 12 bits )
0x43EF
FONT RAM Enable (1: Enable, 0: Disable)
Writes data on the FONT RAM, and enables it.
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7 ELECTRICAL SPECIFICATION
7.1 ABSOLUTE MAXIMUM RATINGS
Table 8. Absolute Maximum Ratings
Characteristics
DC Supply Voltage
Symbol
Rating
Unit
V
1.8V V
3.3V V
2.7
3.8
3.8
6.5
V
DD
DD
DD
DC Input Voltage
V
3.3V input buffer
IN
3.3V interface /
5V tolerant input buffer
DC Output Voltage
V
3.3V output buffer
2.7
3.8
OUT
1.8V interface /
3.3V tolerant output buffer
Latch Up Current
I
± 100
mA
Latch
Storage temperature
T
Plastic
- 65 to 150
°C
STG
7.2 RECOMMENDED OPERATION CONDITIONS
Table 9. Recommended Operating Conditions
Characteristics
DC Supply Voltage
Symbol
Rating
Unit
V
1.8V V
3.3V V
1.8 ± 0.15
3.3 ± 0.3
3.3 ± 0.3
3.0 ~ 5.25
DD
DD
DD
V
DC Input Voltage
V
3.3V input buffer
IN
3.3V interface /
5V tolerant input buffer
DC Output Voltage
Operating Temperature
V
3.3V output buffer
3.3 ± 0.3
OUT
1.8V interface /
3.3V tolerant output buffer
1.8 ± 0.15
T
Commercial
0 to 70
°C
A
80
PRELIMINARY DATASHEET
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7.3 DC ELECTRICAL CHARACTERISTICS
VDD1 = 3.3V ± 0.3V, VDD2 = VDDA = 1.8V ± 0.15V, TA = 25°C
Table 10. DC Electrical Characteristics at 3.3V
Item
Symbol
Condition
Min
Typ
Max
Unit Remark
Supply Digital Power 1
V
V
3.0
3.3
3.6
V
V
V
V
V
V
V
V
V
V
V
V
*1
*2
*3
*4
DD
DD1
Voltage Digital Power 2
Analog Power
V
V
1.65
1.65
2.0
1.8
1.8
1.95
1.95
DD2
DDA
Input
High Level
V
V
IH
IL
Voltage Low Level
Output High Level
Voltage
0.8
V
I
= -2mA
= -4mA
= -20mA
= 2mA
2.4
2.4
2.4
*5
*6
*7
*5
*6
*7
*8
OH
OH
I
OH
I
OH
Low Level
V
I
0.4
0.4
0.4
2.0
OL
OL
I
= 4mA
OL
I
= 20mA
OL
Schmitt Positive-going threshold
Trigger Negative-going threshold
VT+
CMOS
CMOS
= V
-
VT
0.8
-10
V
Input
High
Input buffer
I
V
10
60
mA
*9
IH
IN
DD
Current Level
Input buffer
with
10
33
mA
*10
Pull-down
Low Level Input buffer
I
VIN = VSS
= V or V
DD
-10
-10
10
10
mA
mA
*9
IL
Tri-state Output Leakage Current
I
V
*11
OZ
OUT
SS
Power Consumption
[Remark]
Pd
900
mW
*1 : Pin 10, 39, 76
*4 : All Input Pins
*2 : Pin 21, 57, 94
*5 : Pin 58, 59, 60
*3 : Pin 15, 19
*7 : Pin 72
*6 : Pin 1~2, 8, 31~38, 40~47, 49~56, 73~75, 77~84, 86~93, 95~100
*8 : Pin 6~9, 61~65 *9 : Pin 6~9, 11, 20, 22~29, 61~65, 67~68
*10 : Pin 4~5, 31~38, 40~47, 49~56, 69~71
*11 : Pin 1~2, 31~38, 40~47, 49~56, 77~84, 86~93, 95~100
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7.4 AC ELECTRICAL CHARACTERISTICS
7.4.1 Video Input Timing Characteristics
TV (= 1 / F V)
TVH
TVL
VCK
TSU
THD
VI0 - 7, RI0 - 7,
GI0 - 7, BI0 - 7,
Valid Data
Valid Data
Valid Data
GHS, GVS, FLD
Item
Setup Time to VCK, input
Symbol
Min
Typ
Max
Units
T
2.0
ns
SU
VI0~7, RIO0~7, GIO0~7, BIO0~7,
GHS, GVS, FLD
Hold Time to VCK, input
VI0~7, RIO0~7, GIO0~7, BIO0~7,
GHS, GVS, FLD
T
2.0
ns
HD
Input Frequency
F
90
MHz
ns
V
Input High Duration Time
Input Low Duration Time
T
3.0
3.0
VH
T
ns
VL
82
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7.4.2 Display Output Timing Characteristics
TD
(= 1 / F D)
PCKO
(PCKO_PHASE[2] = 0)
90%
PCKO
(PCKO_PHASE[2] = 1)
10%
Tr
Tf
TPD
T
PD
RO0~7, GO0~7,
BO0~7, PHSO,
PVSO, PDEN
Valid Data
Valid Data
Item
Symbol
Min
Typ
Max
Units
Propagation Delay Time
T
- 3
0
3
ns
PD
from PCKO, Output RO0~7,
GO0~7, BO0~7, PHSO, PVSO, PDEN
Frequency, Output Display Clock
PCKO
F
100
55
3
MHz
%
D
Duty Cycle, Output Display Clock
PCKO
C
45
50
duty
Rise Time, Output Display Clock
PCKO
T
ns
r
Fall Time, Output Display Clock PCKO
T
3
ns
f
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8 PACKAGE DIMENSION
8.1 100-TQFP-1414
16.00 BSC
14.00
0-7
0.09 - 0.20
0.08 MAX
#100
#1
0.17 - 0.27
0.08 MAX
0.05 - 0.15
0.50
(1.00)
1.00
+ 0.05
1.20 MAX
NOTE: Dimensions are in millimeters.
84
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9 FONTS
85
PRELIMINARY DATASHEET
S5D2400X
86
PRELIMINARY DATASHEET
S5D2400X
87
PRELIMINARY DATASHEET
S5D2400X
88
PRELIMINARY DATASHEET
S5D2400X
89
PRELIMINARY DATASHEET
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90
PRELIMINARY DATASHEET
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91
PRELIMINARY DATASHEET
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92
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