S3C7238 [SAMSUNG]
The S3C7238/C7235 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung Arrange; 在S3C7238 / C7235单芯片CMOS微控制器是专为高性能使用三星最新的4位CPU内核， SAM47 （三星安排
| 型号： | S3C7238 |
| 厂家： | 
SAMSUNG |
| 描述： | The S3C7238/C7235 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung Arrange |
| 文件： | 总36页 (文件大小：294K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S3C7238/P7238/C7235/P7235
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
OVERVIEW
The S3C7238/C7235 single-chip CMOS microcontroller has been designed for high performance using
Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
With features such as LCD direct drive capability, 8-bit timer/counter, and serial I/O, the S3C7238/C7235 offer
an excellent design solution for a wide variety of applications that require LCD functions.
Up to 40 pins of the 80-pin QFP package can be dedicated to I/O. Six vectored interrupts provide fast response
to internal and external events. In addition, the S3C7238/C7235's advanced CMOS technology provides for low
power consumption and a wide operating voltage range.
OTP
The S3C7238/C7235 microcontroller is also available in OTP (One Time Programmable) version,
S3P7238/P7235. S3P7238/P7235 microcontroller has an on-chip 8/16-Kbyte one-time-programmable EPROM
instead of masked ROM. The S3P7238/P7235 is comparable to S3C7238/C7235, both in function and in pin
configuration.
1-1
PRODUCT OVERVIEW
S3C7238/P7238/C7235/P7235
FEATURES
Memory
Bit Sequential Carrier
–
Support 16-bit serial data transfer in arbitrary
format
–
–
–
512 ´ 4-bit RAM
8 K ´ 8-bit ROM (S3C7238/P7238)
16 K ´ 8-bit ROM (S3C7235/P7235)
Interrupts
I/O Pins
–
–
–
Three internal vectored interrupts
–
–
–
Input only: 8 pins
Three external vectored interrupts
Two quasi-interrupts
I/O: 24 pins
Output: 8 pins sharing with segment driver
outputs
Memory-Mapped I/O Structure
Data memory bank 15
–
LCD Controller/Driver
–
–
–
Maximum 16-digit LCD direct drive capability
32 segment, 4 common pins
Two Power-Down Modes
–
–
Idle mode (only CPU clock stops)
Display modes: Static, 1/2 duty (1/2 bias),
1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias)
Stop mode (main or sub system oscillation stops)
Oscillation Sources
8-Bit Basic Timer
–
–
–
–
–
Crystal, ceramic, or RC for main system clock
Crystal or external oscillator for subsystem clock
Main system clock frequency: 4.19 MHz (typical)
Subsystem clock frequency: 32.768 kHz
–
–
Programmable interval timer
Watchdog timer
8-Bit Timer/Counter 0
–
–
–
–
Programmable 8-bit timer
CPU clock divider circuit (by 4, 8, or 64)
External event counter
Instruction Execution Times
Arbitrary clock frequency output
Serial I/O interface clock generator
–
–
0.95, 1.91, 15.3 µs at 4.19 MHz (main)
122 µs at 32.768 kHz (subsystem)
Watch Timer
–
–
–
Real-time and interval time measurement
Operating Temperature
Four frequency outputs to BUZ pin
Clock source generation for LCD
° °
– 40 C to 85 C
–
Operating Voltage Range
1.8 V to 5.5 V
8-Bit Serial I/O Interface
–
–
–
–
–
8-bit transmit/receive mode
8-bit receive only mode
Package Type
80-pin QFP
LSB-first or MSB-first transmission selectable
Internal or external clock source
–
1-2
S3C7238/P7238/C7235/P7235
PRODUCT OVERVIEW
BLOCK DIAGRAM
Watch-Dog
Timer
Basic
Timer
Watch
Timer
P2.3/BUZ
BIAS
X
X
IN
XT
OUT
XT
VLC0-VLC2
LCDCK/P3.0
LCDSY/P3.1
COM0-COM3
SEG0-SEG23
INT0, INT1,INT2
RESET
IN
OUT
P1.3/TCL0
8-Bit Timer/
Counter 0
LCD Drive/
Controller
P2.0/TCLO0
Instruction
Register
Interrupt
Control
Block
Clock
P8.0-P8.7/
SEG24-SEG31
4-Bit
Accumulator
P0.0/INT4
P0.1/SCK
P0.2/SO
P0.3/SI
P4.0-P4.3
P5.0-P5.3
I/O Port 3
I/O Port 4
Internal
Interrupts
I/O Port
0
Program
Counter
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/TCL0
Program
Status Word
Input Port 1
P6.0-P6.3/
KS0-KS3
Instruction Decoder
I/O Port 6
I/O Port 7
P2.0/TCLO0
P2.1
P2.2/CLO
P2.3/BUZ
P7.0-P7.3/
KS4-KS7
FLAGS
I/O Port 2
I/O Port 3
Arithmetic and Logic Unit
Stack
Pointer
P3.0/LCDCK
P3.1/LCDSY
P3.2
P8.0-P8.7/
SEG24-SEG31
I/O Port 8
P3.3
Serial I/O
Port
512 x 4-Bit
Data
Memory
8/16-Kbyte
Program
Memory
P0.1 P0.2 P0.3
/SCK /SO /SI
Figure 1-1. S3C7238/C7235 Simplified Block Diagram
1-3
PRODUCT OVERVIEW
S3C7238/P7238/C7235/P7235
PIN ASSIGNMENTS
SEG2
SEG1
SEG0
COM0
COM1
COM2
COM3
BIAS
1
64
SEG19
2
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SEG20
3
SEG21
4
SEG22
5
SEG23
6
P8.0/SEG24
P8.1/SEG25
P8.2/SEG26
P8.3/SEG27
P8.4/SEG28
P8.5/SEG29
P8.6/SEG30
P8.7/SEG31
P7.3/KS7
P7.2/KS6
P7.1/KS5
P7.0/KS4
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
P5.3
7
8
VLC0
9
VLC1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SDAT /
/ VLC2
SCLK
V
S3C7238
S3C7235
/ V
DD
DD
/ V
V
SS
SS
Xout
Xin
(TOP VIEW)
/ TEST
XTin
TEST
XTout
RESET
/
RESET
P0.0/INT4
P0.1/SCK
P0.2/SO
P0.3/SI
P5.2
P1.0/INT0
P5.1
Figure 1-2. S3C7238/C7235 80-QFP Pin Assignment Diagram
1-4
S3C7238/P7238/C7235/P7235
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. S3C7238/C7235 Pin Descriptions
Pin Name Pin
Type
Description
Number
Share
Pin
Reset
Value
Circuit
Type
P0.0
P0.1
P0.2
P0.3
I
4-bit input port.
1-bit and 4-bit read and test are possible.
4-bit pull-up resistors are software assignable.
20
21
22
23
INT4
Input
Input
Input
Input
A-1
D *
D *
A-1
I/O
I/O
I
SCK
SO
SI
P1.0
P1.1
P1.2
P1.3
I
4-bit input port.
1-bit and 4-bit read and test are possible.
4-bit pull-up resistors are software assignable.
24
25
26
27
INT0
INT1
INT2
TCL0
A-1
P2.0
P2.1
P2.2
P2.3
I/O
I/O
4-bit I/O port.
1-bit and 4-bit read/write and test are possible.
4-bit pull-up resistors are software assignable.
28
29
30
31
TCLO0
–
CLO
BUZ
D
P3.0
P3.1
P3.2
P3.3
4-bit I/O port.
32
33
34
35
LCDCK
LCDSY
D
1-bit and 4-bit read/write and test are possible.
Each individual pin can be specified as input
or output. 4-bit pull-up resistors are software
assignable.
P4.0–
P4.3
P5.0–
P5.3
I/O
I/O
4-bit I/O ports. N-channel open-drain output up 36–43
to 5 V. 1-, 4-, and 8-bit read/write and test are
possible. Ports 4 and 5 can be paired to
support 8-bit data transfer. 4-bit pull-up
resistors are software assignable.
–
Input
Input
E
D *
P6.0–
P6.3
P7.0–
P7.3
4-bit I/O ports. Port 6 pins are individually
software configurable as input or output. 1-bit
and 4-bit read/write and test are possible. 4-bit
pull-up resistors are software assignable. Ports
6 and 7 can be paired to enable 8-bit data
transfer.
44–51 KS0–KS3
KS4–KS7
P8.0–
P8.7
O
O
O
O
–
Output port for 1-bit data (for use as CMOS
driver only)
59–52 SEG24–
SEG31
Output
Output
Output
Output
–
H-16
H-15
H-16
H-15
–
SEG0–
SEG23
LCD segment signal output
LCD segment signal output
LCD common signal output
3–1,
–
80–60
SEG24–
SEG31
59–52 P8.0–P8.7
COM0–
COM3
4–7
–
VLC0–VLC2
LCD power supply. Voltage dividing resistors
are assignable by mask option
9–11
SCLK
SDAT
BIAS
–
LCD power control
8
–
–
–
LCDCK
I/O
LCD clock output for display expansion
32
P3.0
Input
D
1-5
PRODUCT OVERVIEW
S3C7238/P7238/C7235/P7235
Table 1-1. S3C7238/C7235 Pin Descriptions (Continued)
Pin Name Pin
Type
Description
Number
Share
Pin
Reset
Value
Circuit
Type
LCDSY
I/O
LCD synchronization clock output for LCD
display expansion
33
P3.1
Input
D
TCL0
TCLO0
SI
I/O
I/O
I
External clock input for timer/counter 0
Timer/counter 0 clock output
Serial interface data input
27
28
23
22
21
P1.3
P2.0
P0.3
P0.2
P0.1
Input
Input
Input
Input
Input
Input
A-1
D
A-1
D *
D *
A-1
SO
I/O
I/O
I
Serial interface data output
Serial I/O interface clock signal
SCK
INT0
INT1
External interrupts. The triggering edge for
INT0 and INT1 is selectable. Only INT0 is
synchronized with the system clock.
24
25
P1.0
P1.1
INT2
I
I
Quasi-interrupt with detection of rising edge
signals.
26
20
P1.2
P0.0
Input
Input
Input
A-1
A-1
D *
INT4
External interrupt input with detection of rising
or falling edge
KS0–KS7
I/O
Quasi-interrupt inputs with falling edge
detection.
44–51
P6.0–P7.3
CLO
BUZ
I/O
I/O
CPU clock output
30
31
P2.2
P2.3
Input
Input
D
D
2, 4, 8 or 16 kHz frequency output for buzzer
sound with 4.19 MHz main system clock or
32.768 kHz subsystem clock.
X
–
–
Crystal, ceramic or RC oscillator pins for main
system clock. (For external clock input, use
15,14
17,18
–
–
–
–
–
–
IN,
X
OUT
XIN and input XIN‘s reverse phase to XOUT
)
XT
XT
Crystal oscillator pins for subsystem clock.
(For external clock input, use XTIN and input
IN,
OUT
XTIN's reverse phase to XTOUT
Main power supply
Ground
)
V
–
–
–
–
12
13
19
16
–
–
–
–
–
–
–
–
B
–
DD
V
SS
Reset signal
Input
–
RESET
Test signal input (must be connected to V
)
SS
TEST
NOTES:
1. Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.
*
2.
D Type has a schmitt trigger circuit at input.
1-6
S3C7238/P7238/C7235/P7235
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
V
DD
V
DD
P-CHANNEL
N-CHNNEL
P-CHANNEL
OUT
DATA
IN
N-CHANNEL
OUTPUT
DISABLE
Figure 1-3. Pin Circuit Type A
Figure 1-5. Pin Circuit Type C
V
DD
V
DD
PULL-UP
RESISTOR
PULL-UP
RESISTOR
RESISTOR
ENABLE
RESISTOR
ENABLE
P-CHANNEL
I/O
P-CHANNEL
IN
DATA
CIRCUIT
TYPE C
OUTPUT
DISABLE
SCHMITT TRIGGER
CIRCUIT TYPE A
Figure 1-4. Pin Circuit Type A-1 (P1, P0.0, P0.3)
Figure 1-6. Pin Circuit Type D
(P0.1, P0.2, P2, P3, P6, P7)
1-7
PRODUCT OVERVIEW
S3C7238/P7238/C7235/P7235
V
DD
PULL-UP
RESISTOR
V
DD
PNE
V
DD
RESISTOR
ENABLE
V
LC0
DATA
P-CH
I/O
V
LC1
OUTPUT
ENABLE
N-CH
LCD SEGMENT/
& PORT 8 DATA
OUT
CIRCUIT TYPE A
Figure 1-7. Pin Circuit Type E (P4, P5)
V
LC2
V
LC0
Figure 1-9. Pin Circuit Type H-16 (P8)
V
LC1
V
DD
LCD SEGMENT/
COMMON DATA
OUT
IN
V
LC2
SCHMITT TRIGGER
Figure 1-8. Pin Circuit Type H-15 (SEG/COM)
Figure 1-10. Pin Circuit Type B (RESET)
1-8
S3C7238/P7238/C7235/P7235
ELECTRICAL DATA
14 ELECTRICAL DATA
OVERVIEW
In this section, information on S3C7238/C7235 electrical characteristics is presented as tables and graphics. The
information is arranged in the following order:
Standard Electrical Characteristics
— Absolute maximum ratings
— D.C. electrical characteristics
— Main system clock oscillator characteristics
— Subsystem clock oscillator characteristics
— I/O capacitance
— A.C. electrical characteristics
— Operating voltage range
Miscellaneous Timing Waveforms
— A.C timing measurement point
— Clock timing measurement at X
IN
— Clock timing measurement at XT
— TCL timing
IN
— Input timing for RESET
— Input timing for external interrupts
— Serial data transfer timing
Stop Mode Characteristics and Timing Waveforms
— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request
14-1
ELECTRICAL DATA
S3C7238/P7238/C7235/P7235
Table 14-1. Absolute Maximum Ratings
°
(T = 25 C)
A
Parameter
Symbol
Conditions
Rating
– 0.3 to + 6.5
Units
VDD
VI1
Supply Voltage
Input Voltage
–
V
– 0.3 to V
– 0.3 to V
– 15
+ 0.3
+ 0.3
All I/O ports
DD
DD
VO
Output Voltage
Output Current High
–
IOH
One I/O pin active
mA
All I/O ports active
One I/O pin active
– 35
IOL
Output Current Low
+ 30 (Peak value)
+ 15 (note)
Total value for ports 0, 2, 3, and 5 + 100 (Peak value)
+ 60 (note)
Total value for ports 4, 6, and 7
+ 100
+ 60 (note)
– 40 to + 85
TA
°
C
Operating Temperature
Storage Temperature
–
–
Tstg
– 65 to + 150
Duty .
NOTE: The values for Output Current Low (IOL) are calculated as Peak Value ´
Table 14-2. D.C. Electrical Characteristics
(T = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
°
°
A
Parameter
Symbol
Conditions
Min
Typ
Max
Units
VIH1
0.7 VDD
VDD
Input high
voltage
All input pins except those
specified below for VIH2, VIH3
–
V
VIH2
VIH3
VIL1
VIL2
VIL3
VOH1
0.8 VDD
VDD
VDD
–
–
–
–
–
–
Ports 0, 1, 6, 7 and RESET
XIN, XOUT, XTIN and XTOUT
VDD – 0.1
0.3 VDD
0.2 VDD
0.1
Input low
voltage
Ports 2, 3, 4 and 5
–
V
V
–
–
Ports 0, 1, 6, 7 and RESET
XIN, XOUT, XTIN and XTOUT
VDD = 4.5 V to 5.5 V
VDD – 1.0
Output high
voltage
–
Ports 0, 2, 3, 4, 5, 6, 7 and BIAS
IOH = – 1 mA
VOH2
VDD = 4.5 V to 5.5 V
VDD – 2.0
–
–
Port 8 ONLY
IOH = – 100 µA
14-2
S3C7238/P7238/C7235/P7235
ELECTRICAL DATA
Table 14-2. D.C. Electrical Characteristics (Continued)
(T = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
°
°
A
Parameter
Symbol
Conditions
VDD = 4.5 V to 5.5 V, Ports 0, 2–7
IOL = 15 mA
Min
Typ
Max
Units
VOL1
Output low
voltage
–
0.4
2
V
V
V
= 4.5 V to 5.5 V, Port 8 only
= 100 µA
–
–
–
–
1
3
OL2
DD
I
OL
I
V
= V
Input high
leakage
current
µA
LIH1
IN DD
All input pins except those specified
below for I
LIH2
= V
IN DD
I
V
–
–
–
–
20
LIH2
X , X
IN OUT,
XT XT
IN and
OUT
I
V
= 0 V
Input low
leakage
current
– 3
LIL1
IN
All input pins except X , X
IN OUT,
XT
XT
OUT
IN and
= 0 V
I
V
IN
– 20
3
LIL2
X , X
IN OUT
V = V
OUT
, XT XT
IN and
OUT
I
Output high
leakage
current
–
–
µA
LOH1
DD
All output pins
V = 0 V
OUT
I
Output low
leakage
current
– 3
LOL
All output pins
R
Pull-up
resistor
Ports 0–7
25
47
100
KW
L1
V
V
= 0 V; V
= 3 V
= 5 V
DD
IN
50
95
200
400
DD
R
L2
100
220
V
V
= 0 V; V
= 5 V, RESET
DD
IN
= 3 V
200
50
450
93
800
140
DD
R
LCD
°
LCD voltage
dividing
TA = 25 C
resistor
RCOM
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
COM output
impedance
SEG output
impedance
–
3
5
6
15
6
RSEG
3
5
15
± 90
VDD = 5 V (VLC0 – COMi)
COM output
voltage
deviation
VDC
VDS
–
–
mV
mV
± 45
Io = ± 15uA (I = 0–3)
VDD = 5 V (VLC0-SEGi)
ñ 45
ñ 90
SEG output
voltage
deviation
Io = ± 15mA (I = 0–31)
14-3
ELECTRICAL DATA
S3C7238/P7238/C7235/P7235
Table 14-2. D.C. Electrical Characteristics (Concluded)
°
°
(T = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
A
Parameter
Symbol
Conditions
Min
0.6 VDD 0.6 VDD 0.6 VDD
0.2
Typ
Max
Units
TA = 25 øC
+
VLC0 Output
voltage
VLC0
V
0.2
0.4 VDD 0.4 VDD 0.4 VDD
– 0.2 + 0.2
0.2 VDD 0.2 VDD 0.2 VDD
–
TA = 25 øC
TA = 25 øC
VLC1 Output
voltage
VLC1
VLC2 Output
voltage
VLC2
(2)
– 0.2
–
+ 0.2
Supply
Current (1)
Main operating:
= 5 V ± 10%
6.0 MHz
4.19 MHz
3.5
2.5
8
mA
I
DD1
V
DD
5.5
CPU = fx/4
SCMOD = 000B
crystal oscillator
C1 = C2 = 22pF
V
DD
= 3 V ± 10%
6.0 MHz
4.19 MHz
1.6
1.2
4
3
(2)
Main Idle mode;
= 5 V ± 10%
6.0 MHz
4.19 MHz
–
1.0
0.9
2.5
2.0
I
DD2
V
DD
CPU = fx/4
SCMOD = 000B
crystal oscillator
C1 = C2 = 22pF
V
DD
= 3 V ± 10%
6.0 MHz
4.19 MHz
0.5
0.4
1.0
0.8
I
Sub operating:
= 3 V ± 10%
–
15
30
µA
DD3
V
DD
CPU = fxt/4
SCMOD = 1001B
32 kHz crystal oscillator
I
I
Sub Idle mode;
–
–
6
15
3
DD4
V
DD
= 3 V ± 10%
CPU = fxt/4, SCMOD = 1101B
32 kHz crystal oscillator
Stop mode;
0.5
DD5
VDD = 5 V ± 10%
CPU = fxt/4, SCMOD = 1101B
(3)
Stop mode;
VDD = 5 V ± 10%
I
DD6
CPU = fx/4, SCMOD = 0100B
NOTES:
1. D.C. electrical values for supply current (I
to I
) do not include current drawn through internal pull-up resistors
DD6
DD1
and through LCD voltage dividing resistors.
2. Data includes the power consumption for sub-system clock oscillation.
3. When the system clock mode register, SCMOD, is set to 0100B, the sub-system clock oscillation stops. The
main-system clock oscillation stops by the STOP instruction.
14-4
S3C7238/P7238/C7235/P7235
ELECTRICAL DATA
Table 14-3. Main System Clock Oscillator Characteristics
= 1.8 V to 5.5 V)
°
°
(T = – 40 C + 85 C, V
A
DD
Oscillator
Clock
Parameter
Test Condition
Min
Typ
Max Units
Configuration
(1)
Ceramic
Oscillator
–
0.4
–
6.0
MHz
Oscillation frequency
X
IN
X
OUT
C1
C2
(2)
Stabilization occurs
–
–
–
4
ms
Stabilization time
when V
is equal to
DD
the minimum oscillator
voltage range.
(1)
Crystal
Oscillator
–
0.4
6.0
MHz
Oscillation frequency
IN
X
OUT
X
C1
C2
(2)
V
V
= 4.5 V to 5.5 V
= 1.8 V to 4.5 V
–
–
–
–
–
–
10
30
ms
DD
Stabilization time
DD
(1)
External
Clock
0.4
6.0
MHz
X
IN
input frequency
X
IN
X
OUT
X
input high and low
–
83.3
0.4
–
–
2
ns
IN
level width (t , t
)
XH XL
Frequency (1)
V
DD
= 5 V
RC
Oscillator
–
MHz
X
IN
X
OUT
2.0
1.0
R = 20 KW, V
R = 38 KW, V
= 5 V
= 3 V
DD
R
DD
NOTES:
1. Oscillation frequency and X input frequency data are for oscillator characteristics only.
IN
2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is
terminated.
14-5
ELECTRICAL DATA
S3C7238/P7238/C7235/P7235
Table 14-4. Subsystem Clock Oscillator Characteristics
= 1.8 V to 5.5 V)
°
°
(T = – 40 C + 85 C, V
A
DD
Oscillator
Clock
Parameter
Test Condition
Min
Typ
Max Units
Configuration
XT XT
Oscillation frequency (1)
Crystal
–
32
32.768
35
kHz
IN
OUT
Oscillator
C1
C2
(2)
V
V
= 4.5 V to 5.5 V
–
–
1.0
–
2
s
DD
Stabilization time
= 1.8 V to 4.5 V
–
10
DD
XT input frequency (1)
IN
External
Clock
32
–
100
kHz
XT
XT
OUT
IN
XT input high and low
IN
–
5
–
15
µs
level width (t
, t )
XTL XTH
NOTES:
1. Oscillation frequency and XT input frequency data are for oscillator characteristics only.
IN
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs.
Table 14-5. Input/Output Capacitance
°
(T = 25 C, V = 0 V )
A
DD
Parameter
Symbol
Condition
Min
Typ
Max
Units
C
Input
capacitance
f = 1 MHz; Unmeasured pins
–
–
15
15
15
pF
pF
pF
IN
are returned to V
SS
C
OUT
Output
capacitance
–
–
–
–
C
IO
I/O capacitance
14-6
S3C7238/P7238/C7235/P7235
ELECTRICAL DATA
Table 14-6. A.C. Electrical Characteristics
°
°
(T = – 40 C to + 85 C, V
= 1.8 V to 5.5 V)
DD
A
Parameter
Symbol
Conditions
= 2.7 V to 5.5 V
= 1.8 V to 4.5 V
Min
0.67
0.95
114
0
Typ
–
Max
64
64
125
1.5
1
Units
t
V
V
Instruction cycle
µs
CY
DD
(1)
–
DD
time
With subsystem clock (fxt)
122
–
f
V
DD
V
DD
V
DD
V
DD
V
DD
= 2.7 V to 5.5 V
= 1.8 V to 5.5V
= 2.7 V to 5.5 V
= 1.8 V to 5.5 V
= 2.7 V to 5.5 V
TCL0 input
MHz
MHz
µs
TI0
frequency
t
, t
TCL0 input high,
low width
0.48
1.8
–
–
–
TIH0 TIL0
t
800
–
ns
SCK cycle time
KCY
External SCK source
Internal SCK source
650
V
DD
= 1.8 V to 5.5 V
3200
External SCK source
Internal SCK source
3800
400
t
, t
KH KL
V
DD
= 1.8 V to 5.5 V
–
–
ns
SCK high, low
width
External SCK source
Internal SCK source
t
/2 – 50
KCY
V
DD
= 1.8 V to 5.5 V
1600
External SCK source
Internal SCK source
t
KCY/2 – 150
t
SI setup time to
100
150
400
400
–
–
–
–
–
–
ns
ns
ns
External SCK source
Internal SCK source
External SCK source
SIK
SCK high
t
SI hold time to
KSI
SCK high
Internal SCK source
VDD = 2.7 V to 5.5 V
External SCK source
Internal SCK source
VDD = 1.8 V to 5.5 V
External SCK source
Internal SCK source
INT0
t
Output delay for
SCK to SO
300
KSO
250
1000
1000
–
(2)
t
,
Interrupt input
high, low width
–
–
µs
µs
INTH
t
INTL
INT1, INT2, INT4, KS0–KS7
Input
10
10
t
–
RESET Input Low
RSL
Width
NOTES:
1. Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock (fx) source.
2. Minimum value for INT0 is based on a clock of 2t or 128/fx as assigned by the IMOD0 register setting.
CY
14-7
ELECTRICAL DATA
S3C7238/P7238/C7235/P7235
CPU Clock
1.5 MHz
Main OSC. Frequency
6 MHz
1.0475 MHz
1.00 MHz
4.19 MHz
3 MHz
750 kHz
500 kHz
250 kHz
15.6 kHz
1
1.8
3
4
5
6
7
Supply Voltage (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64)
Figure 14-1. Standard Operating Voltage Range
Table 14-7. RAM Data Retention Supply Voltage in Stop Mode
°
°
(T = – 40 C to + 85 C)
A
Parameter
Symbol
Conditions
Min
1.8
–
Typ
–
Max
6.5
10
–
Unit
V
V
DDDR
Data retention supply voltage
Data retention supply current
Release signal set time
Oscillator stabilization wait
time (1)
Normal operation
I
V
= 1.8 V
0.1
–
µA
µs
DDDR
DDDR
t
Normal operation
0
SREL
217/fx
(2)
t
–
–
ms
Released by RESET
WAIT
Released by interrupt
–
–
NOTES:
1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator
start-up.
2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
14-8
S3C7238/P7238/C7235/P7235
ELECTRICAL DATA
TIMING WAVEFORMS
INTERNAL
RESET
IDLE MODE
STOP MODE
OPERATING
MODE
DATA RETENTION MODE
VDD
VDDDR
EXECUTION OF
STOP INSTRUCTION
RESET
tWAIT
tSREL
Figure 14-2. Stop Mode Release Timing When Initiated By RESET
IDLE MODE
NORMAL
STOP MODE
OPERATING
MODE
DATA RETENTION MODE
DD
V
VDDDR
tSREL
EXECUTION OF
STOP INSTRUCTION
tWAIT
POWER-DOWN MODE TERMINATING SIGNAL
(INTERRUPT REQUEST)
Figure 14-3. Stop Mode Release Timing When Initiated By Interrupt Request
14-9
ELECTRICAL DATA
S3C7238/P7238/C7235/P7235
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
MEASUREMENT
POINTS
Figure 14-4. A.C. Timing Measurement Points (Except for X and XT )
IN IN
1/f
x
t
t
XH
XL
X
in
V
– 0.1 V
DD
0.1 V
Figure 14-5. Clock Timing Measurement at X
IN
1/f
xt
t
t
XTH
XTL
XT
in
V
– 0.1 V
DD
0.1 V
Figure 14-6. Clock Timing Measurement at XT
IN
14-10
S3C7238/P7238/C7235/P7235
ELECTRICAL DATA
1/f
TI0
t
t
TIH0
TIL0
TCL0
0.8 V
DD
0.2 V
DD
Figure 14-7. TCL0 Timing
tRSL
RESET
0.2 V
DD
Figure 14-8. Input Timing for RESET Signal
tINTL
t
INTH
INT0, 1, 2, 4
KS0 to KS7
0.8 V
DD
0.2 V
DD
Figure 14-9. Input Timing for External Interrupts and Quasi-Interrupts
14-11
ELECTRICAL DATA
S3C7238/P7238/C7235/P7235
t
KCY
t
t
KH
KL
0.8 V
0.2 V
DD
DD
SCK
t
t
KSI
SIK
0.8 V
0.2 V
DD
DD
SI
INPUT DATA
t
KSO
SO
OUTPUT DATA
Figure 14-10. Serial Data Transfer Timing
14-12
S3C7238/P7238/C7235/P7235
MECHANICAL DATA
15 MECHANICAL DATA
The S3C7238/C7235 is available in a 80-QFP-1420 package.
23.90 ± 0.30
20.00 ± 0.20
0-8
+ 0.10
- 0.05
0.15
0.10 MAX
80-QFP-1420C
#80
#1
0.35 + 0.10
0.05 MIN
2.65 ± 0.10
3.00 MAX
0.80
0.15 MAX
(0.80)
0.80 ± 0.20
NOTE: Dimensions are in millimeters.
Figure 15-1. 80-QFP-1420C Package Dimensions
15-1
S3C7238/P7238/C7235/P7235
S3P7238/P7235 OTP
16 S3P7238/P7235 OTP
OVERVIEW
The S3P7238/P7235 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
S3C7238/C7235 microcontroller. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by
a serial data format.
The S3P7238/P7235 is fully compatible with the S3C7238/C7235, both in function and in pin configuration.
Because of its simple programming requirements, the S3P7238/P7235 is ideal for use as an evaluation chip for
the S3C7238/C7235.
16-1
S3P7238/P7235 OTP
S3C7238/P7238/C7235/P7235
SEG2
SEG1
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SEG19
2
SEG20
SEG0
3
SEG21
COM0
4
SEG22
COM1
5
SEG23
COM2
6
P8.0/SEG24
P8.1/SEG25
P8.2/SEG26
P8.3/SEG27
P8.4/SEG28
P8.5/SEG29
P8.6/SEG30
P8.7/SEG31
P7.3/KS7
P7.2/KS6
P7.1/KS5
P7.0/KS4
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
P5.3
COM3
7
BIAS
8
VLC0
9
SDAT / VLC1
SCLK / VLC2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
S3P7238
S3P7235
V
/ V
DD
/ V
SS
Xout
DD
V
SS
(TOP VIEW)
Xin
TEST / TEST
XTin
XTout
RESET
RESET
/
P0.0/INT4
P0.1/SCK
P0.2/SO
P0.3/SI
P5.2
P1.0/INT0
P5.1
NOTE: The bolds indicate an OTP pin names.
Figure 16-1. S3P7238/P7235 Pin Assignments (80-QFP)
16-2
S3C7238/P7238/C7235/P7235
S3P7238/P7235 OTP
Table 16-1. Pin Descriptions Used to Read/Write the EPROM
During Programming
Main Chip
Pin Name
Pin Name
SDAT
Pin No.
I/O
Function
VLC1
10
I/O
Serial data pin. Output port when reading and
input port when writing can be assigned as
Input/push-pull output port respectively.
VLC2
SCLK
11
16
I/O
I
Serial clock pin. Input only pin.
VPP (TEST)
TEST
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is applied, OTP is in reading mode.
(Option)
19
I
I
Chip initialization
RESET
RESET
VDD / VSS
VDD / VSS
Logic power supply pin. VDD should be tied to +5
V during programming.
12/13
Table 16-2. Comparison of S3P7238/P7235 and S3C7238/C7235 Features
Characteristic
S3P7238/P7235
8 K/16 K-byte EPROM
1.8 V to 5.5 V
S3C7238/C7235
Program Memory
8 K/16-Kbyte mask ROM
1.8 V to 5.5 V
Operating Voltage (VDD
)
VDD = 5 V, VPP (TEST) = 12.5 V
OTP Programming Mode
–
Pin Configuration
80 QFP
80 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the Vpp (TEST) pin of the S3P7238/P7235, the EPROM programming mode is
entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins
listed in Table 16-3 below.
Table 16-3. Operating Mode Selection Criteria
V
DD
Vpp
(TEST)
REG/
Address
(A15-A0)
Mode
R/W
MEM
5 V
5 V
0
0
0
1
0000H
0000H
0000H
0E3FH
1
0
1
0
EPROM read
12.5V
12.5V
12.5V
EPROM program
EPROM verify
EPROM read protection
NOTE: "0" means low level; "1" means high level.
16-3
S3P7238/P7235 OTP
S3C7238/P7238/C7235/P7235
Table 16-4. Absolute Maximum Ratings
°
(T = 25 C)
A
Parameter
Symbol
Conditions
Rating
– 0.3 to + 6.5
Units
VDD
VI1
Supply Voltage
Input Voltage
–
V
– 0.3 to V
– 0.3 to V
– 15
+ 0.3
+ 0.3
All I/O ports
DD
DD
VO
Output Voltage
Output Current High
–
IOH
One I/O pin active
mA
All I/O ports active
One I/O pin active
– 35
IOL
Output Current Low
+ 30 (Peak value)
+ 15 (note)
Total value for ports 0, 2, 3, and 5 + 100 (Peak value)
+ 60 (note)
Total value for ports 4, 6, and 7
+ 100
+ 60 (note)
– 40 to + 85
°
C
TA
Operating Temperature
Storage Temperature
–
–
Tstg
– 65 to + 150
Duty .
NOTE: The values for Output Current Low (IOL) are calculated as Peak Value ´
Table 16-5. D.C. Electrical Characteristics
(T = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
°
°
A
Parameter
Symbol
Conditions
Min
Typ
Max
Units
VIH1
0.7 VDD
VDD
Input high
voltage
All input pins except those
specified below for VIH2, VIH3
–
V
VIH2
VIH3
VIL1
VIL2
VIL3
VOH1
0.8 VDD
VDD
VDD
–
–
–
–
–
–
Ports 0, 1, 6, 7 and RESET
XIN, XOUT, XTIN and XTOUT
VDD – 0.1
0.3 VDD
0.2 VDD
0.1
Input low
voltage
Ports 2, 3, 4 and 5
–
V
V
–
–
Ports 0, 1, 6, 7 and RESET
XIN, XOUT, XTIN and XTOUT
VDD = 4.5 V to 5.5 V
VDD – 1.0
Output high
voltage
–
Ports 0, 2, 3, 4, 5, 6, 7 and BIAS
IOH = – 1 mA
VOH2
VDD = 4.5 V to 5.5 V
VDD – 2.0
–
–
Port 8 ONLY
IOH = – 100 µA
16-4
S3C7238/P7238/C7235/P7235
S3P7238/P7235 OTP
Table 16-5. D.C. Electrical Characteristics (Continued)
(T = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
°
°
A
Parameter
Symbol
Conditions
VDD = 4.5 V to 5.5 V, Ports 0, 2–7
IOL = 15 mA
Min
Typ
Max
Units
VOL1
Output low
voltage
–
0.4
2
V
V
V
= 4.5 V to 5.5 V, Port 8 only
= 100 µA
–
–
–
–
1
3
OL2
DD
I
OL
I
V
= V
Input high
leakage
current
µA
LIH1
IN DD
All input pins except those specified
below for I
LIH2
= V
IN DD
I
V
–
–
–
–
20
LIH2
X , X
IN OUT,
XT XT
IN and
OUT
I
V
= 0 V
Input low
leakage
current
– 3
LIL1
IN
All input pins except X , X
IN OUT,
XT
XT
OUT
IN and
= 0 V
I
V
IN
– 20
3
LIL2
X , X
IN OUT
V = V
OUT
, XT XT
IN and
OUT
I
Output high
leakage
current
–
–
µA
LOH1
DD
All output pins
V = 0 V
OUT
I
Output low
leakage
current
– 3
LOL
All output pins
R
Pull-up
resistor
Ports 0–7
25
47
100
KW
L1
V
V
= 0 V; V
= 3 V
= 5 V
DD
IN
50
100
200
50
95
220
450
93
200
400
800
140
DD
R
L2
V
V
= 0 V; V
= 5 V, RESET
DD
IN
= 3 V
DD
°
R
LCD
LCD voltage
dividing
TA = 25 C
resistor
RCOM
RSEG
VDC
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
COM output
impedance
SEG output
impedance
–
3
5
6
15
6
3
5
15
± 90
VDD = 5 V (VLC0 – COMi)
COM output
voltage
deviation
–
–
mV
mV
± 45
Io = ± 15uA (I = 0–3)
VDD = 5 V (VLC0-SEGi)
ñ 45
ñ 90
SEG output
voltage
deviation
VDS
Io = ± 15mA (I = 0–31)
16-5
S3P7238/P7235 OTP
S3C7238/P7238/C7235/P7235
Table 16-5. D.C. Electrical Characteristics (Concluded)
°
°
(T = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
A
Parameter
Symbol
Conditions
Min
0.6 VDD 0.6 VDD 0.6 VDD
– 0.2 0.2
0.4 VDD 0.4 VDD 0.4 VDD
– 0.2 + 0.2
0.2 VDD 0.2 VDD 0.2 VDD
Typ
Max
Units
TA = 25 øC
TA = 25 øC
TA = 25 øC
+
VLC0 Output
voltage
VLC0
V
VLC1 Output
voltage
VLC1
VLC2 Output
voltage
VLC2
(2)
– 0.2
–
+ 0.2
Supply
Current (1)
Main operating:
= 5 V ± 10%
6.0 MHz
4.19 MHz
3.5
2.5
8
mA
I
DD1
V
DD
5.5
CPU = fx/4
SCMOD = 000B
crystal oscillator
C1 = C2 = 22pF
V
DD
= 3 V ± 10%
6.0 MHz
4.19 MHz
1.6
1.2
4
3
(2)
Main Idle mode;
= 5 V ± 10%
6.0 MHz
4.19 MHz
–
1.0
0.9
2.5
2.0
I
DD2
V
DD
CPU = fx/4
SCMOD = 000B
crystal oscillator
C1 = C2 = 22pF
V
DD
= 3 V ± 10%
6.0 MHz
4.19 MHz
0.5
0.4
1.0
0.8
I
Sub operating:
= 3 V ± 10%
–
15
30
µA
DD3
V
DD
CPU = fxt/4
SCMOD = 1001B
32 kHz crystal oscillator
I
I
Sub Idle mode;
–
–
6
15
3
DD4
V
DD
= 3 V ± 10%
CPU = fxt/4, SCMOD = 1101B
32 kHz crystal oscillator
Stop mode;
0.5
DD5
VDD = 5 V ± 10%
CPU = fxt/4, SCMOD = 1101B
(3)
Stop mode;
VDD = 5 V ± 10%
I
DD6
CPU = fx/4, SCMOD = 0100B
NOTES:
1. D.C. electrical values for supply current (I
to I
) do not include current drawn through internal pull-up resistors and
DD6
DD1
through LCD voltage dividing resistors.
2. Data includes the power consumption for sub-system clock oscillation.
3. When the system clock mode register, SCMOD, is set to 0100B, the sub-system clock oscillation stops. The
main-system clock oscillation stops by the STOP instruction.
16-6
S3C7238/P7238/C7235/P7235
S3P7238/P7235 OTP
Table 16-6. Main System Clock Oscillator Characteristics
= 1.8 V to 5.5 V)
°
°
(T = – 40 C + 85 C, V
A
DD
Oscillator
Clock
Parameter
Test Condition
Min
Typ
Max Units
Configuration
(1)
Ceramic
Oscillator
–
0.4
–
6.0
MHz
Oscillation frequency
IN
X
OUT
X
C1
C2
(2)
Stabilization occurs
–
–
–
4
ms
Stabilization time
when V
is equal to
DD
the minimum oscillator
voltage range.
(1)
Crystal
Oscillator
–
0.4
6.0
MHz
Oscillation frequency
X
IN
X
OUT
C1
C2
(2)
V
V
= 4.5 V to 5.5 V
= 1.8 V to 4.5 V
–
–
–
–
–
–
10
30
ms
DD
Stabilization time
DD
(1)
External
Clock
0.4
6.0
MHz
X
IN
input frequency
X
IN
X
OUT
X
input high and low
–
83.3
0.4
–
–
2
ns
IN
level width (t , t
)
XH XL
Frequency (1)
V
DD
= 5 V
RC
Oscillator
–
MHz
IN
X
OUT
X
2.0
1.0
R = 20 KW, V
R = 38 KW, V
= 5 V
= 3 V
DD
R
DD
NOTES:
1. Oscillation frequency and X input frequency data are for oscillator characteristics only.
IN
2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is
terminated.
16-7
S3P7238/P7235 OTP
S3C7238/P7238/C7235/P7235
Table 16-7. Subsystem Clock Oscillator Characteristics
= 1.8 V to 5.5 V)
°
°
(T = – 40 C + 85 C, V
A
DD
Oscillator
Clock
Parameter
Test Condition
Min
Typ
Max Units
Configuration
XT XT
Oscillation frequency (1)
Crystal
IN
OUT
–
32
32.768
35
kHz
Oscillator
C1
C2
(2)
V
V
= 4.5 V to 5.5 V
–
–
1.0
–
2
s
DD
Stabilization time
= 1.8 V to 4.5 V
–
10
DD
XT input frequency (1)
IN
External
Clock
32
–
100
kHz
XT
XT
OUT
IN
XT input high and low
IN
–
5
–
15
µs
level width (t
, t )
XTL XTH
NOTES:
1. Oscillation frequency and XT input frequency data are for oscillator characteristics only.
IN
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs.
Table 16-8. Input/Output Capacitance
°
(T = 25 C, V = 0 V )
A
DD
Parameter
Symbol
Condition
Min
Typ
Max
Units
C
Input
capacitance
f = 1 MHz; Unmeasured pins
–
–
15
15
15
pF
pF
pF
IN
are returned to V
SS
C
OUT
Output
capacitance
–
–
–
–
C
IO
I/O capacitance
16-8
S3C7238/P7238/C7235/P7235
S3P7238/P7235 OTP
Table 16-9. A.C. Electrical Characteristics
°
°
(T = – 40 C to + 85 C, V
= 1.8 V to 5.5 V)
DD
A
Parameter
Symbol
Conditions
= 2.7 V to 5.5 V
= 1.8 V to 4.5 V
Min
0.67
0.95
114
0
Typ
–
Max
64
64
125
1.5
1
Units
t
V
V
Instruction cycle
µs
CY
DD
(1)
–
DD
time
With subsystem clock (fxt)
122
–
f
V
DD
V
DD
V
DD
V
DD
V
DD
= 2.7 V to 5.5 V
= 1.8 V to 5.5V
= 2.7 V to 5.5 V
= 1.8 V to 5.5 V
= 2.7 V to 5.5 V
TCL0 input
MHz
MHz
µs
TI0
frequency
t
, t
TCL0 input high,
low width
0.48
1.8
–
–
–
TIH0 TIL0
t
800
–
ns
SCK cycle time
KCY
External SCK source
Internal SCK source
650
V
DD
= 1.8 V to 5.5 V
3200
External SCK source
Internal SCK source
3800
400
t
, t
KH KL
V
DD
= 1.8 V to 5.5 V
–
–
ns
SCK high, low
width
External SCK source
Internal SCK source
t
/2 – 50
KCY
V
DD
= 1.8 V to 5.5 V
1600
External SCK source
Internal SCK source
t
KCY/2 – 150
t
SI setup time to
100
150
400
400
–
–
–
–
–
–
ns
ns
ns
External SCK source
Internal SCK source
External SCK source
Internal SCK source
VDD = 2.7 V to 5.5 V
External SCK source
Internal SCK source
VDD = 1.8 V to 5.5 V
External SCK source
Internal SCK source
INT0
SIK
SCK high
t
SI hold time to
KSI
SCK high
t
Output delay for
SCK to SO
300
KSO
250
1000
1000
–
(2)
t
,
Interrupt input
high, low width
–
–
µs
µs
INTH
t
INTL
INT1, INT2, INT4, KS0–KS7
Input
10
10
t
–
RESET Input Low
RSL
Width
NOTES:
1. Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock (fx) source.
2. Minimum value for INT0 is based on a clock of 2t or 128/fx as assigned by the IMOD0 register setting.
CY
16-9
S3P7238/P7235 OTP
S3C7238/P7238/C7235/P7235
CPU Clock
1.5 MHz
Main OSC. Frequency
6 MHz
1.0475 MHz
1.00 MHz
4.19 MHz
3 MHz
750 kHz
500 kHz
250 kHz
15.6 kHz
1
1.8
3
4
5
6
7
Supply Voltage (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64)
Figure 16-2. Standard Operating Voltage Range
Table 16-10. RAM Data Retention Supply Voltage in Stop Mode
°
°
(T = – 40 C to + 85 C)
A
Parameter
Symbol
Conditions
Min
1.8
–
Typ
–
Max
6.5
10
–
Unit
V
V
DDDR
Data retention supply voltage
Data retention supply current
Release signal set time
Normal operation
I
V
= 1.8 V
0.1
–
µA
µs
DDDR
DDDR
t
Normal operation
0
SREL
217/fx
(2)
t
Oscillator stabilization wait
–
–
ms
Released by RESET
WAIT
time (1)
Released by interrupt
–
–
NOTES:
1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator
start-up.
2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
16-10
S3C7238/P7238/C7235/P7235
TIMING WAVEFORMS
S3P7238/P7235 OTP
INTERNAL
RESET
IDLE MODE
STOP MODE
OPERATING
MODE
DATA RETENTION MODE
VDD
VDDDR
EXECUTION OF
STOP INSTRUCTION
RESET
tWAIT
tSREL
Figure 16-3. Stop Mode Release Timing When Initiated By RESET
IDLE MODE
NORMAL
STOP MODE
OPERATING
MODE
DATA RETENTION MODE
DD
V
VDDDR
tSREL
EXECUTION OF
STOP INSTRUCTION
tWAIT
POWER-DOWN MODE TERMINATING SIGNAL
(INTERRUPT REQUEST)
Figure 16-4. Stop Mode Release Timing When Initiated By Interrupt Request
16-11
S3P7238/P7235 OTP
S3C7238/P7238/C7235/P7235
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
MEASUREMENT
POINTS
Figure 16-5. A.C. Timing Measurement Points (Except for X and XT )
IN IN
1/f
x
t
t
XH
XL
X
in
V
– 0.1 V
DD
0.1 V
Figure 16-6. Clock Timing Measurement at X
IN
1/f
xt
t
t
XTH
XTL
XT
in
V
– 0.1 V
DD
0.1 V
Figure 16-7. Clock Timing Measurement at XT
IN
16-12
S3C7238/P7238/C7235/P7235
S3P7238/P7235 OTP
1/f
TI0
t
t
TIH0
TIL0
TCL0
0.8 V
DD
0.2 V
DD
Figure 16-8. TCL0 Timing
tRSL
RESET
0.2 V
DD
Figure 16-9. Input Timing for RESET Signal
tINTL
t
INTH
INT0, 1, 2, 4
KS0 to KS7
0.8 V
DD
0.2 V
DD
Figure 16-10. Input Timing for External Interrupts and Quasi-Interrupts
16-13
S3P7238/P7235 OTP
S3C7238/P7238/C7235/P7235
t
KCY
t
t
KH
KL
0.8 V
0.2 V
DD
DD
SCK
t
t
KSI
SIK
0.8 V
0.2 V
DD
DD
SI
INPUT DATA
t
KSO
SO
OUTPUT DATA
Figure 16-11. Serial Data Transfer Timing
16-14
S3C7238/P7238/C7235/P7235
S3P7238/P7235 OTP
START
Address= First Location
V
=5V, V =12.5V
PP
DD
x = 0
Program One 1ms Pulse
Increment X
YES
x = 10
NO
FAIL
FAIL
NO
Verify Byte
Verify 1 Byte
Last Address
Increment Address
V
= V = 5 V
PP
DD
FAIL
Compare All Byte
PASS
Device Failed
Device Passed
Figure 16-12. OTP Programming Algorithm
16-15
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