K9S6408V0M-SSB0 [SAMSUNG]
Flash Card, 8MX8;
| 型号： | K9S6408V0M-SSB0 |
| 厂家： | 
SAMSUNG |
| 描述： | Flash Card, 8MX8 内存集成电路 |
| 文件： | 总26页 (文件大小：481K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM
K9S6408V0M-SSB0
SmartMedia
Document Title
TM
8M x 8 Bit SmartMedia Card
Revision History
Revision No. History
Draft Date
Remark
0.0
Data Sheet, 1997
April 10th 1997
Final
1.0
Data Sheet, 1998
April 10th 1998
Final
1. Changed tBERS parameter : 10ms(Max.) ® 4ms(Max.)
2. Changed Valid Block Number : 1004(Min.) ® 1014(Min.)
1.1
1.2
Data Sheet 1998
July 14th 1998
April 10th 1999
Final
Final
Data Sheet 1999
1. Added CE dont’ care mode during the data-loading and reading
1.3
1.4
1) Revised real-time map-out algorithm(refer to technical notes)
2) Changed voltage-density model marking method on SmartMedia
July 23th 1999
Sep. 15th 1999
Final
Final
Changed device name
- SMFV008 -> K9S6408V0M-SSB0
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
1
TM
K9S6408V0M-SSB0
SmartMedia
8M x 8 Bit SmartMediaTM Card
FEATURES
GENERAL DESCRIPTION
· Single 2.7V~3.6V Supply
· Organization
The K9S6408V0M is a 8M(8,388,608)x8bit NAND Flash Mem-
ory with a spare 256K(262,144)x8bit. Its NAND cell provides the
most cost-effective solution for the solid state mass storage
market. A program operation programs the 528-byte page in
typically 200ms and an erase operation can be performed in typ-
ically 2ms on an 8K-byte block. Data in the page can be read
out at 50ns cycle time per byte. The I/O pins serve as the ports
for address and data input/output as well as command inputs.
The on-chip write controller automates all program and erase
functions including pulse repetition, where required, and inter-
nal verify and margining of data. Even the write-intensive sys-
tems can take advantage of the K9S6408V0M¢s extended
reliability of 1,000,000 program/erase cycles by providing either
ECC(Error Correcting Code) or real time mapping-out algo-
rithm. These algorithms have been implemented in many mass
storage applications and also the spare 16 bytes of a page
combined with the other 512 bytes can be utilized by system-
level ECC.
- Memory Cell Array : (8M + 256K)bit x 8bit
- Data Register : (512 + 16)bit x8bit
· Automatic Program and Erase
- Page Program : (512 + 16)Byte
- Block Erase : (8K + 256)Byte
· 528-Byte Page Read Operation
- Random Access : 7ms(Max.)
- Serial Page Access : 50ns(Min.)
· Fast Write Cycle Time
- Program time : 200ms(typ.)
- Block Erase time : 2ms(typ.)
· Command/Address/Data Multiplexed I/O port
· Hardware Data Protection
- Program/Erase Lockout During Power Transitions
· Reliable CMOS Floating-Gate Technology
- Endurance : 1M Program/Erase Cycles
- Data Retention : 10 years
· Command Register Operation
The K9S6408V0M is an optimum solution for large nonvolatile
storage applications such as solid state file storage, digital
voice recorder, digital still camera and other portable applica-
tions requiring non-volatility.
· 22 pad SmarMediaTM(SSFDC)
TM
SmartMedia CARD(SSFDC)
PIN DESCRIPTION
Pin Name
I/O0 ~ I/O7
CLE
Pin Function
Data Input/Outputs
12
22
22 VCC
21 CE
20 RE
19 R/B
18 GND
17 VCC
16 I/O7
15 I/O6
14 I/O5
13 I/O4
12 VCC
1
2
3
4
5
6
7
8
9
VSS
CLE
ALE
WE
WP
I/O0
I/O1
I/O2
I/O3
Command Latch Enable
Address Latch Enable
Chip Enable
ALE
CE
11
1
RE
Read Enable
3V 8MB
WE
Write Enable
WP
Write Protect
10 VSS
11 VSS
GND
R/B
Ground
Ready/Busy output
Power(3.3V)
TM
VCC
22 PAD SmartMedia
VSS
Ground
N.C
No Connection
NOTE : Connect all VCC and VSS pins of each device to power supply outputs.
Do not leave VCC or VSS disconnected.
2
TM
K9S6408V0M-SSB0
SmartMedia
Figure 1. FUNCTIONAL BLOCK DIAGRAM
VCC
VSS
Y-Gating
2nd half Page Register & S/A
X-Buffers
A9 - A22
Latches
& Decoders
64M + 2M Bit
NAND Flash
ARRAY
Y-Buffers
A0 - A7
Latches
& Decoders
(512 + 16)Byte x 16384
1st half Page Register & S/A
Y-Gating
A8
Command
Command
Register
VCC
VSS
I/O Buffers & Latches
CE
RE
WE
Control Logic
& High Voltage
Generator
I/0 0
I/0 7
Output
Driver
Global Buffers
CLE ALE WP
Figure 2. ARRAY ORGANIZATION
1 Block(=16 Row)
(8K + 256) Byte
1 Page = 528 Bytes
1 Block = 528 Bytes x 16 Pages
= (8K + 256) Bytes
1 Device = 528 Bytes x 16Pages x 1024 Blocks
= 66 Mbits
16K Row
(=1024 Block)
1st half Page Register
(=256 Bytes)
2nd half Page Register
(=256 Bytes)
8 bit
512B column
16 Byte Column
I/O 0 ~ I/O 7
Page Register
512 Byte
16 Byte
I/O 0
A0
I/O 1
A1
I/O 2
A2
I/O 3
A3
I/O 4
A4
I/O 5
I/O 6
A6
I/O 7
A7
1st Cycle
A5
Column Address
Row Address
2nd Cycle
3rd Cycle
A9
A10
A18
A11
A19
A12
A20
A13
A21
A14
A22
A15
*X
A16
*X
(Page Address)
A17
NOTE : Column Address : Starting Address of the Register.
00h Command(Read) : Defines the starting address of the 1st half of the register.
01h Command(Read) : Defines the starting address of the 2nd half of the register.
* A8 is internally set to "Low" or "High" by the 00h or 01h Command.
* X can be High or Low.
3
TM
K9S6408V0M-SSB0
SmartMedia
PRODUCT INTRODUCTION
The K9S6408V0M is a 66Mbit(69,206,016 bit) memory organized as 16,384 rows by 528 columns. Spare sixteen columns are
located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data trans-
fer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells
that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 16
pages formed by one NAND structures, totaling 4,224 NAND structures of 16 cells. The array organization is shown in Figure 2. The
program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory
array consists of 1024 separately erasable 8K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the
K9S6408V0M.
The K9S6408V0M has addresses multiplexed into 8 I/O¢s. This scheme dramatically reduces pin counts and allows systems
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through
I/O¢s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle
except for Block Erase command which requires two cycles: one cycle for erase-setup and another for erase-execution after block
address loading. The 8M byte physical space requires 23 addresses, thereby requiring three cycles for byte-level addressing: col-
umn address, low row address and high row address, in that order. Page Read and Page Program need the same three address
cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used.
Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of
the K9S6408V0M.
Table 1. COMMAND SETS
Function
Sequential Data Input
Read 1
1st. Cycle
80h
2nd. Cycle
Acceptable Command during Busy
-
00h/01h(1)
50h
-
Read 2
-
Read ID
90h
-
Reset
FFh
-
O
O
Page Program
Block Erase
Read Status
10h
-
D0h
-
60h
70h
NOTE : 1. The 00H command defines starting address of the 1st half of registers.
The 01H command defines starting address of the 2nd half of registers.
After data access on the 2nd half of register by the 01h command, the status pointer is
automatically moved to the 1st half register(00h) on the next cycle.
4
TM
K9S6408V0M-SSB0
SmartMedia
PIN DESCRIPTION
Command Latch Enable(CLE)
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched
into the command register through the I/O ports on the rising edge of the WE signal.
Address Latch Enable(ALE)
The ALE input controls the path activation for address and input data to the internal address/data register.
Addresses are latched on the rising edge of WE with ALE high, and input data is latched when ALE is low.
Chip Enable(CE)
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.
However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to standby
mode.
Write Enable(WE)
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
Read Enable(RE)
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge
of RE which also increments the internal column address counter by one.
I/O Port : I/O 0 ~ I/O 7
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z
when the chip is deselected or when the outputs are disabled.
Write Protect(WP)
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when
the WP pin is active low.
Ready/Busy(R/B)
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip
is deselected or when outputs are disabled.
5
TM
K9S6408V0M-SSB0
SmartMedia
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
VCC
Rating
-0.6 to + 4.6
-0.6 to + 4.6
-10 to +65
-20 to +65
5
Unit
Voltage on any pin relative to VSS
V
VIN
Temperature Under Bias
Storage Temperature
Short Circuit Output Current
NOTE :
TBIAS
TSTG
IOS
°C
°C
mA
1. Minimum DC voltage is -0.3V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage reference to GND,TA=0 to 55°C)
Parameter
Supply Voltage
Supply Voltage
Symbol
VCC
Min
2.7
0
Typ.
3.3
0
Max
3.6
0
Unit
V
VSS
V
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
Min
Max
Parameter
Sequential Read
Program
Symbol
ICC1
ICC2
ICC3
ISB1
ISB2
ILI
Test Conditions
Typ
10
10
10
-
Unit
tcycle=50ns, CE=VIL, IOUT=0mA
-
20
Operating
Current
-
-
20
mA
Erase
-
CE=VIH, WP=0V/VCC
CE=VCC-0.2, WP=0V/VCC
VIN=0 to 3.6V
VOUT=0 to 3.6V
-
-
20
Stand-by Current(TTL)
-
-
1
Stand-by Current(CMOS)
Input Leakage Current
10
-
50
-
±10
±10
mA
Output Leakage Current
Input High Voltage, All inputs
Input Low Voltage, All inputs
Output High Voltage Level
Output Low Voltage Level
Output Low Current(R/B)
ILO
-
-
VIH
2.0
-0.3
2.4
-
-
VCC+0.3
VIL
-
-
0.8
-
V
VOH
VOL
IOH=-400mA
-
IOL=2.1mA
-
0.4
-
IOL(R/B) VOL=0.4V
8
10
mA
6
TM
K9S6408V0M-SSB0
SmartMedia
VALID BLOCK
Parameter
Symbol
Min
Typ.
Max
1024
Unit
Valid Block Number
NVB
1014
1020
Blocks
NOTE :
1. The K9S6408V0M may include invalid blocks. Invalid blocks are defined as blocks that contain one or more bad bits. Do not try to access these
invalid blocks for program and erase. During its lifetime of 10 years and/or 1million program/erase cycles, the minimum number of valid blocks are
guaranteed though its initial number could be reduced. (Refer to the attached technical notes)
AC TEST CONDITION(TA=0 to 55°C, VCC=2.7~3.6V unless otherwise noted)
Parameter
Input Pulse Levels
Value
0.4V to 2.4V
Input Rise and Fall Times
Input and Output Timing Levels
Output Load 3.0V±10%
Output Load 3.3V±10%
5ns
0.8V and 2.0V
1 TTL GATE and CL = 50pF
1 TTL GATE and CL = 100pF
CAPACITANCE(TA=25°C, VCC=3.3V, f=1.0MHz)
Item
Symbol
CI/O
Test Condition
VIL=0V
Min
Max
10
Unit
pF
Input/Output Capacitance
Input Capacitance
-
-
CIN
VIN=0V
10
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE
H
L
ALE
CE
L
WE
RE
H
WP
Mode
L
X
Command Input
Read Mode
H
L
H
X
Address Input(3clock)
Command Input
H
L
L
L
H
H
Write Mode
Data Input
H
L
H
H
Address Input(3clock)
L
L
L
H
H
L
L
L
H
H
X
X
X
X
X
Sequential Read & Data Output
During Read(Busy)
During Program(Busy)
During Erase(Busy)
Write Protect
L
L
L
H
X
X
X
X
X
X
X
X
X
X
H
H
X
X
H
L
X(1)
X
X
(2)
X
Stand-by
0V/VCC
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
Program/Erase Characteristics
Parameter
Symbol
tPROG
Nop
Min
Typ
200
-
Max
1000
10
Unit
Program Time
-
-
-
ms
cycles
ms
Number of Partial Program Cycles in the Same Page
Block Erase Time
tBERS
2
4
7
TM
K9S6408V0M-SSB0
SmartMedia
AC Timing Characteristics for Command / Address / Data Input
Parameter
Symbol
tCLS
tCLH
tCS
Min
0
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLE Set-up Time
CLE Hold Time
CE Setup Time
CE Hold Time
-
-
-
-
-
-
-
-
-
-
-
10
0
tCH
10
25
0
WE Pulse Width
ALE Setup Time
ALE Hold Time
Data Setup Time
Data Hold Time
Write Cycle Time
tWP
tALS
tALH
tDS
10
20
10
50
15
tDH
tWC
tWH
WE High Hold Time
AC Characteristics for Operation
Parameter
Data Transfer from Cell to Register
ALE to RE Delay( ID read )
ALE to RE Delay(Read cycle)
CE to RE Delay( ID read)
Ready to RE Low
Symbol
tR
Min
-
Max
Unit
7
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tAR1
tAR2
tCR
100
50
100
20
30
-
-
-
-
tRR
-
RE Pulse Width
tRP
-
WE High to Busy
tWB
100
-
Read Cycle Time
tRC
50
-
RE Access Time
tREA
tRHZ
tCHZ
tREH
tIR
35
30
20
-
RE High to Output Hi-Z
CE High to Output Hi-Z
RE High Hold Time
15
-
15
0
Output Hi-Z to RE Low
Last RE High to Busy(at sequential read)
-
tRB
-
100
CE High to Ready(in case of interception by CE at read)(1)
CE High Hold Time(at the last serial read)(3)
RE Low to Status Output
50 +tr(R/B)(2)
tCRY
tCEH
tRSTO
tCSTO
tWHR
tREADID
tRST
-
100
-
-
35
CE Low to Status Output
-
45
WE High to RE Low
60
-
-
RE access time(Read ID)
35
Device Resetting Time(Read/Program/Erase)
-
5/10/500
NOTE : 1. If CE goes high within 30ns after the rising edge of the last RE, R/B will not return to VOL.
2. The time to Ready depends on the value of the pull-up resistor tied R/B pin.
3. To break the sequential read cycle, CE must be held high for longer time than tCEH.
8
TM
K9S6408V0M-SSB0
SmartMedia Technical Notes
Invalid Block(s)
SmartMedia
Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. Typically,
an invalid block will contain a single bad bit. The information regarding the invalid block(s) is so called as the invalid block informa-
tion. An invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common
source line by a select transistor. The system design must be able to mask out the invalid block(s) via address mapping.
Identifying Invalid Block(s)
SSFDC Forum specifies the logical format and physical format to ensure compatibility of SmartMedia. Samsung pre-formats Smart-
Media in the Forum-compliant format prior to shipping. Physical format standard specifies that block status is defined by the 6th byte
in the spare area. Samsung makes sure that the first page of every invalid block has 00h data at the column address of 517(4MB
SmartMedia and higher densities) or 261(2MB SmartMedia). Other than the blocks with format data and the invalid blocks are
erased(FFh). Since the invalid block information is also erasable in most cases, it is impossible to recover the infor-
mation once it has been erased. Therefore, the system must be able to recognize the invalid block(s) based on the
original invalid block information and create the invalid block table via the following suggested flow chart(Figure 1).
Any intentional erasure of the original invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
Check "FFH" at the column address 517
*
(or 261) of the first page in the block
No
Create (or update)
Invalid Block(s) Table
Check "FFH" ?
Yes
No
Last Block ?
Yes
End
Figure 1. Flow chart to create invalid block table.
9
TM
K9S6408V0M-SSB0
SmartMedia
SmartMedia Technical Notes (Continued)
Error in write or read operation
Over its life time, the additional invalid blocks may occur. Through the tight process control and intensive testing, Samsung mini-
mizes the additional block failure rate, which is projected below 0.1% up until 1million program/erase cycles. Refer to the qualification
report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the
case of status read failure after erase or program, block replacement should be done. To improve the efficiency of memory space, it
is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The
said additional block failure rate does not include those reclaimed blocks.
Failure Mode
Detection and Countermeasure sequence
Erase Failure
Status Read after Erase --> Block Replacement
Status Read after Program --> Block Replacement
Read back ( Verify after Program) --> Block Replacement
or ECC Correction
Write
Read
Program Failure
Single Bit Failure
Verify ECC -> ECC Correction
: Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection
ECC
Program Flow Chart
If ECC is used, this verification
operation is not needed.
Start
Write 00H
Write 80H
Write Address
Wait for tR Time
Write Address
Write Data
Write 10H
*
No
Program Error
Verify Data
Write 70H
Yes
Program Completed
No
SR. 6 = 1 ?
or R/B = 1 ?
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
*
Yes
*
No
Program Error
SR. 0 = 0 ?
Yes
10
TM
K9S6408V0M-SSB0
SmartMedia
SmartMedia Technical Notes (Continued)
Erase Flow Chart
Read Flow Chart
Start
Start
Write 60H
Write 00H
Write Block Address
Write Address
Read Data
Write D0H
Write 70H
ECC Generation
No
No
SR. 6 = 1 ?
or R/B = 1 ?
Reclaim the Error
Verify ECC
Yes
Yes
*
No
Page Read Completed
Erase Error
SR. 0 = 0 ?
Yes
Erase Completed
: If erase operation results in an error, map out
the failing block and replace it with another block.
*
Block Replacement
Buffer
memory
error occurs
When the error happens in Block "A", try to write the
data into another Block "B" by reloading from an exter-
nal buffer. Then, prevent further system access to
Block "A"(by creating a "invalid block" table or other
appropriate scheme.)
Block A
Block B
11
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K9S6408V0M-SSB0
SmartMedia
Pointer Operation of K9S6408V0M
The K9S6408V0M has three read modes to set the destination of the pointer. The pointer is set to "A" area by the "00h" command, to
"B" area by the "01" command, and to "C" area by the "50h" command. Table 1 shows the destination of the pointer, and figure 2
shows the block diagram of its operations.
"A" area
"B" area
"C" area
(00h plane)
(01h plane) (50h plane)
Table 1. Destination of the pointer
256 Byte
256 Byte
16 Byte
Command
Pointer position
Area
00H
01H
50H
0 ~ 255 byte
256 ~ 511 byte
512 ~ 527 byte
1st half array(A)
2nd half array(B)
spare array(C)
"A"
"B"
"C"
Internal
Page Buffer
Pointer select
commnad
(00h, 01h, 50h)
Pointer
Figure 2. Block diagram of pointer Operation
Example of Pointer Operation programming
(1) "A" area program
Address / Data input
10h
"A" area program
Address / Data input
10h
50h
00h
80h
80h
80h
80h
"C" area
"A" area
"A" area program
(2) "B" area program
Address / Data input
10h
Address / Data input
10h
00h
01h
"A" area
"B" area
"B" area program
"A" area program
(3) "C" area program
Address / Data input
10h
Address / Data input
10h
00h
50h
80h
80h
"A" area
"C" area
"C" area program
"C" area program
Table 2. Pointer Status after each operation
Operation
Pointer status after operation
Program/Erase
With previous 00H, Device is set to 00H Plane
With previous 01H, Device is set to 00H Plane*
With previous 50H, Device is set to 50H Plane
Reset
"00h" Plane("A" area)
"00h" Plane("A" area)
Power up
* 01H command is valid just one time when it is used as a pointer for program/erase.
12
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K9S6408V0M-SSB0
SmartMedia
System Interface Using CE don’t-care.
For a easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal
528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for
voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read-
ing would provide significant savings in power consumption.
Figure 3. Program Operation with CE don’t-care.
CLE
CE dont’-care
CE
WE
ALE
80H
Start Add.(3Cycle)
Data Input
Data Input
10H
I/O0~7
CE
(Min. 10ns)
tCS
(Max. 45ns)
tCEA
tCH
CE
RE
tREA
tWP
WE
I/O0~7
out
Timing requirements : If CE is is exerted high during sequential
data-reading, the falling edge of CE to valid data(tCEA) must
be kept greater than 45ns.
Timing requirements : If CE is is exerted high during data-loading,
tCS must be minimum 10ns and tWC must be increased accordingly.
Figure 4. Read Operation with CE don’t-care.
CLE
CE
CE dont’-care
RE
ALE
tR
R/B
WE
Data Output(sequential)
00H
Start Add.(3Cycle)
I/O0~7
13
TM
K9S6408V0M-SSB0
SmartMedia
* Command Latch Cycle
CLE
CE
tCLH
tCH
tCLS
tCS
tWP
WE
tALS
tALH
ALE
tDS
tDH
Command
I/O0 ~ 7
* Address Latch Cycle
CLE
CE
tWC
tCS
tWC
tWP
tWP
tWP
WE
tWH
tCLS
tWH
tALH
tALS
ALE
tDH
tDH
tDH
tDS
tDS
tDS
I/O0 ~ 7
A17~A22
A0~A7
A9~A16
14
TM
K9S6408V0M-SSB0
SmartMedia
* Input Data Latch Cycle
tCLH
CLE
CE
tCH
tWC
tALS
ALE
tWP
tWP
tWP
WE
tWH
tDH
tDH
tDH
tDS
tDS
tDS
DIN 511
I/O0 ~ 7
DIN 0
DIN 1
* Sequential Out Cycle after Read(CLE=L, WE=H, ALE=L)
tRC
CE
tRP
tREA
tREH
tCHZ*
tRHZ*
tREA
tREA
RE
tRHZ
Dout
I/O0 ~ 7
R/B
Dout
Dout
tRR
NOTES : Transition is measured±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
15
TM
K9S6408V0M-SSB0
SmartMedia
* Status Read Cycle
tCLS
CLE
CE
tCLS
tCS
tCLH
tCH
tWP
WE
tCSTO
tCHZ
tWHR
RE
tDH
tRSTO
tDS
tIR
tRHZ
Status Output
I/O0 ~ 7
70H
READ1 OPERATION(READ ONE PAGE)
CLE
tCEH
CE
tCHZ
tWC
WE
ALE
RE
tWB
tAR2
tCRY
tRHZ
tR
tRC
tRR
A9 ~ A16
Dout N+3
Dout 527
tRB
A0 ~ A7
Dout N
Dout N+1 Dout N+2
00h or 01h
A17 ~ A22
I/O0 ~ 7
R/B
Column
Address
Page(Row)
Address
Busy
16
TM
K9S6408V0M-SSB0
SmartMedia
READ1 OPERATION(INTERCEPTED BY CE)
CLE
CE
WE
tWB
tCHZ
tAR2
ALE
RE
tRC
tR
t
tRR
Dout N+3
A9 ~ A16
A17 ~ A22
00h or 01h
A0 ~ A7
Dout N+2
Dout N Dout N+1
I/O0 ~ 7
R/B
Column
Address
Page(Row)
Address
Busy
READ2 OPERATION(READ ONE PAGE)
CLE
CE
WE
ALE
RE
tR
tWB
tAR2
tRR
Dout
Dout
A9 ~ A16 A17 ~ A22
Dout 527
511+M+1
A0 ~ A7
50H
I/O0 ~ 7
R/B
511+M
Selected
Row
M Address
A0 ~ A3 :Valid Address
A4 ~ A7 :Don t care
512
16
Start
address M
17
TM
K9S6408V0M-SSB0
SmartMedia
SEQUENTIAL ROW READ OPERATION
CLE
CE
WE
ALE
RE
Dout
N+1
Dout
N+2
Dout
N
Dout
527
Dout
0
Dout
1
Dout
2
Dout
527
00H
A0 ~ A7 A9 ~ A16 A17 ~ A22
I/O0 ~ 7
R/B
Busy
Busy
M
M+1
N
Output
Output
PAGE PROGRAM OPERATION
CLE
CE
tWC
tWC
tWC
WE
ALE
RE
tWB
tPROG
Din
527
Din
N
Din
N+1
10H
80H
A0 ~ A7 A9 ~ A16 A17 ~ A22
70H
I/O0
I/O0 ~ 7
R/B
Sequential Data
Input Command Address
1 up to 528 Byte Data
Sequential Input
Read Status
Command
Column
Program
Command
Page(Row)
Address
I/O0=0 Successful Program
I/O0=1 Error in Program
18
TM
K9S6408V0M-SSB0
SmartMedia
BLOCK ERASE OPERATION(ERASE ONE BLOCK)
CLE
CE
tWC
tWC
WE
tWB
tBERS
ALE
RE
60H
A9 ~ A16 A17 ~ A22
DOH
70H
I/O0
I/O0 ~ 7
R/B
Block
Address
Busy
Auto Block Erase Setup Command
Erase Command
Read Status I/O0=0 Successful Erase
Command
I/O0=1 Error in Erase
MANUFACTURE & DEVICE ID READ OPERATION
CLE
CE
WE
ALE
RE
tREADID
90H
00H
ECH
E6H
I/O0 ~ 7
Read ID Command
Maker Code
Device Code
19
TM
K9S6408V0M-SSB0
SmartMedia
DEVICE OPERATION
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00H to the command reg-
ister along with three address cycles. Once the command is latched, it does not need to be written for the following page read oper-
ation. Three types of operations are available : random read, serial page read and sequential row read.
The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are trans-
ferred to the data registers in less than 7ms(tR). The CPU can detect the completion of this data transfer(tR) by analyzing the output
of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially pulsing RE.
High to low transitions of the RE clock output the data stating from the selected column address up to the last column address.
After the data of last column address is clocked out, the next page is automatically selected for sequential row read.
Waiting 7ms again allows reading the selected page.The sequential row read operation is terminated by bringing CE high. The way
the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of bytes 512 to
527 may be selectively accessed by writing the Read2 command. Addresses A0 to A3 set the starting address of the spare area
while addresses A4 to A7 are ignored. Unless the operation is aborted, the page address is automatically incremented for sequential
row read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Read1 command(00H/01H) is
needed to move the pointer back to the main area. Figures 3 thru 6 show typical sequence and timings for each read operation.
Figure 3. Read1 Operation
CLE
CE
WE
ALE
tR
R/B
RE
00H
01H
Start Add.(3Cycle)
A0 ~ A7 & A9 ~ A22
Data Output(Sequential)
(01H Command)*
I/O0 ~ 7
(00H Command)
1st half array
2nd half array
1st half array
2nd half array
Data Field
Spare Field
Data Field
Spare Field
* After data access on 2nd half array by 01H command, the start pointer is automatically moved to 1st half array (00H) at next cycle.
20
TM
K9S6408V0M-SSB0
SmartMedia
Figure 4. Read2 Operation
CLE
CE
WE
ALE
R/B
RE
tR
50H
Data Output(Sequential)
Spare Field
Start Add.(3Cycle)
A0 ~ A3 & A9 ~ A22
I/O0 ~ 7
(A4 ~ A7 :
Don't Care)
1st half array
2nd half array
Data Field
Spare Field
Figure 5. Sequential Row Read1 Operation
tR
tR
tR
R/B
I/O0 ~ 7
00H
01H
Start Add.(3Cycle)
A0 ~ A7 & A9 ~ A22
Data Output
1st
Data Output
Data Output
2nd
(528 Byte)
Nth
(528 Byte)
(00H Command)
(01H Command)
1st half array
2nd half array
1st half array
2nd half array
1st
1st
2nd
2nd
Nth
Nth
Data Field
Spare Field
Data Field
Spare Field
21
TM
K9S6408V0M-SSB0
SmartMedia
Figure 6. Sequential Row Read2 Operation
tR
tR
tR
R/B
50H
Start Add.(3Cycle)
A0 ~ A3 & A9 ~ A22
Data Output
1st
Data Output
Data Output
I/O0 ~ 7
2nd
(16 Byte)
Nth
(16 Byte)
(A4 ~ A7 :
Don't Care)
1st half array
2nd half array
1st
2nd
Nth
Data Field
Spare Field
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte or consecutive
bytes up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the same
page without an intervening erase operation must not exceed ten. The addressing may be done in any random order in a block. A
page program cycle consists of a serial data loading period in which up to 528 bytes of data may be loaded into the page register, fol-
lowed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. Serial data loading can
be started from 2nd half array by moving pointer. About the pointer operation, please refer to the attached technical notes.
The serial data loading period begins by inputting the Serial Data Input command(80H), followed by the three cycle address input and
then serial data loading. The bytes other than those to be programmed do not need to be loaded.The Page Program confirm com-
mand(10H) initiates the programming process. Writing 10H alone without previously entering the serial data will not initiate the pro-
gramming process. The internal write controller automatically executes the algorithms and timings necessary for program and verify,
thereby freeing the CPU for other tasks. Once the program process starts, the Read Status Register command may be entered, with
RE and CE low, to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/
B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while pro-
gramming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 7). The internal
write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status
command mode until another valid command is written to the command register.
Figure 7. Program & Read Status Operation
tPROG
R/B
Pass
I/O0 ~ 7
80H
Address & Data Input
I/O0
Fail
10H
70H
A0 ~ A7 & A9 ~ A22
528 Byte Data
22
TM
K9S6408V0M-SSB0
SmartMedia
BLOCK ERASE
The Erase operation is done on a block(8K Byte) basis. Block address loading is accomplished in two cycles initiated by an Erase
Setup command(60H). Only address A13 to A22 is valid while A9 to A12 is ignored. The Erase Confirm command(D0H) following the
block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command
ensures that memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase, erase-verify and pulse
repetition where required. When the erase operation is completed, the Write Status Bit(I/O 0) may be checked.
Figure 8 details the sequence.
Figure 8. Block Erase Operation
tBERS
R/B
Pass
I/O0 ~ 7
60H
I/O0
Fail
70H
Address Input(2Cycle)
Block Add. : A9 ~ A22
D0H
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70H command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, a read command(00H or 50H) should be given before sequential page read cycle.
Table2. Status Register Definition
SR
Status
Definition
"0" : Successful Program / Erase
I/O0
Program / Erase
"1" : Error in Program / Erase
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
"0"
"0"
"0"
"0"
"0"
Reserved for Future
Use
Device Operation
Write Protect
"0" : Busy
"1" : Ready
"1" : Not Protected
"0" : Protected
READ ID
The device contains a product identification mode, initiated by writing 90H to the command register, followed by an address input of
00H. Two read cycles sequentially output the manufacture code(ECH), and the device code (E6H) respectively. The command regis-
ter remains in Read ID mode until further commands are issued to it. Figure 9 shows the operation sequence.
23
TM
K9S6408V0M-SSB0
SmartMedia
READ ID
The device contains a product identification mode, initiated by writing 90H to the command register, followed by an address input of
00H. Two read cycles sequentially output the manufacture code(ECH), and the device code (E6H) respectively. The command regis-
ter remains in Read ID mode until further commands are issued to it. Figure 9 shows the operation sequence.
Figure 9. Read ID Operation
CLE
tCR
CE
WE
tAR1
ALE
RE
tREADID
I/O0 ~ 7
00
E6H
90H
ECH
Address. 1 cycle
Maker code
Device code
RESET
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70H command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
dose not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, a read command(00H or 50H) should be given before sequential page read cycle.
Figure 10. RESET Operation
tRST
R/B
I/O0 ~ 7
FFH
Table3. Device Status
After Power-up
After Reset
Operation Mode
Read 1
Waiting for next command
24
TM
K9S6408V0M-SSB0
SmartMedia
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command reg-
ister or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin
is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. An appropriate pull-up resister is required for proper
operation and the value may be calculated by the following equation.
VCC
VCC(Max.) - VOL(Max.)
3.2V
R/B
Rp =
=
8mA + å IL
IOL + å IL
open drain output
where IL is the sum of the input currents of all devices tied to the
R/B pin.
GND
Device
DATA PROTECTION
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at VIL
during power-up and power-down as shown in Figure 11. The two step command sequence for program/erase provides additional
software protection.
Figure 11. AC Waveforms for Power Transition
~ 2.5V
~ 2.5V
VCC
WP
High
25
TM
K9S6408V0M-SSB0
DIMENSIONS
SmartMedia
Unit:mm
22 PAD SOLID STATE FLOPPY DISK CARD (3.3V)
SOLID STATE PRODUCT OUTLINE
37.0±0.1
0.15±0.05
5.0±0.2
Index Label Area
10.0±0.2
Write Protect Area
Contact Area
(+0.1mm package body surface)
33.0±0.2
45.0±0.1
0.76±0.08
0.5mm Chamfer 4.2(Min)
1.5±0.1
(3.3V Card)
27.0
2.140 TYP
0.400 TYP
22
12
8.650
7.900
6.500
0.000
6.500
7.900
8.650
1
11
26
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