K7D161874B-HC330 [SAMSUNG]
DDR SRAM, 1MX18, 0.2ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153;
| 型号： | K7D161874B-HC330 |
| 厂家： | 
SAMSUNG |
| 描述： | DDR SRAM, 1MX18, 0.2ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153 双倍数据速率 静态存储器 内存集成电路 |
| 文件： | 总16页 (文件大小：440K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K7D163674B
K7D161874B
512Kx36 & 1Mx18 SRAM
Document Title
16M DDR SYNCHRONOUS SRAM
Revision History
RevNo.
Rev. 0.0
Rev. 0.1
History
DraftData
Oct. 2003
Nov. 2003
Remark
Advance
Preliminary
Initial document.
Change JTAG DC OPERATING CONDITONS/AC TEST CONDITIONS
-to support 1.8~2.5V VDD, change some items.
Rev. 0.2
Rev. 0.3
Rev. 1.0
Rev. 1.1
Change DC CHARACTERISTICS (Stop Clock Standby Current)
-ISB1 : 100 -> 150
Feb. 2004
Feb. 2004
Mar. 2004
Jan. 2004
Preliminary
Preliminary
Final
Change JTAG Instruction Cording
- For Reserved
Change DC CHARACTERISTICS (Increase Operating Current)
- x36 : add 40mA, x18 : add 60mA
Add DC CHARACTERISTICS
- VIN-CLK, VDIF-CLK, VCM-CLK
Final
Add AC INPUT CHARACTERISTICS
Add INPUT DEFINITION
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters
of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters.
Rev 1.1
Jan. 2005
- 1 -
K7D163674B
K7D161874B
512Kx36 & 1Mx18 SRAM
FEATURES
• Registered Addresses, Burst Control and Data Inputs.
• Registered Outputs.
• 512Kx36 or 1Mx18 Organizations.
• 1.8~2.5V VDD/1.5V VDDQ.(1.9V max VDDQ)
• HSTL Input and Outputs.
• Double and Single Data Rate Burst Read and Write.
• Burst Count Controllable With Max Burst Length of 4
• Interleved and Linear Burst mode support
• Bypass Operation Support
• Single Differential HSTL Clock.
• Synchronous Pipeline Mode of Operation with Self-Timed
Late Write.
• Programmable Impedance Output Drivers.
• JTAG Boundary Scan (subset of IEEE std. 1149.1)
• 153(9x17) Pin Ball Grid Array Package(14mmx22mm)
• Free Running Active High and Active Low Echo Clock Output
Pin.
• Asynchronous Output Enable.
GENERAL DESCRIPTION
The K7D163674B and K7D161874B are 18,874,368 bit Synchronous Pipeline Burst Mode SRAM devices. They are organized as
524,288 words by 36 bits for K7D163674B and 1,048,576 words by 18 bits for K7D161874B, fabricated using Samsung's advanced
CMOS technology.
Single differential HSTL level clock, K and K are used to initiate the read/write operation and all internal operations are self-timed. At
the rising edge of K clock, all addresses and burst control inputs are registered internally. Data inputs are registered one cycle after
write addresses are asserted(Late Write), at the rising edge of K clock for single data rate (SDR) write operations and at rising and
falling edge of K clock for a double data rate (DDR) write operations.
Data outputs are updated from output registers off the rising edges of K clock for SDR read operations and off the rising and falling
edges of K clock for DDR read operations. Free running echo clocks are supported which are representive of data output access
time for all SDR and DDR operations.
The chip is operated with a single +2.5V power supply and is compatible with Extended HSTL input and output. The package is
9x17(153) Ball Grid Array balls on a 1.27mm pitch.
ORDERING INFORMATION
Maximum
Part Number
Organization
Frequency
K7D163674B-HC37
K7D163674B-HC33
K7D163674B-HC30
K7D163674B-HC27
K7D161874B-HC37
K7D161874B-HC33
K7D161874B-HC30
K7D161874B-HC27
375MHz
333MHz
300MHz
275MHz
375MHz
333MHz
300MHz
275MHz
512Kx36
1Mx18
Rev 1.1
Jan. 2005
- 2 -
K7D163674B
K7D161874B
512Kx36 & 1Mx18 SRAM
FUNCTIONAL BLOCK DIAGRAM
SA[0:18]( or SA[0:19])
Address
Memory Array
512Kx36
or
19(or 20)
Register
17(or 18)
2:1
Dec.
MUX
(Burst Address)
CE
(1Mx18)
Clock
Data Out
36(or 18)x2
K,K
Data In
Buffer
Burst
36(or18)x2
Counter
Comparator
S/A Array
W/D
Advance
Array
(Burst Write
Address)
B
1
3
Control
SD/DD
Write
Address
Register
B
36(or 18)x2
36(or18)x2
Write Buffer
19(or 20)
17(or 18)
(2 stage)
CE
2 : 1 MUX
Synchronous
Select
CE
Strobe_out
&
B
2
Echo Clock
Output
Output
Buffer
Data In
Register
(2 stage)
R/W
R/W control
Data Output Strobe
Data Output Enable
State Machine
LD
Internal
Clock
36(or 18)
DQ
Generator
XDIN
CQ,CQ
G
PIN DESCRIPTION
Pin Name
Pin Description
Differential Clocks
Synchronous Address Input
Pin Name
ZQ
Pin Description
K, K
SA
Output Driver Impedance Control Input
JTAG Test Clock
TCK
TMS
TDI
SA0, SA1
DQ
Synchronous Burst Address Input (SA0 = LSB)
Synchronous Data I/O
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
HSTL Input Reference Voltage
Power Supply
CQ, CQ
B1
Differential Output Echo Clocks
Load External Address
TDO
VREF
VDD
B2
Burst R/W Enable
B3
Single/Double Data Selection
Asynchronous Output Enable
Linear Burst Order
VDDQ
VSS
Output Power Supply
GND
G
LBO
NC
No Connection
Rev 1.1
Jan. 2005
- 3 -
K7D163674B
K7D161874B
512Kx36 & 1Mx18 SRAM
PACKAGE PIN CONFIGURATIONS(TOP VIEW)
K7D163674B(512Kx36)
1
2
3
4
5
ZQ
B1
6
SA
7
8
9
A
B
C
D
E
F
VSS
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
VDDQ
DQ
SA
SA
SA
VDDQ
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
SA
VSS
SA
VSS
SA
SA
VDDQ
DQ
SA
G
SA
VDDQ
DQ
SA
VSS
VDD
VDD
VSS
VDD
VDD
VSS
LBO
VDD
VDD
VSS
SA
VDD
VREF
VDD
K
VSS
VDD
VDD
VSS
VDD
VDD
VSS
MODE
VDD
VDD
VSS
SA
SA
VDDQ
CQ1
VDDQ
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
NC
VDD
SA
VSS
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
SA
VDDQ
CQ2
VDDQ
DQ
G
H
J
K
VDDQ
DQ
VDD
B2
VDDQ
DQ
K
L
VDDQ
CQ1
VDDQ
DQ
B3
VDDQ
CQ2
VDDQ
DQ
M
N
P
R
T
VDD
VREF
VDD
SA1
SA0
TCK
VDDQ
DQ
VDD
SA
VDDQ
DQ
VSS
TDI
VSS
TDO
U
VDDQ
TMS
NC
VDDQ
* Mode Pin(6L) is a internally NC.
K7D161874B(1Mx18)
1
2
3
4
5
ZQ
B1
6
SA
7
8
9
A
B
C
D
E
F
VSS
NC
VSS
DQ
VSS
NC
VSS
DQ
VSS
NC
VSS
DQ
VSS
NC
VSS
DQ
VSS
VDDQ
DQ
SA
SA
SA
VDDQ
NC
VSS
DQ
VSS
NC
VSS
DQ
VSS
NC
VSS
DQ
VSS
NC
VSS
DQ
VSS
NC
VSS
SA
VSS
SA
VSS
SA
SA
VDDQ
NC
SA
G
SA
VDDQ
DQ
SA
VSS
VDD
VDD
VSS
VDD
VDD
VSS
LBO
VDD
VDD
VSS
SA
VDD
VREF
VDD
K
VSS
VDD
VDD
VSS
VDD
VDD
VSS
MODE
VDD
VDD
VSS
SA
SA
VDDQ
CQ1
VDDQ
NC
VSS
NC
VSS
DQ
VSS
NC
VSS
DQ
VSS
SA
VSS
DQ
VSS
NC
VSS
DQ
VSS
NC
VSS
SA
VDDQ
NC
G
H
J
VDDQ
DQ
K
VDDQ
DQ
VDD
B2
VDDQ
NC
K
L
VDDQ
NC
B3
VDDQ
CQ1
VDDQ
NC
M
N
P
R
T
VDD
VREF
VDD
SA1
SA0
TCK
VDDQ
DQ
VDDQ
NC
VDD
SA
VDD
SA
VDDQ
DQ
VSS
TDI
VSS
TDO
U
VDDQ
TMS
NC
VDDQ
* Mode Pin(6L)is a internally NC.
Rev 1.1
Jan. 2005
- 4 -
K7D163674B
K7D161874B
512Kx36 & 1Mx18 SRAM
Read Operation(Single and Double)
During SDR read operations, addresses and controls are registered at the first rising edge of K clock and then the internal array is
read between first and second rising edges of K clock. Data outputs are updated from output registers off the second rising edge of
K clock. During DDR read operations, addresses and controls are registered at the first rising edge of K clock, and then the internal
array is read twice between first and second rising edges of K clock. Data outputs are updated from output registers sequentially by
burst order off the second rising and falling edge of K clock.
Interleave and linear burst operation is controlled by LBO pin and the burst count is controllable with the maximum burst length of 4.
To avoid data contention,at least one NOP operations are required between the last read and the first write operation.
Write Operation(Late Write)
During SDR write operations, addresses and controls are registered at the first rising edge of K clock and data inputs are registered
at the following rising edge of K clock. During DDR write operations, addresses and controls are registered at the first rising edge of
K clock and data inputs are registered twice at the following rising and falling edge of K clock. Write addresses and data inputs are
stored in the data in registers until the next write operation, and only at the next write opeation are data inputs fully written into SRAM
array.
Echo clock operation
Free running type of Echo clocks are generated from K clock regardless of read, write and NOP operations. They will stop operation
only when K clock is in the stop mode.
Echo clocks are designed to represent data output access time and this allows the echo clocks to be used as reference to capture
data outputs outputs.
Bypass Read Operation
Bypass read operation occurs when the last write operation is followed by a read operation where write and read addresses are
identical. For this case, data outputs are from the data in registers instead of SRAM array.
Programmable Impedance Output Driver
The data output and echo clock driver impedance are adjusted by an external resistor, RQ, connected between ZQ pin and VSS, and
are equal to RQ/5. For example, 250Ω resistor will give an output impedance of 50Ω. Output driver impedance tolerance is 15% by
test(10% by design) and is periodically readjusted to reflect the changes in supply voltage and temperature. Impedance updates
occur early in cycles that do not activate the outputs, such as deselect cycles. They may also occur in cycles initiated with G high. In
all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous behavior
in the SRAM. Impedance updates occur no more often than every 32 clock cycles. Clock cycles are counted whether the SRAM is
selected or not and proceed regardless of the type of cycle being executed. Therefore, the user can be assured that after 33 contin-
uous read cycles have occurred, an impedance update will occur the next time G are high at a rising edge of the K clock. There are
no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up, the SRAM needs
1024 non-read cycles.
Power-Up/Power-Down Supply Voltage Sequencing
The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ can be applied
simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-up. The following power-down supply voltage
removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ can be removed simultaneously, as long as VDDQ
does not exceed VDD by more than 0.5V during power-down.
Rev 1.1
Jan. 2005
- 5 -
K7D163674B
K7D161874B
512Kx36 & 1Mx18 SRAM
TRUTH TABLE
K
L
↑
↑
↑
↑
↑
↑
G
X
X
L
B1
X
H
L
B2
X
L
B3
X
X
H
L
DQ
Hi-Z
Hi-Z
DOUT
DOUT
DIN
Operation
Clock Stop
No Operation, Pipeline High-Z
Load Address, Single Read
Load Address, Double Read
Load Address, Single Write
Load Address, Double Write
Increment Address, Continue
H
H
L
L
L
X
X
X
L
H
L
L
L
DIN
H
H
X
B
NOTE : - B(Both) is DIN in write cycle and DOUT in read cycle. Byte write function is not supported. X means "Don't Care".
- K & K are complementary.
BURST SEQUENCE TABLE
4 Burst Operation for Interleaved Burst (LBO = VDDQ)
Interleaved Burst
Case 1
Case 2
Case 3
Case 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
Fourth Address
NOTE : - For Interleave Burst LBO = VDDQ is recommended. If LBO = VDD, it must not exceed 2.63V.
4 Burst Operation for Linear Burst (LBO = VSS)
Case 1
Case 2
Case 3
Case 4
Linear Burst Mode
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
Fourth Address
Rev 1.1
Jan. 2005
- 6 -
K7D163674B
K7D161874B
512Kx36 & 1Mx18 SRAM
BUS CYCLE STATE DIAGRAM
LOAD
NEW ADDRESS
READ
SDR
WRITE
SDR
READ
DDR
WRITE
DDR
INCREMENT
ADDRESS
INCREMENT
ADDRESS
INCREMENT
ADDRESS
INCREMENT
ADDRESS
POWER
UP
NO OP
NOTE :
1. State transitions ; B1 =(Load Address), B1=(Increment Address, Continue)
B2 =(Read), B2 =(Write)
B3 =(Single Data Rate), B3 =(Double Data Rate)
Rev 1.1
Jan. 2005
- 7 -
K7D163674B
K7D161874B
512Kx36 & 1Mx18 SRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Core Supply Voltage Relative to VSS
Output Supply Voltage Relative to VSS
Voltage on any pin Relative to VSS
Output Short-Circuit Current(per I/O)
Storage Temperature
Symbol
VDD
Value
-0.5 to 3.13
Unit
V
VDDQ
VIN
-0.5 to 2.3
V
-0.5 to VDDQ+0.5 (2.3V MAX)
25
V
IOUT
mA
°C
TSTR
-55 to 125
NOTE : Power Dissipation Capability will be dependent upon package characteristics and use environment. See enclosed thermal impedance data.
Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Core Power Supply Voltage
Output Power Supply Voltage
Input High Level Voltage
Symbol
VDD
Min
1.7
Typ
2.5
1.5
-
Max
2.63
Unit
V
Note
VDDQ
VIH
1.4
1.9
V
VREF+0.1
-0.3
VDDQ+0.3
VREF-0.1
0.95
V
1, 2
1, 3
Input Low Level Voltage
VIL
-
V
Input Reference Voltage
VREF
0.68
-0.3
0.75
-
V
Clock Input Signal Voltage
Clock Input Differential Voltage
Clock Input Common Mode Voltage
VIN-CLK
VDIF-CLK
VCM-CLK
VDDQ+0.3
VDDQ+0.6
0.9
V
1, 4
1, 5
1, 6
0.1
-
V
0.68
0.75
V
NOTE :1. These are DC test criteria. DC design criteria is VREF±50mV. The AC VIH/VIL levels are defined separately for measuring
timing parameters.
2. VIH (Max)DC=VDDQ+0.3, VIH (Max)AC=2.6V (2.1V for DQs) (pulse width ≤ 20% of cycle time).
3. VIL (Min)DC=-0.3V, VIL (Min)AC=-1.0V (-0.5V for DQs) (pulse width ≤ 20% of cycle time).
4. VIN-CLK specifies the maximum allowable DC level for the differential clock. i.e VIL-CLK and VIH-CLK.
5. VDIF-CLK specifies the minimum Clock differential voltage required for switching. i.e DC voltage difference between VIL-CLK and VIH-CLK.
6. VCM-CLK specifies the Clock crossing point for the differential clock or the allowable common clock level for a single ended clock.
DC CHARACTERISTICS
Min
Max
Parameter
Symbol
Unit
Note
IDD37
IDD33
IDD30
IDD27
540
490
440
420
Average Power Supply Operating Current(x36)
(Cycle time = tKHKH min)
-
mA
1,2
IDD37
IDD33
IDD30
IDD27
510
460
410
390
Average Power Supply Operating Current(x18)
(Cycle time = tKHKH min)
-
mA
1,2
1
Stop Clock Standby Current
(VIN=VDD-0.2V or 0.2V fixed, K=Low, K=High)
Input Leakage Current
(VIN=VSS or VDDQ)
Output Leakage Current
(VOUT=VSS or VDDQ)
ISB1
ILI
-
150
1
mA
µA
µA
-1
-1
ILO
1
Output High Voltage(Programmable Impedance Mode)
Output Low Voltage(Programmable Impedance Mode)
Output High Voltage(IOH=-0.1mA)
VOH1
VOL1
VOH2
VOL2
VDDQ/2
VSS
VDDQ-0.2
VSS
VDDQ
VDDQ/2
VDDQ
0.2
V
V
V
V
3
4
5
5
Output Low Voltage(IOL=0.1mA)
NOTE :1. Minimum cycle. IOUT=0mA.
2. 50% read cycles.
3. |IOH|=(VDDQ/2)/(RQ/5)±15% @VOH=VDDQ/2 for 175Ω ≤ RQ ≤ 350Ω.
4. |IOL|=(VDDQ/2)/(RQ/5)±15% @VOL=VDDQ/2 for 175Ω ≤ RQ ≤ 350Ω.
5. Minimum Impedance Mode when ZQ pin is connected to VSS.
Rev 1.1
Jan. 2005
- 8 -
K7D163674B
K7D161874B
512Kx36 & 1Mx18 SRAM
PIN CAPACITANCE
Parameter
Input Capacitance
Symbol
CIN
COUT
Test Condition
VIN=0V
TYP
-
-
Max
4
5
Unit
pF
pF
Data Output Capacitance
VOUT=0V
NOTE : Periodically sampled and not 100% tested.(TA=25°C, f=1MHz)
AC INPUT CHARACTERISTICS
Parameter
AC Input Logic High
AC Input Logic Low
Clock Input Differential Voltage
VREF Peak-to-Peak AC Voltage
Symbol
VIH (AC)
VIL (AC)
VDIF (AC)
VREF (AC)
Min
VREF + 0.4
Max
Unit
Note
V
V
V
V
-
-
-
-
VREF - 0.4
0.8
5% VREF (DC)
AC INPUT DEFINITION
CK
V
(AC)
DIF
CK
VIH(AC)
VREF
Setup
Time
Hold
Time
VIL(AC)
AC TEST CONDITIONS(TA=0 to 70°C, VDD=1.7 -2.63V, VDDQ=1.5V)
Parameter
Input High/Low Level
Input Reference Level
Input Rise/Fall Time
Symbol
VIH/VIL
VREF
Value
1.25/0.25
0.75
0.5/0.5
0.75
Unit
V
V
ns
V
V
Note
-
-
-
-
-
-
TR/TF
Output Timing Reference Level
Clock Input Timing Reference Level
Output Load
Cross Point
See Below
Rev 1.1
Jan. 2005
- 9 -
K7D163674B
K7D161874B
512Kx36 & 1Mx18 SRAM
AC TEST OUTPUT LOAD
50Ω
0.75V
50Ω
50Ω
5pF
0.75V
25Ω
DQ
50Ω
0.75V
5pF
AC TIMING CHARACTERISTICS
-33
-30
-27
-37
PARAMETER
SYMBOL
UNITS NOTES
Min
Max
Min
Max
Min
Max
Min
Max
Clock
Clock Cycle Time
tKHKH
tKHKL
tKLKH
2.66
1.3
-
-
-
3.0
1.3
1.3
-
-
-
3.3
1.5
1.5
-
-
-
3.63
1.7
-
-
-
ns
ns
ns
1
Clock High Pulse Width
Clock Low Pulse Width
Setup Times
1.3
1.7
Address Setup Time
tAVKH
tBVKH
tDVKX
0.4
0.4
-
-
-
0.4
0.4
0.3
-
-
-
0.4
0.4
0.3
-
-
-
0.5
0.5
0.4
-
-
-
ns
ns
ns
Control(B1,B2,B3) Setup Time
Data Setup Time
0.25
2
2
Hold Times
Address Hold Time
tKHAX
tKHBX
tKXDX
0.4
0.4
-
-
-
0.4
0.4
0.3
-
-
-
0.4
0.4
0.3
-
-
-
0.5
0.5
0.4
-
-
-
ns
ns
ns
Control(B1,B2,B3) Hold Time
Data Hold Time
0.25
Output Times
tKHKL-0.1 tKHKL+0.1 tKHKL-0.1 tKHKL+0.1 tKHKL-0.1 tKHKL+0.1 tKHKL-0.1 tKHKL+0.1
tKLKH-0.1 tKLKH+0.1 tKLKH-0.1 tKLKH+0.1 tKLKH-0.1 tKLKH+0.1 tKLKH-0.1 tKLKH+0.1
2
2
3
3
Echo Clock High Pulse Width
Echo Clock Low Pulse Width
Clock Crossing to Echo Clock
Clock Crossing to Echo Clock
Echo Clock High to Output Vaild
Echo Clock Low to Output Valid
Echo Clock High to Output Hold
Echo Clock Low to Output Hold
tCHCL
tCLCH
tCXCH
tCXCL
tCHQV
tCLQV
tCHQX
tCLQX
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.5
2.3
2.3
0.5
2.3
2.3
0.5
2.3
2.3
0.5
2.3
2.3
0.5
0.5
0.5
0.5
-0.20
-0.20
-0.20
-0.20
0.20
0.20
-0.20
-0.20
-0.20
-0.20
0.20
0.20
-0.20
-0.20
-0.20
-0.20
0.20
0.20
-0.20
-0.20
-0.20
-0.20
0.20
0.20
Echo Clock High to Output High-Z tCHQZ
0.20
1.7
0.20
1.7
0.20
1.9
0.20
2.0
Echo Clock High to Output Low-Z
G Low to Output Valid
tCHLZ
tGLQV
tGHQX
tGHQZ
-0.20
-0.20
-0.20
-0.20
-
0.5
-
-
0.5
-
-
0.5
-
-
0.5
-
4
4
4
G High to Output Low-Z
G High to Output High-Z
1.7
1.7
1.9
2.0
Notes: 1. The maximum cycle time must be limited to guarantee AC timing specification.
2. This parameter is guaranteed by design, and may not be tested at values shown in the table.
3. This parameter refers to CQ and CQ rising and falling edges.
4. This parameter is only for 16Mb density
5. K and K Clocks must be used differencitally to meet AC timing specifications.
Rev 1.1
Jan. 2005
- 10
K7D163674B
K7D161874B
512Kx36 & 1Mx18 SRAM
TIMING WAVEFORMS FOR DOUBLE DATA RATE CYCLES
(Burst Length=4, 2)
READ
READ
CONTINUE READ
(burst of 2)
WRITE
READ
NOP
READ
CONTINUE READ
CONTINUE
CONTINUE
NOP
NOP
WRITE
READ
(burst of 4)
(burst of 4)
(burst of 4)
(burst of 4)
9
5
1
2
4
7
6
8
10
12
11
3
K
K
tKHKH
tKHKL
tKLKH
B1
B2
tBVKH
tKHBX
B3
SA
G
A
2
A5
A1
A3
A0
tAVKH
t
KHAX
t
KHDX
DVKH
t
GHQZ
t
tGGLLQQVX
tGHQX
t
DQ
Q01
Q02
Q03
Q04
Q51
Q52
Q53
Q54
Q11
Q12
D
21
D22
D23
D24
Q31
QX2
t
CHQV
tCHQX
tCLQV
tKXCV
tKXCL
tCHCL tCLCH
tCHQZ
tCHLZ
CQ
CQ
DON’T CARE
UNDEFINED
NOTE
1. Q01 refers to output from address A. Q02 refers to output from the next internal burst address following A, etc.
2. Outputs are disabled(High-Z) one clock cycle after NOP detected or after no pending data requests are present.
3. Doing more than one Read Continue or Write Continue will cause the address to wrap around.
Rev 1.1
Jan. 2005
- 11
K7D163674B
K7D161874B
512Kx36 & 1Mx18 SRAM
TIMING WAVEFORMS FOR SINGLE DATA RATE CYCLES
(Burst Length=4, 2, 1)
READ
READ
READ
WRITE
READ
NOP
READ
CONTINUE CONTINUE CONTINUE READ
CONTINUE
CONTINUE
NOP
NOP
WRITE
READ
(burst of 4)
(burst of 1)
(burst of 2)
(burst of 2)
1
2
3
4
5
6
7
8
9
10
11
12
K
tKHKL
tKLKH
tKHKH
K
B1
B2
B3
tBVKH
tKHBX
A2
A1
A3
A0
SA
G
tDVKH
tAVKH
tKHAX
tKHDX
t
t
tGGHHQQXZ
tGGLLQQVX
DQ
Q01
Q02
Q03
Q04
Q11
QX1
D21
D22
Q31
tKXCV
tCHQX
tCHQV
tKXCL
tCHCL tCLCH
tCHLZ
tCHQZ
CQ
CQ
DON’T CARE
UNDEFINED
NOTE :
1. Q01 refers to output from address A0. Q02 refers to output from the next internal burst address following A0, etc.
2. Outputs are disabled(High-Z) one clock cycle after NOP detected or after no pending data requests are present.
3. This devices supports cycle lengths of 1, 2, 4. Continue(B1=HIGH, B2=HIGH, B3=X) up to three times following a B1 operation. Any further
Continue assertions constitute invalid operations.
4. This device will have an address wraparound if further Continues are applied.
Rev 1.1
Jan. 2005
- 12
K7D163674B
K7D161874B
512Kx36 & 1Mx18 SRAM
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
The SRAM provides a limited set of IEEE standard 1149.1 JTAG functions. This is to test the connectivity during manufacturing
between SRAM, printed circuit board and other components. Internal data is not driven out of SRAM under JTAG control. In conform-
ance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Register, Bypass Register and ID register. The TAP control-
ler has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required. It is possible to use
this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the SRAM, TCK must
be tied to VSS to preclude mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the
application of a logic 1, and therefore can be left unconnected. But they may also be tied to VDD through a resistor. TDO should be left
unconnected.
JTAG Block Diagram
JTAG Instruction Coding
IR2 IR1 IR0 Instruction
TDO Output
Notes
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
EXTEST
IDCODE
SAMPLE-Z
Boundary Scan Register
Identification Register
Boundary Scan Register
1
3
2
6
5
6
6
4
0
0
0
RESERVED Do Not Use
1
SAMPLE
Boundary Scan Register
SRAM
1
RESERVED Do Not Use
RESERVED Do Not Use
CORE
1
1
SA
SA
BYPASS
Bypass Register
NOTE :
1. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs. This instruction is not IEEE 1149.1 compliant.
TDI
BYPASS Reg.
Identification Reg.
Instruction Reg.
TDO
2. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs.
3. TDI is sampled as an input to the first ID register to allow for the serial shift
of the external TDI data.
4. Bypass register is initiated to VSS when BYPASS instruction is invoked. The
Bypass Register also holds serially loaded TDI when exiting the Shift DR
states.
5. SAMPLE instruction dose not places DQs in Hi-Z.
6. This instruction is reserved for future use.
Control Signals
TAP Controller
TMS
TCK
TAP Controller State Diagram
Test Logic Reset
0
Run Test Idle
1
0
1
1
0
1
Select DR
0
Select IR
0
1
1
1
1
Capture IR
Capture DR
0
0
0
Shift IR
Shift DR
1
1
Exit1 IR
Exit1 DR
0
0
Pause DR
Pause IR
0
0
0
0
1
1
Exit2 DR
Exit2 IR
1
1
Update IR
1
1
0
Update DR
0
Rev 1.1
Jan. 2005
- 13
K7D163674B
K7D161874B
512Kx36 & 1Mx18 SRAM
SCAN REGISTER DEFINITION
Part
Instruction Register
Bypass Register
1 bits
ID Register
32 bits
Boundary Scan
68 bits
512Kx36
1M x 18
3 bits
3 bits
1 bits
32 bits
49 bits
ID REGISTER DEFINITION
Revision Number
Part Configuration
Vendor Definition
(17:12)
Samsung JEDEC Code
(11: 1)
Start Bit
(0)
Part
(31:28)
(27:18)
512Kx36
1M x 18
0000
0000
00111 00100
01000 00011
XXXXXX
XXXXXX
00001001110
00001001110
1
1
BOUNDARY SCAN EXIT ORDER(x36)
BOUNDARY SCAN EXIT ORDER(x18)
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
4A
4C
3A
3B
3C
3D
2B
1B
2D
3F
1D
2F
1F
3H
2H
1H
5A
5B
5K
5L
SA
SA
SA
SA
SA
SA
DQ
DQ
DQ
DQ
DQ
CQ
DQ
DQ
DQ
DQ
ZQ
B1
SA
SA
SA
SA
SA
SA
DQ
DQ
DQ
DQ
DQ
CQ
DQ
DQ
DQ
DQ
G
6A
6C
7A
7B
7C
7D
8B
9B
8D
7F
9D
8F
9F
7H
8H
9H
5C
5G
5H
6L
9K
8K
7K
9M
8M
9P
7M
8P
9T
8T
7P
7T
6R
5T
5R
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
26
27
28
29
30
31
32
4A
4C
3A
3B
3C
3D
2B
SA
SA
SA
SA
SA
SA
DQ
SA
SA
SA
SA
SA
SA
6A
6C
7A
7B
7C
7D
25
24
23
22
21
20
DQ
DQ
DQ
9B
8D
7F
19
18
17
33
34
1D
2F
DQ
CQ
DQ
DQ
9F
8H
16
15
35
3H
DQ
36
37
38
39
40
41
1H
5A
5B
5K
5L
4L
DQ
ZQ
B1
B2
B3
G
K
K
MODE
DQ
5C
5G
5H
6L
14
13
12
11
10
K
K
B2
B3
MODE
DQ
DQ
DQ
DQ
CQ
DQ
DQ
DQ
DQ
DQ
SA
SA
SA
SA
SA
4L
LBO
DQ
DQ
DQ
DQ
CQ
DQ
DQ
DQ
DQ
DQ
SA
SA
LBO
9K
1K
2K
3K
1M
2M
1P
3M
2P
1T
42
43
2K
DQ
DQ
DQ
7K
9
1M
CQ
DQ
8M
9P
8
7
8
7
6
5
4
3
2
1
44
45
46
3M
2P
1T
DQ
DQ
DQ
DQ
SA
SA
SA
SA
SA
8T
7P
7T
6R
5T
5R
6
5
4
3
2
1
2T
3T
4R
47
48
49
3P
3T
4R
SA
SA
SA
* Reserved for Mode Pin
* Reserved for Mode Pin
Rev 1.1
Jan. 2005
- 14
K7D163674B
K7D161874B
512Kx36 & 1Mx18 SRAM
JTAG DC OPERATING CONDITIONS
Parameter
Symbol
Min
1.7
Typ
Max
2.6
Unit
V
Note
Power Supply Voltage
VDD
VIH
2.5
Input High Level
0.7*VDD
-0.3
-
-
-
-
VDD+0.3
0.3*VDD
VDD
V
Input Low Level
VIL
V
Output High Voltage(IOH=-2mA)
Output Low Voltage(IOL=2mA)
VOH
VOL
0.75*VDD
VSS
V
0.25*VDD
V
NOTE : 1. The input level of SRAM pin is to follow the SRAM DC specification.
JTAG AC TEST CONDITIONS
Parameter
Symbol
VIH/VIL
TR/TF
Min
Unit
V
Note
Input High/Low Level
VDD/0.0
1.0/1.0
VDD/2
Input Rise/Fall Time
ns
V
Input and Output Timing Reference Level
NOTE : 1. See SRAM AC test output load on page 5.
1
JTAG AC Characteristics
Parameter
Symbol
Min
50
20
20
5
Max
Unit
Note
TCK Cycle Time
tCHCH
tCHCL
tCLCH
tMVCH
tCHMX
tDVCH
tCHDX
tCLQV
-
-
ns
ns
ns
ns
ns
ns
ns
ns
TCK High Pulse Width
TCK Low Pulse Width
TMS Input Setup Time
TMS Input Hold Time
TDI Input Setup Time
TDI Input Hold Time
-
-
5
-
5
-
5
-
Clock Low to Output Valid
0
10
JTAG TIMING DIAGRAM
TCK
tCHCH
tCHCL
tCLCH
tMVCH
tCHMX
tCHDX
TMS
TDI
tDVCH
tCLQV
TDO
Rev 1.1
Jan. 2005
- 15
K7D163674B
K7D161874B
512Kx36 & 1Mx18 SRAM
153 BGA PACKAGE DIMENSIONS
1.27
0.60 ±0.10
0.050
0.024 ±0.004
9 8 7 6 5 4 3 2 1
0.56 ±0.04
0.022 ±0.002
12.50 ±0.10
0.492 ±0.004
14.00 ±0.10
0.551 ±0.004
0.75 ±0.15
0.90 ±0.10
153-∅
∅0.3/0.012MAX
0.030 ±0.006
0.035 ±0.004
2.21
MAX
0.087
0.15
MAX
0.006
BOTTOM VIEW
TOP VIEW
NOTE :
1. All Dimensions are in Millimeters.
2. Solder Ball to PCS Offset : 0.10 MAX.
3. PCB to Cavity Offset : 0.10 MAX.
153 BGA PACKAGE THERMAL CHARACTERISTICS
Parameter
Junction to Ambient(at still air)
Junction to Case
Symbol
Theta_JA
Theta_JC
Theta_JB
Thermal Resistance
Unit
°C/W
°C/W
°C/W
Note
TBD
TBD
TBD
Junction to Board
NOTE : 1. Junction temperature can be calculated by : TJ = TA + PD x Theta_JA.
Rev 1.1
Jan. 2005
- 16
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