K6X0808C1D-GQ700 [SAMSUNG]
Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, 0.450 INCH, PLASTIC, SOP-28;
| 型号： | K6X0808C1D-GQ700 |
| 厂家： | 
SAMSUNG |
| 描述： | Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, 0.450 INCH, PLASTIC, SOP-28 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总9页 (文件大小：117K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K6X0808C1D Family
CMOS SRAM
Document Title
32Kx8 bit Low Power CMOS Static RAM
Revision History
Revision No. History
Draft Data
Remark
0.0
Initial draft
October 09, 2002
Preliminary
1.0
Finalized
December 16, 2003
Final
- Changed ICC from 10mA to 5mA
- Changed ICC1 from 8mA to 7mA
- Changed ICC2 from 35mA to 25mA
- Changed ISB from 3mA to 0.4mA
- Changed IDR for K6X0808C1D-F 15µA to 10µA
- Changed IDR for K6X0808C1D-Q 25µA to 20µA
- Errata correction
2.0
3.0
Revised
July 15, 2004
Final
Final
- Changed ISB1 of Automotive product from 25µA to 30µA
- Deleted 55ns Automotive product
Revised
March 27, 2005
- Changed ISB1 of Automotive product from 30µA to 50µA
- Changed IDR of Automotive product from 20µA to 25µA
- Added Lead Free Products
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 3.0
March 2005
K6X0808C1D Family
CMOS SRAM
32Kx8 bit Low Power full CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
• Process Technology: Full CMOS
• Organization: 32K x 8
The K6X0808C1D families are fabricated by SAMSUNG′s
advanced CMOS process technology. The families support
verious operating temperature ranges and have various pack-
age types for user flexibility of system design. The families
also support low data retention voltage for battery back-up
operation with low data retention current.
• Power Supply Voltage: 4.5~5.5V
• Low Data Retention Voltage: 2V(Min)
• Three state output and TTL Compatible
• Package Type: 28-DIP-600B, 28-SOP-450,
28-TSOP1-0813.4F/R
PRODUCT FAMILY
Power Dissipation
PKG Type
Product Family Operating Temperature Vcc Range Speed
Standby
Operating
(ISB1, Max) (ICC2, Max)
28-DIP-600B, 28-SOP-450,
28-TSOP1-0813.4F/R
K6X0808C1D-F
Industrial(-40~85°C)
551)/70ns
70ns
15µA
4.5~5.5V
25mA
K6X0808C1D-Q Automotive(-40~125°C)
1. The parameters are tested with 50pF test load
PIN DESCRIPTION
50µA
28-SOP-450, 28-TSOP1-0813.4F
FUNCTIONAL BLOCK DIAGRAM
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CS
OE
A11
A9
2
3
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
Clk gen.
Precharge circuit.
4
A8
A14
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A13
A8
5
A13
WE
VCC
A14
A12
A7
6
2
28-TSOP
Type1 - Forward
7
8
3
9
4
A6
10
11
12
13
14
Row
select
A6
Row
Addresses
Memory array
5
A5
A9
A5
A1
A4
6
A11
OE
A4
A2
A3
28-DIP
7
A3
28-SOP
8
14
13
12
11
10
9
A3
A4
A10
CS
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A2
A2
A1
9
A1
A5
A0
A6
I/O1
I/O2
I/O3
VSS
I/O4
I/O5
I/O6
I/O7
I/O8
CS
10
11
12
13
14
I/O8
I/O7
I/O6
I/O5
I/O4
A0
I/O1
I/O8
Data
cont
I/O Circuit
A7
A12
A14
VCC
WE
A13
A8
Column select
I/O1
I/O2
I/O3
VSS
8
28-TSOP
Type1 - Reverse
7
6
Data
cont
5
4
A9
3
A11
Column Addresses
2
1
A10
OE
Pin Name
CS
Function
Chip Select Input
Output Enable Input
Write Enable Input
Address Inputs
Pin Name
I/O1~I/O8
Vcc
Function
CS
Data Inputs/Outputs
Power
Control
logic
WE
OE
OE
WE
Vss
Ground
A0~A14
NC
No connect
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
2
Revision 3.0
March 2005
K6X0808C1D Family
CMOS SRAM
PRODUCT LIST
Industrial Temp. Products(-40~85°C)
Automotive Temp. Products(-40~125°C)
Part Name
Function
Part Name
Function
K6X0808C1D-DF55
K6X0808C1D-DF70
K6X0808C1D-GF55
K6X0808C1D-GF70
K6X0808C1D-BF551)
K6X0808C1D-BF701)
K6X0808C1D-TF55
K6X0808C1D-TF70
K6X0808C1D-LF551)
K6X0808C1D-LF701)
K6X0808C1D-RF55
K6X0808C1D-RF70
28-DIP, 55ns, LL Pwr
28-DIP, 70ns, LL Pwr
28-SOP, 55ns, LL Pwr
28-SOP, 70ns, LL Pwr
28-SOP, 55ns, LL Pwr, LF
28-SOP, 70ns, LL Pwr, LF
28-TSOP-F, 55ns, LL Pwr
28-TSOP-F, 70ns, LL Pwr
28-TSOP-F, 55ns, LL Pwr, LF
28-TSOP-F, 70ns, LL Pwr, LF
28-TSOP-R, 55ns, LL Pwr
28-TSOP-R, 70ns, LL Pwr
K6X0808C1D-GQ70
K6X0808C1D-BQ701)
K6X0808C1D-TQ70
K6X0808C1D-LQ701)
28-SOP, 70ns, L Pwr
28-SOP, 70ns, L Pwr, LF
28-TSOP-F, 70ns, L Pwr
28-TSOP-F, 70ns, L Pwr, LF
1.Lead Free Products
FUNCTIONAL DESCRIPTION
CS
H
L
OE
X1)
H
WE
X1)
H
I/O
High-Z
High-Z
Dout
Mode
Deselected
Power
Standby
Output Disabled
Read
Active
Active
Active
L
L
H
X1)
L
L
Din
Write
1. X means don′t care (Must be in high or low states)
ABSOLUTE MAXIMUM RATINGS1)
Item
Symbol
Ratings
Unit
V
Remark
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
VIN,VOUT
VCC
-0.5 to VCC+0.5V(Max. 7.0V)
-
-0.3 to 7.0
1.0
V
-
PD
W
-
Storage temperature
TSTG
-65 to 150
-40 to 85
-40 to 125
°C
°C
°C
-
K6X0808C1D-F
K6X0808C1D-Q
Operating Temperature
TA
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 3.0
March 2005
K6X0808C1D Family
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Symbol
Vcc
Min
4.5
0
Typ
Max
5.5
0
Unit
V
Supply voltage
Ground
5.0
Vss
0
-
V
Vcc+0.52)
0.8
Input high voltage
Input low voltage
Note:
VIH
2.2
V
-0.53)
VIL
-
V
1. Industrial Product: TA=-40 to 85°C, Otherwise specified
Automotive Product: TA=-40 to 125°C, Otherwise specified
2. Overshoot: Vcc+3.0V in case of pulse width≤30ns.
3. Undershoot: -3.0V in case of pulse width≤30ns.
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Item
Input capacitance
Symbol
CIN
Test Condition
VIN=0V
Min
Max
8
Unit
pF
-
-
Input/Output capacitance
CIO
VIO=0V
10
pF
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Item
Symbol
ILI
Test Conditions
Min Typ Max Unit
Input leakage current
VIN=Vss to Vcc
-1
-1
-
-
-
-
1
1
5
µA
µA
Output leakage current
Operating power supply current
ILO
CS=VIH or OE=VIH or WE=VIL, VIO=VSS to Vcc
IIO=0mA, CS=VIL, VIN=VIH or VIL, Read
ICC
mA
Cycle time=1µs, 100% duty, IIO=0mA, CS≤0.2V,
VIN≤0.2VIN≥Vcc -0.2V
ICC1
-
-
7
mA
Average operating current
ICC2
VOL
VOH
ISB
Cycle time=Min,100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL
-
-
-
-
-
-
-
25
0.4
-
mA
V
Output low voltage
Output high voltage
Standby Current(TTL)
IOL=2.1mA
-
IOH=-1.0mA
2.4
V
CS=VIH, Other inputs=VIH or VIL
-
-
-
0.4
15
50
mA
µA
µA
K6X0808C1D-F
Standby Current (CMOS)
ISB1
CS≥Vcc-0.2V, Other inputs=0~Vcc
K6X0808C1D-Q
4
Revision 3.0
March 2005
K6X0808C1D Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS (Test Load and Test Input/Output Reference)
Input pulse level: 0.8 to 2.4V
1)
Input rising and falling time: 5ns
CL
Input and output reference voltage: 1.5V
Output load (See right): CL=100pF+1TTL
CL=50pF+1TTL
1. Including scope and jig capacitance
AC CHARACTERISTICS (Vcc=4.5~5.5V, Industrial product: TA=-40 to 85°C, Automotive product: TA=-40 to 125°C)
Speed Bins
551)ns
Max
Parameter List
Symbol
Units
70ns
Min
55
-
Min
70
-
Max
Read cycle time
tRC
tAA
-
55
55
25
-
-
70
70
35
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
Chip select to output
tCO
tOE
tLZ
-
-
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
-
-
Read
10
5
10
5
tOLZ
tHZ
-
-
0
20
20
-
0
30
30
-
tOHZ
tOH
tWC
tCW
tAS
0
0
10
55
45
0
10
70
60
0
-
-
Chip select to end of write
Address set-up time
-
-
-
-
Address valid to end of write
Write pulse width
tAW
tWP
tWR
tWHZ
tDW
tDH
45
40
0
-
60
50
0
-
-
-
Write
Write recovery time
-
-
Write to output high-Z
0
20
-
0
25
-
Data to write time overlap
Data hold from write time
End write to output low-Z
25
0
30
0
-
-
tOW
5
-
5
-
1. The parameter is tested with 50pF test load. Industrial Product only.
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
Min
Typ
Max
5.5
10
25
-
Unit
Vcc for data retention
VDR
CS≥Vcc-0.2V
2.0
-
-
-
-
-
-
V
K6X0808C1D-F
K6X0808C1D-Q
Data retention current
IDR
Vcc=3.0V, CS≥Vcc-0.2V
µA
-
Data retention set-up time
Recovery time
tSDR
tRDR
0
See data retention waveform
ms
5
-
5
Revision 3.0
March 2005
K6X0808C1D Family
CMOS SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC
Address
tAA
tOH
Data Valid
Data Out
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO
CS
tHZ
tOE
OE
tOHZ
tOLZ
tLZ
High-Z
Data out
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
6
Revision 3.0
March 2005
K6X0808C1D Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
tCW(2)
tWR(4)
CS
tAW
tWP(1)
WE
tAS(3)
tDW
tDH
Data Valid
Data in
tWHZ
tOW
Data Undefined
Data out
TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)
tWC
Address
tCW(2)
tAS(3)
tWR(4)
CS
tAW
tWP(1)
WE
tDW
tDH
Data in
Data Valid
High-Z
Data out
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE
going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write
to the end of write.
2. tCW is measured from the CS going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS or WE going high.
DATA RETENTION WAVE FORM
CS controlled
Data Retention Mode
tSDR
tRDR
VCC
4.5V
2.2V
VDR
CS≥VCC - 0.2V
CS
GND
7
Revision 3.0
March 2005
K6X0808C1D Family
CMOS SRAM
PACKAGE DIMENSIONS
Units: millimeter(inch)
28 PIN DUAL INLINE PACKAGE(600mil)
+0.10
-0.05
0.25
+0.004
-0.002
0.010
#28
#15
13.60±0.20
0.535±0.008
#1
#14
0~15°
3.81±0.20
36.72
1.446
MAX
0.150±0.008
5.08
0.200
MAX
36.32±0.20
1.430±0.008
3.30±0.30
0.46±0.10
0.130±0.012
0.018±0.004
0.38
0.015
2.54
0.100
1.65
0.065
1.52±0.10
MIN
(
)
0.060±0.004
28 PIN PLASTIC SMALL OUTLINE PACKAGE(450mil)
0~8°
#28
#15
8.38±0.20
11.81±0.30
0.330±0.008
0.465±0.012
#1
#14
1.02±0.20
+0.10
0.15
-0.05
0.040±0.008
2.59±0.20
18.69
MAX
+0.004
-0.002
0.006
0.102±0.008
0.736
3.00
0.118
MAX
18.29±0.20
0.720±0.008
0.10 MAX
0.004 MAX
0.89
0.035
1.27
0.050
0.41±0.10
(
)
0.05
0.002
MIN
0.016±0.004
8
Revision 3.0
March 2005
K6X0808C1D Family
CMOS SRAM
PACKAGE DIMENSIONS
Units: millimeter(inch)
28 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)
13.40±0.20
0.528±0.008
+0.10
0.20
-0.05
+0.004
0.008
-0.002
#1
#28
0.425
0.017
(
)
0.55
0.0217
#14
#15
1.00±0.10
0.039±0.004
0.05
0.002
MIN
1.20
MAX
0.047
28 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4R)
+0.10
-0.05
13.40±0.20
0.528±0.008
0.20
0.008+0.004
-0.002
#14
#15
0.425
0.017
(
)
0.55
0.0217
#1
#28
0.25
0.010
11.80±0.10
0.465±0.004
+0.10
-0.05
1.00±0.10
0.039±0.004
0.05
0.002
TYP
0.15
MIN
0.006+0.004
-0.002
1.20
MAX
0.047
0~8°
0.50
0.020
0.45 ~0.75
0.018 ~0.030
(
)
9
Revision 3.0
March 2005
相关型号：
©2020 ICPDF网 联系我们和版权申明