K6X0808C1D-Q [SAMSUNG]

32Kx8 bit Low Power CMOS Static RAM; 32Kx8位低功耗CMOS静态RAM


型号：	K6X0808C1D-Q
厂家：	SAMSUNG
描述：	32Kx8 bit Low Power CMOS Static RAM 32Kx8位低功耗CMOS静态RAM
文件：	总9页 (文件大小：168K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K6X0808C1D Family

CMOS SRAM

Document Title

32Kx8 bit Low Power CMOS Static RAM

Revision History

Revision No. History

Draft Data

Remark

0.0

Initial draft

October 09, 2002

Preliminary

1.0

Finalized

December 16, 2003

Final

- Changed ICC from 10mA to 5mA

- Changed ICC1 from 8mA to 7mA

- Changed ICC2 from 35mA to 25mA

- Changed ISB from 3mA to 0.4mA

- Changed IDR for K6X0808C1D-F 15mA to 10mA

- Changed IDR for K6X0808C1D-Q 25mA to 20mA

- Errata correction

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and

products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices.

Revision 1.0

December 2003

K6X0808C1D Family

CMOS SRAM

32Kx8 bit Low Power full CMOS Static RAM

FEATURES

GENERAL DESCRIPTION

· Process Technology: Full CMOS

· Organization: 32K x 8

The K6X0808C1D families are fabricated by SAMSUNG¢s

advanced CMOS process technology. The families support

verious operating temperature ranges and have various pack-

age types for user flexibility of system design. The families

also support low data retention voltage for battery back-up

operation with low data retention current.

· Power Supply Voltage: 4.5~5.5V

· Low Data Retention Voltage: 2V(Min)

· Three state output and TTL Compatible

· Package Type: 28-DIP-600B, 28-SOP-450,

28-TSOP1-0813.4F/R

PRODUCT FAMILY

Power Dissipation

PKG Type

Product Family Operating Temperature Vcc Range Speed

Standby

Operating

(ISB1, Max) (ICC2, Max)

28-DIP-600B, 28-SOP-450,

28-TSOP1-0813.4F/R

K6X0808C1D-F

Industrial(-40~85°C)

15mA

55¹⁾/70ns

4.5~5.5V

25mA

K6X0808C1D-Q Automotive(-40~125°C)

1. The parameters are tested with 50pF test load

PIN DESCRIPTION

25mA

28-SOP-450, 28-TSOP1-0813.4F

FUNCTIONAL BLOCK DIAGRAM

A10

A11

I/O8

I/O7

I/O6

I/O5

I/O4

VSS

I/O3

I/O2

I/O1

Clk gen.

Precharge circuit.

A14

A12

VCC

A13

VCC

A14

A12

28-TSOP

Type1 - Forward

Row

select

Row

Addresses

Memory array

A11

28-DIP

28-SOP

A10

I/O1

I/O2

I/O3

VSS

I/O4

I/O5

I/O6

I/O7

I/O8

I/O7

I/O6

I/O5

I/O4

I/O1

I/O8

Data

cont

I/O Circuit

A12

A14

VCC

A13

Column select

I/O1

I/O2

I/O3

VSS

28-TSOP

Type1 - Reverse

Data

cont

A11

Column Addresses

A10

Pin Name

Function

Chip Select Input

Output Enable Input

Write Enable Input

Address Inputs

Pin Name

I/O1~I/O8

Vcc

Function

Data Inputs/Outputs

Power

Control

logic

Vss

Ground

A0~A14

No connect

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

Revision 1.0

December 2003

K6X0808C1D Family

CMOS SRAM

PRODUCT LIST

Industrial Temp. Products(-40~85°C)

Automotive Temp. Products(-40~125°C)

Part Name

Function

Part Name

Function

K6X0808C1D-DF55

K6X0808C1D-DF70

K6X0808C1D-GF55

K6X0808C1D-GF70

K6X0808C1D-TF55

K6X0808C1D-TF70

K6X0808C1D-RF55

K6X0808C1D-RF70

28-DIP, 55ns, LL Pwr

28-DIP, 70ns, LL Pwr

K6X0808C1D-GQ55

K6X0808C1D-GQ70

K6X0808C1D-TQ55

K6X0808C1D-TQ70

28-SOP, 55ns, L Pwr

28-SOP, 70ns, L Pwr

28-TSOP-F, 55ns, L Pwr

28-TSOP-F, 70ns, L Pwr

28-SOP, 55ns, LL Pwr

28-SOP, 70ns, LL Pwr

28-TSOP-F, 55ns, LL Pwr

28-TSOP-F, 70ns, LL Pwr

28-TSOP-R, 55ns, LL Pwr

28-TSOP-R, 70ns, LL Pwr

FUNCTIONAL DESCRIPTION

X¹⁾

I/O

High-Z

Dout

Mode

Power

Standby

Active

Deselected

Output Disabled

Read

Active

X¹⁾

Din

Write

Active

1. X means don¢t care (Must be in high or low states)

ABSOLUTE MAXIMUM RATINGS¹⁾

Item

Symbol

Ratings

Unit

Remark

Voltage on any pin relative to Vss

Voltage on Vcc supply relative to Vss

Power Dissipation

VIN,VOUT

VCC

-0.5 to VCC+0.5V(Max. 7.0V)

-0.3 to 7.0

1.0

Storage temperature

TSTG

-65 to 150

-40 to 85

-40 to 125

°C

K6X0808C1D-F

K6X0808C1D-Q

Operating Temperature

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be

restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Revision 1.0

December 2003

K6X0808C1D Family

CMOS SRAM

RECOMMENDED DC OPERATING CONDITIONS¹⁾

Item

Symbol

Vcc

Min

4.5

Typ

Max

5.5

Unit

Supply voltage

Ground

5.0

Vss

Vcc+0.5²⁾

0.8

Input high voltage

Input low voltage

Note:

VIH

2.2

-0.5³⁾

VIL

1. Industrial Product: TA=-40 to 85°C, Otherwise specified

Automotive Product: TA=-40 to 125°C, Otherwise specified

2. Overshoot: Vcc+3.0V in case of pulse width£30ns.

3. Undershoot: -3.0V in case of pulse width£30ns.

4. Overshoot and undershoot are sampled, not 100% tested.

CAPACITANCE¹⁾(f=1MHz, TA=25°C)

Item

Input capacitance

Symbol

CIN

Test Condition

VIN=0V

Min

Max

Unit

Input/Output capacitance

CIO

VIO=0V

1. Capacitance is sampled, not 100% tested

DC AND OPERATING CHARACTERISTICS

Item

Symbol

ILI

Test Conditions

Min Typ Max Unit

Input leakage current

VIN=Vss to Vcc

-1

Output leakage current

Operating power supply current

ILO

CS=VIH or OE=VIH or WE=VIL, VIO=VSS to Vcc

IIO=0mA, CS=VIL, VIN=VIH or VIL, Read

ICC

Cycle time=1ms, 100% duty, IIO=0mA, CS£0.2V,

VIN£0.2VIN³ Vcc -0.2V

ICC1

Average operating current

ICC2

VOL

VOH

ISB

Cycle time=Min,100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL

0.4

Output low voltage

Output high voltage

Standby Current(TTL)

IOL=2.1mA

IOH=-1.0mA

2.4

CS=VIH, Other inputs=VIH or VIL

0.4

K6X0808C1D-F

Standby Current (CMOS)

ISB1

CS³ Vcc-0.2V, Other inputs=0~Vcc

K6X0808C1D-Q

Revision 1.0

December 2003

K6X0808C1D Family

CMOS SRAM

AC OPERATING CONDITIONS

TEST CONDITIONS (Test Load and Test Input/Output Reference)

Input pulse level: 0.8 to 2.4V

Input rising and falling time: 5ns

Input and output reference voltage: 1.5V

Output load (See right): CL=100pF+1TTL

CL=50pF+1TTL

1. Including scope and jig capacitance

AC CHARACTERISTICS (Vcc=4.5~5.5V, Commercial product: TA=0 to 70°C, Industrial product: TA=-40 to 85°C)

Speed Bins

55¹⁾ns

Max

Parameter List

Symbol

Units

70ns

Min

Max

Read cycle time

tRC

tAA

Address access time

Chip select to output

tCO

tOE

tLZ

Output enable to valid output

Chip select to low-Z output

Output enable to low-Z output

Chip disable to high-Z output

Output disable to high-Z output

Output hold from address change

Write cycle time

Read

tOLZ

tHZ

tOHZ

tOH

tWC

tCW

tAS

Chip select to end of write

Address set-up time

Address valid to end of write

Write pulse width

tAW

tWP

tWR

tWHZ

tDW

tDH

tOW

Write

Write recovery time

Write to output high-Z

Data to write time overlap

Data hold from write time

End write to output low-Z

1. The parameter is tested with 50pF test load.

DATA RETENTION CHARACTERISTICS

Item

Symbol

Test Condition

Min

Typ

Max

5.5

Unit

Vcc for data retention

VDR

CS³ Vcc-0.2V

2.0

K6X0808C1D-F

K6X0808C1D-Q

Data retention current

IDR

Vcc=3.0V, CS³ Vcc-0.2V

Data retention set-up time

Recovery time

tSDR

tRDR

See data retention waveform

Revision 1.0

December 2003

K6X0808C1D Family

CMOS SRAM

TIMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)

tRC

Address

tAA

tOH

Data Valid

Data Out

Previous Data Valid

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

tRC

Address

tOH

tAA

tCO

tHZ

tOE

tOHZ

tOLZ

tLZ

High-Z

Data out

Data Valid

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

Revision 1.0

December 2003

K6X0808C1D Family

CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

tWC

Address

tCW(2)

tWR(4)

tAW

tWP(1)

tAS(3)

tDW

tDH

Data Valid

Data in

tWHZ

tOW

Data Undefined

Data out

TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)

tWC

Address

tCW(2)

tAS(3)

tWR(4)

tAW

tWP(1)

tDW

tDH

Data in

Data Valid

High-Z

Data out

High-Z

NOTES (WRITE CYCLE)

1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE

going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write

to the end of write.

2. tCW is measured from the CS going low to the end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS or WE going high.

DATA RETENTION WAVE FORM

CS controlled

Data Retention Mode

tSDR

tRDR

VCC

4.5V

2.2V

VDR

CS³ VCC - 0.2V

GND

Revision 1.0

December 2003

K6X0808C1D Family

CMOS SRAM

PACKAGE DIMENSIONS

Units: millimeter(inch)

28 PIN DUAL INLINE PACKAGE(600mil)

+0.10

-0.05

0.25

+0.004

-0.002

0.010

#28

#15

13.60±0.20

0.535±0.008

#14

0~15°

3.81±0.20

0.150±0.008

36.72

1.446

MAX

5.08

0.200

MAX

36.32±0.20

1.430±0.008

3.30±0.30

0.46±0.10

0.130±0.012

0.018±0.004

0.38

0.015

2.54

0.100

1.65

0.065

1.52±0.10

0.060±0.004

MIN

(

)

28 PIN PLASTIC SMALL OUTLINE PACKAGE(450mil)

0~8°

#28

#15

8.38±0.20

0.330±0.008

11.81±0.30

0.465±0.012

#14

1.02±0.20

0.040±0.008

+0.10

0.15

-0.05

2.59±0.20

0.102±0.008

18.69

MAX

+0.004

-0.002

0.006

0.736

3.00

0.118

MAX

18.29±0.20

0.720±0.008

0.10 MAX

0.004 MAX

0.89

0.035

1.27

0.050

0.41±0.10

0.016±0.004

(

)

0.05

0.002

MIN

Revision 1.0

December 2003

K6X0808C1D Family

CMOS SRAM

PACKAGE DIMENSIONS

Units: millimeter(inch)

28 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)

13.40±0.20

0.528±0.008

+0.10

-0.05

+0.004

0.20

0.008

-0.002

#28

0.425

0.017

(

)

0.55

0.0217

#14

#15

1.00±0.10

0.039±0.004

0.05

0.002

MIN

1.20

MAX

0.047

28 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4R)

+0.10

-0.05

13.40±0.20

0.528±0.008

0.20

0.008^+0.004

-0.002

#14

#15

0.425

0.017

(

)

0.55

0.0217

#28

0.25

0.010

11.80±0.10

0.465±0.004

+0.10

-0.05

1.00±0.10

0.039±0.004

0.05

0.002

TYP

0.15

MIN

0.006^+0.004

-0.002

1.20

MAX

0.047

0~8°

0.50

0.020

0.45 ~0.75

0.018 ~0.030

(

)

Revision 1.0

December 2003

K6X0808C1D-Q [SAMSUNG]

相关型号：

K6X0808C1D-RF55

K6X0808C1D-RF550

K6X0808C1D-RF70

K6X0808C1D-TF55

K6X0808C1D-TF550

K6X0808C1D-TF70

K6X0808C1D-TF700

K6X0808C1D-TQ55

K6X0808C1D-TQ550

K6X0808C1D-TQ70

K6X0808C1D-TQ700

K6X0808T1D