K6L0908V2A-YD85T [SAMSUNG]
Standard SRAM, 64KX8, 85ns, CMOS, PDSO32;
| 型号： | K6L0908V2A-YD85T |
| 厂家： | 
SAMSUNG |
| 描述： | Standard SRAM, 64KX8, 85ns, CMOS, PDSO32 静态存储器 光电二极管 |
| 文件： | 总10页 (文件大小：193K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K6L0908V2A, K6L0908U2A Family
CMOS SRAM
Document Title
64Kx8 bit Low Power and Low Voltage CMOS Static RAM
Revision History
Revision No. History
Draft Data
Remark
0.0
0.1
Design target
January 17, 1996
April 15, 1996
Advance
Initial draft
Preliminary
- One datasheet for commercial, extended and industrial product.
- Add 85ns part on KM68V512AFamily.
1.0
2.0
Finalize
June 17, 1996
Final
Final
Revise
September 10, 1996
- Add 32-sTSOP type package on product.
3.0
Revise
February 12, 1998
Final
- Change datasheet format
- Improve power dissipation 0.7 to 1.0W
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 3.0
February 1998
K6L0908V2A, K6L0908U2A Family
CMOS SRAM
64Kx8 bit Low Power and Low Voltage CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
· Process Technology: Poly Load
· Organization: 64Kx8
The K6L0908V2A and K6L0908U2A families are fabricated
by SAMSUNG¢s advanced CMOS process technology. The
families support various operating temperature ranges and
have various package types for user flexibility of system
design. The family also support low data retention voltage for
battery back-up operation with low data retention current.
· Power Supply Voltage
K6L0908V2A family: 2.7~3.3V
K6L0908U2A family: 3.0~3.3V
· Low Data Retention Voltage: 2V(Min)
· Three state output and TTL Compatible
· Package Type: 32-SOP-525, 32-TSOP1-0820F,
32-TSOP1-0813.4F
PRODUCT FAMILY
Power Dissipation
Product Family Operating Temperature
VCC Range
Speed
PKG Type
Standby
(Isb1, Max)
Operating
(Icc2, Max)
701)/85/100ns
851)/100ns
K6L0908V2A-B
3.0 ~ 3.6V
2.7 ~ 3.3V
3.0 ~ 3.6V
2.7 ~ 3.3V
3.0 ~ 3.6V
2.7 ~ 3.3V
10mA
10mA
20mA
15mA
20mA
15mA
Commercial(0~70°C)
K6L0908U2A-B
32-SOP
701)/85/100ns
851)/100ns
32-TSOP1-F
32-sTSOP1-F
K6L0908V2A-D
Extended(-25~85°C)
40mA
K6L0908U2A-D
701)/85/100ns
851)/100ns
K6L0908V2A-F
Industrial (-40~85°C)
K6L0908U2A-F
1. The parameter is measured with 30pF test load.
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTION
A11
A9
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
2
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
Clk gen.
Precharge circuit.
A8
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A13
WE
CS2
A15
VCC
N.C
N.C
A14
A12
A7
N.C
N.C
A14
A12
A7
1
VCC
A15
CS2
WE
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
2
32-TSOP
Type1 - Forward
(8mm x 20mm)
A4
A5
3
4
5
A13
A8
A6
A7
A8
6
A6
Memory array
512 rows
128´ 8 columns
Row
select
7
A9
A5
A6
A5
A4
A1
A2
A3
8
A11
OE
A4
32-SOP
A12
A13
A14
A15
9
A3
10
11
12
13
14
15
16
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
A2
A11
A9
A8
1
2
3
4
5
6
7
32
31
30
29
28
27
26
OE
A1
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A0
A13
WE
CS2
A15
VCC
N.C
N.C
A14
A12
A7
I/O1
I/O2
I/O3
VSS
32-sTSOP
I/O1
I/O8
Data
cont
I/O Circuit
Type1 - Forward
8
9
25
24
(8mm x 13.4mm)
23
Column select
10
11
12
13
14
15
16
22
21
20
19
18
17
A6
A5
A4
A1
A2
A3
Data
cont
A0 A1 A2 A3 A9 A10 A11
Name Name
CS1,CS2
OE
Function
Chip Select Inputs
Output Enable Input
Write Enable Input
Address Inputs
Data Inputs/Outputs
Power
CS1
CS2
Control
logic
WE
WE
OE
A0~A15
I/O1~I/O8
Vcc
Vss
Ground
N.C
No Connection
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
2
Revision 3.0
February 1998
K6L0908V2A, K6L0908U2A Family
CMOS SRAM
PRODUCT LIST
Industrial Temperature Products
Commercial Temperature Products
Extended Temperature Products
(-25~85°C)
(-40~85°C)
(0~70°C)
Part Name
Function
Part Name
Function
Part Name
Function
K6L0908V2A-GB70 32-SOP, 70ns, 3.3V, LL
K6L0908V2A-GB85 32-SOP, 85ns, 3.3V, LL
K6L0908V2A-GB10 32-SOP, 100ns, 3.3V, LL
K6L0908V2A-TB70 32-TSOP F, 70ns, 3.3V, LL
K6L0908V2A-TB85 32-TSOP F, 85ns, 3.3V, LL
K6L0908V2A-TB10 32-TSOP F, 100ns, 3.3V,LL
K6L0908V2A-YB70 32-sTSOP F,70ns,3.3V,LL
K6L0908V2A-GD70 32-SOP, 70ns, 3.3V, LL
K6L0908V2A-GD85 32-SOP, 85ns, 3.3V, LL
K6L0908V2A-GD10 32-SOP, 100ns, 3.3V, LL
K6L0908V2A-GF70 32-SOP, 70ns, 3.3V, LL
K6L0908V2A-GF85 32-SOP, 85ns, 3.3V, LL
K6L0908V2A-GF10 32-SOP, 100ns, 3.3V, LL
K6L0908V2A-TF70 32-TSOP F, 70ns, 3.3V, LL
K6L0908V2A-TF85 32-TSOP F, 85ns, 3.3V, LL
K6L0908V2A-TF10 32-TSOP F, 100ns, 3.3V,LL
K6L0908V2A-YF70 32-sTSOP F,70ns,3.3V,LL
K6L0908V2A-TD70
K6L0908V2A-TD85
K6L0908V2A-TD10
K6L0908V2A-YD70
K6L0908V2A-YD85
K6L0908V2A-YD10
32-TSOP F, 70ns, 3.3V, LL
32-TSOP F, 85ns, 3.3V, LL
32-TSOP F, 100ns, 3.3V,LL
32-sTSOP F,70ns,3.3V,LL
32-sTSOP F,85ns,3.3V,LL
32-sTSOP F,100ns,3.3V,LL
K6L0908V2A-YB85
K6L0908V2A-YB10
K6L0908V2A-YF85
K6L0908V2A-YF10
32-sTSOP F,85ns,3.3V,LL
32-sTSOP F,100ns,3.3V,LL
32-sTSOP F,85ns,3.3V,LL
32-sTSOP F,100ns,3.3V,LL
K6L0908U2A-GB85
K6L0908U2A-GB10
K6L0908U2A-TB85
K6L0908U2A-TB10
K6L0908U2A-YB85
K6L0908U2A-YB10
K6L0908U2A-GD85
K6L0908U2A-GD10
K6L0908U2A-TD85
K6L0908U2A-TD10
K6L0908U2A-YD85
K6L0908U2A-YD10
K6L0908U2A-GF85
K6L0908U2A-GF10
K6L0908U2A-TF85
K6L0908U2A-TF10
K6L0908U2A-YF85
K6L0908U2A-YF10
32-SOP, 85ns, 3.0V, LL
32-SOP, 85ns, 3.0V, LL
32-SOP, 85ns, 3.0V, LL
32-SOP, 100ns, 3.0V, LL
32-TSOP F, 85ns, 3.0V, LL
32-TSOP F, 100ns, 3.0V, LL
32-sTSOP F, 85ns, 3.0V, LL
32-sTSOP F, 100ns,3.0V, LL
32-SOP, 100ns, 3.0V, LL
32-TSOP F, 85ns, 3.0V, LL
32-TSOP F, 100ns, 3.0V, LL
32-sTSOP F, 85ns, 3.0V, LL
32-sTSOP F, 100ns,3.0V, LL
32-SOP, 100ns, 3.0V, LL
32-TSOP F, 85ns, 3.0V, LL
32-TSOP F, 100ns, 3.0V, LL
32-sTSOP F, 85ns, 3.0V, LL
32-sTSOP F, 100ns,3.0V, LL
FUNCTIONAL DESCRIPTION
CS1
H
CS2
X1)
L
OE
X1)
X1)
H
WE
X1)
X1)
H
I/O
Mode
Power
Standby
Standby
Active
High-Z
High-Z
Deselected
Deselected
X1)
L
H
High-Z
Dout
Din
Output Disabled
Read
L
H
L
H
Active
X1)
L
H
L
Write
Active
1. X means don¢t care(Must be low or high state.)
ABSOLUTE MAXIMUM RATINGS1)
Item
Symbol
VIN,VOUT
VCC
Ratings
Unit
V
Remark
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to
Power Dissipation
-0.5 to VCC+0.5
-0.3 to 4.6
-
-
-
-
V
PD
1.0
W
°C
°C
°C
°C
-
Storage temperature
TSTG
-65 to 150
0 to 70
K6L0908V2A-B, K6L0908U2A-B
K6L0908V2A-D, K6L0908U2A-D
K6L0908V2A-F, K6L0908U2A-F
-
Operating Temperature
TA
-25 to 85
-40 to 85
Soldering temperature and time
TSOLDER
260°C, 10sec (Lead Only)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 3.0
February 1998
K6L0908V2A, K6L0908U2A Family
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Symbol
Product
K6L0908V2A Family
Min
3.0
2.7
0
Typ
3.3
3.0
0
Max
Unit
V
3.6
Supply voltage
Vcc
K6L0908U2A Family
3.3
V
Ground
Vss
VIH
VIL
All Family
0
V
Vcc+0.3V2)
0.4
Input high voltage
Input low voltage
Note:
K6L0908V2A, K6L0908U2A Family
K6L0908V2A, K6L0908U2A Family
2.2
-0.33)
-
V
-
V
1. Commercial Product : TA=0 to 70°C, otherwise specified
Extended Product : TA=-25 to 85°C, otherwise specified
Industrial Product : TA=-40 to 85°C, otherwise specified
2. Overshoot : VCC+3.0V in case of pulse width£30ns
3. Undershoot : -3.0V in case of pulse width£30ns
4. Overshoot and undershoot are sampled, not 100% tested
CAPACITANCE1) (f=1MHz, TA=25°C)
Item
Symbol
CIN
Test Condition
VIN=0V
Min
Max
Unit
Input capacitance
-
-
6
8
pF
pF
Input/Output capacitance
CIO
VIO=0V
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Item
Symbol
ILI
Min Typ Max Unit
Test Conditions
Input leakage current
VIN=Vss to Vcc
-1
-1
-
-
-
-
1
1
5
mA
mA
Output leakage current
Operating power supply current
ILO
CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc
IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL
ICC
mA
Cycle time=1ms, 100% duty, IIO=0mA,
CS1£0.2V, CS2³ Vcc-0.2V, VIN£0.2V or VIN³ Vcc-0.2V
ICC1
ICC2
-
-
-
-
5
mA
mA
Average operating current
Cycle time=Min, 100% duty, IIO=0mA
CS1=VIL, CS2=VIH, VIN=VIL or VIH
40
Output low voltage
Output high voltage
Standby Current(TTL)
VOL
VOH
ISB
IOL=2.1mA
-
2.4
-
-
-
-
-
0.4
-
V
V
IOH=-1.0mA
CS1=VIH, CS2=VIL, Other inputs=VIL or VIH
K6L0908V2A-B
0.3
10
mA
mA
-
K6L0908V2A-D
K6L0908V2A-F
-
-
20
mA
CS1³ Vcc-0.2V, CS2³ Vcc-0.2V, or
CS2£0.2V, Other inputs=0~Vcc
Standby Current(CMOS)
ISB1
K6L0908U2A-B
-
-
-
-
10
15
mA
mA
K6L0908U2A-D
K6L0908U2A-F
4
Revision 3.0
February 1998
K6L0908V2A, K6L0908U2A Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS( Test Load and Input/Output Reference)
Input pulse level : 0.4 to 2.2V
Input rising and falling time : 5ns
Input and output reference voltage :1.5V
1)
CL
Output load(see right) : CL=100pF+1TTL
1)CL=30pF+1TTL
1. K6L0908V2A-70 Family, K6L0908U2A-85 Family
1. Including scope and jig capacitance
AC CHARACTERISTICS (K6L0908V2B Family:Vcc=3.0~3.6V, K6L0908U2B Family:Vcc=2.7~3.3V,
Commercial product:TA=0 to 70°C, Extended product:TA=-25 to 85°C, Industrial product:TA=-40 to 85°C)
Speed Bins
85ns
Parameter List
Symbol
Units
70ns
100ns
Min
70
-
Max
Min
Max
Min
100
-
Max
Read cycle time
tRC
tAA
-
70
70
35
-
85
-
-
85
85
45
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
100
Chip select to output
tCO
tOE
-
-
-
100
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
-
-
-
50
-
Read
tLZ
10
5
10
5
10
5
tOLZ
tHZ
-
-
-
0
25
25
-
0
30
20
-
0
30
20
-
tOHZ
tOH
tWC
tCW
tAS
0
0
0
10
70
60
0
10
85
70
0
15
100
80
0
-
-
-
Chip select to end of write
Address set-up time
-
-
-
-
-
-
Address valid to end of write
Write pulse width
tAW
tWP
tWR
tWHZ
tDW
tDH
60
55
0
-
70
60
0
-
80
70
0
-
-
-
-
Write
Write recovery time
-
-
-
Write to output high-Z
0
25
-
0
25
-
0
30
-
Data to write time overlap
Data hold from write time
End write to output low-Z
30
0
35
0
40
0
-
-
-
tOW
5
-
5
-
5
-
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
Min
Typ
Max
Unit
1)
Vcc for data retention
VDR
2.0
-
3.6
V
CS1 ³ Vcc-0.2V
K6L0908V2A-B
K6L0908V2A-D
K6L0908V2A-F
-
-
-
-
-
-
10
15
15
Vcc=3.0V, CS1³ Vcc-0.2V,
CS2³ Vcc-0.2V or CS2£0.2V
Data retention current
IDR
mA
K6L0908U2A-B
K6L0908U2A-D
K6L0908U2A-F
-
-
-
-
-
-
8
10
10
Data retention set-up time
Recovery time
tSDR
tRDR
0
5
-
-
-
-
See data retention waveform
ms
1. CS1³ Vcc-0.2V, CS2 ³ Vcc-0.2V( CS1 controlled) or CS2£0.2V(CS2 controlled)
5
Revision 3.0
February 1998
K6L0908V2A, K6L0908U2A Family
CMOS SRAM
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, WE=VIH)
tRC
Address
tAA
tOH
Data Valid
Data Out
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO1
CS1
tHZ(1,2)
CS2
tCO2
tOE
OE
tOHZ
tOLZ
tLZ
High-Z
Data out
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
6
Revision 3.0
February 1998
K6L0908V2A, K6L0908U2A Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
tCW(2)
tWR(4)
CS1
tAW
CS2
tCW(2)
tWP(1)
WE
tAS(3)
tDW
tDH
Data Valid
Data in
tWHZ
tOW
Data Undefined
Data out
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)
tWC
Address
CS1
tCW(2)
tAS(3)
tWR(4)
tAW
CS2
tWP(1)
WE
tDW
tDH
Data in
Data out
Data Valid
High-Z
High-Z
7
Revision 3.0
February 1998
K6L0908V2A, K6L0908U2A Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (CS1 Controlled)
tWC
Address
CS1
tAS(3)
tCW(2)
tWR(4)
tAW
CS2
tCW(2)
tWP(1)
WE
tDH
tDW
Data Valid
Data in
High-Z
High-Z
Data out
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,
CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,
tWP is measured from the begining of write to the end of write.
2. tCW is measured from the CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR(1) applied in case a write ends as CS1 or WE going high tWR(2)
applied in case a write ends as CS2 going to low.
DATA RETENTION WAVE FORM
CS1 controlled
Data Retention Mode
tSDR
tRDR
VCC
3.0/2.7V
2.2V
VDR
CS1³ VCC - 0.2V
CS1
GND
CS2 controlled
Data Retention Mode
VCC
3.0/2.7V
CS2
tSDR
tRDR
VDR
CS2£0.2V
0.4V
GND
.
8
Revision 3.0
February 1998
K6L0908V2A, K6L0908U2A Family
CMOS SRAM
Units: millimeter(inch)
PACKAGE DIMENSIONS
32 PIN SMALL OUTLINE PACKAGE (525mil)
0~8°
#32
#17
14.12±0.30
0.556±0.012
11.43±0.20
0.450±0.008
0.80±0.20
0.031±0.008
#1
#16
+0.10
-0.05
0.20
2.74±0.20
20.87
MAX
0.108±0.008
+0.004
0.822
0.008
-0.002
3.00
0.118
MAX
20.47±0.20
0.806±0.008
0.10 MAX
0.004 MAX
+0.100
-0.050
0.41
0.71
0.028
1.27
0.050
+0.004
-0.002
(
)
0.05
0.002
0.016
MIN
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)
+0.10
-0.05
20.00±0.20
0.787±0.008
0.20
0.008+0.004
-0.002
#1
#32
0.25
0.010
(
)
8.40
0.331
MAX
0.50
0.0197
#16
#17
1.00±0.10
0.039±0.004
0.05
0.002
MIN
1.20
MAX
0.047
0.25
0.010
18.40±0.10
0.724±0.004
TYP
+0.10
0.15
-0.05
0.006+0.004
-0.002
0~8°
0.45 ~0.75
0.018 ~0.030
0.50
0.020
(
)
9
Revision 3.0
February 1998
K6L0908V2A, K6L0908U2A Family
CMOS SRAM
Units: millimeter(inch)
PACKAGE DIMENSIONS
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)
+0.10
-0.05
+0.004
13.40±0.10
0.528±0.008
0.20
0.008
-0.002
0.25
0.010
(
)
#1
#32
8.40
0.331
MAX
0.50
0.0197
1.00±0.10
0.039±0.004
0.05
0.002
MIN
#16
#17
1.20
0.047
MAX
0.25
0.010
TYP
11.80±0.10
0.465±0.004
+0.10
-0.05
0.15
0.006+0.004
-0.002
0~8°
0.50
0.020
0.45 ~0.75
0.018 ~0.030
(
)
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4R)
+0.10
-0.05
+0.004
13.40±0.10
0.528±0.008
0.20
0.008
-0.002
#16
#17
0.25
0.010
(
)
8.40
0.331
MAX
0.50
0.0197
#32
#1
1.00±0.10
0.039±0.004
0.05
0.002
MIN
1.20
MAX
0.047
0.25
0.010
TYP
11.80±0.10
0.465±0.004
+0.10
-0.05
0.15
+0.004
0.006
-0.002
0~8°
0.45 ~0.75
0.018 ~0.030
0.50
0.020
(
)
10
Revision 3.0
February 1998
相关型号：
K6L1008U2C-ND10
Standard SRAM, 128KX8, 100ns, CMOS, PDSO32, 8 X 13.40 MM, REVERSE, STSOP1-32
SAMSUNG
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