K6L1008U2C-GD85 [SAMSUNG]
Standard SRAM, 128KX8, 85ns, CMOS, PDSO32, 0.525 INCH, PLASTIC, SOP-32;
| 型号： | K6L1008U2C-GD85 |
| 厂家： | 
SAMSUNG |
| 描述： | Standard SRAM, 128KX8, 85ns, CMOS, PDSO32, 0.525 INCH, PLASTIC, SOP-32 静态存储器 光电二极管 |
| 文件： | 总11页 (文件大小：210K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K6L1008V2C, K6L1008U2C Family
CMOS SRAM
Document Title
128K x8 bit Low Power and Low Voltage CMOS Static RAM
Revision History
Revision No. History
Draft Data
Remark
0.0
1.0
Initial draft
July 3, 1996
Preliminary
Finalize
December 16, 1996
Final
- Increased ISB, IDR
Commercial part = 10mA
Industrial part = 20mA
2.0
Revise
November 25, 1997
Final
- Change speed bin
KM68V1000C Family: 70/85ns ® 70/100ns
KM68U1000C Family: 70/100ns ® 85/100ns
- Improved operating current: 40mA ® 35mA
- Improved power dissipation
PD: 0.7W ® 1.0W
- Improved standby current
Extended/Industrial: 20 ® 10mA
- VIL: 0.4V ® 0.6V
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
Revision 2.0
November 1997
1
K6L1008V2C, K6L1008U2C Family
CMOS SRAM
128K x8 bit Low Power and Low Voltage CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
· Process Technology: 0.4mm CMOS
· Organization: 128K x8
The K6L1008V2C and K6L1008U2C families are fabricated by
SAMSUNG¢s advanced CMOS process technology. The fami-
lies support various operating temperature ranges and have
various package types for user flexibility of system design. The
families also supports low data retention voltage for battery
back-up operation with low data retention current.
· Power Supply Voltage:
K6L1008V2C family: 3.0~3.6V
K6L1008U2C family: 2.7~3.3V
· Low Data Retention Voltage: 2V(Min)
· Three state output and TTL Compatible
· Package Type: 32-SOP-525, 32-TSOP1-0820F/R,
32-TSOP1-0813.4F/R
PRODUCT FAMILY
Power Dissipation
Product Family
Operating Temperature Vcc Range
Speed
PKG Type
Standby
(ISB1, Max)
Operating
(ICC2, Max)
K6L1008V2C-B
K6L1008U2C-B
K6L1008V2C-D
K6L1008U2C-D
K6L1008V2C-F
K6L1008U2C-F
3.0~3.6V
2.7~3.3V
3.0~3.6V
2.7~3.3V
3.0~3.6V
2.7~3.3V
70/100ns
85/100ns
70/100ns
85/100ns
70/100ns
85/100ns
Commercial(0~70°C)
Extended(-25~85°C)
Industrial(-40~85°C)
32-SOP
32-TSOP1-F/R
32-sTSOP1-F/R
10mA
35mA
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
A11
A9
A8
A13
WE
CS2
A15
VCC
NC
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
Clk gen.
Precharge circuit.
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A4
A5
A6
VCC
VSS
VCC
A15
CS2
N.C
A16
A14
A12
A7
1
32
32-TSOP
2
31
32-STSOP
9
30
3
A16
WE A14
A12
Type1-Forward
10
11
12
13
14
15
16
A7
A8
Memory array
1024 rows
128´ 8 columns
29
4
Row
select
28
A13
5
A7
A12
A13
A14
A15
A6
A8
A1
A2
A3
27
A6
6
A5
26
A9
A4
A5
7
32-SOP 25
A11
8
A4
24
23
22
21
20
19
18
17
OE
A4
A3
9
16
15
14
13
12
11
10
9
8
7
6
5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A3
A2
A1
A0
A16
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
A5
A6
A7
A2
10
11
12
13
14
15
16
A1
I/O1
I/O2
I/O3
VSS
I/O4
I/O5
I/O6
I/O7
I/O8
CS1
A10
OE
A12
A14
A16
NC
VCC
A15
CS2
WE
A13
A8
A0
I/O Circuit
Data
cont
I/O1
I/O8
I/O1
I/O2
I/O3
VSS
Column select
32-TSOP
32-STSOP
Type1-Reverse
4
3
2
1
A9
A11
A10 A0 A1 A2 A3 A9 A11
Name
CS1, CS2
OE
Function
Chip Select Inputs
Output Enable Input
Write Enable Input
Address Inputs
Data Inputs/Outputs
Power
CS1
Control
logic
CS2
WE
OE
WE
A0~A16
I/O1~I/O8
Vcc
Vss
Ground
N.C
No Connection
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
Revision 2.0
November 1997
2
K6L1008V2C, K6L1008U2C Family
CMOS SRAM
PRODUCT LIST
Commercial Temperature Products
Extended Temperature Products
(-25~85°C)
Industrial Temperature Products
(0~70°C)
(-40~85°C)
Part Name
Function
Part Name
Function
Part Name
Function
K6L1008V2C-GB70
K6L1008V2C-GB10
K6L1008V2C-TB70
K6L1008V2C-TB10
K6L1008V2C-RB70
K6L1008V2C-RB10
32-SOP, 70ns, 3.3V
K6L1008V2C-GD70
K6L1008V2C-GD10
K6L1008V2C-TD70
K6L1008V2C-TD10
K6L1008V2C-RD70
32-SOP, 70ns, 3.3V
K6L1008V2C-GF70
K6L1008V2C-GF10
K6L1008V2C-TF70
K6L1008V2C-TF10
K6L1008V2C-RF70
32-SOP, 70ns, 3.3V
32-SOP, 100ns, 3.3V
32-TSOP F, 70ns, 3.3V
32-TSOP F, 100ns, 3.3V
32-TSOP R, 70ns, 3.3V
32-SOP, 100ns, 3.3V
32-TSOP F, 70ns, 3.3V
32-TSOP F, 100ns, 3.3V
32-TSOP R, 70ns, 3.3V
32-SOP, 100ns, 3.3V
32-TSOP F, 70ns, 3.3V
32-TSOP F, 100ns, 3.3V
32-TSOP R, 70ns, 3.3V
32-TSOP R, 100ns, 3.3V
32-TSOP R, 100ns, 3.3V K6L1008V2C-RD10
32-TSOP R, 100ns, 3.3V K6L1008V2C-RF10
K6L1008U2C-GB85
K6L1008U2C-GB10
K6L1008U2C-TB85
K6L1008U2C-TB10
K6L1008U2C-RB85
K6L1008U2C-RB10
32-SOP, 85ns, 3.0V
K6L1008U2C-GD85
K6L1008U2C-GD10
K6L1008U2C-TD85
K6L1008U2C-TD10
K6L1008U2C-RD85
32-SOP, 85ns, 3.0V
K6L1008U2C-GF85
K6L1008U2C-GF10
K6L1008U2C-TF85
K6L1008U2C-TF10
K6L1008U2C-RF85
32-SOP, 85ns, 3.0V
32-SOP, 100ns, 3.0V
32-TSOP F, 85ns, 3.0V
32-TSOP F, 100ns, 3.0V
32-TSOP R, 85ns, 3.0V
32-SOP, 100ns, 3.0V
32-TSOP F, 85ns, 3.0V
32-TSOP F, 100ns, 3.0V
32-TSOP R, 85ns, 3.0V
32-SOP, 100ns, 3.0V
32-TSOP F, 85ns, 3.0V
32-TSOP F, 100ns, 3.0V
32-TSOP R, 85ns, 3.0V
32-TSOP R, 100ns, 3.0V
32-TSOP R, 100ns, 3.0V K6L1008U2C-RD10
32-TSOP R, 100ns, 3.0V K6L1008U2C-RF10
K6L1008V2C-YB70
K6L1008V2C-YB10
K6L1008V2C-NB70
K6L1008V2C-NB10
32-sTSOP F, 70ns, 3.3V
32-sTSOP F, 100ns, 3.3V K6L1008V2C-YD10
32-sTSOP R, 70ns, 3.3V K6L1008V2C-ND70
32-sTSOP R, 100ns, 3.3V K6L1008V2C-ND10
K6L1008V2C-YD70
32-sTSOP F, 70ns, 3.3V K6L1008V2C-YF70
32-sTSOP F, 70ns, 3.3V
32-sTSOP F, 100ns, 3.3V
32-sTSOP R, 70ns, 3.3V
32-sTSOP R, 100ns, 3.3V
32-sTSOP F, 100ns, 3.3V K6L1008V2C-YF10
32-sTSOP R, 70ns, 3.3V K6L1008V2C-NF70
32-sTSOP R, 100ns, 3.3V K6L1008V2C-NF10
K6L1008U2C-YB85
K6L1008U2C-YB10
K6L1008U2C-NB85
K6L1008U2C-NB10
32-sTSOP F, 85ns, 3.0V
32-sTSOP F, 100ns, 3.0V K6L1008U2C-YD10
32-sTSOP R, 85ns, 3.0V K6L1008U2C-ND85
32-sTSOP R, 100ns, 3.0V K6L1008U2C-ND10
K6L1008U2C-YD85
32-sTSOP F, 85ns, 3.0V
K6L1008U2C-YF85
32-sTSOP F, 85ns, 3.0V
32-sTSOP F, 100ns, 3.0V
32-sTSOP R, 85ns, 3.0V
32-sTSOP R, 100ns, 3.0V
32-sTSOP F, 100ns, 3.0V K6L1008U2C-YF10
32-sTSOP R, 85ns, 3.0V K6L1008U2C-NF85
32-sTSOP R, 100ns, 3.0V K6L1008U2C-NF10
FUNCTIONAL DESCRIPTION
CS1
H
CS2
X1)
L
OE
X1)
X1)
H
WE
X1)
X1)
H
I/O Pin
High-Z
High-Z
High-Z
Dout
Mode
Deselected
Deselected
Output Disabled
Read
Power
Standby
Standby
Active
X1)
L
H
L
H
L
H
Active
X1)
L
H
L
Din
Write
Active
1. X means don¢t care(Must be in high or low status.)
ABSOLUTE MAXIMUM RATINGS1)
Item
Symbol
VIN,VOUT
VCC
Ratings
Unit
Remark
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to
Power Dissipation
-0.5 to VCC+0.5
-0.3 to 4.6
V
V
-
-
PD
1.0
W
°C
°C
°C
°C
-
-
Storage temperature
TSTG
-65 to 150
-
0 to 70
K6L1008V2C-L/K6L1008U2C-L
K6L1008V2C-N/K6L1008U2C-N
K6L1008V2C-P/K6L1008U2C-P
-
Operating Temperature
TA
-25 to 85
-40 to 85
Soldering temperature and time
TSOLDER
260°C, 10sec (Lead Only)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Revision 2.0
November 1997
3
K6L1008V2C, K6L1008U2C Family
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Symbol
Product
Min
Typ
Max
Unit
K6L1008V2C Family
K6L1008U2C Family
3.0
2.7
3.3
3.0
3.6
3.3
Supply voltage
Vcc
V
Ground
Vss
VIH
VIL
All Family
0
0
-
0
V
V
V
Vcc+0.32)
0.6
Input high voltage
Input low voltage
K6L1008V2C, K6L1008U2C Family
K6L1008V2C, K6L1008U2C Family
2.2
-0.33)
-
1. Commercial Product: TA=0 to 70°C, unless otherwise specified
Extended Product: TA=-25 to 85°C, unless otherwise specified
Industrial Product: TA=-40 to 85°C, unless otherwise specified
2. Overshoot: VCC+3.0V in case of pulse width £30ns
3. Undershoot: -3.0V in case of pulse width £30ns
4. Overshoot and undershoot is sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Item
Input capacitance
Symbol
CIN
Test Condition
VIN=0V
Min
Max
Unit
-
-
6
8
pF
pF
Input/Output capacitance
CIO
VIO=0V
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Item
Symbol
ILI
Min Typ Max Unit
Test Conditions
Input leakage current
Output leakage current
Operating power supply
VIN=Vss to Vcc
-1
-1
-
-
-
1
1
mA
mA
ILO
CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc
IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIL or VIH, Read
ICC
2
5
mA
Read
Write
-
1.5
10
25
-
5
Cycle time=1ms, 100% duty, IIO=0mA,
CS1£0.2V, CS2³ VCC-0.2V, VIN£0.2V or VIN³ VCC-0.2V
ICC1
mA
Average operating current
15
35
0.4
-
Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIL or VIH
IOL=2.1mA
ICC2
VOL
VOH
ISB
-
mA
V
Output low voltage
-
2.2
-
Output high voltage
Standby Current(TTL)
Standby Current(CMOS)
IOH=-1.0mA
-
V
CS1=VIH, CS2=VIL, Other inputs=VIL or VIH
CS1³ Vcc-0.2V, CS2³ Vcc-0.2V or CS2£0.2V, Other inputs=0~Vcc
-
0.3
mA
mA
ISB1
-
0.3
10
Revision 2.0
November 1997
4
K6L1008V2C, K6L1008U2C Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
1)
CL
Input and output reference voltage:1.5V
Output load(see right): CL=100pF+1TTL
1. Including scope and jig capacitance
AC CHARACTERISTICS (Commercial product:TA=0 to 70°C, Extended product:TA=-25 to 85°C, Industrial product: TA=-40 to 85°C
K6L1008V2C Family: Vcc=3.0~3.6V, K6L1008U2C Family: Vcc=2.7~3.3V)
Speed Bins
Parameter List
Symbol
Units
70ns
Max
85ns
Max
100ns
Min
70
-
Min
85
-
Min
Max
Read cycle time
tRC
tAA
-
70
70
35
-
-
85
85
40
-
100
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
100
Chip select to output
tCO1, tCO2
tOE
-
-
-
100
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
-
-
-
50
-
Read
tLZ
10
5
10
5
10
5
tOLZ
tHZ
-
-
-
0
25
25
-
0
25
25
-
0
30
30
-
tOHZ
tOH
0
0
0
10
70
60
0
15
85
70
0
15
100
80
0
tWC
-
-
-
Chip select to end of write
Address set-up time
tCW
-
-
-
tAS
-
-
-
Address valid to end of write
Write pulse width
tAW
60
55
0
-
70
60
0
-
80
70
0
-
tWP
-
-
-
Write
Write recovery time
tWR
-
-
-
Write to output high-Z
tWHZ
tDW
0
25
-
0
30
-
0
30
-
Data to write time overlap
Data hold from write time
End write to output low-Z
30
0
35
0
40
0
tDH
-
-
-
tOW
5
-
5
-
5
-
DATA RETENTION CHARACTERISTICS
Test Condition1)
Item
Symbol
VDR
Min
Typ
Max Unit
1)
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
2.0
-
-
0.3
-
3.6
V
CS1 ³ Vcc-0.2V
IDR
Vcc=3.0V, CS1³ Vcc-0.2V, CS2³ VCC-0.2V, or CS2£0.2V
5
-
mA
tSDR
0
See data retention waveform
ms
tRDR
5
-
-
1. CS1³ Vcc-0.2V, CS2³ VCC-0.2V, or CS2£0.2V
Revision 2.0
November 1997
5
K6L1008V2C, K6L1008U2C Family
CMOS SRAM
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC
Address
tAA
tOH
Data Out
Data Valid
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO1
CS1
tHZ(1,2)
CS2
tCO2
tOE
OE
tOHZ
tOLZ
tLZ
High-Z
Data out
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
Revision 2.0
November 1997
6
K6L1008V2C, K6L1008U2C Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
tCW(2)
tWR(4)
CS1
tAW
CS2
tCW(2)
tWP(1)
WE
tAS(3)
tDW
tDH
Data Valid
Data in
tWHZ
tOW
Data Undefined
Data out
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)
tWC
Address
tCW(2)
tAS(3)
tWR(4)
CS1
tAW
CS2
tWP(1)
WE
tDW
tDH
Data in
Data out
Data Valid
High-Z
High-Z
Revision 2.0
November 1997
7
K6L1008V2C, K6L1008U2C Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)
tWC
Address
CS1
tAS(3)
tCW(2)
tWR(4)
tAW
CS2
tCW(2)
tWP(1)
WE
tDH
tDW
Data in
Data Valid
High-Z
High-Z
Data out
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,
CS2 going high and WE going low: A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,
tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR(1) applied in case a write ends as CS1 or WE going high tWR(2)
applied in case a write ends as CS2 going to low.
DATA RETENTION WAVE FORM
CS1 controlled
Data Retention Mode
tSDR
tRDR
VCC
3.0/2.7V1)
2.2V
VDR
CS1³ VCC-0.2V
CS1
GND
CS2 controlled
Data Retention Mode
VCC
3.0/2.7V1)
CS2
tSDR
tRDR
VDR
CS2£0.2V
0.4V
GND
1. 3.0V for K6L1008V2C Family, 2.7V for K6L1008U2C Family
Revision 2.0
November 1997
8
K6L1008V2C, K6L1008U2C Family
CMOS SRAM
PACKAGE DIMENSIONS
Units: millimeter(inch)
32 PIN PLASTIC SMALL OUTLINE PACKAGE (525mil)
0~8°
#32
#17
14.12±0.30
0.556±0.012
11.43±0.20
0.450±0.008
#1
#16
0.80±0.20
0.031±0.008
+0.10
-0.05
0.20
2.74±0.20
20.87
0.822
MAX
0.108±0.008
+0.004
0.008
-0.002
3.00
MAX
0.118
20.47±0.20
0.806±0.008
0.10 MAX
0.004 MAX
+0.100
-0.050
0.41
0.71
0.028
1.27
0.050
+0.004
-0.002
(
)
0.05
0.002
0.016
MIN
Revision 2.0
November 1997
9
K6L1008V2C, K6L1008U2C Family
CMOS SRAM
Units: millimeter(inch)
PACKAGE DIMENSIONS
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)
13.40±0.20
0.528±0.008
+0.10
-0.05
+0.004
-0.002
0.20
0.008
#1
#32
0.25
0.010
(
)
0.50
0.0197
#16
#17
1.00±0.10
0.039±0.004
0.25
0.010
0.05
0.002
MIN
TYP
11.80±0.10
0.465±0.004
+0.10
-0.05
+0.004
-0.002
0.15
1.20
MAX
0.047
0.006
0~8°
0.50
0.020
0.45~0.75
0.018~0.030
(
)
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4R)
13.40±0.20
0.528±0.008
+0.10
-0.05
+0.004
-0.002
0.20
0.008
#16
#17
0.25
0.010
(
)
0.50
0.0197
#1
#32
1.00±0.10
0.039±0.004
0.25
0.010
0.05
0.002
TYP
11.80±0.10
0.465±0.004
MIN
+0.10
-0.05
+0.004
-0.002
0.15
1.20
MAX
0.047
0.006
0~8°
0.50
0.020
0.45~0.75
0.018~0.030
(
)
Revision 2.0
November 1997
10
K6L1008V2C, K6L1008U2C Family
CMOS SRAM
Units: millimeter(inch)
PACKAGE DIMENSIONS
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)
+0.10
-0.05
+0.004
20.00±0.20
0.787±0.008
0.20
0.008
-0.002
#1
#32
0.25
0.010
(
)
8.40
0.331
MAX
0.50
0.0197
#17
#16
1.00±0.10
0.039±0.004
0.05
0.002
MIN
1.20
MAX
0.047
0.25
0.010
18.40±0.10
0.724±0.004
TYP
+0.10
0.15
-0.05
+0.004
0.006
-0.002
0~8°
0.50
0.020
0.45 ~0.75
0.018 ~0.030
(
)
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820R)
+0.10
-0.05
20.00±0.20
0.787±0.008
0.20
+0.004
-0.002
0.008
#16
#17
0.25
0.010
(
)
0.50
0.0197
#1
#32
1.00±0.10
0.039±0.004
0.05
0.002
MIN
1.20
MAX
0.047
18.40±0.10
0.724±0.004
0.25
0.010
TYP
+0.10
-0.05
0.15
+0.004
-0.002
0.006
0~8°
0.50
0.020
0.45 ~0.75
0.018 ~0.030
(
)
Revision 2.0
November 1997
11
相关型号：
K6L1008U2C-ND10
Standard SRAM, 128KX8, 100ns, CMOS, PDSO32, 8 X 13.40 MM, REVERSE, STSOP1-32
SAMSUNG
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