K4S643232F-TP70_技术文档

K4S643232F-TI/P

CMOS SDRAM

2M x 32 SDRAM

512K x 32bit x 4 Banks

Synchronous DRAM

LVTTL(3.3V)

Industrial Temperature

86-TSOP

Revision 1.0

January 2002

Samsung Electronics reserves the right to change products or specification without notice.

Rev. 1.0 (Jan. 2002)

- 1 -

K4S643232F-TI/P

CMOS SDRAM

Revision History

Revision 1.0 (January 16, 2001)

• Defined DC spec.

Revision 0.0 (December 28, 2001)

• Initial draft

• Industrial Temperature (-40°c ~ 85°c )

Rev. 1.0 (Jan. 2002)

- 2 -

K4S643232F-TI/P

CMOS SDRAM

512K x 32Bit x 4 Banks Synchronous DRAM

FEATURES

GENERAL DESCRIPTION

• 3.3V power supply

The K4S643232F is 67,108,864 bits synchronous high data

rate Dynamic RAM organized as 4 x 524,288 words by 32 bits,

fabricated with SAMSUNG¢s high performance CMOS technol-

ogy. Synchronous design allows precise cycle control with the

use of system clock. I/O transactions are possible on every

clock cycle. Range of operating frequencies, programmable

burst length and programmable latencies allow the same device

to be useful for a variety of high bandwidth, high performance

memory system applications.

• LVTTL compatible with multiplexed address

• Four banks operation

• MRS cycle with address key programs

-. CAS latency ( 2 & 3)

-. Burst length (1, 2, 4, 8 & Full page)

-. Burst type (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the system

clock

• Burst read single-bit write operation

• DQM for masking

ORDERING INFORMATION

• Auto & self refresh

Part NO.

Max Freq.

166MHz

143MHz

Interface Package

• 15.6us refresh duty cycle(4K/64ms)

K4S643232F-TI/P60

K4S643232F-TI/P70

86

LVTTL

• Industrial Temperature range : -40°c ~ 85°c

TSOP(II)

* -I/P : Industrial temperature (-40°c to + 85°c)

FUNCTIONAL BLOCK DIAGRAM

LWE

Data Input Register

LDQM

Bank Select

512K x 32

DQi

CLK

ADD

Column Decoder

Latency & Burst Length

LCKE

Programming Register

LRAS

LCBR

LWE

LCAS

LWCBR

LDQM

Timing Register

CLK

CKE

CS

RAS

CAS

WE

DQM

Samsung Electronics reserves the right to

change products or specification without

notice.

*

Rev. 1.0 (Jan. 2002)

- 3 -

K4S643232F-TI/P

CMOS SDRAM

PIN CONFIGURATION (Top view)

VDD

DQ0

VDDQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VDDQ

DQ5

DQ6

VSSQ

DQ7

N.C

VDD

DQM0

WE

CAS

RAS

CS

1

2

3

4

5

6

7

8

VSS

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VDDQ

DQ8

N.C

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

VSS

DQM1

N.C

CLK

CKE

A9

A8

A7

A6

A5

A4

A3

N.C

BA0

BA1

A10/AP

A0

A1

A2

DQM2

VDD

N.C

DQM3

VSS

N.C

DQ16

VSSQ

DQ17

DQ18

VDDQ

DQ19

DQ20

VSSQ

DQ21

DQ22

VDDQ

DQ23

VDD

DQ31

VDDQ

DQ30

DQ29

VSSQ

DQ28

DQ27

VDDQ

DQ26

DQ25

VSSQ

DQ24

VSS

86Pin TSOP (II)

(400mil x 875mil)

(0.5 mm Pin pitch)

Rev. 1.0 (Jan. 2002)

- 4 -

K4S643232F-TI/P

CMOS SDRAM

PIN FUNCTION DESCRIPTION

Name

System clock

Input Function

CLK

Active on the positive going edge to sample all inputs.

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM.

CS

Chip select

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disables input buffers for power down mode.

CKE

Clock enable

Row/column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA10, Column address : CA0 ~ CA7

A0 ~ A10

BA0,1

RAS

Address

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

Bank select address

Row address strobe

Column address strobe

Write enable

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

CAS

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

WE

Makes data output Hi-Z, tSHZ after the clock and masks the output.

Blocks data input when DQM active.

DQM0 ~ 3

Data input/output mask

DQ0 ~ 31

VDD/VSS

Data input/output

Data inputs/outputs are multiplexed on the same pins.

Power and ground for the input buffers and the core logic.

Power supply/ground

Isolated power supply and ground for the output buffers to provide improved noise

immunity.

VDDQ/VSSQ

NC

Data output power/ground

No Connection

This pin is recommended to be left No connection on the device.

Rev. 1.0 (Jan. 2002)

- 5 -

K4S643232F-TI/P

CMOS SDRAM

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to Vss

Voltage on VDD supply relative to Vss

Storage temperature

Symbol

VIN, VOUT

VDD, VDDQ

TSTG

Value

-1.0 ~ 4.6

-55 ~ +150

1

Unit

V

°C

W

Power dissipation

PD

Short circuit current

IOS

50

mA

Note :

Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -40°C to 85°C)

Parameter

Supply voltage

Symbol

VDD, VDDQ

VIH

Min

3.0

2.0

-0.3

2.4

-

Typ

Max

Unit

V

Note

3.3

3.6

Input logic high voltage

Input logic low voltage

Output logic high voltage

Output logic low voltage

Input leakage current

3.0

VDDQ+0.3

V

1

VIL

0

-

0.8

-

V

2

VOH

V

IOH = -2mA

IOL = 2mA

3

VOL

-

0.4

10

V

ILI

-10

-

uA

Notes :

1. VIH (max) = 5.6V AC.The overshoot voltage duration is £ 3ns.

2. VIL (min) = -2.0V AC. The undershoot voltage duration is £ 3ns.

3. Any input 0V £ VIN £ VDDQ,

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

4. The VDD condition of K4S643232F-60 is 3.135V ~ 3.6V

CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV)

Symbol

CCLK

CIN

Min

Max

4

Unit

pF

Clock

-

RAS, CAS, WE, CS, CKE, DQM

Address

4.5

6.5

pF

CADD

COUT

pF

DQ0 ~ DQ31

pF

Rev. 1.0 (Jan. 2002)

- 6 -

K4S643232F-TI/P

CMOS SDRAM

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, TA = -40°C to 85°C, VIH(min)/VIL(max)=2.0V/0.8V)

Speed

CAS

Latency

Parameter

Symbol

Test Condition

Unit Note

-60

-70

3

2

130

Operating Current

(One Bank Active)

Burst Length =1

ICC1

mA

2

tRC ³ tRC(min), tCC ³ tCC(min), Io = 0mA

110

ICC2P

CKE £ VIL(max), tCC = 15ns

2

Precharge Standby Current in

power-down mode

ICC2PS

CKE & CLK £ VIL(max), tCC = ¥

CKE ³ VIH(min), CS ³ VIH(min), tCC = 15ns

12

ICC2N

Input signals are changed one time during 30ns

Precharge Standby Current

in non power-down mode

mA

CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥

Input signals are stable

7

ICC2NS

ICC3P

CKE £ VIL(max), tCC = 15ns

CKE £ VIL(max), tCC = ¥

4

Active Standby Current

in power-down mode

ICC3PS

CKE ³ VIH(min), CS ³ VIH(min), tCC = 15ns

Input signals are changed one time during 30ns

40

ICC3N

Active Standby Current

in non power-down mode

(One Bank Active)

CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥

Input signals are stable

35

ICC3NS

3

2

3

2

150

140

120

Operating Current

(Burst Mode)

Io = 0 mA, Page Burst

All bank Activated, tCCD = tCCD(min)

ICC4

ICC5

ICC6

mA

2

3

120

Refresh Current

tRC ³ tRC(min)

CKE £ 0.2V

120

2

mA

uA

4

5

Self Refresh Current

450

Notes :

1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL.

2. Measured with outputs open.

3. Refresh period is 64ms.

4. K4S643232F-TI**

5. K4S643232F-TP**

Rev. 1.0 (Jan. 2002)

- 7 -

K4S643232F-TI/P

CMOS SDRAM

AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = -40°C to 85°C)

Parameter

AC input levels (Vih/Vil)

Value

2.4/0.4

1.4

Unit

V

Input timing measurement reference level

Input rise and fall time

V

tr/tf = 1/1

1.4

ns

V

Output timing measurement reference level

Output load condition

See Fig. 2

3.3V

Vtt = 1.4V

1200W

50W

VOH (DC) = 2.4V, IOH = -2mA

VOL (DC) = 0.4V, IOL = 2mA

Output

Z0 = 50W

30pF

870W

(Fig. 1) DC output load circuit

(Fig. 2) AC output load circuit

1. The VDD condition of K4S643232F-60 is 3.135V ~ 3.6V

Notes :

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Version

Parameter

CAS Latency

Symbol

Unit Note

-60

-70

CL

3

6

2

3

7

2

CLK

ns

CLK cycle time

tCC(min)

10

2

Row active to row active delay

tRRD(min)

CLK

1

RAS to CAS delay

Row precharge time

tRCD(min)

tRP(min)

3

7

2

5

3

7

2

5

CLK

1

tRAS(min)

Row active time

Row cycle time

100

tRAS(max)

tRC(min)

us

10

7

10

7

CLK

1

Last data in to row precharge

Last data in to new col.address delay

Last data in to burst stop

tRDL(min)

tCDL(min)

tBDL(min)

tCCD(min)

tMRS(min)

2

1

2

1

CLK

2

3

Col. address to col. address delay

Mode Register Set cycle time

CAS Latency=3

CAS Latency=2

Number of valid

output data

ea

4

Note :

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then

rounding off to the next higher integer. Refer to the following ns-unit based AC table.

Rev. 1.0 (Jan. 2002)

- 8 -

K4S643232F-TI/P

CMOS SDRAM

Version

Parameter

Symbol

Unit

-60

12

18

42

-70

14

20

49

Row active to row active delay tRRD(min)

ns

us

ns

RAS to CAS delay

Row precharge time

tRCD(min)

tRP(min)

tRAS(min)

tRAS(max)

tRC(min)

Row active time

Row cycle time

100

60

70

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

-60

-70

Parameter

Symbol

tCC

Unit Note

Max

Min

6

Max

Min

CAS Latency=3

7

10

-

CLK cycle time

1000

ns

1

CAS Latency=2

CAS Latency=3

CAS Latency=2

10

-

5.5

CLK to valid

output delay

tSAC

1, 2

-

6

-

6

Output data hold time

tOH

tCH

2

-

2

-

ns

2

3

CAS Latency=3

CAS Latency=2

CAS Latency=3

CAS Latency=2

CAS Latency=3

CAS Latency=2

2.5

3

-

3

-

CLK high pulse

width

-

3

-

2.5

3

-

3

-

CLK low

pulse width

tCL

tSS

ns

3

1.5

2.5

1

-

1.75

2.5

1

-

Input setup time

-

Input hold time

tSH

-

ns

3

2

CLK to output in Low-Z

tSLZ

1

-

1

-

CAS latency=3

CAS latency=2

-

5.5

6

-

5.5

6

CLK to output

in Hi-Z

tSHZ

ns

-

Note :

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf)=1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]ns should be added to the parameter.

Rev. 1.0 (Jan. 2002)

- 9 -

K4S643232F-TI/P

CMOS SDRAM

SIMPLIFIED TRUTH TABLE

,

Command

CKEn-1 CKEn

CS

RAS

CAS

WE

DQM BA0,1

A10/AP

Note

A9 ~ A0

Register

Refresh

Mode register set

Auto refresh

H

X

H

L

X

OP code

1,2

3

L

H

X

Entry

3

Self

L

H

L

H

X

L

H

X

H

X

H

3

refresh

Exit

L

H

3

Bank active & row addr.

H

X

V

Row address

Column

address

(A0 ~ A7)

Read &

column address

Auto precharge disable

Auto precharge enable

Auto precharge disable

Auto precharge enable

L

H

L

4

4,5

4

L

H

L

H

L

Column

address

(A0 ~ A7)

Write &

column address

H

X

V

H

X

L

4,5

6

Burst Stop

Precharge

H

X

L

H

L

H

L

X

Bank selection

All banks

V

X

H

L

X

V

X

H

X

V

X

V

X

H

X

V

X

V

X

H

X

V

Entry

H

L

X

Clock suspend or

active power down

X

Exit

L

H

L

X

H

L

X

Entry

H

Precharge power down mode

H

L

Exit

L

H

X

DQM

H

V

X

7

H

L

X

H

X

H

X

H

No operation command

(V=Valid, X=Don¢t care, H=Logic high, L=Logic low)

Notes :

1. OP Code : Operand code

A0 ~ A10 & BA0 ~ BA1 : Program keys. (@ MRS)

2. MRS can be issued only at all banks precharge state.

A new command can be issued after 2 CLK cycles of MRS.

3. Auto refresh functions are as same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

4. BA0 ~ BA1 : Bank select addresses.

If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.

If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.

If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.

If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.

If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst.

6. Burst stop command is valid at every burst length.

7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),

but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

Rev. 1.0 (Jan. 2002)

- 10

K4S643232F-TI/P

CMOS SDRAM

MODE REGISTER FIELD TABLE TO PROGRAM MODES

Register Programmed with MRS

BA0 ~ BA1

RFU

A10/AP

RFU

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

Address

Function

W.B.L

TM

CAS Latency

BT

Burst Length

Test Mode

CAS Latency

Burst Type

Burst Length

A8

0

A7

0

Type

Mode Register Set

Reserved

A6

A5

0

A4

0

Latency

Reserved

2

A3

0

Type

A2

A1 A0

BT = 0

BT = 1

0

1

Sequential

Interleave

1

2

4

8

1

2

4

8

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Reserved

1

3

1

Reserved

0

Reserved

Reserved Reserved

Full Page Reserved

Write Burst Length

Length

0

1

A9

0

1

0

Burst

1

Single Bit

Full Page Length : x32 (256)

POWER UP SEQUENCE

SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

1. Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.

2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.

3. Issue precharge commands for all banks of the devices.

4. Issue 2 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode register.

cf.) Sequence of 4 & 5 is regardless of the order.

The device is now ready for normal operation.

Note : 1. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.

2. RFU (Reserved for future use) should stay "0" during MRS cycle.

Rev. 1.0 (Jan. 2002)

- 11

K4S643232F-TI/P

CMOS SDRAM

BURST SEQUENCE (BURST LENGTH = 4)

Initial Address

Sequential

Interleave

A1

A0

0

1

0

1

0

1

0

1

2

3

1

2

3

0

2

3

0

1

3

0

1

2

0

1

2

3

1

0

3

2

3

0

1

3

2

1

0

BURST SEQUENCE (BURST LENGTH = 8)

Initial Address

Sequential

Interleave

A2

A1

A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

1

2

3

4

5

6

7

0

2

3

4

5

6

7

0

1

3

4

5

6

7

0

1

2

4

5

6

7

0

1

2

3

5

6

7

0

1

2

3

4

6

7

0

1

2

3

4

5

7

0

1

2

3

4

5

6

0

1

2

3

4

5

6

7

1

0

3

2

5

4

7

6

2

3

0

1

6

7

4

5

3

2

1

0

7

6

5

4

5

6

7

0

1

2

3

5

4

7

6

1

0

3

2

6

7

4

5

2

3

0

1

7

6

5

4

3

2

1

0

Rev. 1.0 (Jan. 2002)

- 12


型号：	K4S643232F-TP70
厂家：	SAMSUNG
描述：	2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL3.3V 2M ×32 SDRAM 512K X 32位×4银行同步DRAM LVTTL3.3V 存储内存集成电路光电二极管动态存储器时钟
文件：	总12页 (文件大小：101K)
中文：	中文翻译
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K4S643232F-TP70 [SAMSUNG]

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