K4S643232H-TC/L50 [SAMSUNG]
64Mb H-die (x32) SDRAM Specification; 64MB H-模具（ X32 ） SDRAM规格
| 型号： | K4S643232H-TC/L50 |
| 厂家： | 
SAMSUNG |
| 描述： | 64Mb H-die (x32) SDRAM Specification |
| 文件： | 总12页 (文件大小：120K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SDRAM 64Mb H-die (x32)
CMOS SDRAM
64Mb H-die (x32) SDRAM Specification
Revision 1.4
August 2004
*Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.4 August 2004
- 1 -
SDRAM 64Mb H-die (x32)
CMOS SDRAM
Revision History
Revision 0.0 (June, 2003)
- Target spec First release.
Revision 0.1 (July, 2003)
- Delete speed 4.5ns.
Revision 0.2 (September, 2003)
- Preliminary spec release.
Revision 1.0 (November, 2003)
- Final spec release.
Revision 1.1 (December, 2003)
- Corrected typo.
Revision 1.2 (December, 2003)
- Modified load cap 50pF -> 30pF & Typo.
Revision 1.3 (February, 2004)
- Corrected typo.
Revision 1.4 (August, 2004)
- Corrected typo.
Rev. 1.4 August 2004
- 2 -
SDRAM 64Mb H-die (x32)
CMOS SDRAM
512K x 32Bit x 4 Banks SDRAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period(4K Cycle)
GENERAL DESCRIPTION
The K4S643232H is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits, fabricated
with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock.
I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable
latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
Ordering Information
Part No.
Orgainization
Max Freq.
Interface
Package
K4S643232H-TC/L70
K4S643232H-TC/L60
K4S643232H-TC/L55
K4S643232H-TC/L50
143MHz(CL=3)
166MHz(CL=3)
183MHz(CL=3)
200MHz(CL=3)
2Mb x 32
LVTTL
86pin TSOP(II)
Organization
2Mx32
Row Address
A0~A10
Column Address
A0-A7
Row & Column address configuration
Rev. 1.4 August 2004
- 3 -
SDRAM 64Mb H-die (x32)
CMOS SDRAM
Package Physical Dimension
0~8°C
0.25
0.010
TYP
#86
#44
#1
#43
+0.075
-0.035
+0.003
-0.001
0.125
0.005
22.62
0.891
MAX
22.22
0.875
± 0.10
0.21 ± 0.05
1.00 ± 0.10
1.20
0.047
MAX
± 0.004
± 0.002
± 0.004
0.008
0.039
0.10
0.004
MAX
0.05
0.002
+0.07
MIN
0.20
0.50
0.0197
0.61
0.024
-0.03
(
)
+0.003
0.0079
-0.001
86Pin TSOP(II) Package Dimension
Rev. 1.4 August 2004
- 4 -
SDRAM 64Mb H-die (x32)
CMOS SDRAM
FUNCTIONAL BLOCK DIAGRAM
LWE
Data Input Register
LDQM
Bank Select
512K x 32
512K x 32
512K x 32
512K x 32
DQi
CLK
ADD
Column Decoder
Latency & Burst Length
LCKE
Programming Register
LWCBR
LDQM
LRAS
LCBR
LWE
LCAS
Timing Register
CLK
CKE
CS
RAS
CAS
WE
DQM
Rev. 1.4 August 2004
- 5 -
SDRAM 64Mb H-die (x32)
CMOS SDRAM
PIN CONFIGURATION (Top view)
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5 10
DQ6 11
VSSQ
DQ7 13
N.C
VDD
DQM0
WE
CAS 18
RAS 19
CS
N.C
BA0
BA1
1
2
3
4
5
6
7
8
9
VSS
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
N.C
12
14
15
16
17
VSS
DQM1
N.C
N.C
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
20
21
22
23
A10/AP 24
A0
A1
A2
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
DQM2
VDD
N.C
DQM3
VSS
N.C
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS
86Pin TSOP (II)
(400mil x 875mil)
(0.5 mm Pin pitch)
Rev. 1.4 August 2004
- 6 -
SDRAM 64Mb H-die (x32)
CMOS SDRAM
PIN FUNCTION DESCRIPTION
Pin
Name
System clock
Input Function
CLK
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM.
CS
Chip select
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disables input buffers for power down mode.
CKE
Clock enable
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, Column address : CA0 ~ CA7
A0 ~ A10
BA0,1
RAS
Address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Bank select address
Row address strobe
Column address strobe
Write enable
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
CAS
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
WE
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
DQM0 ~ 3
Data input/output mask
DQ0 ~ 31
VDD/VSS
Data input/output
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Power supply/ground
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
VDDQ/VSSQ
NC
Data output power/ground
No Connection
This pin is recommended to be left No connection on the device.
Rev. 1.4 August 2004
- 7 -
SDRAM 64Mb H-die (x32)
CMOS SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Symbol
VIN, VOUT
VDD, VDDQ
TSTG
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
Unit
V
V
°C
W
Power dissipation
PD
Short circuit current
IOS
50
mA
Note :
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter
Supply voltage
Symbol
VDD, VDDQ
VIH
Min
3.0
2.0
-0.3
2.4
-
Typ
3.3
3.0
0
Max
Unit
V
Note
3.6
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
VDDQ+0.3
V
1
VIL
0.8
-
V
2
VOH
-
V
IOH = -2mA
IOL = 2mA
3
VOL
-
0.4
10
V
ILI
-10
-
uA
Notes :
1. VIH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ,
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV)
Pin
Symbol
CCLK
CIN
Min
Max
4
Unit
pF
Clock
-
-
-
-
RAS, CAS, WE, CS, CKE, DQM
Address
4.5
4.5
6.5
pF
CADD
COUT
pF
DQ0 ~ DQ31
pF
Rev. 1.4 August 2004
- 8 -
SDRAM 64Mb H-die (x32)
CMOS SDRAM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C
Speed
CAS
Latency
Parameter
Symbol
Test Condition
Unit Note
50
55
60
70
3
2
140
140
130
130
Operating Current
(One Bank Active)
Burst Length =1
ICC1
mA
mA
2
tRC ≥ tRC(min), tCC ≥ tCC(min), Io = 0mA
110
2
ICC2P
CKE ≤ VIL(max), tCC = 10ns
Precharge Standby Current in
power-down mode
ICC2PS
CKE & CLK ≤ VIL(max), tCC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
2
ICC2N
12
7
Input signals are changed one time during 30ns
Precharge Standby Current
in non power-down mode
mA
mA
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
ICC2NS
ICC3P
CKE ≤ VIL(max), tCC = 10ns
CKE ≤ VIL(max), tCC = ∞
4
4
Active Standby Current
in power-down mode
ICC3PS
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 30ns
ICC3N
40
35
Active Standby Current
in non power-down mode
(One Bank Active)
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
ICC3NS
3
2
170
150
160
150
150
140
140
120
Operating Current
(Burst Mode)
Io = 0 mA, Page Burst
All bank Activated, tCCD = tCCD(min)
ICC4
ICC5
ICC6
mA
mA
2
3
120
3
Refresh Current
tRC ≥ tRC(min)
CKE ≤ 0.2V
2
120
2
mA
uA
4
5
C
L
Self Refresh Current
450
Notes :
1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL.
2. Measured with outputs open.
3. Refresh period is 64ms.
4. K4S643232H-TC
5. K4S643232H-TL
Rev. 1.4 August 2004
- 9 -
SDRAM 64Mb H-die (x32)
CMOS SDRAM
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
AC input levels (Vih/Vil)
Value
2.4/0.4
1.4
Unit
V
Input timing measurement reference level
Input rise and fall time
V
tr/tf = 1/1
1.4
ns
V
Output timing measurement reference level
Output load condition
See Fig. 2
3.3V
Vtt = 1.4V
1200Ω
50Ω
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
Output
Z0 = 50Ω
30pF
30pF
870Ω
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
50
55
60
70
Parameter
Symbol
Unit
Note
Min
Max
Min
Max
Min
Max
Min
Max
CAS
CAS
5
5.5
6
7
CLK cycle time
tCC
1000
1000
1000
1000
ns
1
10
10
10
10
Row active to row active delay
RAS to CAS delay
tRRD(min)
tRCD(min)
tRP(min)
2
CLK
CLK
CLK
CLK
us
1
1
1
1
3
3
8
2
2
5
3
3
7
2
2
5
3
3
7
2
2
5
3
3
7
2
2
5
Row precharge time
tRAS(min)
tRAS(max)
Row active time
Row cycle time
100
tRC(min)
11
7
10
7
10
7
10
7
CLK
1
Last data in to row precharge
Last data in to new col.address delay
Last data in to burst stop
tRDL(min)
tCDL(min)
tBDL(min)
tCCD(min)
tMRS(min)
2
1
1
1
2
2
1
CLK
CLK
CLK
CLK
CLK
2
2
2
3
Col. address to col. address delay
Mode Register Set cycle time
CAS Latency=3
CAS Latency=2
Number of valid
output data
ea
4
Note :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer. Refer to the following ns-unit based AC table.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Rev. 1.4 August 2004
- 10
SDRAM 64Mb H-die (x32)
CMOS SDRAM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
50
55
60
70
Parameter
Symbol
tCC
Unit Note
Min
5
Max
Min
5.5
10
-
Max
Min
6
Max
Min
Max
CAS Latency=3
7
10
-
CLK cycle time
1000
1000
1000
1000
ns
ns
1
CAS Latency=2
CAS Latency=3
CAS Latency=2
10
-
10
-
4.5
5.0
5.5
5.5
CLK to valid
output delay
tSAC
1, 2
-
6
-
6
-
6
-
6
Output data hold time
tOH
tCH
2
-
2
-
2
-
-
2
-
ns
ns
2
3
CAS Latency=3
CAS Latency=2
CAS Latency=3
CAS Latency=2
CAS Latency=3
CAS Latency=2
2
-
2
-
2.5
3
3
-
CLK high pulse
width
3
-
3
-
-
3
-
2
-
-
2
-
-
2.5
3
-
3
-
-
CLK low
pulse width
tCL
tSS
ns
ns
3
3
3
3
-
3
1.5
2.5
1
-
1.5
2.5
1
-
1.5
2.5
1
-
1.75
2.5
1
-
Input setup time
-
-
-
-
Input hold time
tSH
-
-
-
-
ns
ns
3
2
CLK to output in Low-Z
tSLZ
1
-
1
-
1
-
1
-
CAS latency=3
CAS latency=2
-
4.5
6
-
5.0
6
-
5.5
6
-
5.5
6
CLK to output
in Hi-Z
tSHZ
ns
-
-
-
-
-
Note :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Rev. 1.4 August 2004
- 11
SDRAM 64Mb H-die (x32)
CMOS SDRAM
SIMPLIFIED TRUTH TABLE
A11,
A9 ~ A0
CKEn-1 CKEn
CS
RAS
CAS
WE
DQM BA0,1
A10/AP
Note
Command
Mode register set
Register
Refresh
H
H
X
H
L
L
L
L
L
X
OP code
1,2
3
Auto refresh
L
L
L
H
X
X
X
X
Entry
Exit
3
Self
refresh
L
H
L
H
X
L
H
X
H
H
X
H
3
L
H
3
Bank active & row addr.
H
H
X
X
X
X
V
V
Row address
Read &
column address
Auto precharge disable
Auto precharge enable
Auto precharge disable
Auto precharge enable
L
H
L
4
4,5
4
Column
address
L
L
H
H
L
L
H
L
Write &
column address
Column
address
H
X
X
V
H
4,5
6
Burst Stop
Precharge
H
H
X
X
L
L
H
L
H
H
L
L
X
X
X
Bank selection
All banks
V
X
L
X
H
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
H
L
X
Clock suspend or
active power down
X
X
Exit
L
H
L
X
H
L
X
X
Entry
H
Precharge power down mode
H
L
Exit
L
H
X
X
DQM
H
H
V
X
X
X
7
H
L
X
H
X
H
No operation command
(V=Valid, X=Don′t care, H=Logic high, L=Logic low)
Notes :
1. OP Code : Operand code
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Rev. 1.4 August 2004
- 12
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