K4E661612C-TC60 [SAMSUNG]
4M x 16bit CMOS Dynamic RAM with Extended Data Out; 4M X 16位CMOS动态随机存储器与扩充数据输出
| 型号： | K4E661612C-TC60 |
| 厂家： | 
SAMSUNG |
| 描述： | 4M x 16bit CMOS Dynamic RAM with Extended Data Out |
| 文件： | 总36页 (文件大小：885K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K4E661612C,K4E641612C
CMOS DRAM
4M x 16bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
This is a family of 4,194,304 x 16 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random
access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption(Nor-
mal or Low power) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden
refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 4Mx16 EDO Mode DRAM family is fabricated
using Samsung¢s advanced CMOS process to realize high band-width, low power consumption and high reliability.
FEATURES
• Extended Data Out Mode operation
• 2 CAS Byte/Word Read/Write operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Fast parallel test mode capability
• Self-refresh capability (L-ver only)
• LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Part Identification
- K4E661612C-TC/L(3.3V, 8K Ref.)
- K4E641612C-TC/L(3.3V, 4K Ref.)
• ActivePowerDissipation
Unit : mW
4K
Speed
-45
8K
• Available in Plastic TSOP(II) packages
• +3.3V±0.3V power supply
324
288
252
468
-50
432
-60
396
• Refresh Cycles
FUNCTIONAL BLOCK DIAGRAM
Part
NO.
Refresh
cycle
Refresh time
Normal
L-ver
RAS
UCAS
LCAS
W
K4E661612C*
K4E641612C
8K
4K
Vcc
Vss
64ms
128ms
Control
Clocks
VBB Generator
* Access mode & RAS only refresh mode
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)
CAS-before-RAS & Hidden refresh mode
Lower
Data in
Buffer
DQ0
to
Row Decoder
Refresh Timer
DQ7
Lower
Data out
Buffer
: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)
Refresh Control
Memory Array
OE
4,194,304 x 16
Cells
Refresh Counter
Upper
Data in
Buffer
• Performance Range
DQ8
to
DQ15
Speed
Row Address Buffer
Col. Address Buffer
tRAC
45ns
50ns
60ns
tCAC
12ns
13ns
15ns
tRC
74ns
84ns
104ns
tHPC
17ns
20ns
25ns
A0~A12
(A0~A11)*1
Upper
Data out
Buffer
-45
-50
-60
A0~A8
(A0~A9)*1
Column Decoder
Note) *1 : 4K Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
K4E661612C,K4E641612C
CMOS DRAM
PIN CONFIGURATION (Top Views)
• K4E661612C-T
• K4E641612C-T
1
2
3
4
5
6
7
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
VCC
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
N.C
VCC
W
RAS
N.C
N.C
N.C
N.C
A0
VSS
DQ15
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
N.C
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VSS
LCAS
UCAS
OE
N.C
N.C
A12(N.C)*
A11
A10
A9
A8
A1
A2
A3
A4
A5
VCC
A7
A6
VSS
26
(400mil TSOP(II))
*(N.C) : N.C for 4K Refresh Product
Pin Name
Pin function
A0 - A12
A0 - A11
DQ0 - 15
VSS
Address Inputs(8K Product)
Address Inputs(4K Product)
Data In/Out
Ground
RAS
Row Address Strobe
Upper Column Address Strobe
Lower Column Address Strobe
Read/Write Input
UCAS
LCAS
W
OE
Data Output Enable
Power(+3.3V)
VCC
N.C
No Connection
K4E661612C,K4E641612C
CMOS DRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
VIN,VOUT
VCC
Rating
-0.5 to +4.6
-0.5 to +4.6
-55 to +150
1
Units
V
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Storage Temperature
V
Tstg
°C
W
Power Dissipation
PD
Short Circuit Output Current
IOS Address
50
mA
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)
Parameter
Supply Voltage
Symbol
VCC
VSS
Min
3.0
0
Typ
Max
3.6
0
Units
3.3
V
V
V
V
Ground
0
-
*1
Input High Voltage
Input Low Voltage
VIH
2.0
Vcc+0.3
0.8
*2
VIL
-
-0.3
*1 : Vcc+1.3V at pulse width£15ns which is measured at VCC
*2 : -1.3 at pulse width£15ns which is measured at VSS
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Parameter
Symbol
Min
Max
Units
Input Leakage Current (Any input 0£VIN£VCC+0.3V,
all other pins not under test=0 Volt)
II(L)
-5
5
uA
Output Leakage Current
(Data out is disabled, 0V£VOUT£VCC)
IO(L)
-5
5
uA
Output High Voltage Level(IOH=-2mA)
Output Low Voltage Level(IOL=2mA)
VOH
VOL
2.4
-
-
V
V
0.4
K4E661612C,K4E641612C
CMOS DRAM
DC AND OPERATING CHARACTERISTICS (Continued)
Max
Symbol
Power
Speed
Units
K4E661612C
K4E641612C
-45
-50
-60
90
80
70
130
120
110
mA
mA
mA
ICC1
ICC2
ICC3
Don¢t care
Normal
L
1
1
1
1
mA
mA
Don¢t care
-45
-50
-60
90
80
70
130
120
110
mA
mA
mA
Don¢t care
Don¢t care
-45
-50
-60
100
90
80
100
90
80
mA
mA
mA
ICC4
ICC5
ICC6
Normal
L
0.5
200
0.5
200
mA
uA
Don¢t care
-45
-50
-60
130
120
110
130
120
110
mA
mA
mA
Don¢t care
ICC7
ICCS
L
L
Don¢t care
Don¢t care
350
350
350
350
uA
uA
ICC1* : Operating Current (RAS and UCAS, LCAS, Address cycling @tRC=min.)
ICC2 : Standby Current (RAS=UCAS=LCAS=W=VIH)
ICC3* : RAS-only Refresh Current (UCAS=LCAS=VIH, RAS, Address cycling @tRC=min.)
ICC4* : Extended Data Out Mode Current (RAS=VIL, UCAS or LCAS, Address cycling @tHPC=min.)
ICC5 : Standby Current (RAS=UCAS=LCAS=W=VCC-0.2V)
ICC6* : CAS-Before-RAS Refresh Current (RAS and UCAS or LCAS cycling @tRC=min)
ICC7 : Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, UCAS, LCAS=CAS-before-RAS cycling or 0.2V
W, OE=VIH, Address=Don¢t care, DQ=Open, TRC=31.25us
ICCS : Self Refresh Current
RAS=UCAS=LCAS=0.2V, W=OE=A0 ~ A12(A11)=VCC-0.2V or 0.2V, DQ0 ~ DQ15=VCC-0.2V, 0.2V or Open
*Note :
ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In ICC4,
address can be changed maximum once within one EDO mode cycle time, tHPC.
K4E661612C,K4E641612C
CMOS DRAM
CAPACITANCE (TA=25°C, VCC=3.3V, f=1MHz)
Parameter
Input capacitance [A0 ~ A12]
Symbol
CIN1
Min
Max
Units
pF
-
-
-
5
7
7
Input capacitance [RAS, UCAS, LCAS, W, OE]
Output capacitance [DQ0 - DQ15]
CIN2
pF
CDQ
pF
AC CHARACTERISTICS (0°C£TA£70°C, See note 2)
Test condition : VCC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V
-45
-50
-60
Unit
s
Parameter
Symbol
Note
Min
74
Max
Min
Max
Min
104
138
Max
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
84
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
101
113
tRWC
tRAC
tCAC
tAA
45
12
23
50
13
25
60
15
30
3,4,10
3,4,5
3,10
3
Access time from CAS
Access time from column address
CAS to output in Low-Z
3
3
3
3
3
3
tCLZ
tCEZ
tOLZ
tT
Output buffer turn-off delay from CAS
OE to output in Low-Z
13
50
13
50
13
50
6,20
3
3
3
3
Transition time (rise and fall)
RAS precharge time
1
1
1
2
25
45
8
30
50
8
40
60
10
40
10
14
12
5
tRP
RAS pulse width
10K
10K
10K
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCH
tWP
RAS hold time
CAS hold time
35
7
38
8
CAS pulse width
5K
33
22
10K
37
10K
45
RAS to CAS delay time
11
9
11
9
4
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
25
30
10
5
5
0
0
0
7
7
10
0
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold time referenced to CAS
Read command hold time referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data set-up time
0
0
13
13
7
7
10
30
0
23
0
25
0
0
0
0
8
8
0
0
0
7
7
10
10
10
10
0
6
7
8
8
tRWL
tCWL
tDS
7
7
16
0
0
9,19
K4E661612C,K4E641612C
AC CHARACTERISTICS (Continued)
Parameter
CMOS DRAM
-45
-50
-60
Symbol
Units
Note
Min
Max
Min
Max
Min
Max
Data hold time
7
7
10
ns
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
9,19
tDH
Refresh period (Normal)
64
64
64
tREF
Refresh period (L-ver)
128
128
128
tREF
Write command set-up time
0
0
0
7
7,15
7
tWCS
tCWD
tRWD
tAWD
tCSR
tCHR
tRPC
tCPA
tHPC
tHPRWC
tCP
CAS to W delay time
24
57
35
5
27
64
39
5
32
77
47
5
RAS to W delay time
Column address to W delay time
CAS set-up time (CAS -before-RAS refresh)
CAS hold time (CAS -before-RAS refresh)
RAS to CAS precharge time
Access time from CAS precharge
Hyper Page cycle time
7
17
18
10
5
10
5
10
5
24
28
35
3
17
47
6.5
45
24
20
47
7
25
56
10
60
35
21
21
14
Hyper Page read-modify-write cycle time
CAS precharge time (Hyper page cycle)
RAS pulse width (Hyper page cycle)
RAS hold time from CAS precharge
OE access time
200K
12
50
30
200K
13
200K
15
tRASP
tRHCP
tOEA
tOED
tCPWD
tOEZ
tOEH
tWTS
tWTH
tWRP
tWRH
tDOH
tREZ
3
6
OE to data delay
8
36
3
10
41
3
13
52
3
CAS precharge to W delay time
Output buffer turn off delay time from OE
OE command hold time
11
13
13
5
5
5
Write command set-up time (Test mode in)
Write command hold time (Test mode in)
W to RAS precharge time (C-B-R refresh)
W to RAS hold time (C-B-R refresh)
Output data hold time
10
10
10
10
4
10
10
10
10
5
10
10
10
10
5
11
11
Output buffer turn off delay from RAS
Output buffer turn off delay from W
W to data delay
3
13
13
3
13
13
3
13
13
6,20
6
3
3
3
tWEZ
tWED
tOCH
tCHO
tOEP
tWPE
tRASS
tRPS
tCHS
8
15
5
15
5
OE to CAS hold time
5
CAS hold time to OE
5
5
5
OE precharge time
5
5
5
W pulse width (Hyper Page Cycle)
RAS pulse width (C-B-R self refresh)
RAS precharge time (C-B-R self refresh)
CAS hold time (C-B-R self refresh)
5
5
5
100
74
-50
100
90
-50
100
110
-50
22,23,24
22,23,24
22,23,24
K4E661612C,K4E641612C
CMOS DRAM
( Note 11 )
TEST MODE CYCLE
-45
-50
-60
Parameter
Symbol
Units
Note
Min
79
Max
Min
89
Max
Min
109
145
Max
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
110
121
tRWC
tRAC
tCAC
tAA
50
17
55
18
65
20
3,4,10,12
3,4,5,12
3,10,12
Access time from CAS
Access time from column address
RAS pulse width
28
30
35
50
12
18
39
28
29
62
40
22
52
50
10K
10K
55
13
18
43
30
35
72
47
25
53
55
10K
10K
65
15
20
50
35
39
84
54
30
61
65
10K
10K
tRAS
tCAS
tRSH
tCSH
tRAL
CAS pulse width
RAS hold time
CAS hold time
Column Address to RAS lead time
CAS to W delay time
7
7
tCWD
tRWD
tAWD
tHPC
tHPRWC
tRASP
tCPA
tOEA
tOED
tOEH
RAS to W delay time
Column Address to W delay time
Hyper Page cycle time
7
21
21
Hyper Page read-modify-write cycle time
RAS pulse width (Hyper page cycle)
Access time from CAS precharge
OE access time
200K
29
200K
33
200K
40
3
3
17
18
20
OE to data delay
13
13
18
18
20
20
OE command hold time
K4E661612C,K4E641612C
CMOS DRAM
NOTES
An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
1.
2.
Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition
times are measured between VIH(min) and VIL(max) and are assumed to be 2ns for all inputs.
Measured with a load equivalent to 1 TTL load and 100pF.
3.
4.
Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.
Assumes that tRCD³ tRCD(max).
5.
6.
This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol.
tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electric charac-
teristics only. If tWCS³ tWCS(min), the cycles is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If tCWD³ tCWD(min), tRWD³ tRWD(min) and tAWD³ tAWD(min), then the cycle is a read-modify-write cycle
and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the
condition of the data out is indeterminate.
7.
8.
9.
Either tRCH or tRRH must be satisfied for a read cycle.
This parameters are referenced to the CAS leading edge in early write cycles and to the W falling edge in OE controlled write
cycle and read-modify-write cycles.
10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If
tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.
11.
These specifiecations are applied in the test mode.
12. In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
13.
14.
tASC, tCAH are referenced to the earlier CAS falling edge.
tCP is specified from the last CAS rising edge in the previous cycle to the first CAS falling edge in the next cycle.
15. tCWD is referenced to the later CAS falling edge at word read-modify-write cycle.
K4E64(6)1612C Truth Table
RAS
H
L
LCAS
UCAS
W
X
X
H
H
H
L
OE
X
DQ0 - DQ7
Hi-Z
DQ8-DQ15
Hi-Z
STATE
Standby
Refresh
X
H
L
X
H
H
L
X
Hi-Z
Hi-Z
L
L
DQ-OUT
Hi-Z
Hi-Z
Byte Read
Byte Read
Word Read
Byte Write
Byte Write
Word Write
-
L
H
L
L
DQ-OUT
DQ-OUT
-
L
L
L
DQ-OUT
DQ-IN
-
L
L
H
L
H
H
H
H
L
H
L
L
DQ-IN
DQ-IN
Hi-Z
L
L
L
DQ-IN
Hi-Z
L
L
L
H
K4E661612C,K4E641612C
CMOS DRAM
tCWL is specified from W falling edge to the earlier CAS rising edge.
16.
17. tCSR is referenced to earlier CAS falling before RAS transition low.
18.
tCHR is referenced to the later CAS rising high after RAS transition low.
RAS
LCAS
UCAS
tCSR
tCHR
19. tDS is specified for the earlier CAS falling edge and tDH is specified by the later CAS falling edge in early write cycle.
LCAS
UCAS
tDS
tDH
Din
DQ0 ~ DQ15
20. If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going.
21.
22.
23.
tASC³ 6ns, Assume tT=2.0ns, if tASC£6ns, then tHPC(min) and tCAS(min) must be increased by the value of "6ns-tASC".
If tRASS³ 100us, then RAS precharge time must use tRPS instead of tRP.
For RAS-only-Refresh and Burst CAS-before-RAS refresh mode, 4096 cycles(4K/8K) of burst refresh must be executed within
64ms before and after self refresh, in order to meet refresh specification.
24.
For distributed CAS-before-RAS with 15.6us interval, CBR refresh should be executed with in 15.6us immediately before and
after self refresh in order to meet refresh specification.
K4E661612C,K4E641612C
CMOS DRAM
WORD READ CYCLE
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCSH
tCRP
tCRP
tRCD
tRCD
tRSH
tCAS
VIH -
UCAS
VIL -
tCRP
tCRP
tRSH
tCAS
VIH -
LCAS
VIL -
tRAD
tRAL
tASR
tRAH
tASC
tRCS
tCAH
VIH -
VIL -
COLUMN
ADDRESS
ROW
ADDRESS
A
W
tRCH
tRRH
VIH -
VIL -
tAA
tOLZ
tOEA
VIH -
VIL -
OE
tCAC
tCLZ
tCEZ
tCEZ
tOEZ
DATA-OUT
DQ0 ~ DQ7
VOH -
VOL -
tRAC
OPEN
OPEN
tCAC
tCLZ
tOEZ
DATA-OUT
DQ8 ~ DQ15
tRAC
VOH -
VOL -
Don¢t care
Undefined
K4E661612C,K4E641612C
CMOS DRAM
LOWER BYTE READ CYCLE
NOTE : DIN = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tRPC
tCRP
VIH -
UCAS
VIL -
tCSH
tCRP
tRCD
tRSH
tCAS
VIH -
LCAS
VIL -
tRAD
tRAL
tASR
tRAH
tASC
tRCS
tCAH
VIH -
VIL -
COLUMN
ADDRESS
ROW
ADDRESS
A
W
tRCH
tRRH
VIH -
VIL -
tCEZ
tOEZ
tAA
VIH -
VIL -
tOEA
tCAC
OE
tCLZ
DQ0 ~ DQ7
VOH -
VOL -
tRAC
OPEN
DATA-OUT
tOLZ
DQ8 ~ DQ15
VOH -
OPEN
VOL -
Don¢t care
Undefined
K4E661612C,K4E641612C
CMOS DRAM
UPPER BYTE READ CYCLE
NOTE : DIN = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
UCAS
VIL -
tCRP
tRPC
VIH -
LCAS
VIL -
tRAD
tRAL
tASR
tRAH
tASC
tRCS
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
W
tRCH
tRRH
VIH -
VIL -
tCEZ
tOEZ
tAA
VIH -
VIL -
tOEA
tOLZ
OE
DQ0 ~ DQ7
VOH -
VOL -
OPEN
tCAC
tCLZ
DQ8 ~ DQ15
tRAC
VOH -
DATA-OUT
OPEN
VOL -
Don¢t care
Undefined
K4E661612C,K4E641612C
CMOS DRAM
WORD WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
UCAS
VIL -
tCRP
tCRP
tRCD
tRSH
VIH -
LCAS
tCAS
VIL -
tRAD
tRAL
tASR
tRAH
tASC
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
W
tWCS
tWCH
VIH -
VIL -
tWP
VIH -
VIL -
OE
tDS
tDS
DQ0 ~ DQ7
VIH -
VIL -
tDH
DATA-IN
tDH
DATA-IN
DQ8 ~ DQ15
VIH -
VIL -
Don¢t care
Undefined
K4E661612C,K4E641612C
CMOS DRAM
LOWER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRP
VIH -
VIL -
RAS
UCAS
LCAS
tCRP
tCRP
VIH -
VIL -
tCSH
tCRP
tRCD
tRSH
VIH -
VIL -
tCAS
tRAD
tRAH tASC
tRAL
tASR
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
W
tWCS
tWCH
VIH -
VIL -
tWP
VIH -
VIL -
OE
tDS
tDH
DATA-IN
DQ0 ~ DQ7
VIH -
VIL -
DQ8 ~ DQ15
VIH -
VIL -
Don¢t care
Undefined
K4E661612C,K4E641612C
CMOS DRAM
UPPER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRP
VIH -
VIL -
RAS
UCAS
LCAS
tCSH
tCRP
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
VIL -
VIH -
VIL -
tRAD
tRAH tASC
tRAL
tASR
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
tWCS
tWCH
VIH -
VIL -
tWP
W
VIH -
VIL -
OE
DQ0 ~ DQ7
VIH -
VIL -
tDS
tDH
DATA-IN
DQ8 ~ DQ15
VIH -
VIL -
Don¢t care
Undefined
K4E661612C,K4E641612C
CMOS DRAM
WORD WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tRCD
tCRP
tRSH
tCAS
VIH -
VIL -
UCAS
LCAS
tCSH
tCRP
tCRP
tRCD
tRSH
VIH -
VIL -
tCAS
tRAD
tASC
tRAL
tASR
tRAH
tCAH
VIH -
VIL -
COLUMN
ADDRESS
ROW
ADDRESS
A
W
tCWL
tRWL
VIH -
VIL -
tWP
VIH -
VIL -
OE
tOEH
tOED
tDS
tDS
tDH
DATA-IN
DQ0 ~ DQ7
VIH -
VIL -
tDH
DATA-IN
DQ8 ~ DQ15
VIH -
VIL -
Don¢t care
Undefined
K4E661612C,K4E641612C
CMOS DRAM
LOWER BYTE WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tRPC
tCRP
VIH -
UCAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
VIL -
LCAS
tRAD
tRAH tASC
tRAL
tASR
tCAH
COLUMN
ADDRESS
VIH -
VIL -
ROW
ADDRESS
A
tCWL
tRWL
VIH -
VIL -
tWP
W
VIH -
VIL -
tOEH
OE
tOED
tDS
tDH
DATA-IN
DQ0 ~ DQ7
VIH -
VIL -
DQ8 ~ DQ15
VIH -
VIL -
Don¢t care
Undefined
K4E661612C,K4E641612C
CMOS DRAM
UPPER BYTE WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
VIL -
UCAS
LCAS
tCRP
tCRP
VIH -
VIL -
tRAD
tASC
tRAL
tCWL
tASR
tRAH
tCAH
COLUMN
VIH -
VIL -
ROW
ADDRESS
A
ADDRESS
tRWL
VIH -
VIL -
W
tWP
VIH -
VIL -
tOEH
OE
tOED
DQ0 ~ DQ7
VIH -
VIL -
tDS
tDH
DATA-IN
DQ8 ~ DQ15
VIH -
VIL -
Don¢t care
Undefined
K4E661612C,K4E641612C
CMOS DRAM
WORD READ - MODIFY - WRITE CYCLE
tRWC
tRAS
tRP
VIH -
RAS
VIL -
tCRP
tCRP
tRCD
tRCD
tRSH
tCAS
VIH -
VIL -
UCAS
LCAS
tRSH
tCAS
VIH -
VIL -
tRAD
tRAH
tCSH
tASR
tASC
tCAH
VIH -
VIL -
ROW
ADDR.
COLUMN
ADDRESS
A
tAWD
tRWL
tCWL
tWP
tCWD
VIH -
VIL -
W
tRWD
tOEA
VIH -
VIL -
OE
tOLZ
tCLZ
tCAC
tAA
tOED
tOEZ
tDS
tDH
DQ0 ~ DQ7
tRAC
VI/OH -
VALID
DATA-OUT
VALID
DATA-IN
VI/OL -
tOLZ
tCLZ
tCAC
tAA
tOED
tOEZ
tDS
tDH
DQ8 ~ DQ15
tRAC
VI/OH -
VALID
DATA-OUT
VALID
DATA-IN
VI/OL -
Don¢t care
Undefined
K4E661612C,K4E641612C
CMOS DRAM
LOWER-BYTE READ - MODIFY - WRITE CYCLE
tRWC
tRAS
tRP
VIH -
RAS
VIL -
tRPC
tCRP
VIH -
UCAS
VIL -
tCRP
tRCD
tRSH
VIH -
VIL -
tCAS
LCAS
tRAD
tRAH
tCSH
tASR
tASC
tCAH
VIH -
VIL -
COLUMN
ADDRESS
ROW
ADDR.
A
tAWD
tRWL
tCWL
tWP
tCWD
VIH -
VIL -
W
tRWD
tOEA
VIH -
VIL -
OE
tOLZ
tCLZ
tCAC
tOED
tOEZ
tAA
tDS
tDH
DQ0 ~ DQ7
VI/OH -
tRAC
VALID
DATA-OUT
VALID
DATA-IN
VI/OL -
DQ8 ~ DQ15
VOH -
OPEN
VOL -
Don¢t care
Undefined
K4E661612C,K4E641612C
CMOS DRAM
UPPER-BYTE READ - MODIFY - WRITE CYCLE
tRWC
tRAS
tRP
VIH -
VIL -
RAS
UCAS
LCAS
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
VIL -
tRPC
VIH -
VIL -
tRAD
tRAH
tCSH
tASR
tASC
tCAH
VIH -
VIL -
ROW
ADDR
COLUMN
ADDRESS
A
tAWD
tRWL
tCWL
tWP
tCWD
VIH -
VIL -
W
tRWD
tOEA
VIH -
VIL -
OE
DQ0 ~ DQ7
VOH -
VOL -
OPEN
tOLZ
tCLZ
tCAC
tOED
tOEZ
tAA
tDS
tDH
DQ8 ~ DQ15
tRAC
VI/OH -
VALID
DATA-OUT
VALID
DATA-IN
VI/OL -
Don¢t care
Undefined
K4E661612C,K4E641612C
CMOS DRAM
HYPER PAGE MODE WORD READ CYCLE
tRASP
tRP
VIH -
RAS
VIL -
tCSH
tHPC
tRHCP
tCAS
tHPC
tCAS
tHPC
tCRP
tCP
tCP
tCP
tRCD
tCAS
tCAS
VIH -
VIL -
UCAS
tREZ
tCRP
tASR
tCP
tCP
tCP
tRCD
tCAS
tCAH
tCAS
tCAH
tCAS
tCAH
tCAS
tCAH
VIH -
VIL -
LCAS
tRAD
tRAH tASC
tASC
tASC
tASC
VIH -
VIL -
ROW
ADDR
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDR
COLUMN
ADDRESS
A
tRAL
tRRH
tRCS
tRCH
VIH -
VIL -
W
tCPA
tCAC
tAA
tAA
tCPA
tCAC
tCAC
tAA
tCPA
tCHO
tOEP
tOCH
tOEA
tOEA
VIH -
VIL -
OE
tCAC
tOEP
tOEZ
tDOH
DQ0 ~ DQ7
VOH -
tRAC
tOEZ
tOEZ
VALID
VALID
VALID
VALID
VALID
DATA-OUT
DATA-OUT
DATA-OUT
DATA-OUT
DATA-OUT
VOL -
tOLZ
tCLZ
tCAC
tOEP
tOEZ
tDOH
tOEZ
tRAC
DQ8 ~ DQ15
VOH -
VALID
VALID
VALID
VALID
VALID
DATA-OUT
DATA-OUT
DATA-OUT
DATA-OUT
DATA-OUT
VOL -
tOLZ
tCLZ
Don¢t care
Undefined
K4E661612C,K4E641612C
CMOS DRAM
HYPER PAGE MODE LOWER BYTE READ CYCLE
tRP
tRASP
VIH -
RAS
VIL -
¡ó
tRPC
tCRP
VIH -
UCAS
tCSH
tRHCP
tHPC
VIL -
tHPC
tHPC
tREZ
tCP
tCP
tCP
tRCD
tCAS
tCAH
tCAS
tCAS
tCAS
tCAH
VIH -
VIL -
LCAS
tRAD
tRAH tASC
tASR
tASC
tCAH
tASC
tCAH tASC
VIH -
VIL -
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDR
COLUMN
ADDRESS
ROW
ADDR
A
tRAL
tRRH
tRCS
tRCH
VIH -
VIL -
W
tCPA
tCAC
tAA
tAA
tCPA
tCAC
tCAC
tAA
tCPA
tAA
tOEA
tCHO
tOEP
tOCH
tOEA
VIH -
VIL -
OE
tCAC
tOEP
tOEZ
tDOH
DQ0 ~ DQ7
VOH -
VOL -
tOEZ
tOEZ
tRAC
VALID
DATA-OUT
VALID
VALID
VALID
VALID
DATA-OUT
DATA-OUT
DATA-OUT
DATA-OUT
tOLZ
tCLZ
DQ8 ~ DQ15
VOH -
OPEN
VOL -
Don¢t care
Undefined
K4E661612C,K4E641612C
CMOS DRAM
HYPER PAGE MODE UPPER BYTE READ CYCLE
tRASP
tRP
VIH -
RAS
VIL -
¡ó
tCSH
tRHCP
tCAS
tHPC
tHPC
tCAS
tHPC
tCRP
tCP
tCP
tCP
tRPC
tRPC
tRCD
tCAS
tCAS
VIH -
VIL -
UCAS
tCRP
tASR
VIH -
VIL -
LCAS
tRAD
tRAH tASC
tCAH
tASC
tCAH
tASC
tCAH
tASC
tCAH
tREZ
VIH -
VIL -
ROW
ADDR.
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDR.
COLUMN
ADDRESS
A
tRAL
tRRH
tRCS
tRCH
VIH -
VIL -
W
tCPA
tCAC
tAA
tCAC
tAA
tCPA
tAA
tCPA
tCAC
tCHO
tOEP
tOCH
tOEA
tOEA
VIH -
VIL -
OE
DQ0 ~ DQ7
VOH -
VOL -
OPEN
tCAC
tOEP
tOEZ
tDOH
tOEZ
tOEZ
tRAC
DQ8 ~ DQ15
VOH -
VALID
DATA-OUT
VALID
VALID
VALID
VALID
DATA-OUT
DATA-OUT
DATA-OUT
DATA-OUT
VOL -
tOLZ
tCLZ
Don¢t care
Undefined
K4E661612C,K4E641612C
CMOS DRAM
HYPER PAGE MODE WORD WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRASP
tRP
VIH -
RAS
tRHCP
VIL -
¡ó
tHPC
tHPC
tHPC
tHPC
tRSH
tCRP
tCRP
tCP
tCP
tCP
tCP
tCRP
tRCD
tRCD
VIH -
VIL -
tCAS
tCAS
¡ó
tCAS
UCAS
LCAS
tRSH
VIH -
VIL -
tCAS
tCAS
¡ó
tCAS
tRAD
tRAH
tRAL
tCAH
tCSH
tASC
tASR
tCAH
tASC
tCAH
tASC
¡ó
¡ó
VIH -
VIL -
ROW
ADDR
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
A
tWCS tWCH
tWP
tWCS
tWCH
tWP
tWCS
tWCH
tWP
¡ó
VIH -
VIL -
W
¡ó
¡ó
VIH -
VIL -
OE
tDS
tDS
tDH
tDS
tDH
tDS
tDH
DQ0 ~ DQ7
VIH -
¡ó
¡ó
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
VIL -
tDH
tDS
tDH
tDS
tDH
DQ8 ~ DQ15
¡ó
¡ó
VIH -
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
VIL -
Don¢t care
Undefined
K4E661612C,K4E641612C
CMOS DRAM
HYPER PAGE MODE LOWER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRASP
tRP
VIH -
tRHCP
RAS
VIL -
¡ó
tRPC
tCRP
VIH -
UCAS
VIL -
tHPC
tHPC
tRSH
tCRP
tRCD
tCP
tCP
VIH -
VIL -
tCAS
tCAS
¡ó
tCAS
LCAS
tRAD
tRAL
tCAH
tCSH
tASC
tASR
tASC
tCAH
tRAH
tASC
tCAH
COLUMN
¡ó
¡ó
VIH -
VIL -
ROW
ADDR
COLUMN
ADDRESS
COLUMN
ADDRESS
A
ADDRESS
tWCS
tWP
tWCH
tWCS
tWCH
tWP
tWCS
tWCH
tWP
¡ó
VIH -
VIL -
W
¡ó
¡ó
VIH -
VIL -
OE
tDS
tDH
tDS
tDH
tDS
tDH
DQ0 ~ DQ7
VIH -
VIL -
¡ó
¡ó
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
DQ8 ~ DQ15
VIH -
VIL -
Don¢t care
Undefined
K4E661612C,K4E641612C
CMOS DRAM
HYPER PAGE MODE UPPER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRASP
tRP
VIH -
tRHCP
RAS
VIL -
¡ó
tHPC
tHPC
tRSH
tCRP
tCRP
tRCD
tCP
tCP
VIH -
VIL -
tCAS
tCAS
¡ó
tCAS
UCAS
LCAS
tRPC
VIH -
VIL -
tRAD
tRAH
tRAL
tCAH
tCSH
tASC
tASR
tCAH
tASC
tCAH
COLUMN
tASC
¡ó
¡ó
VIH -
VIL -
ROW
ADDR
COLUMN
ADDRESS
COLUMN
ADDRESS
A
ADDRESS
tWCS
tWP
tWCH
tWCS
tWCH
tWP
tWCS
tWCH
tWP
¡ó
VIH -
VIL -
W
¡ó
¡ó
VIH -
VIL -
OE
DQ0 ~ DQ7
VIH -
VIL -
¡ó
¡ó
tDS
tDH
tDS
tDH
tDS
tDH
DQ8 ~ DQ15
¡ó
¡ó
VIH -
VIL -
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
Don¢t care
Undefined
K4E661612C,K4E641612C
CMOS DRAM
HYPER PAGE MODE WORD READ - MODIFY - WRITE CYCLE
tRP
tRASP
VIH -
VIL -
tCSH
tHPRWC
RAS
tRSH
tCAS
tCRP
tCRP
tRCD
tRCD
tCRP
tCRP
tCP
tCP
VIH -
VIL -
tCAS
tCAS
UCAS
LCAS
VIH -
VIL -
tCAS
tRAD
tRAH
tRAL
tCAH
tCAH
tASR
tASC
tASC
VIH -
VIL -
ROW
ADDR
COL.
ADDR
COL.
ADDR
A
W
tRWL
tCWL
tRCS
tCWL
tRCS
VIH -
VIL -
tWP
tWP
tCWD
tAWD
tRWD
tCWD
tAWD
tCPWD
VIH -
VIL -
tOEA
tOEA
OE
tOED
tOED
tCAC
tCAC
tCLZ
tDH
tDH
tAA
tAA
tDS
tDS
tOEZ
tOEZ
DQ0 ~ DQ7
tRAC
VI/OH -
VI/OL -
tCLZ
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
tOED
tOED
tCAC
tAA
tCAC
tDH
tDH
tAA
tDS
tDS
tOEZ
tOEZ
DQ8 ~ DQ15
tRAC
tCLZ
VI/OH -
VI/OL -
tCLZ
VALID
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-OUT
DATA-IN
Don¢t care
Undefined
K4E661612C,K4E641612C
CMOS DRAM
HYPER PAGE MODE LOWER BYTE READ - MODIFY - WRITE CYCLE
tRP
tRASP
VIH -
VIL -
tCSH
tHPRWC
RAS
tRPC
tCRP
tCRP
VIH -
VIL -
UCAS
LCAS
tRSH
tCAS
tCP
tCRP
tRCD
VIH -
VIL -
tCAS
tRAD
tRAH
tRAL
tCAH
tCAH
tASR
tASC
tASC
VIH -
VIL -
ROW
ADDR
COL.
ADDR
COL.
ADDR
A
W
tRWL
tCWL
tRCS
tRCS
tCWL
VIH -
VIL -
tWP
tWP
tCWD
tAWD
tCWD
tAWD
tCPWD
tRWD
VIH -
VIL -
tOEA
tOEA
OE
tOED
tOED
tCAC
tCAC
tDH
tAA
tDH
tAA
tDS
tOEZ
tDS
DQ0 ~ DQ7
VI/OH -
tRAC
tOEZ
VI/OL -
tCLZ
tCLZ
tOLZ
tOLZ
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
DQ8 ~ DQ15
VI/OH -
OPEN
VI/OL -
Don¢t care
Undefined
K4E661612C,K4E641612C
CMOS DRAM
HYPER PAGE MODE UPPER BYTE READ - MODIFY - WRITE CYCLE
tRP
tRASP
VIH -
tCSH
tHPRWC
RAS
VIL -
tCRP
tCRP
tRSH
tCAS
tCP
tRCD
tCRP
VIH -
VIL -
tCAS
UCAS
LCAS
tRPC
VIH -
VIL -
tRAD
tRAH
tRAL
tCAH
tCAH
tASR
tASC
tASC
VIH -
VIL -
ROW
ADDR
COL.
ADDR
COL.
A
W
ADDR
tRWL
tCWL
tRCS
tRCS
tCWL
VIH -
VIL -
tWP
tWP
tCWD
tAWD
tRWD
tCWD
tAWD
tCPWD
VIH -
VIL -
tOEA
tOEA
OE
DQ0 ~ DQ7
VI/OH -
OPEN
VI/OL -
tOLZ
tOLZ
tOED
tOED
tCAC
tCAC
tAA
tDH
tAA
tDH
tDS
tOEZ
tDS
DQ8 ~ DQ15
tRAC
tCLZ
tOEZ
VI/OH -
VI/OL -
tCLZ
VALID
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-IN
DATA-IN
Don¢t care
Undefined
K4E661612C,K4E641612C
CMOS DRAM
HYPER PAGE READ AND WRITE MIXED CYCLE
tRP
tRASP
VIH -
VIL -
READ(tCAC)
READ(tCPA)
READ(tAA)
WRITE
RAS
tRHCP
tHPC
tHPC
tHPC
tCP
tCP
tCP
tCP
tCP
tCP
VIH -
VIL -
tCAS
tCAS
tCAS
tCAS
tHPC
tCAS
tHPC
UCAS
LCAS
tRCD
tHPC
tCAS
VIH -
VIL -
tCAS
tCAS
tCAH
tRAD
tRAH
tASC
tCAH
tASR
tCAH
tASC
tASC
tCAH
tASC
VIH -
VIL -
COLUMN
ADDRESS
COL.
ADDR
COL.
ADDR
ROW
ADDR
COLUMN
A
ADDRESS
tRCS
tRAL
tRCH
tRCS
tRCH
tWCH
tRCH
VIH -
VIL -
tWCS
W
tWPE
tCPA
tCLZ
tWED
VIH -
VIL -
OE
tOEA
tDH
tDS
tWEZ
tCAC
tAA
tRAC
tAA
tAA
tREZ
tWEZ
DQ0 ~ DQ7
VI/OH -
VALID
VALID
VALID
DATA-OUT
VALID
DATA-OUT
DATA-IN
DATA-OUT
VI/OL -
tOEA
tCAC
tAA
tRAC
tDH
tDS
tWEZ
tWEZ
tREZ
DQ8 ~ DQ15
VI/OH -
VALID
VALID
VALID
VALID
DATA-OUT
DATA-IN
DATA-OUT
DATA-OUT
VI/OL -
Don¢t care
Undefined
K4E661612C,K4E641612C
CMOS DRAM
RAS - ONLY REFRESH CYCLE
NOTE : W, OE , DIN = Don¢t care
DOUT = OPEN
tRC
tRP
VIH -
RAS
VIL -
tRAS
tRPC
tCRP
VIH -
UCAS
VIL -
tCRP
VIH -
LCAS
VIL -
tASR
tRAH
VIH -
VIL -
ROW
ADDR
A
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE, A = Don¢t care
tRC
tRP
tRP
tRAS
VIH -
RAS
VIL -
tRPC
tCP
tRPC
tCSR
tCSR
VIH -
VIL -
tCHR
tCHR
UCAS
LCAS
tCP
VIH -
VIL -
DQ0 ~ DQ7
VOH -
VOL -
tCEZ
OPEN
OPEN
DQ8 ~ DQ15
VOH -
VOL -
tWRP
tWRH
VIH -
VIL -
W
Don¢t care
Undefined
K4E661612C,K4E641612C
CMOS DRAM
HIDDEN REFRESH CYCLE ( READ )
tRC
tRAS
tRC
tRAS
tRP
tRP
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
tRSH
tCHR
VIH -
VIL -
UCAS
LCAS
tCRP
tCHR
tRCD
VIH -
VIL -
tRAD
tASR
ROW
tRAH
tASC
tCAH
COLUMN
ADDRESS
VIH -
VIL -
A
W
ADDRESS
tWRH
tRCS
VIH -
VIL -
tRAL
tAA
VIH -
VIL -
tOEA
tOLZ
OE
tCEZ
tREZ
tCAC
tCLZ
tRAC
tWEZ
DQ0 ~ DQ7
VOH -
VOL -
tOEZ
DATA-OUT
OPEN
DQ8 ~ DQ15
VOH -
DATA-OUT
OPEN
VOL -
Don¢t care
Undefined
* In Hidden refresh cycle of 64Mb A-die & B-die, when CAS signal transits from Low to High, the valid data may be cut off.
K4E661612C,K4E641612C
CMOS DRAM
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : DOUT = OPEN
tRC
tRC
tRP
tRP
tRAS
tRAS
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
tRSH
tCHR
tCHR
VIH -
UCAS
VIL -
tCRP
tRCD
VIH -
LCAS
VIL -
tRAD
tASR
tRAH
tASC
tCAH
COLUMN
ADDRESS
VIH -
VIL -
ROW
ADDRESS
A
W
tWRH
tWRP
tWCS
tWCH
VIH -
VIL -
tWP
VIH -
VIL -
OE
tDS
tDS
tDH
DATA-IN
DQ0 ~ DQ7
VIH -
VIL -
tDH
DATA-IN
DQ8 ~ DQ15
VIH -
VIL -
Don¢t care
Undefined
K4E661612C,K4E641612C
CMOS DRAM
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE , A = Don¢t care
tRP
tRASS
tRPS
VIH -
RAS
VIL -
tRPC
tCP
tRPC
tCHS
tCHS
tCSR
tCSR
VIH -
VIL -
UCAS
LCAS
tCP
VIH -
VIL -
tCEZ
DQ0 ~ DQ7
VOH -
OPEN
OPEN
VOL -
DQ8 ~ DQ15
VOH -
VOL -
tWRP
tWRH
VIH -
VIL -
W
TEST MODE IN CYCLE
NOTE : OE , A = Don¢t care
tRC
tRP
tRP
tRAS
VIH -
RAS
VIL -
tRPC
tCP
tRPC
tCSR
tCSR
VIH -
VIL -
tCHR
tCHR
UCAS
LCAS
tCP
VIH -
VIL -
tWTS
tWTH
VIL -
VIH -
W
tCEZ
DQ0 ~ DQ15
VOH -
VOL -
OPEN
Don¢t care
Undefined
K4E661612C,K4E641612C
CMOS DRAM
PACKAGE DIMENSION
50 TSOP(II) 400mil
Units : Inches (millimeters)
0.004 (0.10)
0.010 (0.25)
0.841 (21.35)
MAX
0.821 (20.85)
0.829 (21.05)
0.047 (1.20)
MAX
0.010 (0.25)
TYP
O
0~8
0.018 (0.45)
0.030 (0.75)
0.034 (0.875)
0.0315 (0.80)
0.002 (0.05)
MIN
0.010 (0.25)
0.018 (0.45)
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