K4C89093AF-GIF50_技术文档

K4C89363AF

Target

288Mb x36 Network-DRAM-II Specification

Version 0.2

- 1 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Revision History

Version 0.0 (Nov. 2002)

- First Release

Version 0.1 (Jan. 2003)

- Added JTAG

- Corrected # of row/column addresses.

- Corrected pin assignment in page 4.

- Changed operating temperature from Ta(0~70’C) to Tc(0~85’C).

- Changed tDSS(DS input Falling Edge to Clock Setup Time)

From

To

F6

0.9

-

FB

0.9

-

F5

1.0

-

G7

F6

0.75

-

FB

0.8

-

F5

1.0

-

CL4

CL5

CL6

CL7

0.75

- Changed capacitance of ADDR/CMD/CLK

From

To

Min

1.5

Max

2.5

Min

1.5

Max

3.0

Addr/CMD/CLK

- Added CL7 for 800Mbps

Version 0.11 (Apr. 2003)

- Corrected typo in page 3.(Deleted bi-directional strobe)

- Corrected min. Vref to VDDQ/2x95% in page 7

- Separated data in/out to DQ buffer of block diagram in page 6

- Added tDQSQA(Data Output Skew from QS to all DQs) and tDSSK(UDS-LDS Skew) in page 10.

Version 0.2 (Aug. 2003)

- Added package physical dimension

- Extracted 800Mbps(G7) binning from target spec ( G7 will be added in the future)

- Changed DC test condition

From

To

Changed point

Changed condition

newly inserted

IDD1S,IDD2N,IDD2P,IDD5,IDD6 IDD1S,IDD2N,IDD2P,IDD5B,IDD6

-

IDD4W, IDD4R

- Changed low frequency spec like below

From

To

FB

6.0

Unit : ns

F6

7.5

FB

7.5

F5

F6

F5

6.0

tCK max@CL=4

tCK max@CL=5

tCK max@CL=6

7.5

6.0

- Changed AC test load picture

- 2 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

2,097,152-WORDS x 4 BANKS x 36-BITS DOUBLE DATA RATE Network-DRAM

DESCRIPTION

K4C89363AF is a CMOS Double Data Rate Network-DRAM containing 301,989,888 memory cells. K4C89363AF is organized as

2,097,152-words x 4 banks x36 bits. K4C89363AF feature a fully synchronous operation referenced to clock edge whereby all opera-

tions are synchronized at a clock input which enables high performance and simple user interface coexistence. K4C89363AF can oper-

ate fast core cycle compared with regular DDR SDRAM.

K4C89363AF is suitable for Server, Network and other applications where large memory density and low power consumption are

required. The Output Driver for Network-DRAM is capable of high quality fast data transfer under light loading condition.

FEATURES

K4C89363AF

Parameter

F6

FB

F5

t_CKClock Cycle Time (min)

CL = 4

CL = 5

CL = 6

4.0 ns

3.33 ns

3.0ns

4.5 ns

3.75 ns

3.33 ns

22.5 ns

5.0 ns

4.5 ns

4.0 ns

25 ns

t

_RCRandom Read/Write Cycle Time (min)

20.0 ns

t_RACRandom Access Time (min)

20.0 ns

TBD

22.5 ns

TBD

25 ns

TBD

I

_DD1SOperating Current (single bank) (max)

_DD2SPower Down Current (max)

TBD

_DD3SSelf-Refresh Current (max)

TBD

•

Fully Synchronous Operation

- Double Data Rate (DDR)

- Data input/output are synchronized with both edges of DS / QS.

- Differential Clock (CLK and CLK) inputs

- CS, FN and all address input signals are sampled on the positive edge of CLK.

- Output data (DQs and QS) is aligned to the crossings of CLK and CLK.

Fast clock cycle time of 3.0 ns minimum

- Clock : 333 MHz maximum

•

- Data : 666 Mbps/pin maximum

•

Quad Independent Banks operation

Fast cycle and Short Latency

Uni-directional Data Strobe

Distributed Auto-Refresh cycle in 3.9us

Self-Refresh

Power Down Mode

Variable Write Length Control

Write Latency = CAS Latency-1

Programable CAS Latency and Burst Length

- CAS Laatency = 4, 5, 6

- Burst Length = 2,4

•

Organization : 2,097,152 words x 4 banks x 36 bits

Power Supply Voltage V_DD: 2.5V ± 0.125V

•

V_DDQ: 1.4V ∼ 1.9V

•

Low voltage CMOS I/O covered with SSTL - 1.8 (half strength driver) and HSTL

Package : 144Ball BGA, 1mm x 0.8mm Ball pitch

JTAG boundary scan

Notice : Network-DRAM is trademark of Samsung Electronics., Co LTD

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REV. 0.2 Aug. 2003

K4C89363AF

Target

Pin Names

A0 ~ A13

BA0, BA1

DQ0 ~ DQ35

CS

Name

Address Input

Bank Address

Data Input/Output

Chip Select

FN

Function Control

Power Down Control

Clock Input

PD

CLK, CLK

LDS, UDS

LQS, UQS

VDD

Write Data Strobe

Read Data Strobe

Power (+2.5V)

Ground

V_SS

V_DDQ

V_SSQ

V_REF

Power (+1.8V)(for I/O buffer)

Ground(for I/O buffer)

Reference Voltage

NC

No Connection

TMS, TDI, TCK, TDO

Boundary Scan Test Access Ports

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REV. 0.2 Aug. 2003

K4C89363AF

Target

PIN ASSIGNMENT (TOP VIEW)

ball pitch=1.0 x 0.8mm

1

2

3

4

5

6

7

8

9

10

11

12

Index

A

B

C

D

E

F

V

DD

SS

DD

SS

DD

V

Q

DQ16

DQ14

DQ12

DQ10

LDS

DQ17

DQ15

DQ13

DQ11

DQ9

/CLK

CLK

V

Q

V

Q

DQ0

DQ2

DQ4

DQ6

DQ8

A13

DQ1

DQ3

DQ5

DQ7

LQS

FN

V

Q

DD

V

Q

V

SS

DD

V

Q

V

Q

V

Q

V

Q

SS

DD

SS

DD

SS

DD

SS

DD

V

Q

V

Q

V

Q

V

Q

G

H

J

V

Q

V

Q

V

SSQ

SS

REF

SS

SSQ

V

/PD

A12

V

/CS

NC

V

SS

DD

SS

DD

V

A11

V

BA1

A0

BA0

A10

V

DD

K

L

V

A9

A8

V

SS

A7

A6

A2

A1

DD

M

N

P

R

T

V

Q

A5

A4

V

Q

V

Q

NC

A3

V

Q

DD

V

Q

UDS

DQ25

DQ23

DQ21

DQ19

TCK

DQ26

DQ24

DQ22

DQ20

DQ18

V

Q

V

Q

DQ27

DQ29

DQ31

DQ33

DQ35

UQS

DQ28

DQ30

DQ32

DQ34

TD0

V

Q

SS

DD

V

Q

V

Q

V

Q

V

Q

SS

V

Q

V

Q

V

Q

V

Q

DD

U

V

SS

TMS

V

TD1

SS

DD

SS

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REV. 0.2 Aug. 2003

K4C89363AF

Target

Block Diagram

CLK

PD

DLL

CLOCK

BUFFER

To Each Block

BANK #3

BANK #2

BANK #1

BANK #0

CONTROL

SIGNAL

CS

FN

COMMAND

DECODER

GENERATOR

MEMORY

CELL

ARRAY

MODE

REGISTER

ADDRESS

BUFFER

A0 ~ A14

BA0, BA1

UPPER ADDRESS

LATCH

COLUMN DECODER

LOWER ADDRESS

LATCH

REFRESH

COUNTER

READ

DATA

BUFFER

WRITE

DATA

BUFFER

WRITE ADDRESS

BURST

COUNTER

LATCH

ADDRESS

COMPARATOR

UDS

UQS

LDS

LQS

DQ BUFFER

DQ18 ~ DQ35

DQ0 ~ DQ17

Note : The K4C89363AF configuration is 4 Bank of 16384 x 128 x 36 of cell array with the DQ pins numbered DQ0~DQ35.

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REV. 0.2 Aug. 2003

K4C89363AF

Target

Absolute Maximum Ratings

Symbol

Parameter

Rating

Units

Notes

V_DD

Power Supply Voltage

Power Supply Voltage (for I/O buffer)

Input Voltage

-0.3 ~ 3.3

V

V_DDQ

V_IN

-0.3 ~ V_DD+ 0.3

-0.3 ~ V_DDQ+ 0.3

0 ~ 70

V

V_OUT

V_REF

T_OPR

T_STG

T_SOLDER

P_D

DQ pin Voltage

V

Input Reference Voltage

Operating Temperature

Storage Temperature

V

^OC

W

mA

-55 ~ 150

260

Soldering Temperature(10s)

Power Dissipation

2

I_OUT

Short Circuit Output Current

± 50

Caution : Conditions outside the limits listed under "ABSOLUTE MAXIMUM RATINGS" may cause permanent damage to the device.

The device is not meant to be operated under conditions outside the limits described in the operational section of this specifi-

cation. Exposure to "ABSOLUTE MAXIMUM RATINGS" conditions for extended periods may affect device reliability.

Recommended DC,AC Operating Conditions (Notes : 1) (Tc = 0 ~ 85^OC)

Symbol

Parameter

Min

Typ

Max

Units Notes

V_DD

Power Supply Voltage

2.375

2.5

2.625

V

V_DDQ

V_REF

Power Supply Voltage (for I/O Buffer)

Input Reference Voltage

Input DC high Voltage

1.4

V_DDQ/2x95%

V_REF+0.125

-0.1

-

1.9

V

V_DDQ/2

V_DDQ/2x105%

V_DDQ+0.2

V

2

V_IH(DC)

V_IL(DC)

-

5

Input DC Low Voltage

V_REF-0.125

V_DDQ+0.1

5

V_ICK(DC) Differential Clock DC Input Voltage

-0.1

10

V_ID(DC)

V_IH(AC)

V_IL(AC)

V_ID(AC)

V_X(AC)

Input Differential Voltage. CLK and CLK Inputs (DC)

0.4

V_DDQ+0.2

7,10

3,6

4,6

7,10

8,10

9,10

Input AC High Voltage

V_REF+0.2

-0.1

V_DDQ+0.2

Input AC Low Voltage

V_REF-0.2

Input Differential Voltage. CLK and CLK Inputs (AC)

Differential AC Input Cross Point Voltage

0.55

V_DDQ+0.2

V_DDQ/2-0.125

V_DDQ/2+0.125

V_ISO(AC) Differential Clock AC Middle Level

- 7 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

1. All voltages are referenced to Vss, VssQ.

Notes:

2. V_REFis expected to track variations in VddQ DC level of the transmitting device.

Peak to peak AC noise on V_REFmay not exceed ± 2% of V_REF(DC).

3. Overshoot Iimit : V_IH(max.) = VddQ + 0.7V with a pulse width <= 5ns

4. Undershoot Iimit : V_IL(min.) = -0.7V with a pulse width <= 5ns

5. V_IH(DC) and V_IL(DC) are levels to maintain the current logic state.

6. V_IH(AC) and V_IL(AC) are levels to change to the new logic state.

7. V_IDis magnitude of the difference between CLK input level and CLK input level.

8. The value of Vx(AC) is expected to equal VddQ/2 of the transmitting device.

9. V_ISOmeans [V_ICK(CLK) + V_ICK(CLK)]/2

10. Refer to the figure below.

CLK

V_X

V_ID(AC)

CLK

V_ICK

V_SS

V_ID(AC)

0 V Differential

V_ISO

V_ISO(min)

V_ISO(max)

V_SS

11. In the case of external termination, VTT(Termination Voltage) should be gone in the range of V_REF(DC) ± 0.04V.

o

Pin Capacitance (V = 2.5V, V

= 1.8V, f = 1 MHz, Ta = 25 C)

DD

DDQ

Symbol

Parameter

Min

1.5

2.5

-

Max

3.0

3.5

1.5

Delts

0.25

0.5

Units

pF

C_IN

C_INC

C_I/O

C_NC

Input Pin Capacitance

Clock Pin (CLK, CLK) Capacitance

DQ, DS, QS Capacitance

NC Pin Capacitance

pF

-

pF

Note : These parameters are periodically sampled and not 100% tested.

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REV. 0.2 Aug. 2003

K4C89363AF

Target

DC Characteristics and Operating Conditions (VDD = 2.5V ± 0.125V, VDDQ = 1.8V ± 0.1V, Tcase = 0~85 °C)

Max

Parameter

Symbol

Units Notes

F6

FB

F5

Operating Current

One bank Read or Write operation;

t_CK= min, I_RC= min, I_OUT= 0mA;

Burst Length = 4, CAS Latency = 6, Free running QS mode;

I_DD1S

TBD

1, 2

0V ≤ V_IN≤ V_IL(AC)(max.), V_IH(AC)(min.) ≤ V_IN≤ V_DDQ;

Address inputs change up to 2 times during minimum I_RC

Read data change twice per clock cycle

,

Standby Current

All Banks : inactive state;

t_CK=min, CS = V_IH, PD = V_IH

;

I_DD2N

TBD

1

0V ≤ V_IN≤ V_IL(AC)(max.), V_IH(AC)(min.) ≤ V_IH≤ V_DDQ;

Other input signals change one time during 4*t_CK,

DQ and DS inputs change twice per clock cycle

Standby (Power Down) Current

All Banks : inactive state;

t_CK=min, PD = V_IL(Power Down);

CAS Latency = 6, Free running QS mode;

0V ≤ V_IN≤ V_IL(AC)(max), V_IH(AC)(min) ≤ V_IN≤ V_DDQ

I_DD2P

;

Other input signals change one time during 4*t_CK

,

DQ and DS inputs are floating(V_DDQ/2)

Write Operating Current(4 Banks)

4 Bank intereaved continuous burst write operation;

t_CK= min, I_RC= min;

mA

I_DD4W

Burst Length = 4, CAS Latency = 6, Free running QS mode;

0V ≤ V_IN≤ V_IL(AC) (max.), V_IH(AC)(min.) ≤ V_IN≤ V_DDQ;

TBD

1

Address inputs change once per clock cycle,

DQ and DS inputs change twice per clock cycle

Read Operating Current(4 Banks)

4 Bank intereaved continuous burst write operation;

t_CK= min, I_RC= min, I_OUT= 0mA;

I_DD4R

Burst Length = 4, CAS Latency = 6, Free running QS mode;

0V ≤ V_IN≤ V_IL(AC) (max.), V_IH(AC)(min.) ≤ V_IN≤ V_DDQ;

1,2

1,3

Address inputs change once per clock cycle,

Read data change twice per clock cycle

Burst Auto-Refresh Current

Refresh command at every I_REFCinterval;

t_CK= min, I_REFC= min;

I_DD5B

CAS Latency = 6, Free running QS mode;

0V ≤ V_IN≤ V_IL(AC) (max.), V_IH(AC) (min.) ≤ V_IN≤ V_DDQ;

TBD

Address change up to 2 times during minimum I_REFC

,

DQ and DS inputs change twice per clock cycle

Self-Refresh Current

PD = 0.2V;

Other input signals are floating(V_DDQ/2),

I_DD6

DQ and DS inputs are floating(V_DDQ/2)

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REV. 0.2 Aug. 2003

K4C89363AF

Target

DC Characteristics and Operating Conditions (VDD = 2.5V ± 0.125V, VDDQ = 1.8V ± 0.1V, Tcase = 0~85 °C)

Parameter

Symbol

Min

Max

Unit

Notes

Input Leakage Current (0V<=V_IN<=VddQ, All other pins not under test = 0V)

I_LI

-5

5

-

uA

Output Leakage Current (Output disabled, 0V<=V_OUT<=VddQ)

I_LO

-5

uA

V

_REFCurrent

I_REF

-5

uA

V

_OH= 1.420V

I_OH(DC)

I_OL(DC)

I_OH(DC)

I_OL(DC)

I_OH(DC)

I_OL(DC)

I_OH(DC)

I_OL(DC)

I_OH(DC)

I_OL(DC)

I_OH(DC)

I_OL(DC)

-5.6

5.6

-9.8

9.8

-2.8

2.8

-4

4

Normal Output

Driver

V

_OL= 0.280V

-

V_OH= 1.420V

V_OL= 0.280V

V_OH= 1.420V

-

Output DC Current

(V_DDQ= 1.7 ~ 1.9V)

Strong Output

Driver

mA

-

Weak Output

Driver

V

_OL= 0.280V

V_OH= V_DDQ- 0.4

_OL= 0.4V

V_OH= V_DDQ- 0.4

_OL= 0.4V

-

3

Normal Output

Driver

V

-4

-

-8

-

Output DC Current

(V_DDQ= 1.4 ~ 1.6V)

Strong Output

Driver

mA

V

-8

-

Not defined

-

Weak Output

Driver

-

Notes : 1. These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of

_CK, t_RCand I_RC

t

.

2. These parameters depend on the output loading. The specified values are obtained with the output open.

3. I_DD5Bis specified under burst refresh condition. Actual system should use distributed refresh that meet to t_REFIspecification

4. Refer to output driver characteristics for the detail. Output Driver Strength is selected by Extended Mode Register.

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REV. 0.2 Aug. 2003

K4C89363AF

Target

AC Characteristics and Operating Conditions (Notes : 1, 2)

F6

FB

F5

Symbol

Parameter

Units Notes

Min

20.0

4.0

Max

-

Min

22.5

4.5

Max

-

Min

25

Max

-

t_RC

Random Cycle Time

3

C_L= 4

6.0

20.0

6.0

22.5

5.0

6.0

25

t_CK

C

_L= 5

_L= 6

Clock Cycle Time

3.33

3.0

3.75

3.33

-

4.5

4.0

t_RAC

t_CH

Random Access Time

-

0.45*t_CK

Clock High Time

-

3

t_CL

0.45*t_CK

Clock Low Time

-

t_CKQS

t_QSQ

t_QSQA

t_AC

QS Access Time from CLK

Data Output Skew from QS

Data Output Skew from QS to All DQ

Data Access Time from CLK

Data Output Hold Time from CLK

-0.45

-

0.45

0.2

0.3

0.5

-0.45

-

0.45

0.25

0.35

0.5

-0.5

-

0.5

0.3

0.4

0.6

3, 8

4

-

4

-0.5

-0.6

3, 8

t_OH

min(t_CH

t_CL

,

min(t_CH

,

min(t_CH

,

t_HP

CLK half period ( minium of Actual t_CH, t_CL)

-

3

)

t_CL

)

t_CL

)

t_QSP

t_HP-t_QHS

QS(Read) Pulse Width

-

4, 8

t_QSQV

Data Output Valid Time from QS

0.055x

t_CK+0.17

0.055x

t_CK+0.17

0.055x

t_CK+0.17

t_QHS

DQ, QS Hold skew factor

-

t_DQSS

0.8*t_CK

0.4*t_CK

1.2*t_CK

0.8*t_CK

0.4*t_CK

1.2*t_CK

0.8*t_CK

0.4*t_CK

1.2*t_CK

DS(Write) Low to High Setup Time

DS(Write) Preamble Pulse Width

DS First Input Setup Time

3

ns

t_DSPRE

t_DSPRES

t_DSPREH

t_DSP

-

4

3

0

-

0

-

0

-

0.3*t_CK

0.45*t_CK

0.3*t_CK

0.45*t_CK

0.3*t_CK

0.45*t_CK

DS First Low Input Hold Time

DS High or Low Input Pulse Width

-

0.55*t_CK

4

C

_L= 4

0.75

-

0.8

-

1.0

-

3, 4

4

C_L= 5

DS Input Falling Edge to Clock Setup

Time

t_DSS

C

_L= 6

_L= 7

0.75

0.8

1.0

-

t_DSPST

0.45*t_CK

DS(Write) Postamble Pulse Width

DS(Write) Postamble Hold Time

C_L= 4

_L= 5

0.75

-

0.8

-

1.0

-

3, 4

C

t_DSPSTH

C_L= 6

C_L= 7

-

t_DSSK

t_DS

t_DH

t_IS

UDS - LDS Skew

-0.4 x tCK 0.4 x tCK -0.4 x tCK 0.4 x tCK -0.4 x tCK 0.4 x tCK

Data Input Setup Time from DS

Data Input Hold Time from DS

Command / Address Input Setup Time

Command / Address Input Hold Time

0.3

0.6

-

0.35

0.6

-

0.4

0.7

-

4

3

t_IH

0.6

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REV. 0.2 Aug. 2003

K4C89363AF

Target

AC Characteristics and Operating Conditions (Notes : 1, 2) (Continued)

F6

FB

F5

Symbol

Parameter

Units Notes

Min

-0.5

-

Max

Min

-0.5

-

Max

Min

-0.6

-

Max

t_LZ

Data-out Low Impedance Time from CLK

Data-out High Impedance Time from CLK

Last Output to PD High Hold Time

Power Down Exit Time

-

0.5

-

0.5

-

0.6

-

3, 6, 8

3, 7, 8

t_HZ

t_QPDH

t_PDEX

t_T

0

0.6

-

0.6

-

0.7

-

3

Input Transition Time

0.1

1

0.1

1

0.1

1

t_FPDL

t_REFI

t_PAUSE

-0.5*t_CK

PD Low Input Window for Self-Refresh Entry

Auto-Refresh Average Interval

Pause Time after Power-up

5

3

0.4

3.9

0.4

3.9

0.4

3.9

5

us

200

5

-

200

-

200

-

C_L= 4

C_L= 5

5

6

7

-

5

6

7

-

Random Read/Write Cycle Time

(Applicable to Same Bank)

6

I_RC

C

_L= 6

_L= 7

7

-

RDA/WRA to LAL Command Input Delay

(Applicable to Same Bank)

I_RCD

1

C

_L= 4

_L= 5

_L= 6

_L= 7

4

5

6

-

4

5

6

-

4

5

6

-

LAL to RDA/WRA Command Input Delay

(Applicable to Same Bank)

I_RAS

Random Bank Access Delay

(Applicable to Other Bank)

I_RBD

I_RWD

I_WRD

2

-

2

-

2

-

BL = 2

BL = 4

2

3

-

2

3

-

2

3

-

LAL following RDA to WRA Delay

(Applicable to Other Bank)

LAL following WRA to RDA Delay

(Applicable to Other Bank)

1

-

1

-

1

-

C_L= 4

7

-

7

-

7

-

Cycle

C

_L= 5

C_L= 6

_L= 7

I_RSC

Mode Register Set Cycle Time

C

I_PD

PD Low to Inactive State of Input Buffer

PD High to Active State of Input Buffer

-

2

-

2

-

2

I_PDA

1

-

1

-

1

-

C_L= 4

C_L= 5

19

23

25

19

23

25

19

23

25

Power down mode valid from REF com-

mand

I_PDV

C

_L= 6

_L= 7

C_L= 4

_L= 5

19

23

25

-

19

23

25

-

19

23

25

-

C

I_REFC

Auto-Refresh Cycle Time

C_L= 6

C_L= 7

REF Command to Clock Input Disable

at Self-Refresh Entry

I_CKD

I_REFC

200

I_REFC

200

I_REFC

200

-

I_LOCK

DLL Lock-on Time (Applicable to RDA command)

- 12 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

AC Test Conditions

Symbol

Parameter

Input high voltage (minimum)

Value

Units

Notes

V_IH(min)

V_REF+ 0.2

V

_IL(max)

V_REF

V_TT

V_REF- 0.2

Input low voltage (maximum)

Input reference voltage

VddQ/2

V_REF

V

Termination voltage

V

V_SWING

V_R

_ID(AC)

Input signal peak to peak swing

Differential clock input reference level

Input differential voltage

0.7

V

V_X(AC)

V

1.0

2.5

V

SLEW

V_OTR

Input signal minimum slew rate

Output timing measurement reference voltage

V/ns

V

VddQ/2

9

VddQ

V_TT

V_IHmin_(AC)

25 Ω

V_SWING

V_REF

Output

V_ILmax_(AC)

Measurement Point

Vss

∆T

AC Test Load

Slew=(V min

- V max

)/∆T

(AC)

IH

(AC)

IL

Notes : 1. Transition times are measured between V_IHmin_(DC)and V_ILmax_(DC)

.

Transition (rise and fall) of input signals have a fixed slope.

2. If the result of nominal calculation with regard to t_CKcontains more than

one decimal place, the result is rounded up to the nearest decimal place.

(i.e., t_DQSS= 0.8*t_CK, t_CK= 3.3ns, 0.8*3.3 ns = 2.64 ns is rounded up to 2.7 ns.)

3. These parameters are measured from the differential clock (CLK and CLK) AC cross point.

4. These parameters are measured from signal transition point of DS crossing V_REFlevel.

5. The t_REFI(MAX.) applies to equally distributed refresh method.

The t_REFI(MIN.) applies to both burst refresh method and distributed refresh method.

In such case, the average interval of eight consecutive Auto-Refresh commands has to be more than 400ns always. In

other words, the number of Auto- Refresh cycles which can be performed within 3.2us (8X400ns) is to 8 times in the

maximum.

6. Low Impedance State is speified at VddQ/2± 0.2V from steady state.

7. High Impedance State is specified where output buffer is no longer driven.

8. These parameters depend on the clock jitter. These parameters are measured at stable clock.

9. Output timing is measured by using Normal driver strength at V_DDQ= 1.7V ~ 1.9V.

Output timing is measured by using Strong driver strength at V_DDQ= 1.4V ~ 1.6V

- 13 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Power Up Sequence

1. As for PD, being maintained by the low state (<0.2V) is desirable before a power-supply injection.

2. Apply V_DDbefore or at the same time as V_DDQ

.

3. Apply V_DDQbefore or at the same time as V_REF

.

4. Start clock (CLK, CLK) and maintain stable condition for 200us (min.).

5. After stable power and clock, apply DESL and take PD = H.

6. Issue EMRS to enable DLL and to define driver strength and data strobe type. (Note : 1)

7. Issue MRS for set CAS Latency (CL), Burst Type (BT), and Burst Length (BL). (Note : 1)

8. Issue two or more Auto-Refresh commands. (Note:1)

9. Ready for normal operation after 200 clocks from Extended Mode Register programming.

Note : 1. Sequence 6, 7 and 8 can be issued in random order.

2. L=Logic Low, H = Logic High

3. DQ output is Hi-Z state during power up sequence.

2.5V(TYP)

V_DD

1.8V(TYP)

V_DDQ

0.9V(TYP)

V_REF

CLK

t

PDEX

I

l

REFC

PDA

RSC

REFC

200 µs(min)

PD

200 clock cycle(min)

Command

Address

DQ

DESL

RDA MRS DESL

op-code

RDA MRS

DESL WRA REF

DESL

WRA REF DESL

op-code

EMRS

MRS

L/UDS

Hi-Z

L/UQS

Low

(Uni-QS mode)

QS

(Free Running mode)

EMRS

MRS

Auto Refresh cycle

Normal Operation

- 14 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Basic Timing Diagrams

Input Timing

t_CK

Command and Address

t_CH

t_CL

t_CK

CK

t_IS

t_IH

t_IS

t_IH

1st

2nd

LA

CS

FN

t_IPW

t_IH

t_IS

1st

t_IPW

t_IH

t_IS

t_IH

A0-A14

BA0.BA1

UA, BA

Data

LDS/UDS

t_DS

t_DH

t_DS

t_DH

DQn (Input)

DQm (Input)

t_DS

t_DH

t_DS

t_DH

Refer to the Command Truth Table.

Timing of the CLK, CLK

t_CH

t_CL

V_IH

V_IH(AC)

CLK

V_IL(AC)

CLK

V_IL

t_T

t_CK

V_IH

V_IL

CLK

V_ID(AC)

V_X

- 15 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Read Timing (Burst Length = 4)

Unidirectional DS/QS mode

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

t_CH

t_CL

t_CK

CK

t_ISt_IH

(after RDA)

LAL

Input

(Control &

Addresses)

DESL

LDS/UDS

(Input)

t_CKQS

t_QSP

CAS latency = 4

LQS/UQS

(Output)

Low

t_QSQV

t_QSQ

t_LZ

t_QSQ

Q0

t_QSQV

t_HZ

DQ

High-Z

(Output)

Q1

t_AC

Q2

t_AC

Q3

t_AC

t_OH

t_CKQS

t_QSP

CAS latency = 5

LQS/UQS

(Output)

Low

t_QSQV

t_QSQ

t_LZ

t_QSQ

Q0

t_QSQV

t_HZ

DQ

High-Z

(Output)

Q1

t_AC

Q2

t_AC

Q3

t_AC

t_OH

t_CKQS

t_QSP

CAS latency = 6

LQS/UQS

(Output)

Low

t_QSQV

t_QSQ

t_LZ

t_QSQ

Q0

t_QSQV

t_HZ

DQ

High-Z

(Output)

Q1

t_AC

Q2

t_AC

Q3

t_AC

t_OH

Note : DQ0 to DQ17 are aligned with LQS.

DQ18 to DQ35 are aligned with UQS.

- 16 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Read Timing (Burst Length = 4)

Unidirectional DS/Free Running QS mode

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

t_CH

t_CL

t_CK

CK

t_ISt_IH

(after RDA)

LAL

Input

(Control &

Addresses)

DESL

LDS/UDS

(Input)

t_CKQS

t_QSP

CAS latency = 4

LQS/UQS

(Output)

t_QSQV

t_QSQ

t_LZ

t_QSQ

Q0

t_QSQV

t_HZ

DQ

High-Z

(Output)

Q1

t_AC

Q2

t_AC

Q3

t_AC

t_OH

t_CKQS

t_QSP

CAS latency = 5

LQS/UQS

(Output)

t_QSQV

t_QSQ

t_LZ

t_QSQ

Q0

t_QSQV

t_HZ

DQ

High-Z

(Output)

Q1

t_AC

Q2

t_AC

Q3

t_AC

t_OH

t_CKQS

t_QSP

CAS latency = 6

LQS/UQS

(Output)

t_QSQV

t_QSQ

t_LZ

t_QSQ

Q0

t_QSQV

t_HZ

DQ

High-Z

(Output)

Q1

t_AC

Q2

t_AC

Q3

t_AC

t_OH

Note : DQ0 to DQ17 are aligned with LQS.

DQ18 to DQ35 are aligned with UQS.

LQS/UQS is always asserted in Free Running QS mode.

- 17 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Write Timing (Burst Length = 4)

Unidirectional DS/QS mode, Unidirectional DS/Free Running QS mode

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

t_CH

t_CL

t_CK

CK

t_ISt_IH

(after RDA)

LAL

Input

(Control &

Addresses)

DESL

t_DSPSTH

t_DSS

t_DSPt_DSPST

t_DQSS

t_DSPRES

t_DSPREH

t_DSP

CAS latency = 4

LDS/UDS

(Input)

t_DSS

t_DS

Preamble

t_DSPRE

Postamble

t_DS

t_DH

Q2

t_DH

Q3

DQ

Q0

Q1

(Input)

t_DSS

t_DQSS

t_DSPRES

t_DSPREH

t_DSPSTH

t_DSS

t_DSP

t_DSPt_DSPST

CAS latency = 5

LDS/UDS

(Input)

Preamble

Postamble

t_DSPRE

t_DS

t_DH

Q0

t_DH

Q2

t_DH

Q3

DQ

Q1

(Input)

t_DSS

t_DSPSTH

t_DSPt_DSPST

t_DQSS

t_DSPRES

t_DSS

t_DSP

t_DSPREH

CAS latency = 6

LDS/UDS

(Input)

Preamble

Postamble

t_DSPRE

t_DS

t_DH

Q0

t_DH

Q2

t_DH

Q3

DQ

Q1

(Input)

LQS/UQS

(Uni-QS)

Low

LQS/UQS

(Free Runninig)

Note : DQ0 to DQ17 are sampled at both edges of LDS.

DQ18 to DQ35 are sampled at both edges of UDS.

- 18 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

t_REFI, t_PAUSE, Ixxxx Timing

CLK

t_IS

t_IH

t_{REFI, PAUSE, XXXX}

t

I

t_IS

t_IH

Input

(Control &

Addresses)

Command

Note. "I_XXXX"means "I_RC", "I_RCD", "I_RAS", etc.

- 19 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Function Truth Table (Notes : 1,2,3)

Command Truth Table (Notes : 4)

•The First Command

Symbol

Function

CS

H

FN

X

BA1-BA0

A13-A10

A9~A8

X

A7

X

A6-A0

X

DESL Device Deselect

X

RDA

Read with Auto-close

Write with Auto-close

L

H

BA

UA

WRA

L

UA

•The Second Command (The next clock of RDA or WRA command)

Symbol

LAL

Function

Lower Address Latch

CS

H

FN

X

BA1-BA0 A13-A12 A11-A10

A9

X

A8

A7 A6-A0

X

V

X

L

X

L

X

L

X

V

LA

X

REF

Auto-Refresh

L

X

MRS

Mode Register Set

L

X

L

V

Notes :1. L=Logic Low,H=Logic High,X=eitherL or H,V=Valid(SpecifiedValue),BA=Bank Address,UA=Upper Address,

LA = Lower Address.

2. All commands are assumed to issue at a valid state.

3. All inputs for command (excluding SELFX and PDEX) are latched on the crossing point of differential clock input where

CLK goes to High.

4. Operation mode is decided by the comination of 1st command and 2nd command refer to "STATE DIAGRAM" and the

command table below.

Read Command Table

Command (Symbol)

CS

L

FN

H

BA1-BA0

A13-A10 A9-A8

A7

UA

X

A6-A0

UA

Notes

RDA (1st)

LAL (2nd)

BA

X

UA

X

UA

X

H

X

LA

Write Command Table

BA1-

BA0

A9~

Command (Symbol)

CS

FN

A13

A12

UA

A11

A10

A7 A6-A0

A8

UA

X

WRA (1st)

LAL (2nd)

L

BA

X

UA

X

UA

X

UA

X

UA

LA

H

X

VW0 VW1

Notes : 5. A13~A12 are used for Variable Write Length (VW) control at Write Operation.

VW Truth Table

Function

Write All Words

VW0

L

VW1

X

BL = 2

BL = 4

Write First One Word

Reserved

H

X

L

Write All Words

H

L

Write First Two Words

Write First One Word

L

H

- 20 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Function Truth Table (Continued)

Mode Register Set Command Truth Table

Command (Symbol)

RDA (1st)

CS

L

FN

H

BA1-BA0

A13-A9

A8

X

A7

X

A6-A0

Notes

X

V

X

L

X

V

MRS (2nd)

L

X

L

V

6

Note : 6. Refer to "Mode Register Table".

Auto-Refresh Command Table

PD

Command

(Symbol)

Current

State

Function

CS

n

FN BA1-BA0 A13-A9

A8

A7

A6-A0 Notes

n-1

H

Active

Auto-Refresh

WRA(1st)

REF(2nd)

Standby

Active

H

L

X

H

X

Self-Refresh Command Table

PD

Command

Function

Current

State

BA1-

BA0

CS FN

A13-A9 A8 A7 A6-A0 Notes

(Symbol)

n-1

n

H

L

Active

WRA(1st)

REF(2nd)

-

Standby

Active

H

L

X

Self-Refresh Entry

Self-Refresh Continue

Self-Refresh Exit

7, 8

9

Self-Refresh

L

X

H

SELFX

L

H

Power Down Table

PD

Command

(Symbol)

Current

State

BA1-

BA0

Function

CS FN

A13-A9 A8

A7 A6-A0 Notes

n-1

H

n

L

Power Down Entry

Power Down Continue

Power Down Exit

PDEN

-

Standby

H

X

H

X

8

9

Power Down

L

PDEX

L

H

Notes : 7. PD has to be brought to Low within t_FPDLfrom REF command.

8. PD should be brought to Low after DQ’s state turned high impedance.

9. When PD is brought to High from Low, this function is executed asynchronously.

- 21 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Function Truth Table (Continued)

PD

Current State

CS

FN

Address

Command

Action

Notes

n-1

H

L

n

H

L

H

L

X

H

L

X

DESL

RDA

WRA

PDEN

-

NOP

BA, UA

Row activate for Read

Row activate for Write

Power Down Entry

Illegal

L

BA, UA

Idle

H

L

X

H

L

X

10

L

X

H

L

X

H

L

X

-

Refer to Power Down state

Begin read

H

L

LA

LAL

Op-Code

MRS/EMRS Access to Mode Register

PDEN Illegal

MRS/EMRS Illegal

Row Active for Read

Row Active for Write

H

L

X

L

X

H

L

X

H

L

X

-

Invalid

H

L

LA

LAL

Begin Write

Auto-Refresh

Illegal

X

REF

PDEN

H

L

X

L

X

REF (Self) Self-Refresh entry

X

H

L

X

H

L

X

-

Invalid

H

L

X

DESL

RDA

WRA

PDEN

-

Continue burst read to end

BA, UA

Illegal

11

L

BA, UA

Illegal

Read

Write

H

L

X

H

L

X

Illegal

L

X

Illegal

X

H

L

X

H

L

X

-

Invalid

H

L

X

DESL

RDA

WRA

PDEN

-

Data write & continue burst write to end

BA, UA

Illegal

11

L

BA, UA

Illegal

H

L

X

Illegal

L

Illegal

X

H

X

H

-

Invalid

H

DESL

NOP-> Idle after I_REFC

H

L

H

L

H

L

BA, UA

RDA

WRA

PDEN

-

Illegal

BA, UA

Illegal

Auto-Refreshing

H

L

X

Self-Refresh entry

Illegal

12

L

X

H

X

H

-

Refer to Self-Refreshing state

Nop-> Idle after I_RSC

H

DESL

H

L

H

L

H

L

BA, UA

RDA

Illegal

BA, UA

WRA

Illegal

Mode Register Accessing

H

L

X

PDEN

Illegal

L

-

Illegal

X

L

X

H

-

Invalid

H

L

-

Invalid

Maintain Power Down Mode

Exit Power Down Mode->Idle after t_PDEX

Power Down

L

H

RDEX

L

H

L

H

X

L

X

H

X

-

Illegal

-

Invalid

-

Maintain Self-Refresh

Exit Self-Refresh->Idle after I_REFC

Se;f-Refreshing

L

H

SELFX

L

H

L

X

-

Illegal

Notes : 10. Illegal if any bank is not idle.

11. Illegal to bank in specified states : Function may be Legal in the bank indicated by bank Address (BA).

12. Illegal if t_FPDLis not Stisfied.

- 22 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Mode Register Table

Regular Mode Register (Notes : 1)

Address

BA1^*1

BA0^*1

A7^*3

A13-A8

A6-A4

A3

A2-A0

Register

0

TM

CL

BT

BL

A7

0

Test Mode (TE)

Regular (Default)

Test Mode Entry

A3

0

Burst Type (BT)

Sequential

1

Interleave

A6

A5

A4

CAS Latency (CL)

A2

A1

A0

Burst Length (BL)

Reserved ^*2

0

X

0

1

0

1

0

1

0

1

X

1

0

1

X

2

4

Reserved ^*2

4

1

0

1

Reserved ^*2

5

6

1

0

1

Reserved ^*2

Extended Mode Register (Notes : 4)

BA1^*4

BA0^*4

A0^*5

Address

A13-A7

A6~A5

A4-A3

A2~A1

Register

0

1

0

SS

DIC(QS)

DIC(DQ)

DS

A6

A5

Strobe Select

Reserved^*2

QS

DQ

A1

0

Output Driver Impedance Control

(DIC)

0

A4

0

A3

A2

0

1

0

1

Normal Output Driver

Strong Output Driver

Weak Output Driver

Reserved

0

1

0

1

0

1

Unidirectional DS/QS

1

0

Unidirectional DS/Free Running QS

1

Note : 1. Regular Mode Register Is Chosen Using the combination of BA0 = 0 and BA1 = 0.

2. "Reserved" places in Regular Mode Register should not be set.

A0

0

DLL Switch (DS)

DLL Enable

3. A7 in Regular Mode Register must be set to "0"(Low state).

Because Test Mode is specific mode for supplier.

1

DLL Disable

4. Extended Mode Register is chosen using the Combination of BA0 = 1 and BA1 = 0.

5. A0 in Extended Mode Register must be set to "0" to enable DLL for normal operation.

- 23 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

State Diagram

Self

Refresh

Power

Down

PDEX

SELFX

(PD = H)

PDEN

(PD = L)

PD = L

Standby

(Idle)

PD = H

Auto-

Refresh

Mode

Register

WRA

RDA

REF

MRS

Active

(Restore)

Active

LAL

Write

(Buffer)

Read

Command Input

Automatic Return

The second command at Active

state must be issued 1clock after

RDA or WRA command input

- 24 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Timing Diagrams

Single Bank Read Timing (CL=4)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

l_RC=5cycles

DESL

l_RC=5cycles

DESL

l_RC=5cycles

DESL

Command

Address

RDA

LAL

RDA

LAL

RDA

LAL

RDA

UA

l_RCD=1cycle

l_RAS=4cycles

l_RCD=1cycle

l_RAS=4cycles

l_RCD=1cycle

l_RAS=4cycles

UA

LA

UA

LA

UA

LA

Bank Add.

#0

Unidirectional DS/QS mode

BL =2

LDS/UDS

(Input)

LQS/UQS

(Output)

Low

CL=4

Hi-Z

DQ

(Output)

Q0 Q1

Q0

BL =4

LDS/UDS

(Input)

LQS/UQS

(Output)

Low

Hi-Z

CL=4

DQ

Q0 Q1 Q2 Q3

Q0

(Output)

Unidirectional DS/Free Running QS mode

BL =2

LDS/UDS

(Input)

LQS/UQS

(Output)

CL=4

Hi-Z

DQ

(Output)

Q0 Q1

Q0

BL =4

LDS/UDS

(Input)

LQS/UQS

(Output)

CL=4

Hi-Z

DQ

(Output)

Q0

Q0 Q1 Q2 Q3

- 25 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Single Bank Read Timing (CL=5)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

l_RC=6cycles

Command

Address

RDA

LAL

DESL

RDA

LAL

DESL

RDA

LAL

LA

DESL

l_RCD=1cycle

l_RAS=5cycles

l_RCD=1cycle

l_RAS=5cycles

l_RCD=1cycle

UA

LA

UA

#0

LA

UA

#0

Bank Add.

#0

Unidirectional DS/QS mode

BL =2

LDS/UDS

(Input)

LQS/UQS

(Output)

Low

Hi-Z

CL=5

DQ

(Output)

Q0 Q1

BL =4

LDS/UDS

(Input)

LQS/UQS

(Output)

Low

Hi-Z

CL=5

DQ

Q0 Q1 Q2 Q3

(Output)

Unidirectional DS/Free Running QS mode

BL =2

LDS/UDS

(Input)

LQS/UQS

(Output)

CL=5

Hi-Z

DQ

(Output)

Q0 Q1

BL =4

LDS/UDS

(Input)

LQS/UQS

(Output)

CL=5

Hi-Z

DQ

(Output)

Q0 Q1 Q2 Q3

- 26 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Single Bank Read Timing (CL=6)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

l_RC=7cycles

DESL

l_RC=7cycles

DESL

Command

Address

RDA

LAL

RDA

LAL

RDA

LAL

l_RCD=1cycle

l_RAS=6cycles

l_RCD=1cycle

l_RAS=6cycles

l_RCD=1cycle

UA

LA

UA

#0

LA

UA

#0

LA

Bank Add.

#0

Unidirectional DS/QS mode

BL =2

LDS/UDS

(Input)

LQS/UQS

(Output)

Low

CL=6

Hi-Z

DQ

(Output)

Q0 Q1

BL =4

LDS/UDS

(Input)

LQS/UQS

(Output)

Low

Hi-Z

CL=6

DQ

Q0 Q1 Q2 Q3

Q0 Q1 Q2

(Output)

Unidirectional DS/Free Running QS mode

BL =2

LDS/UDS

(Input)

LQS/UQS

(Output)

CL=6

Hi-Z

DQ

(Output)

Q0 Q1

BL =4

LDS/UDS

(Input)

LQS/UQS

(Output)

CL=6

Hi-Z

DQ

(Output)

Q0 Q1 Q2 Q3

Q0 Q1 Q2

- 27 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Single Bank Write Timing (CL=4)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

l_RC=5cycles

DESL

l_RC=5cycles

DESL

l_RC=5cycles

DESL

Command

Address

WRA

LAL

WRA

LAL

WRA

LAL

WRA

UA

l_RCD=1cycle

l_RAS=4cycles

l_RCD=1cycle

l_RAS=4cycles

l_RCD=1cycle

l_RAS=4cycles

UA

LA

UA

LA

UA

LA

Bank Add.

#0

Unidirectional DS/QS mode

BL =2

LDS/UDS

(Input)

LQS/UQS

(Output)

Low

WL=3

DQ

(Output)

D0 D1

BL =4

LDS/UDS

(Input)

LQS/UQS

(Output)

Low

DQ

(Output)

D0 D1 D2 D3

Unidirectional DS/Free Running QS mode

BL =2

LDS/UDS

(Input)

LQS/UQS

(Output)

DQ

(Output)

D0 D1

BL =4

LDS/UDS

(Input)

LQS/UQS

(Output)

DQ

(Output)

D0 D1 D2 D3

- 28 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Single Bank Write Timing (CL=5)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

l_RC=6cycles

Command

Address

WRA

LAL

DESL

WRA

LAL

DESL

WRA

LAL

DESL

l_RCD=1cycle

l_RAS=5cycles

l_RCD=1cycle

l_RAS=5cycles

l_RCD=1cycle

UA

LA

UA

LA

UA

LA

Bank Add.

#0

Unidirectional DS/QS mode

BL =2

LDS/UDS

(Input)

LQS/UQS

(Output)

Low

WL=4

DQ

(Output)

D0 D1

BL =4

LDS/UDS

(Input)

LQS/UQS

(Output)

Low

DQ

(Output)

D0 D1 D2 D3

Unidirectional DS/Free Running QS mode

BL =2

LDS/UDS

(Input)

LQS/UQS

(Output)

DQ

(Output)

D0 D1

BL =4

LDS/UDS

(Input)

LQS/UQS

(Output)

DQ

(Output)

D0 D1 D2 D3

- 29 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Single Bank Write Timing (CL=6)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

l_RC=7cycles

WRA

LAL

DESL

WRA

LAL

DESL

WRA

LAL

Command

Address

l_RCD=1cycle

l_RAS=6cycles

l_RCD=1cycle

l_RAS=6cycles

l_RCD=1cycle

UA

LA

UA

#0

LA

UA

#0

LA

Bank Add.

#0

Unidirectional DS/QS mode

BL =2

LDS/UDS

(Input)

LQS/UQS

(Output)

Low

WL=5

DQ

(Output)

D0 D1

BL =4

LDS/UDS

(Input)

LQS/UQS

(Output)

Low

WL=5

DQ

(Output)

D0 D1 D2 D3

Unidirectional DS/Free Running QS mode

BL =2

LDS/UDS

(Input)

LQS/UQS

(Output)

WL=5

DQ

(Output)

D0 D1

BL =4

LDS/UDS

(Input)

LQS/UQS

(Output)

WL=5

DQ

(Output)

D0 D1 D2 D3

- 30 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Single Bank Read-Write Timing (CL=4)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

l_RC=5cycles

DESL

l_RC=5cycles

DESL

l_RC=5cycles

DESL

Command

Address

RDA

UA

LAL

LA

WRA

UA

LAL

LA

RDA

UA

LAL

LA

WRA

UA

Bank Add.

#0

Unidirectional DS/QS mode

BL =2

LDS/UDS

(Input)

LQS/UQS

(Output)

Low

CL=4

WL=3

CL=4

Hi-Z

DQ

(Output)

Q0 Q1

D0 D1

Q0

BL =4

LDS/UDS

(Input)

LQS/UQS

(Output)

Low

Hi-Z

CL=4

WL=3

CL=4

DQ

Q0 Q1 Q2 Q3

D0 D1 D2 D3

Q0

(Output)

Unidirectional DS/Free Running QS mode

BL =2

LDS/UDS

(Input)

LQS/UQS

(Output)

CL=4

WL=3

CL=4

Hi-Z

DQ

(Output)

Q0 Q1

D0 D1

BL =4

LDS/UDS

(Input)

LQS/UQS

(Output)

CL=4

WL=3

CL=4

Hi-Z

DQ

(Output)

Q0 Q1 Q2 Q3

D0 D1 D2 D3

- 31 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Single Bank Read-Write Timing (CL=5)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

l_RC=6cycles

Command

Address

RDA

UA

LAL

LA

DESL

WRA

UA

LAL

LA

DESL

RDA

UA

LAL

LA

DESL

Bank Add.

#0

Unidirectional DS/QS mode

BL =2

LDS/UDS

(Input)

LQS/UQS

(Output)

Low

CL=5

WL=4

Hi-Z

DQ

(Output)

Q0 Q1

D0 D1

BL =4

LDS/UDS

(Input)

LQS/UQS

(Output)

Low

Hi-Z

CL=5

WL=4

DQ

Q0 Q1 Q2 Q3

D0 D1 D2 D3

(Output)

Unidirectional DS/Free Running QS mode

BL =2

LDS/UDS

(Input)

LQS/UQS

(Output)

CL=5

WL=4

Hi-Z

DQ

(Output)

Q0 Q1

D0 D1

BL =4

LDS/UDS

(Input)

LQS/UQS

(Output)

CL=5

WL=4

Hi-Z

DQ

Q0 Q1 Q2 Q3

Read data

D0 D1 D2 D3

Write data

(Output)

- 32 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Single Bank Read-Write Timing (CL=6)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

l_RC=7cycles

RDA

UA

LAL

LA

DESL

WRA

UA

LAL

LA

DESL

RDA

UA

LAL

LA

Command

Address

Bank Add.

#0

Unidirectional DS/QS mode

BL =2

LDS/UDS

(Input)

LQS/UQS

(Output)

Low

CL=6

WL=5

Hi-Z

DQ

(Output)

Q0 Q1

D0 D1

BL =4

LDS/UDS

(Input)

LQS/UQS

(Output)

Low

Hi-Z

CL=6

WL=5

DQ

Q0 Q1 Q2 Q3

D0 D1 D2 D3

(Output)

Unidirectional DS/Free Running QS mode

BL =2

LDS/UDS

(Input)

LQS/UQS

(Output)

CL=6

WL=5

Hi-Z

DQ

(Output)

Q0 Q1

D0 D1

BL =4

LDS/UDS

(Input)

LQS/UQS

(Output)

CL=6

WL=5

Hi-Z

DQ

Q0 Q1 Q2 Q3

Read data

D0 D1 D2 D3

Write data

(Output)

- 33 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Multiple Bank Read Timing (CL=4)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

l_RBD=2cycles

LAL

l_RBD=2cycles

LAL

l_RBD=2cycles

LAL

l_RBD=2cycles

LAL

l_RBD=2cycles

LAL

RDA

UA

RDA

UA

LAL

LA

DESL

RDA

UA

RDA

UA

RDA

UA

RDA

UA

RDA

UA

LAL

LA

RDA

UA

Command

Address

LA

Bank

"a"

Bank

"b"

Bank

"a"

Bank

"b"

Bank

"c"

Bank

"d"

Bank

"a"

Bank

"b"

Bank Add.

l_RC(Bank"a")=5cycles

Unidirectional DS/QS mode

BL =2

LDS/UDS

(Input)

Low

LQS/UQS

(Output)

CL=4

Hi-Z

DQ

(Output)

Qa0 Qa1

Qb0 Qb1

Qa0 Qa1

Qb0 Qb1

Qc0 Qc1

BL =4

LDS/UDS

(Input)

Low

Hi-Z

LQS/UQS

(Output)

CL=4

DQ

(Output)

Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3

Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Qc0 Qc1 Qc2

Unidirectional DS/Free Running QS mode

BL =2

LDS/UDS

(Input)

LQS/UQS

(Output)

CL=4

Hi-Z

DQ

Qa0 Qa1

Qb0 Qb1

Qa0 Qa1

Qb0 Qb1

Qc0 Qc1

(Output)

BL =4

LDS/UDS

(Input)

LQS/UQS

(Output)

CL=4

Hi-Z

DQ

(Output)

Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3

Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Qc0 Qc1 Qc2

Note : l_RCto the same bank must be satisfied

- 34 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Multiple Bank Read Timing (CL=5)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

l_RBD=2cycles

LAL

l_RBD=2cycles

LAL

l_RBD=2cycles

LAL

l_RBD=2cycles

LAL

l_RBD=2cycles

LAL

RDA

UA

RDA

UA

LAL

LA

DESL

RDA

UA

RDA

UA

RDA

UA

RDA

UA

RDA

UA

LAL

LA

Command

Address

LA

Bank

"a"

Bank

"b"

Bank

"a"

Bank

"b"

Bank

"c"

Bank

"d"

Bank

"a"

Bank Add.

l_RC(Bank"a")=6cycles

Unidirectional DS/QS mode

BL =2

LDS/UDS

(Input)

Low

LQS/UQS

(Output)

CL=5

Hi-Z

DQ

(Output)

Qa0 Qa1

Qb0 Qb1

Qa0 Qa1

Qb0 Qb1

BL =4

LDS/UDS

(Input)

Low

Hi-Z

LQS/UQS

(Output)

CL=5

DQ

(Output)

Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3

Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2

Unidirectional DS/Free Running QS mode

BL =2

LDS/UDS

(Input)

LQS/UQS

(Output)

CL=5

Hi-Z

DQ

(Output)

Qa0 Qa1

Qb0 Qb1

Qa0 Qa1

Qb0 Qb1

BL =4

LDS/UDS

(Input)

LQS/UQS

(Output)

CL=5

Hi-Z

DQ

(Output)

Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3

Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2

- 35 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Multiple Bank Read Timing (CL=6)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

l_RBD=2cycles

LAL

l_RBD=2cycles

LAL

l_RBD=2cycles

LAL

l_RBD=2cycles

LAL

l_RBD=2cycles

LAL

RDA

UA

RDA

UA

LAL

LA

DESL

RDA

UA

RDA

UA

RDA

UA

RDA

UA

RDA

UA

Command

Address

LA

Bank

"a"

Bank

"b"

Bank

"a"

Bank

"b"

Bank

"c"

Bank

"d"

Bank

"a"

Bank Add.

l_RC(Bank"a")=7cycles

Unidirectional DS/QS mode

BL =2

LDS/UDS

(Input)

Low

LQS/UQS

(Output)

CL=6

Hi-Z

DQ

(Output)

Qa0 Qa1

Qb0 Qb1

Qa0 Qa1

BL =4

LDS/UDS

(Input)

Low

Hi-Z

LQS/UQS

(Output)

CL=6

DQ

(Output)

Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3

Qa0 Qa1 Qa2

Unidirectional DS/Free Running QS mode

BL =2

LDS/UDS

(Input)

LQS/UQS

(Output)

CL=6

Hi-Z

DQ

(Output)

Qa0 Qa1

Qb0 Qb1

Qa0 Qa1

BL =4

LDS/UDS

(Input)

LQS/UQS

(Output)

CL=6

Hi-Z

DQ

(Output)

Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3

Qa0 Qa1 Qa2

- 36 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Multiple Bank Write Timing (CL=4)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

l_RBD=2cycles

LAL

l_RBD=2cycles

LAL

l_RBD=2cycles

LAL

l_RBD=2cycles

LAL

l_RBD=2cycles

LAL

WRA

UA

WRA

UA

LAL

LA

DESL

WRA

UA

WRA

UA

WRA

UA

WRA

UA

WRA

UA

LAL

LA

WRA

UA

Command

Address

LA

Bank

"a"

Bank

"b"

Bank

"a"

Bank

"b"

Bank

"c"

Bank

"d"

Bank

"a"

Bank

"b"

Bank Add.

l_RC(Bank"a")=5cycles

l_RC(Bank"b")=5cycles

Unidirectional DS/QS mode

BL =2

LDS/UDS

(Input)

Low

LQS/UQS

(Output)

WL=3

DQ

(Output)

Da0 Da1

Db0 Db1

Da0 Da1

Db0 Db1

Dc0 Dc1

Dd0 Dd1

BL =4

LDS/UDS

(Input)

Low

LQS/UQS

(Output)

WL=3

DQ

(Output)

Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3

Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Dc0 Dc1 Dc2 Dc3 Dd0 Dd1

Unidirectional DS/Free Running QS mode

BL =2

LDS/UDS

(Input)

LQS/UQS

(Output)

WL=3

DQ

(Output)

Da0 Da1

Db0 Db1

Da0 Da1

Db0 Db1

Dc0 Dc1

Dd0 Dd1

BL =4

LDS/UDS

(Input)

LQS/UQS

(Output)

WL=3

DQ

(Output)

Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3

Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Dc0 Dc1 Dc2 Dc3 Dd0 Dd1

- 37 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Multiple Bank Write Timing (CL=5)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

l_RBD=2cycles

LAL

l_RBD=2cycles

LAL

l_RBD=2cycles

LAL

l_RBD=2cycles

LAL

l_RBD=2cycles

LAL

WRA

UA

WRA

UA

LAL

LA

DESL

WRA

UA

WRA

UA

WRA

UA

WRA

UA

WRA

UA

LAL

LA

Command

Address

LA

Bank

"a"

Bank

"b"

Bank

"a"

Bank

"b"

Bank

"c"

Bank

"d"

Bank

"a"

Bank Add.

l_RC(Bank"a")=6cycles

l_RC(Bank"b")=6cycles

Unidirectional DS/QS mode

BL =2

LDS/UDS

(Input)

Low

LQS/UQS

(Output)

WL=4

DQ

(Output)

Da0 Da1

Db0 Db1

Da0 Da1

Db0 Db1

Dc0 Dc1

BL =4

LDS/UDS

(Input)

Low

LQS/UQS

(Output)

WL=4

DQ

(Output)

Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3

Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Dc0 Dc1

Unidirectional DS/Free Running QS mode

BL =2

LDS/UDS

(Input)

LQS/UQS

(Output)

WL=4

DQ

(Output)

Da0 Da1

Db0 Db1

Da0 Da1

Db0 Db1

Dc0 Dc1

BL =4

LDS/UDS

(Input)

LQS/UQS

(Output)

WL=4

DQ

(Output)

Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3

Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Dc0 Dc1

Note :I_RCto the same bank must be satisfied.

- 38 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Multiple Bank Write Timing (CL=6)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

l_RBD=2cycles

LAL

l_RBD=2cycles

LAL

l_RBD=2cycles

LAL

l_RBD=2cycles

LAL

l_RBD=2cycles

LAL

WRA

UA

WRA

UA

LAL

LA

DESL

WRA

UA

WRA

UA

WRA

UA

WRA

UA

WRA

UA

Command

Address

LA

Bank

"a"

Bank

"b"

Bank

"a"

Bank

"b"

Bank

"c"

Bank

"d"

Bank

"a"

Bank Add.

l_RC(Bank"a")=7cycles

Unidirectional DS/QS mode

BL =2

LDS/UDS

(Input)

Low

LQS/UQS

(Output)

WL=5

DQ

(Output)

Da0 Da1

Db0 Db1

Da0 Da1

Db0 Db1

BL =4

LDS/UDS

(Input)

Low

LQS/UQS

(Output)

WL=5

DQ

(Output)

Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3

Da0 Da1 Da2 Da3 Db0 Db1

Unidirectional DS/Free Running QS mode

BL =2

LDS/UDS

(Input)

LQS/UQS

(Output)

WL=5

DQ

(Output)

Da0 Da1

Db0 Db1

Da0 Da1

Db0 Db1

BL =4

LDS/UDS

(Input)

LQS/UQS

(Output)

WL=5

DQ

(Output)

Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3

Da0 Da1 Da2 Da3 Db0 Db1

Note :I_RCto the same bank must be satisfied.

- 39 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Multiple Bank Read-Write Timing (BL=2)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

l_RBD=2cycles

LAL

WRA

UA

RDA

UA

LAL

LA

DESL

WRA

UA

LAL

LA

RDA

UA

LAL

LA

DESL

WRA

UA

LAL

LA

RDA

UA

LAL

LA

DESL

WRA

UA

Command

Address

LA

Bank

"a"

Bank

"b"

Bank

"c"

Bank

"d"

Bank

"a"

Bank

"b"

Bank

"c"

Bank Add.

l_RC(Bank"a")

Unidirectional DS/QS mode

CL =4

LDS/UDS

(Input)

Low

LQS/UQS

(Output)

CL=4

Da0 Da1

WL=3

Hi-Z

DQ

Qb0 Qb1

Dc0 Dc1

Qd0 Qd1

Da0 Da1

(Output)

CL =5

LDS/UDS

(Input)

Low

Hi-Z

LQS/UQS

(Output)

CL=5

Da0 Da1

WL=4

DQ

Qb0 Qb1

Dc0 Dc1

Qd0 Qd1

Da0 Da1

(Output)

CL =6

LDS/UDS

(Input)

Low

Hi-Z

LQS/UQS

(Output)

CL=6

WL=5

DQ

Da0 Da1

Qb0 Qb1

Dc0 Dc1

Qd0 Qd1

(Output)

Note :I_RCto the same bank must be satisfied.

- 40 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Multiple Bank Read-Write Timing (BL=2)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

l_RBD=2cycles

LAL

WRA

UA

RDA

UA

LAL

LA

DESL

WRA

UA

LAL

LA

RDA

UA

LAL

LA

DESL

WRA

UA

LAL

LA

RDA

UA

LAL

LA

DESL

WRA

UA

Command

Address

LA

Bank

"a"

Bank

"b"

Bank

"c"

Bank

"d"

Bank

"a"

Bank

"b"

Bank

"c"

Bank Add.

l_RC(Bank"a")

Unidirectional DS/Free Running QS mode

CL =4

LDS/UDS

(Input)

LQS/UQS

(Output)

CL=4

Da0 Qa1

WL=3

Hi-Z

DQ

Qb0 Qb1

Dc0 Qc1

Qd0 Qd1

Da0 Da1

(Output)

CL =5

LDS/UDS

(Input)

LQS/UQS

(Output)

CL=5

Da0 Da1

WL=4

Hi-Z

DQ

Qb0 Qb1

Dc0 Dc1

Qd0 Qd1

Da0 Da1

(Output)

CL =6

LDS/UDS

(Input)

LQS/UQS

(Output)

CL=6

WL=5

Hi-Z

DQ

Da0 Da1

Qb0 Qb1

Dc0 Dc1

Qd0 Qd1

(Output)

Note :I_RCto the same bank must be satisfied.

- 41 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Multiple Bank Read-Write Timing (BL=4)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

l_RBD=2cycles

LAL

WRA

UA

RDA

LAL

LA

DESL

l_RWD=3cycles

WRA

UA

LAL

RDA

LAL

LA

DESL

WRA

UA

LAL

RDA

LAL

LA

Command

l_WRD=1cycle

l_RWD=3cycles

l_WRD=1cycle

Address

LA

UA

LA

UA

LA

UA

Bank

"a"

Bank

"b"

Bank

"c"

Bank

"d"

Bank

"a"

Bank

"b"

Bank Add.

l_RC(Bank"a")

Unidirectional DS/QS mode

CL =4

LDS/UDS

(Input)

Low

LQS/UQS

(Output)

CL=4

Da0 Da1 Da2 Da3

WL=3

Hi-Z

DQ

Qb0 Qb1 Qb2 Qb3

Da0 Da1 Da2 Da3

Qb0 Qb1 Qb2 Qb3

(Output)

CL =5

LDS/UDS

(Input)

Low

Hi-Z

LQS/UQS

(Output)

CL=5

Da0 Da1 Da2 Da3

WL=4

DQ

Qb0 Qb1 Qb2 Qb3

Da0 Da1 Da2 Da3

Qb0 Qb1 Qb2 Qb3

(Output)

CL =6

LDS/UDS

(Input)

Low

Hi-Z

LQS/UQS

(Output)

CL=6

WL=5

DQ

Da0 Da1

Qb0 Qb1 Qb2 Qb3

Da0 Da1

Qb0 Qb1

Da2 Da3

(Output)

Note :I_RCto the same bank must be satisfied.

- 42 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Multiple Bank Read-Write Timing (BL=4)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

l_RBD=2cycles

LAL

WRA

UA

RDA

LAL

LA

DESL

l_RWD=3cycles

WRA

UA

LAL

RDA

LAL

LA

DESL

WRA

UA

LAL

RDA

LAL

LA

Command

l_WRD=1cycle

l_RWD=3cycles

l_WRD=1cycle

Address

LA

UA

LA

UA

LA

UA

Bank

"a"

Bank

"b"

Bank

"c"

Bank

"d"

Bank

"a"

Bank

"b"

Bank Add.

l_RC(Bank"a")

Unidirectional DS/Free Running QS mode

CL =4

LDS/UDS

(Input)

LQS/UQS

(Output)

CL=4

Da0 Da1 Da2 Da3

WL=3

WL=4

WL=5

Hi-Z

DQ

Qb0 Qb1 Qb2 Qb3

Da0 Da1 Da2 Da3

Qb0 Qb1 Qb2 Qb3

(Output)

CL =5

LDS/UDS

(Input)

LQS/UQS

(Output)

CL=5

Da0 Da1 Da2 Da3

Hi-Z

DQ

Qb0 Qb1 Qb2 Qb3

Da0 Da1 Da2 Da3

Qb0 Qb1 Qb2 Qb3

(Output)

CL =6

LDS/UDS

(Input)

LQS/UQS

(Output)

CL=6

Hi-Z

DQ

Da0 Da1 Da2 Da3

Qb0 Qb1 Qb2 Qb3

Da0 Da1 Da2 Da3

Qb0 Qb1

(Output)

Note :I_RCto the same bank must be satisfied.

- 43 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Write with Variable Write Length (VW) Control(CL=4)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

BL=2, SEQUENTIAL MODE

WRA

LAL

DESL

WRA

UA

LAL

DESL

Command

Address

LA=#3

VW=All

LA=#1

VW=1

UA

VW0 = Low

VW1 = don’t care

VW0 = High

VW1 = don’t care

Bank

"a"

Bank

"a"

Bank Add.

LDS/UDS

(Input)

LQS/UQS

(Input)

D0 D1

D0

Lower Address #3 #2

#1 (#0)

Last one data is masked.

BL=4, SEQUENTIAL MODE

WRA

LAL

DESL

WRA

UA

LAL

DESL

WRA

UA

LAL

DESL

Command

LA=#3

VW=All

LA=#1

VW=1

LA=#2

VW=2

UA

Address

VW0 = High

VW1 = Low

VW0 = High

VW1 = High

VW0 = Low

VW1 = High

Bank

"a"

Bank

"a"

Bank

"a"

Bank Add.

LDS/UDS

(Input)

LQS/UQS

(Input)

D0 D1 D2 D3

Lower Address #3 #0 #1 #2

D0

D0 D1

#1 (#2) (#3) (#0)

Last three data are masked.

#2 #3 (#0) (#1)

Last two data are masked.

Note : DS input must be continued till end of burst count even if some of laster data is masked.

- 44 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Power Down Timing (CL=4, BL=4)

Read cycle to Power Down Mode

0

1

2

3

4

5

6

7

8

9

10

n-1

n

n+1

n+2

n+3

CLK

BL=2, SEQUENTIAL MODE

RDA

or

RDA

LAL

DESL

Command

Address

WRA

I_PDA

UA

LA

UA

I_PD=2 cycle

t_IS

t_IH

PD

t_QPDH

t_PDEX

I_RC(min),t_REFI(max)

Unidirectional DS/QS mode

LDS/UDS

(Input)

LQS/UQS

(Output)

Low

CL=4

Hi-Z

DQ

(Output)

Q0 Q1 Q2 Q3

Unidirectional DS/Free Running QS mode

LDS/UDS

(Input)

LQS/UQS

(Output)

CL=4

Hi-Z

DQ

(Output)

Q0 Q1 Q2 Q3

Power Down Entry

Power Down Exit

Note :

PD must be kept "High" level until end of Burst data output.

PD should be brought to "High" within t_REFI(max.) to maintain the data written into cell.

In Power Down Mode, PD "Low" and a stable clock signal must be maintained.

When PD is brought to "High", a valid executable command may be applied I_PDAcycles later.

- 45 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Power Down Timing (CL=4, BL=4)

Write cycle to Power Down Mode

0

1

2

3

4

5

6

7

8

9

10

n-1

n

n+1

n+2

n+3

CLK

I_PDA

RDA

or

WRA

UA

LAL

LA

DESL

Command

Address

WRA

UA

I_PD=2 cycle

t_IS

t_IH

PD

t_PDEX

I_PD=2 cycle

WL=3

I_RC(min),t_REFI(max)

Unidirectional DS/QS mode

LDS/UDS

(Input)

Low

LQS/UQS

(Output)

WL=3

DQ

(Output)

D0 D1 D2 D3

Unidirectional DS/Free Running QS mode

LDS/UDS

(Input)

LQS/UQS

(Output)

WL=3

DQ

(Output)

D0 D1 D2 D3

Note :

PD must be kept "High" level until end of Burst data output.

PD should be brought to "High" within t_REFI(max.) to maintain the data written into cell.

In Power Down Mode, PD "Low" and a stable clock signal must be maintained.

When PD is brought to "High", a valid executable command may be applied I_PDAcycles later.

- 46 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Mode Register Set Timing (CL=4, BL=2)

From Read operation to Mode Register Set operation

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

l_RC=7cycles

RDA

or

RDA

UA

LAL

LA

DESL

RDA

MRS

DESL

LAL

LA

Command

A14~A0

WRA

Valid

(opcode)

UA

BA0="0"

BA1="0"

BA0, BA1

BA

CL + BL/2

Unidirectional DS/QS mode

LDS/UDS

(Input)

Low

LQS/UQS

(Output)

DQ

(Output)

Q0 Q1

Unidirectional DS/Free Running QS mode

LDS/UDS

(Input)

LQS/UQS

(Output)

DQ

(Output)

Q0 Q1

Note : Minimum delay from LAL following RDA to RDA of MRS operation is CL+BL/2.

- 47 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Mode Register Set Timing (CL=4, BL=4)

From Write operation to Mode Register Set operation

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

l_RC=7cycles

RDA

or

WRA

UA

LAL

LA

DESL

RDA

MRS

DESL

LAL

LA

Command

A14~A0

WRA

Valid

(opcode)

UA

BA0="0"

BA1="0"

BA0, BA1

BA

WL + BL/2

Unidirectional DS/QS mode

LDS/UDS

(Input)

Low

LQS/UQS

(Output)

DQ

(Output)

D0 D1 D2 D3

Unidirectional DS/Free Running QS mode

LDS/UDS

(Input)

LQS/UQS

(Output)

DQ

(Output)

D0 D1 D2 D3

Note : Minimum delay from LAL following WRA to RDA of MRS operation is WL+BL/2.

- 48 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Extended Mode Register Set Timing (CL=4, BL=2)

From Read operation to Extended Mode Register Set operation

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

l_RC=7cycles

RDA

or

RDA

UA

LAL

LA

DESL

RDA

MRS

DESL

LAL

LA

Command

A14~A0

WRA

Valid

(opcode)

UA

BA0="0"

BA1="0"

BA0, BA1

BA

CL + BL/2

Unidirectional DS/QS mode

LDS/UDS

(Input)

LQS/UQS

(Output)

Low

DQ

(Output)

Q0 Q1

Unidirectional DS/Free Running QS mode

LDS/UDS

(Input)

LQS/UQS

(Output)

DQ

(Output)

Q0 Q1

Note :

Minimum delay from LAL following RDA to RDA of EMRS operation is CL+BL/2.

When DQ strobe mode is changed by EMRS, QS output is invalid for I_RSCperiod.

DLL switch in Extended Mode Register must be set to enable mode for normal operation.

DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence.

- 49 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Extended Mode Register Set Timing (CL=4, BL=4)

From Write operation to Extended Mode Register Set operation

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CLK

l_RC=7cycles

RDA

or

WRA

UA

LAL

LA

DESL

RDA

MRS

DESL

LAL

LA

Command

A14~A0

WRA

Valid

(opcode)

UA

BA0="0"

BA1="0"

BA0, BA1

BA

WL + BL/2

Unidirectional DS/QS mode

LDS/UDS

(Input)

Low

LQS/UQS

(Output)

DQ

(Output)

D0 D1 D2 D3

Unidirectional DS/Free Running QS mode

LDS/UDS

(Input)

LQS/UQS

(Output)

DQ

(Output)

D0 D1 D2 D3

Note :

When DQ strobe mode is changed by EMRS, QS output is invalid for I_RSCperiod.

DLL switch in Extended Mode Register must be set to enable mode for normal operation.

DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence.

Minimum delay from LAL following WRA to RDA of EMRS operation is WL+BL/2.

- 50 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Auto-Refresh Timing (CL=4, BL=4)

Unidirectional DS/QS mode

0

1

2

3

4

5

6

7

n-1

n

n+1

n+2

CLK

l_RC=5cycles

l_REFC=19cycles

DESL

RDA

or

LAL or

MRS or

REF

RDA

LAL

LA

DESL

WRA

REF

Command

WRA

Bank,

UA

Bank, Address

l_RCD=1cycle

Low

l_RAS=4cycles

l_RCD=1cycle

LQS/UQS

(output)

Low

CL=4

Hi-Z

DQ

(output)

Q0 Q1 Q2 Q3

Unidirectional DS/Free Running QS mode

CLK

l_RC=5cycles

l_REFC=19cycles

RDA

or

LAL or

MRS or

REF

RDA

LAL

LA

DESL

WRA

REF

DESL

Command

WRA

Bank,

UA

Bank, Address

l_RCD=1cycles

l_RAS=4cycles

l_RCD=1cycles

LQS/UQS

(output)

CL=4

Hi-Z

DQ

(output)

Q0 Q1 Q2 Q3

Note :

In case of CL=4, I_REFCmust be meet 19 clock cycles.

When the Auto-Refresh operation is perfomed, the synthetic average interval of Auto-Refresh command

specified by t_REFImust be satisfied.

t_REFIis average interval time in 8 Refresh cycles that is sampled randomly.

t₁

t₂

t₃

t₇

t₈

CLK

WRA REF

8 Refresh cycle

t +t +t +t +t +t +t +t

8

Total time of 8 Refresh cycle

1

2

3

4

5

6

7

t_REFI

=

8

t

_REFIis specified to avoid partly concentrated current of Refresh operation that is acivated

larger are than Read/Write operation.

- 51 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Self-Refresh Entry Timing

Unidirectional DS/Free Running QS mode

0

1

2

3

4

5

m-1

m

m+1

CLK

l_RCD=1cycle

l_REFC

WRA

REF

DESL

Command

PD

t_{FPDL (min)}t_{FPDL (max)}

Auto Refresh

Self Refresh Entry

*2

l_PDV

t_QPDH

l_CKD

Hi-Z

LQS/UQS

(output)

DQ

(output)

Qx

Note :

1.

is don’t care.

2. PD must be brought to "Low" within the timing between t_FPDL(min) and t_FPDL(max) to Self Refresh mode. When PD is brought to

"Low" after I_PDV,K4C89183AF perform Auto Refresh and enter Power down mode. In case of PD fall between t_FPDL(max) and I_PDV

,

K4C89363AF will either entry self refresh mode or power down mode after auto refresh operation. It can’t be specified which mode

K4C89363AF operates.

3. It is desirable that clock input is continued at least I_CKDfrom REF command even though PD is brought to "Low" for Self-Refresh Entry.

4. In case of self refresh entry after write operation from the LAL command following WRA to the REF command delay time is write

latency(WL) + 2 clock clycles minimum.

Self-Refresh Exit Timing

Unidirectional DS/Free Running QS mode

0

1

3

m-1

m

m+1

m+2

n-1

n

n+1

p-1

p

CLK

Command (1st)^*6

l_REFC

DESL

Command (2nd)^*6

DESL

l_PDA=2cycles^*4

WRA^*5

REF^*5

RDA^*7

LAL^*7

Command

l_RCD=1cycle

t_PDEX

PD

l_LOCK

LQS/UQS

(output)

Hi-Z

DQ

(output)

Self-Refresh Exit

Note :

1.

is don’t care.

2. Clock should be stable prior to PD = "High" if clock input is suspended in Self-Refresh mode.

3. DESL command must be asserted during I_REFCafter PD is brought to "High"

4. l_PDAis defined from the first clock rising edge after PD is brought to "High"

5. It is desirable that one Auto-Refresh command is issued just after Self-Refresh Exit before any other

operation.

6. Any command (except Read command) can be issued after l_REFC

.

7. Read command (RDA +LAL) can be issued after l_LOCK

.

8. QS output is invalid until DLL lock from Self-Refresh exit.

- 52 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Function Description

Network - DRAM

Network - DRAM is an acronym of Double Data Rate Network - DRAM.

Network - DRAM is competent to perform fast random core access, low latency and high-speed data transfer.

Pin Functions

Clock Inputs : CLK & CLK

The CLK and CLK inputs are used as the reference for synchronous operation. CLK is master clock input. The CS, FN and all

address input signals are sampled on the crossing of the positive edge of CLK and the negative edge of CLK. The QS and DQ output

data are aligned to the crossing point of CLK and CLK. The timing reference point for the differential clock is when the CLK and CLK

signals cross during a transition.

Power Down : PD

The PD input controls the entry to the Power Down or Self-Refresh modes. The PD input does not have a Clock Suspend function like

a CKE input of a standard SDRAMs, therefore it is illegal to bring PD pin into low state if any Read or Write operation is being per-

formed.

Chip Select & Function Control : CS & FN

The CS and FN inputs are a control signal for forming the operation commands on Network-DRAM. Each operation mode is decided

by the combination of the two consecutive operation commands using the CS and FN inputs.

Bank Addresses : BA0 & BA1

The BA0 and BA1 inputs are latched at the time of assertion of the RDA or WRA command and are selected the bank to be used for

the operation. BA0 and BA1 also define which mode register is loaded during the Mode Register Set command (MRS or EMRS).

BA0

0

BA1

0

Bank #0

Bank #1

Bank #2

Bank #3

1

0

1

Address Inputs : A0 to A13

Address inputs are used to access the arbitrary address of the memory cell array within each bank. The Upper Addresses with Bank

address are latched at the RDA or WRA command and the Lower Addresses are latched at the LAL command. The A0 to A14 inputs

are also used for setting the data in the Regular or Extended Mode Register set cycle.

Upper Address

Lower Address

K4C89363AF

A0 to A13

A0 to A7

- 53 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Functional Description (Continued)

Data Input/Output : DQ0 ~ DQ35

The input data of DQ0 to DQ35 are taken in synchronizing with the both edges of LDS/UDS input signal.

The output data of DQ0 to DQ35 are outputted synchronizing with the both edges of LQS/UQS output signal.

Data Strobe : DS(LDS/UDS) or QS(LQS/UQS)

Method of data strobe is chosen by Extended mode register.

(1) Unidirectional DS/QS mode

DS is input signal and QS is output signal. Both edges of DS are used to sample all DQs at Write operation. Both edges of QS

are used for trigger signal of all DQs at Read operation. During Write, Auto-Refresh and NOP cycle, QS assert always "Low"

level. QS is Hi-Z in Self-Refresh mode.

(2) Unidirectional DS/Free running QS mode

DS is input signal and QS is output signal. Both edges of DS are used to sample all DQs at Write operation. Both edges of QS

are used for trigger signal of all DQs at Read operation. QS assert always toggle signal except Self-Refresh mode. This strobe

type is easy to use for pin to pin connect application.

Power Supply : V_DD, V_DDQ, V_SS, V_SSQ

V_DDand V_SSare supply pins for memory core and peripheral circuits.

V_DDQand V_SSQare power supply pins for the output buffer.

Reference Voltage : V_REF

V_REFis reference voltage for all input signals.

- 54 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Command Functions and Operations

K4C89363AF is introduced the two consecutive command input method. Therefore, except for Power Down mode, each operation

mode decided by the combination of the first command and the second command from stand-by states of the bank to be accessed.

Read Operation (1st command + 2nd command = RDA + LAL)

Issuing the RDA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address in

a read mode. When the LAL command with Lower Addresses is issued at the next clock of the RDA command, the data is read out

sequentially synchronizing with the both edges of QS output signal (Burst Read Operation). The initial valid read data appears after

CAS latency, the burst length of read data and the burst type must be set in the Mode Register beforehand. The read operated bank

goes back automatically to the idle state after I_RC

.

Write Operation (1st command + 2nd command = WRA + LAL)

Issuing the WRA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address in

a write mode. When the LAL command with Lower Addresses is issued at the next clock of the WRA command, the input data is

latched sequentially synchronizing with the both edges of DS input signal (Burst Write Operation). The data and DS inputs have to be

asserted in keeping with clock input after CAS latency-1 from the issuing of the LAL command. The DS have to be provided for a burst

length. The CAS latency and the burst type must be set in the Mode Register beforehand. The write operated bank goes back automat-

ically to the idle state after I_RC. Write Burst Length is controlled by VW0 and VW1 inputs with LAL command. See VW truth table.

Auto-Refresh Operation (1st command + 2nd command = WRA + REF)

K4C89363AF is required to refresh like a standard SDRAM. The Auto-Refresh operation is begun with the REF command following to

the WRA command. The Auto-Refresh mode can be effective only when all banks are in the idle state and all DQ are in Hi-Z states. In

a point to notice, the write mode started with the WRA command is canceled by the REF command having gone into the next clock of

the WRA command instead of the LAL command. The minimum period between the Auto-Refresh command and the next command is

specified by I_REFC. However, about a synthetic average interval of Auto-Refresh command, it must be careful. In case of equally distrib-

uted refresh, Auto-Refresh command has to be issued within once for every 3.9 us by the maximum In case of burst refresh or random

distributed refresh, the average interval of eight consecutive Auto-Refresh command has to be more than 400ns always. In other words,

the number of Auto-Refresh cycles which can be performed within 3.2 us (8x400ns) is to 8 times in the maximum.

Self-Refresh Operation (1st command + 2nd command = WRA + REF with PD="L")

It is the function of Self-Refresh operation that refresh operation can be performed automatically by using an internal timer. When all

banks are in the idle state and all outputs are in Hi-z states, the K4C89363AF become Self-Refresh mode by issuing the Self-Refresh

command. PD has to be brought to "Low" within t_FPDLfrom the REF command following to the WRA command for a Self-Refresh mode

entry. In order to satisfy the refresh period, the Self-Refresh entry command should be asserted within 3.9us after the latest Auto-

Refresh command. Once the device enters Self-Refresh mode, the DESL command must be continued for I_REFCperiod. In addition, it

is desirable that clock input is kept in I_CKDperiod. The device is in Self-Refresh mode as long as PD held "Low". During Self-Refresh

mode, all input and output buffers except for PD are disabled, therefore the power dissipation lowers. Regarding a Self-Refresh mode

exit, PD has to be changed over from "Low" to "High" along with the DESL command, and the DESL command has to be continuously

issued in the number of clocks specified by I_REFC. The Self-Refresh exit function is asynchronous operation. It is required that one Auto-

Refresh command is issued to avoid the violence of the refresh period just after I_REFCfrom Self-Refresh exit.

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REV. 0.2 Aug. 2003

K4C89363AF

Target

Power Down Mode( PD="L" )

When all banks are in the idle state and all DQ outputs are in Hi-Z states, the K4C89363AF become Power Down Mode by asserting

PD is "Low". When the device enters the Power Down Mode, all input and output buffers except for PD, CLK, CLK and QS. Therefore,

the power dissipation lowers. To exit the Power Down Mode, PD has to be brought to "High" and the DESL command has to be issued

for I_PDAcycle after PD goes high. The Power Down exit function is asynchronous operation.

Mode Register Set (1st command + 2nd command = RDA + MRS)

When all banks are in the idle state, issuing the MRS command following to the RDA command can program the Mode Register. In a

point to notice, the read mode started with the RDA command is canceled by the MRS command having gone into the next clock of

the RDA command instead of the LAL command. The data to be set in the Mode Register is transferred using A0 to A14, BA0 and BA1

address inputs. The K4C89363AF have two mode registers. These are Regular and Extended Mode Register. The Regular or

Extended Mode Register is chosen by BA0 and BA1 in the MRS command.The Regular Mode Register designates the operation mode

for a read or write cycle. The Regular Mode Register has four function fields.

The four fields are as follows :

(R-1) Burst Length field to set the length of burst data

(R-2) Burst Type field to designate the lower address access sequence in a burst cycle

(R-3) CAS Latency field to set the access time in clock cycle

(R-4) Test Mode field to use for supplier only.

The Extended Mode Register has two function fields.

The two fields are as follows:

(E-1) DLL Switch field to choose either DLL enable or DLL disable

(E-2) Output Driver Impedance Control field.

(E-3) Data Strobe Select

Once these fields in the Mode Register are set up, the register contents are maintained until the Mode Register is set up again by

another MRS command or power supply is lost. The initial value of the Regular or Extended Mode Register after power-up is unde-

fined, therefore the Mode Register Set command must be issued before proper operation.

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• Regular Mode Register/Extended Mode Register change bits (BA0, BA1)

These bits are used to choose either Regular MRS or Extended MRS

BA1

BA0

0

A13~A0

0

1

Regular MRS cycle

Extended MRS cycle

Reserved

1

X

Regular Mode Register Fields

(R-1) Burst Length field (A2 to A0)

This field specifies the data length for column access using the A2 to A0 pins and sets the Burst Length to be 2 or 4

words.

A2

0

A1

0

A0

0

Burst Length

Reserved

2 words

0

1

0

1

0

4 words

0

1

Reserved

1

X

(R-2) Burst Type field (A3)

This Burst Type can be chosen Interleave mode or Sequential mode. When the A3 bit is " 0", Sequential mode is

selected. When the A3 bit is "1", Interleave mode is selected. Both burst types support burst length of 2 and 4 words.

A3

0

Burst Type

Sequential

Interleave

1

• Addressing sequence of Sequential mode (A3)

A column access is started from the inputted lower address and is performed by incrementing the lower address input to

the device.

CAS Latency = 4 (Free Running QS mode)

CK

Command

QS

RDA

LAL

DQ

Data 0 Data 1 Data 2 Data 3

Addressing sequence for Sequential mode

Data

Access Address

Burst Length

Data 0

Data 1

Data 2

Data 3

n

2 words (Address bits is LA0)

not carried from LA0~LA1

4 words(Address bits is LA1, LA0)

not carried from LA1~LA2

n + 1

n + 2

n + 3

- 57 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Functional Description (Continued)

• Addressing sequence of Inteleave mode

A column access is started from the inputted lower address and is performed by interleaving the address bits in the

sequence shown as the following.

Addressing sequence for Interleave mode

Data

Access Address

Burst Length

Data 0

Data 1

Data 2

Data 3

...A8 A7 A6 A5 A4 A3 A2 A1 A0

2 words

4 words

(R-3) CAS Latency field (A6 to A4)

This field specifies the number of clock cycles from the assertion of the LAL command following the RDA command to

the first data read. The minimum values of CAS Latency depends on the frequency of CLK. In a write mode, the place of

clock which should input write data is CAS Latency cycles - 1.

Addressing sequence for Interleave mode

A6

0

A5

0

A4

0

CAS Latency

Reserved

0

1

Reserved

0

1

0

Reserved

0

1

Reserved

1

0

4

5

6

7

1

0

1

0

1

(R-4) Test Mode field (A7)

This bit is used to enter Test Mode for supplier only and must be set to "0" for normal operation.

(R-5) Reserved field in the Regular Mode Register

• Reserved bits (A8 to A14)

These bits are reserved for future operations. They must be set to "0" for normal operation.

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REV. 0.2 Aug. 2003

K4C89363AF

Target

Extended Mode Register Fields

(E-1) DLL Switch field (A0)

This bit is used to enable DLL. When the A0 bit is set "0", DLL is enabled.

(E-2) Output Driver Impedance Control field (A1 to A4)

This field is used to choose Output Driver Strength. Four types of Driver Strength are supported. QS and DQ Driver

Strength can be chosen separately. A2-A1 specified the DQ Driver Strength. A4-A3 specified the QS Driver Strength.

QS

DQ

Output Driver Impedance Control

A4

0

A3

0

A2

0

A1

0

Normal Output Driver

Strong Output Driver

Weak Output Driver

Reserved

0

1

0

1

0

1

0

1

(E-3) Strobe Select (A6/A5)

Two types of strobe are supported. This field is used to choose the type of data strobe.

(1) Unidirectional DS/QS mode

Data strobe is separated DS for write strobe and QS for read strobe.

DS is used to sample write data at write operation. QS is aligned with read data at Read operation.

(2) Unidirectional DS/Free running QS mode

Data strobe is separated DS for write strobe and QS for read strobe.

DS is used to sample write data at write operation. QS is aligned with read data and always clocking

A6

0

A5

0

Strobe Select

Reserved

0

1

Reserved

1

0

Unidirectional DS/QS mode

Unidirectional DS/Free running QS mode

1

(E-4)Reserved fied (A7 to A14)

These bits are reserved for future operations and must be set to "0" for normal operation.

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BOUNDARY SCAN TEST ACCESS PORT OPERATIONS

The TC59LM836DMB has a serial boundary scan test accessport (TAP) which is compatible IEEE Standard 1149.1 ~1990, but which

does not implement all the functions required for 1149.1 ~ 1990 compliance. TCK must be tied to V_SSor V_DDto disable the TAP when

TAP operation is not required.

Test Access Port Signals

Symbol

Description

All Test Access Port inputs are sampled on the rising edge of TCK. To

TCK

Test Clock Input

disable the TAP, TCK must be tied toV_SSor V_DD

.

The signal presented at TMS is sampled on the rising edge of TCK.

This input is intemally pulled up so as to recognize a floating input as

a logical High (Test-Logic-Reset).

TMS

Test Mode Select Input

Values presented at TDI are clocked into the selected register on the

rising edge of TCK. This input is internally pulled up. This enables

detection of when the TDI input to the board is open-circuit.

TDI

Test Data Input

TDO is the serial output for test instructions and data from the test

logic. This output is controlled by the falling edge of TCK.

TDO

Test Data Output

Test Access Port Registers

Register

Symbol

Length(bits)

Description

The Instruction register controls five states (EXTEST, sample-Z,

Sample, Bypass, ID code).

Instruction Register

IR[2 : 0]

3

The Register includes information on revision number, organization

and TOSHIBA ID number.

ID Register

IDR[31 : 0]

BR

32

1

Test Data

Register

Bypass Register

The register connects TDI and TDO.

The Boundary Scan register is comprised of boundary scan cells at

each input and I/O pin. The BSCs are serially connected between

TDI and TDO.

Boundary Scan

Register

BSR[62 : 0]

63

Test Controller instruction Set

IR2

IR1

IR0

Instruction

Description\

Moves the Preloaded data on to the output pins. Samples the inputs connected to

the BSCs.

0

EXTEST

0

1

0

1

ID CODE

SAMPLE-Z

RESERVED

Access ID code.

Tristates the RAM outputs and samples the inputs connected to the BSCs.

This instruction is reserved for future use.

Samples the input connected to the BSCs. Load the sampled data at I/Os to the

parallel output of the BSCs. Does not affect RAM operation.

1

0

SAMPLE

1

0

1

0

1

RESERVED

BYPASS

This instruction is reserved for future use.

Bypasses TDI and TDO using the Bypass register.

The first bit to be scanned into TDI is taken to be the least significant bit (IR0).

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REV. 0.2 Aug. 2003

K4C89363AF

Target

ID Register

BIT# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Value

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Fi

xe

d

Content

Memory Type

SAMSUNG ID number

ID Register

BIT

0

BALL LAYOUT

U10

U11

T10

BALL NAME

DQ35

DQ34

DQ33

DQ32

DQ31

DQ30

DQ29

DQ28

DQ27

UQS

A4

BIT

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

BALL LAYOUT

BALL NAME

DQ17

B3

B2

C3

C2

D3

1

DQ16

2

DQ15

3

T11

DQ14

4

R10

R11

P10

P11

DQ13

5

6

D2

E3

E2

F3

F2

G3

H3

H2

J2

DQ12

DQ11

DQ10

DQ9

LDS

/CLK

CLK

/PD

7

8

N10

N11

M3

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

M11

L10

A3

A2

L11

A1

K10

K11

A0

A12

A10

J3

A11

J10

BA1

K2

K3

L2

A9

J11

BA0

A8

G10

G11

H10

F11

A13

A7

FN

L3

A6

/CS

M2

N2

N3

P2

P3

R2

A5

LQS

DQ8

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

UDS

DQ26

DQ25

DQ24

DQ23

F10

E11

E10

D11

D10

C11

C10

B11

R3

T2

T3

U2

U3

DQ22

DQ21

DQ20

DQ19

DQ18

B10

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K4C89363AF

Target

TAP CONTROLLER STATE DIAGRAM

TMS = 1 Test - Logic - Reset

TMS = 0

TMS = 1

TMS = 0

Run - Test/Idle

Select - DR - Scan

TMS = 0

TMS = 1 TMS = 1

Capture - DR

TMS = 0

TMS = 1

TMS = 0

Shift - DR

TMS = 1

TMS = 0

Exit1 - DR

TMS = 0

Pause - DR

TMS = 1

Exit2 - DR

TMS = 1

Exit2 - DR

TMS = 1

TMS = 0 TMS = 0

TMS = 1

Update - DR

TMS = 0

TMS = 1

TMS = 0

Notes :

1. To enter the Test-Logic-Reset state in to initialize the device, TMS High for at least five rising edges of the TCK.

2. The TDO output buffer is active only during shift operations (the Shift-DR and Shift-IR states) and is inactive (High-Z)

during other states.

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TAP DC OPERATING CHARACTERISTICS

Symbol

Parameter

Test Condition

Min

TYP

Max

Unit

uA

Output Deselected

V_OUT= 0 to V_DD

Output Leakage Current

(TDO pin)

I_LO

-10

-

10

V_IN= 1.7V to V_DD

-20

-

10

uA

I_I

Input Current

V_IN= 0 to 0.7V

-100

Input High Voltage

(TCK, TMS, TDI pins)

V_IH

V_IL

V

_REF+ 0.4

V_DDQ+ 0.2

V_REF- 0.4

-

V

input Low Voltage

(TCK, TMS, TDI pins)

-

-0.1

V_OH

V_OL

I_OH= 2 mA

Output High Voltage (TDO pin)

1.5

-

V

0.45

AC CHARACTERISTICS (T_CASE= 0~85°C, V_DD= 2.5V ± 0.125V, V_DDQ= 1.4V~1.9V)

TC59LM836DMB

Symbol

Parameter

Unit

TYP

Max

t_THTH

t_THTL

t_TLTH

t_MVTH

t_THMX

t_CS

TCK Cycle Time

50

20

10

-

ns

TCK High Pulse Width

TCK Low Pulse Width

-

TMS Setup Time to TCK

-

TMS Hold Time to TCK

-

Capture Setup time to TCK

Capture Hold time to TCK

TDI Setup Time to TCK

-

t_CH

-

t_DVTH

t_THDX

t_TLQV

t_TLQX

t_TLQLZ

t_TLQHZ

-

TDI Setup Time to TCK

-

Output Valid Time fom TCK Low

Output Hold Time fom TCK Low

Output Low-Z Time fom TCK Low

Output High-Z Time fom TCK Low

20

-

0

5

-

5

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REV. 0.2 Aug. 2003

K4C89363AF

Target

TAP AC TEST CONDITIONS

Fig. 2

Input Pulse Level

1.8V / 0.0V

2ns

Z = 50Ω

TDO

Input Pulse Rise and Fall Time

Input Timing Measurement Reference Level

Output Timing Measurement Reference Level

Output Load

R_L= 50Ω

V_L= 0.9V

0.9V

Fig.2

Output Load

TAP TIMING DIAGRAMS

t

TLTH

THTH

THTL

TCK

t

MVTH THMX

TMS

TDI

t

DVTH THDX

t

CS

Capture

Data

t

TLQV

t

TLQHZ

TLQLZ

TDO

- 64 -

REV. 0.2 Aug. 2003

K4C89363AF

Target

Package Outline Drawing (FBGA 144ball, 1.0 x 0.8 mm)

10.50

± 0.10

0.80 x 11 = 8.80

Window Mold Area

4.40

0.80

2.00

8

2.00

5

10.5 0

± 0.10

12 11 10

9

7 6

4

3

2

1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

0.35

± 0.05

144 -

∅0.45 solder ball

1.10 0.10

±

BOTTOM VIEW

TOP VIEW

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REV. 0.2 Aug. 2003

K4C89363AF

Target

General Information

Organization

288M(x9)

F6 (667Mbps@CL6)

FB (600Mbps@CL6 )

K4C89093AF-GCFB

K4C89183AF-GCFB

K4C89363AF-GCFB

F5 (500Mbps@CL6 )

K4C89093AF-GC(I)F5

K4C89183AF-GC(I)F5

K4C89363AF-GC(I)F5

K4C89093AF-GCF6

K4C89183AF-GCF6

K4C89363AF-GCF6

288M(x18)

288M(x36)

1

2

3

4

5

6

7

8

9

10 11

K 4 C XX XX X X X - X X XX

Memory

DRAM

Speed

Temperature & Power

Package

Small Classification

Density and Refresh

Version

Organization

Bank

Interface (VDD & VDDQ)

1. SAMSUNG Memory : K

8. Version

F : 7th Generation

2. DRAM : 4

3. Small Classification

C : Network-DRAM

9. Package

G : 144 FBGA

4. Density & Refresh

89 : 288M 8K/32ms

10. Temperature & Power

C : (Commercial, Normal)

5. Organization

I

: (Industrial, Normal)

32 : x32

36 : x36

11. Speed

F6 : 667Mbps/pin (333MHz, CL=6)

FB :533Mbps/pin (266MHz,CL=5)

F5 : 400Mbps/pin (200MHz, CL=4)

6. Bank

3 : 4 Bank

7. Interface (VDD & VDDQ)

A: SSTL-2(2.5V, 1.8V)

- 66 -

REV. 0.2 Aug. 2003


型号：	K4C89093AF-GIF50
厂家：	SAMSUNG
描述：	DDR DRAM, 32MX9, 0.6ns, CMOS, PBGA144, 1 X 1 MM PITCH, FBGA-144 动态存储器双倍数据速率内存集成电路
文件：	总66页 (文件大小：2038K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

K4C89093AF-GIF50 [SAMSUNG]

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