K4C89093AF-GIF60 [SAMSUNG]
DDR DRAM, 32MX9, 0.5ns, CMOS, PBGA60, 1 MM PITCH, FBGA-60;
| 型号： | K4C89093AF-GIF60 |
| 厂家： | 
SAMSUNG |
| 描述： | DDR DRAM, 32MX9, 0.5ns, CMOS, PBGA60, 1 MM PITCH, FBGA-60 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总67页 (文件大小：2177K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K4C89093AF
Network-DRAM-II Specification
Version 0.11
- 1 -
REV. 0.11 Apr. 2003
K4C89093AF
Revision History
Version 0.0 (Nov. 2002)
- First Release
Version 0.1 (Apr. 2003)
- Added 800Mbps(400Mhz) product
- Changed operating temperature from Ta to Tc.
- Changed capacitance of ADDR/CMD/CLK
From
To
Min
1.5
Max
2.5
Min
1.5
Max
3.0
Addr/CMD/CLK
- Changed tDSS(DS input Falling Edge to Clock Setup Time)
From
To
F6
0.9
0.9
0.9
-
FB
0.9
0.9
0.9
-
F5
1.0
1.0
1.0
-
G7
F6
0.75
0.75
0.75
-
FB
0.8
0.8
0.8
-
F5
1.0
1.0
1.0
-
CL4
CL5
CL6
CL7
0.75
0.75
0.75
0.75
- Added CL7 for 800Mbps
- Deleted TSOP package outline
Version 0.11 (Apr. 2003)
- Corrected typo in page 3.(Deleted bi-directional strobe)
- Corrected min. Vref to VDDQ/2x95% in page 7
- 2 -
REV. 0.11 Apr. 2003
K4C89093AF
8,388,608-WORDS x 4 BANKS x 9-BITS DOUBLE DATA RATE Network-DRAM
DESCRIPTION
K4C89093AF is a CMOS Double Data Rate Network-DRAM containing 301,989,888 memory cells. K4C89093AF is organized as
8,388,608-words x 4 banks x9 bits. K4C89093AF feature a fully synchronous operation referenced to clock edge whereby all operations
are synchronized at a clock input which enables high performance and simple user interface coexistence. K4C89093AF can operate
fast core cycle compared with regular DDR SDRAM.
K4C89093AF is suitable for Server, Network and other applications where large memory density and low power consumption are
required. The Output Driver for Network-DRAM is capable of high quality fast data transfer under light loading condition.
FEATURES
K4C89093AF
Parameter
G7
F6
4.0 ns
3.33 ns
3.0ns
-
FB
4.5 ns
3.75 ns
3.33 ns
-
F5
5.0 ns
4.5 ns
4.0 ns
-
CL = 4
CL = 5
CL = 6
CL = 7
4.0 ns
3.33 ns
3.0ns
t
CK Clock Cycle Time (min)
2.5ns
tRC Random Read/Write Cycle Time (min)
tRAC Random Access Time (min)
20.0 ns
20.0 ns
22.5 ns
25 ns
20.0 ns
TBD
20.0 ns
TBD
22.5 ns
TBD
25 ns
TBD
TBD
TBD
IDD1S Operating Current (single bank) (max)
I
DD2S Power Down Current (max)
TBD
TBD
TBD
IDD3S Self-Refresh Current (max)
TBD
TBD
TBD
•
Fully Synchronous Operation
- Double Data Rate (DDR)
- Data input/output are synchronized with both edges of DS / QS.
- Differential Clock (CLK and CLK) inputs
- CS, FN and all address input signals are sampled on the positive edge of CLK.
- Output data (DQs and QS) is aligned to the crossings of CLK and CLK.
Fast clock cycle time of 2.5 ns minimum
- Clock : 400 MHz maximum
•
- Data : 800 Mbps/pin maximum
•
•
•
•
•
•
•
•
•
Quad Independent Banks operation
Fast cycle and Short Latency
Uni-directional data Strobe
Distributed Auto-Refresh cycle in 3.9us
Self-Refresh
Power Down Mode
Variable Write Length Control
Write Latency = CAS Latency-1
Programable CAS Latency and Burst Length
- CAS Laatency = 4, 5, 6, 7
- Burst Length = 2,4
•
•
Organization : 8,388,608 words x 4 banks x 9 bits
Power Supply Voltage VDD : 2.5V ± 0.125V
•
VDDQ : 1.4V ∼ 1.9V
•
•
•
1.8V CMOS I/O comply with SSTL - 1.8 (half strength driver) and HSTL
Package : 60Ball BGA, 1mm x 1mm Ball pitch
Notice : Network-DRAM is trademark of Samsung Electronics., Co LTD
- 3 -
REV. 0.11 Apr. 2003
K4C89093AF
PIN ASSIGNMENT (TOP VIEW)
ball pitch=1.0 x 1.0mm
Pin Names
Pin
Name
x9
A0 ~ A14
BA0, BA1
DQ0 ~ DQ8
CS
Address Input
Bank Address
1
2
3
4
5
6
Index
Data Input/Output
Chip Select
Vss
DQ5
NC
NC
DQ0
VDD
DQ1
NC
A
B
C
D
E
F
FN
Function Control
Power Down Control
Clock Input
Vss
Q
VDDQ
PD
CLK, CLK
DS/QS
VDD
VDD
Q
VssQ
Write/Read Strobe
Power (+2.5V)
Ground
DQ6
NC
NC
NC
DQ2
NC
VSS
Vss
Q
VDDQ
VDDQ
Power (+1.8V)
(for I/O buffer)
DQ7
NC
VDD
Q
Vss
Q
DQ3
NC
VSSQ
Ground
(for I/O buffer)
G
H
J
Vss
Q
VDDQ
VREF
NC
Reference Voltage
No Connection
DQ8
VREF
CLK
A12
A11
A8
DS
QS
VDD
FN
DQ4
A14
A13
NC
Vss
CLK
PD
A9
K
L
CS
BA1
A0
M
N
P
R
BA0
A10
A1
A7
A5
A6
A2
VSS
A4
A3
VDD
- 4 -
REV. 0.11 Apr. 2003
K4C89093AF
Block Diagram
CLK
CLK
PD
DLL
CLOCK
BUFFER
To Each Block
BANK #3
BANK #2
BANK #1
BANK #0
CONTROL
SIGNAL
CS
FN
COMMAND
DECODER
GENERATOR
MEMORY
CELL
ARRAY
MODE
REGISTER
ADDRESS
BUFFER
A0 ~ A14
BA0, BA1
UPPER ADDRESS
LATCH
COLUMN DECODER
LOWER ADDRESS
LATCH
REFRESH
COUNTER
READ
DATA
BUFFER
WRITE
DATA
BUFFER
WRITE ADDRESS
BURST
COUNTER
LATCH
ADDRESS
COMPARATOR
DS
QS
DQ BUFFER
DQ0 ~ DQ8
Note : The K4C89093AD configuration is 4 Bank of 65536 x 128 x 9 of cell array with the DQ pins numbered DQ0~DQ8.
- 5 -
REV. 0.11 Apr. 2003
K4C89093AF
Absolute Maximum Ratings
Symbol
Parameter
Rating
Units
Notes
VDD
Power Supply Voltage
Power Supply Voltage (for I/O buffer)
Input Voltage
-0.3 ~ 3.3
V
VDDQ
VIN
-0.3 ~ VDD + 0.3
-0.3 ~ VDD + 0.3
-0.3 ~ VDDQ + 0.3
-0.3 ~ VDDQ + 0.3
0 ~ 70
V
V
VOUT
VREF
TOPR
TSTG
TSOLDER
PD
DQ pin Voltage
V
Input Reference Voltage
Operating Temperature
Storage Temperature
V
OC
OC
OC
W
mA
-55 ~ 150
260
Soldering Temperature(10s)
Power Dissipation
2
IOUT
Short Circuit Output Current
± 50
Caution : Conditions outside the limits listed under "ABSOLUTE MAXIMUM RATINGS" may cause permanent damage to the device.
The device is not meant to be operated under conditions outside the limits described in the operational section of this specifi-
cation. Exposure to "ABSOLUTE MAXIMUM RATINGS" conditions for extended periods may affect device reliability.
Recommended DC,AC Operating Conditions (Notes : 1) (Tc = 0 ~ 85 OC)
Symbol
Parameter
Min
Typ
Max
Units Notes
VDD
Power Supply Voltage
2.375
2.5
2.625
V
VDDQ
VREF
Power Supply Voltage (for I/O Buffer)
Input Reference Voltage
Input DC high Voltage
1.7
VDDQ/2x95%
VREF+0.125
-0.1
1.8
1.9
V
VDDQ/2
VDDQ/2x105%
VDDQ+0.2
V
V
V
V
V
V
V
V
V
V
2
VIH (DC)
VIL(DC)
-
-
-
-
-
-
-
-
-
5
Input DC Low Voltage
VREF-0.125
VDDQ+0.1
5
VICK (DC) Differential Clock DC Input Voltage
-0.1
10
VID (DC)
VIH (AC)
VIL (AC)
VID (AC)
VX (AC)
Input Differential Voltage. CLK and CLK Inputs (DC)
0.4
VDDQ+0.2
7,10
3,6
4,6
7,10
8,10
9,10
Input AC High Voltage
VREF+0.2
-0.1
VDDQ+0.2
Input AC Low Voltage
VREF-0.2
Input Differential Voltage. CLK and CLK Inputs (AC)
Differential AC Input Cross Point Voltage
0.55
VDDQ+0.2
VDDQ/2-0.125
VDDQ/2-0.125
VDDQ/2+0.125
VDDQ/2+0.125
VISO (AC) Differential Clock AC Middle Level
- 6 -
REV. 0.11 Apr. 2003
K4C89093AF
1. All voltages are referenced to Vss, VssQ.
Notes:
2. VREF is expected to track variations in VddQ DC level of the transmitting device.
Peak to peak AC noise on VREF may not exceed ± 2% of VREF (DC).
3. Overshoot Iimit : VIH(max.) = VddQ + 0.7V with a pulse width <= 5ns
4. Undershoot Iimit : VIL(min.) = -0.7V with a pulse width <= 5ns
5. VIH(DC) and VIL(DC) are levels to maintain the current logic state.
6. VIH(AC) and VIL(AC) are levels to change to the new logic state.
7. VID is magnitude of the difference between CLK input level and CLK input level.
8. The value of Vx(AC) is expected to equal VddQ/2 of the transmitting device.
9. VISO means [VICK(CLK) + VICK(CLK)]/2
10. Refer to the figure below.
CLK
VX
VX
VX
VX
VX
VID(AC)
CLK
VICK
VICK
VICK
VICK
VSS
VID(AC)
0 V Differential
VISO
VISO(min)
VISO(max)
VSS
11. In the case of external termination, VTT(Termination Voltage) should be gone in the range of VREF(DC) ± 0.04V.
o
Pin Capacitance (V = 2.5V, V
= 1.8V, f = 1 MHz, Ta = 25 C)
DD
DDQ
Symbol
Parameter
Min
1.5
1.5
2.5
-
Max
3.0
3.0
3.5
1.5
Delts
0.25
0.25
0.5
Units
pF
CIN
CINC
CI/O
CNC
Input Pin Capacitance
Clock Pin (CLK, CLK) Capacitance
DQ, DS, QS Capacitance
NC Pin Capacitance
pF
pF
-
pF
Note : These parameters are periodically sampled and not 100% tested.
- 7 -
REV. 0.11 Apr. 2003
K4C89093AF
DC Characteristics and Operating Conditions (Vdd = 2.5V ± 0.125V, VddQ = 1.8V ± 0.1V, Tc = 0~85 °C)
Max
Parameter
Symbol
Units Notes
G7
F6
FB
F5
Operating Current
tCK = min, IRC=min
Read/Write command cycling
OV<=VIN<=VIL(AC) (max.) VIH(AC)(min.) <=VIN<=VDDQ
IDD1S
TBD
TBD
TBD
TBD
1, 2
1 bank operation, Burst Length = 4
Address change up to 2 times during minimum IRC
.
Standby Current
tCK=min, CS = VIH, PD = VIH
,
0V<=VIN<=VIL(AC)(max.) VIH(AC)(min.)<=VIH<=VDDQ
IDD2N
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
1
All Banks : inactive state
Other input signals are changed one time during 4*tCK
Standby (Power Down) Current
tCK=min, CS = VIH, PD = VIL (Power Down)
mA
IDD2P
1
0V<=VIN<=VDDQ
All Banks : inactive state
Auto-Refresh Current
tCK = min, IREFC= min, tREFI = min
Auto-Refresh command cycling
0V<=VIN<=VIL(AC) (max.), VIH(AC) (min.) <=VIN<=VDDQ
IDD5
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
1
Address change up to 2 times during minimum IREFC
.
Self-Refresh Current
self-Refresh mode
IDD6
PD = 0.2V, OV<=VIN<=VDDQ
Parameter
Symbol
Min
-5
Max
Unit
uA
Notes
Input Leakage Current (0V<=VIN<=VddQ, All other pins not under test = 0V)
Output Leakage Current (Output disabled, 0V<=VOUT<=VddQ)
ILI
5
5
5
-
ILO
-5
uA
V
REF Current
IREF
-5
uA
VOH = 1.420V
VOL = 0.280V
VOH = 1.420V
IOH(DC)
IOL(DC)
IOH(DC)
IOL(DC)
IOH(DC)
IOL(DC)
IOH(DC)
IOL(DC)
IOH(DC)
IOL(DC)
-5.6
5.6
-9.8
9.8
-2.8
2.8
TBD
TBD
TBD
TBD
-
3
3
3
3
3
Normal Output
Driver
-
-
Output DC Current
(VDDQ = 1.7 ~ 1.9V)
Strong Output
Driver
mA
VOL = 0.280V
-
VOH = 1.420V
VOL = 0.280V
-
Weak Output
Driver
-
VOH = VDDQ/2 Driver impedence = TBD
VOH = VDDQ/2 Driver impedence = TBD
VOH = VDDQ/2 Driver impedence = TBD
VOH = VDDQ/2 Driver impedence = TBD
Not defined
-
3
3
3
3
Normal Output
Driver
-
-
Output DC Current
(VDDQ = 1.4 ~ 1.6V)
Strong Output
Driver
mA
-
IOH(DC)
-
Weak Output
Driver
IOL(DC)
Not defined
-
-
Notes : 1. These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of
tCK, tRC and IRC
.
2. These parameters depend on the output loading. The specified values are obtained with the output open.
3. Refer to output driver characteristics for the detail. Output Driver Strength is selected by Extended Mode Register.
- 8 -
REV. 0.11 Apr. 2003
K4C89093AF
AC Characteristics and Operating Conditions (Notes : 1, 2)
G7
F6
FB
F5
Symbol
Parameter
Units Notes
Min
20.0
4.0
Max
Min
20.0
4.0
Max
-
Min
22.5
4.5
Max
-
Min
Max
-
tRC
Random Cycle Time
25
3
3
3
3
3
3
CL = 4
7.5
7.5
7.5
7.5
7.5
-
7.5
7.5
7.5
-
5.0
7.5
7.5
7.5
-
C
C
C
L = 5
L = 6
L = 7
3.33
3.0
3.33
3.0
3.75
3.33
-
4.5
tCK
Clock Cycle Time
7.5
4.0
2.5
7.5
-
-
tRAC
tCH
Random Access Time
-
20.0
-
20.0
-
22.5
-
25
0.45*tCK
0.45*tCK
0.45*tCK
0.45*tCK
Clock High Time
-
-
-
-
-
-
3
3
tCL
0.45*tCK
-0.45
-
0.45*tCK
-0.45
-
0.45*tCK
-0.45
-
0.45*tCK
-0.5
-
Clock Low Time
-
-
tCKQS
tQSQ
tAC
QS Access Time from CLK
Data Output Skew from QS
Data Access Time from CLK
Data Output Hold Time from CLK
0.45
0.2
0.5
0.5
0.45
0.2
0.5
0.5
0.45
0.25
0.5
0.5
0.5
0.3
0.6
0.6
3, 8
4
-0.5
-0.5
-0.5
-0.6
-0.6
3, 8
3, 8
tOH
-0.5
-0.5
-0.5
min(tCH
tCL
,
min(tCH
tCL
,
min(tCH
tCL
,
min(tCH
,
tHP
CLK half period ( minium of Actual tCH, tCL)
-
-
-
3
)
)
)
tCL
)
tQSP
tHP-tQHS
tHP-tQHS
tHP-tQHS
tHP-tQHS
tHP-tQHS
tHP-tQHS
tHP-tQHS
tHP-tQHS
QS(Read) Pulse Width
-
-
-
-
-
-
4, 8
4, 8
tQSQV
Data Output Valid Time from QS
0.055x
tCK+0.17
0.055x
tCK+0.17
0.055x
tCK+0.17
0.055x
tCK+0.17
tQHS
DQ, QS Hold skew factor
-
-
-
-
ns
3
tDQSS
0.8*tCK
0.4*tCK
1.2*tCK
0.8*tCK
0.4*tCK
1.2*tCK
0.8*tCK
0.4*tCK
1.2*tCK
0.8*tCK
0.4*tCK
1.2*tCK
DS(Write) Low to High Setup Time
DS(Write) Preamble Pulse Width
DS First Input Setup Time
tDSPRE
tDSPRES
tDSPREH
tDSP
-
-
-
-
4
3
3
0
-
0
-
0
-
0
-
0.3*tCK
0.45*tCK
0.3*tCK
0.45*tCK
0.3*tCK
0.45*tCK
0.3*tCK
0.45*tCK
DS First Low Input Hold Time
DS High or Low Input Pulse Width
-
-
-
-
0.55*tCK
0.55*tCK
0.55*tCK
0.55*tCK
4
C
C
L = 4
L = 5
0.75
0.75
-
-
-
-
-
-
-
-
-
-
0.75
0.75
-
-
-
-
-
-
-
-
-
-
0.8
0.8
-
-
-
-
1.0
1.0
-
-
-
-
-
-
-
3, 4
3, 4
3, 4
3, 4
4
DS Input Falling Edge to Clock Setup
Time
tDSS
CL = 6
CL = 7
0.75
0.75
0.8
1.0
0.75
-
-
-
tDSPST
0.45*tCK
0.45*tCK
0.45*tCK
0.45*tCK
DS(Write) Postamble Pulse Width
DS(Write) Postamble Hold Time
CL = 4
0.75
0.75
0.75
0.75
0.3
0.75
0.75
0.75
-
0.8
0.8
0.8
-
-
-
-
-
-
1.0
1.0
1.0
-
3, 4
3, 4
3, 4
3, 4
4
C
C
L = 5
L = 6
tDSPSTH
CL = 7
-
-
-
-
-
tDS
tDH
tIS
Data Input Setup Time from DS
Data Input Hold Time from DS
0.3
0.35
0.4
0.3
0.6
0.6
-
-
-
0.3
0.6
0.6
-
-
-
0.35
0.6
-
-
-
0.4
0.7
0.7
4
3
3
Command / Address Input Setup Time
Command / Address Input Hold Time
tIH
0.6
- 9 -
REV. 0.11 Apr. 2003
K4C89093AF
AC Characteristics and Operating Conditions (Notes : 1, 2) (Continued)
G7
F6
FB
F5
Symbol
Parameter
Units Notes
Min
-0.5
-
Max
Min
-0.5
-
Max
Min
-0.5
-
Max
Min
-0.6
-
Max
tLZ
Data-out Low Impedance Time from CLK
Data-out High Impedance Time from CLK
Last Output to PD High Hold Time
Power Down Exit Time
-
0.5
-
-
0.5
-
-
0.5
-
-
0.6
-
3, 6, 8
3, 7, 8
tHZ
tQPDH
tPDEX
tT
0
0
0
0
0.6
0.1
-
0.6
-
0.6
-
0.7
-
3
Input Transition Time
1
0.1
1
0.1
1
0.1
1
tFPDL
tREFI
tPAUSE
-0.5*tCK
0.4
-0.5*tCK
-0.5*tCK
-0.5*tCK
PD Low Input Window for Self-Refresh Entry
Auto-Refresh Average Interval
Pause Time after Power-up
5
5
5
5
3
3.9
0.4
3.9
0.4
3.9
0.4
3.9
5
us
200
5
-
-
-
-
-
200
5
-
-
-
-
-
200
-
-
-
-
-
200
-
-
-
-
-
CL = 4
CL = 5
5
6
7
-
5
6
7
-
Random Read/Write Cycle Time
(Applicable to Same Bank)
6
6
IRC
C
C
L = 6
L = 7
7
7
8
-
RDA/WRA to LAL Command Input Delay
(Applicable to Same Bank)
IRCD
1
1
1
1
1
1
1
1
C
C
C
C
L = 4
L = 5
L = 6
L = 7
4
5
6
7
-
-
-
-
4
5
6
-
-
-
-
-
4
5
6
-
-
-
-
-
4
5
6
-
-
-
-
-
LAL to RDA/WRA Command Input Delay
(Applicable to Same Bank)
IRAS
Random Bank Access Delay
(Applicable to Other Bank)
IRBD
IRWD
IWRD
2
-
2
-
2
-
2
-
BL = 2
BL = 4
2
3
2
3
-
-
2
3
-
-
2
3
-
-
LAL following RDA to WRA Delay
(Applicable to Other Bank)
LAL following WRA to RDA Delay
(Applicable to Other Bank)
1
1
-
1
-
1
-
CL = 4
7
7
7
7
-
7
7
7
-
-
-
7
7
7
-
-
-
7
7
7
-
-
-
Cycle
C
L = 5
CL = 6
L = 7
IRSC
Mode Register Set Cycle Time
C
IPD
PD Low to Inactive State of Input Buffer
PD High to Active State of Input Buffer
2
-
-
2
-
2
-
2
IPDA
1
1
-
-
-
-
1
-
-
-
-
1
-
-
-
-
CL = 4
CL = 5
19
23
25
27
19
23
25
27
19
23
25
19
23
25
19
23
25
Power down mode valid from REF com-
mand
IPDV
C
C
L = 6
L = 7
CL = 4
L = 5
19
23
25
-
-
-
19
23
25
-
-
-
19
23
25
-
-
-
C
IREFC
Auto-Refresh Cycle Time
CL = 6
CL = 7
REF Command to Clock Input Disable
at Self-Refresh Entry
ICKD
IREFC
200
IREFC
200
IREFC
200
IREFC
200
-
-
-
-
-
-
-
-
ILOCK
DLL Lock-on Time (Applicable to RDA command)
- 10 -
REV. 0.11 Apr. 2003
K4C89093AF
AC Test Conditions
Symbol
Parameter
Input high voltage (minimum)
Value
Units
Notes
VIH(min)
VREF + 0.2
V
V
V
IL (max)
VREF
VTT
VREF - 0.2
Input low voltage (maximum)
Input reference voltage
VddQ/2
VREF
V
Termination voltage
V
VSWING
VR
ID(AC)
Input signal peak to peak swing
Differential clock input reference level
Input differential voltage
0.7
V
VX(AC)
V
V
1.0
2.5
V
SLEW
VOTR
Input signal minimum slew rate
Output timing measurement reference voltage
V/ns
V
VddQ/2
9
VTT
VddQ
50 Ω
VIH min(AC)
Z=50Ω
Z=50Ω
25 Ω
VSWING
VREF
Output
VIL max(AC)
50 Ω
Vss
VTT
∆T
∆T
Slew=(V min
- V max
)/∆T
AC Test Load
IH
(AC)
IL
(AC)
Notes : 1. Transition times are measured between VIH min(DC) and VIL max(DC)
.
Transition (rise and fall) of input signals have a fixed slope.
2. If the result of nominal calculation with regard to tCK contains more than
one decimal place, the result is rounded up to the nearest decimal place.
(i.e., tDQSS = 0.8*tCK, tCK = 3.3ns, 0.8*3.3 ns = 2.64 ns is rounded up to 2.7 ns.)
3. These parameters are measured from the differential clock (CLK and CLK) AC cross point.
4. These parameters are measured from signal transition point of DS crossing VREF level.
5. The tREFI (MAX.) applies to equally distributed refresh method.
The tREFI (MIN.) applies to both burst refresh method and distributed refresh method.
In such case, the average interval of eight consecutive Auto-Refresh commands has to be more than 400ns always. In
other words, the number of Auto- Refresh cycles which can be performed within 3.2us (8X400ns) is to 8 times in the
maximum.
6. Low Impedance State is speified at VddQ/2± 0.2V from steady state.
7. High Impedance State is specified where output buffer is no longer driven.
8. These parameters depend on the clock jitter. These parameters are measured at stable clock.
9. Output timing is measured by using Normal driver strength.
In case of VDDQ = 1.4~1.6 V, output timing is measured by using Strong driver strength.
- 11 -
REV. 0.11 Apr. 2003
K4C89093AF
Power Up Sequence
1. As for PD, being maintained by the low state (<0.2V) is desirable before a power-supply injection.
2. Apply VDD before or at the same time as VDDQ
.
3. Apply VDDQ before or at the same time as VREF
.
4. Start clock (CLK, CLK) and maintain stable condition for 200us (min.).
5. After stable power and clock, apply DESL and take PD = H.
6. Issue EMRS to enable DLL and to define driver strength and data strobe type. (Note : 1)
7. Issue MRS for set CAS Latency (CL), Burst Type (BT), and Burst Length (BL). (Note : 1)
8. Issue two or more Auto-Refresh commands. (Note:1)
9. Ready for normal operation after 200 clocks from Extended Mode Register programming.
Note : 1. Sequence 6, 7 and 8 can be issued in random order.
2. L=Logic Low, H = Logic High
2.5V(TYP)
VDD
1.8V(TYP)
VDDQ
0.9V(TYP)
VREF
CLK
CLK
t
PDEX
I
l
l
l
l
REFC
PDA
RSC
RSC
REFC
200 µs(min)
PD
200 clock cycle(min)
Command
Address
DQ
DESL
RDA MRS DESL
op-code
RDA MRS
DESL WRA REF
DESL
WRA REF DESL
op-code
EMRS
MRS
DS
Hi-Z
QS
Low
(Uni-QS mode)
QS
(Free Running mode)
EMRS
MRS
Auto Refresh cycle
Normal Operation
- 12 -
REV. 0.11 Apr. 2003
K4C89093AF
Basic Timing Diagrams
Input Timing
tCK
Command and Address
tCH
tCL
tCK
CK
CK
tIS
tIH
tIS
tIS
tIS
tIH
1st
2nd
2nd
LA
CS
FN
tIPW
tIH
tIH
tIS
1st
tIPW
tIH
tIS
tIH
A0-A14
BA0.BA1
UA, BA
Data
DS
tDS
tDH
tDS
tDH
DQn (Input)
DQm (Input)
tDS
tDH
tDS
tDH
Refer to the Command Truth Table.
Timing of the CLK, CLK
tCH
tCL
VIH
VIH(AC)
CLK
VIL(AC)
CLK
VIL
tT
tT
tCK
VIH
VIL
CLK
CLK
VID(AC)
VX
VX
VX
- 13 -
REV. 0.11 Apr. 2003
K4C89093AF
Read Timing (Burst Length = 4)
Unidirectional DS/QS mode
tCH
tCL
tCK
CK
CK
tIS tIH
(after RDA)
LAL
Input
(Control &
Addresses)
DESL
DS
(Input)
tCKQS
tCKQS
tCKQS
tQSP
tQSP
CAS latency = 4
QS
Low
Low
(Output)
tQSQV
tQSQ
tQSQ
tLZ
tQSQ
Q0
tQSQV
tHZ
DQ
High-Z
(Output)
Q1
tAC
Q2
tAC
Q3
tAC
tOH
tCKQS
tCKQS
tCKQS
tQSP
tQSP
CAS latency = 5
QS
Low
Low
(Output)
tQSQV
tQSQ
tQSQ
tLZ
tQSQ
Q0
tQSQV
tHZ
DQ
High-Z
(Output)
Q1
tAC
Q2
tAC
Q3
tAC
tOH
- 14 -
REV. 0.11 Apr. 2003
K4C89093AF
Read Timing (Burst Length = 4)
Unidirectional DS/QS mode
0
1
2
3
4
5
6
13
14
15
16
17
18
19
20
21
22
23
tCH
tCL
tCK
CK
CK
tIS tIH
(after RDA)
LAL
Input
(Control &
Addresses)
DESL
DS
(Input)
tCKQS
tCKQS
tCKQS
tQSP
tQSP
CAS latency = 6
QS
Low
Low
(Output)
tQSQV
tQSQ
tQSQ
tLZ
tQSQ
Q0
tQSQV
tHZ
DQ
High-Z
(Output)
Q1
tAC
Q2
tAC
Q3
tAC
tOH
tCKQS
tCKQS
tCKQS
tQSP
tQSP
CAS latency = 7
QS
Low
Low
(Output)
tQSQV
tQSQ
tQSQ
tLZ
tQSQ
Q0
tQSQV
tHZ
DQ
High-Z
(Output)
Q1
tAC
Q2
tAC
Q3
tAC
tOH
- 15 -
REV. 0.11 Apr. 2003
K4C89093AF
Read Timing (Burst Length = 4)
Unidirectional DS/Free Running QS mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
tCH
tCL
tCK
CK
CK
tIS tIH
(after RDA)
LAL
Input
(Control &
Addresses)
DESL
DS
(Input)
tCKQS
tCKQS
tCKQS
tQSP
tQSP
CAS latency = 4
QS
(Output)
tQSQV
tQSQ
tQSQ
tLZ
tQSQ
Q0
tQSQV
tHZ
DQ
High-Z
(Output)
Q1
tAC
Q2
tAC
Q3
tAC
tOH
tCKQS
tCKQS
tCKQS
tQSP
tQSP
CAS latency = 5
QS
(Output)
tQSQV
tQSQ
tQSQ
tLZ
tQSQ
Q0
tQSQV
tHZ
DQ
High-Z
(Output)
Q1
tAC
Q2
tAC
Q3
tAC
tOH
Note : QS is always asserted in Free Running QS mode.
- 16 -
REV. 0.11 Apr. 2003
K4C89093AF
Read Timing (Burst Length = 4)
Unidirectional DS/Free Running QS mode
0
1
2
3
4
5
6
13
14
15
16
17
18
19
20
21
22
23
tCH
tCL
tCK
CK
CK
tIS tIH
(after RDA)
LAL
Input
(Control &
Addresses)
DESL
DS
(Input)
tCKQS
tCKQS
tCKQS
tQSP
tQSP
CAS latency = 6
QS
(Output)
tQSQV
tQSQ
tQSQ
tLZ
tQSQ
Q0
tQSQV
tHZ
DQ
High-Z
(Output)
Q1
tAC
Q2
tAC
Q3
tAC
tOH
tCKQS
tCKQS
tCKQS
tQSP
tQSP
CAS latency = 7
QS
(Output)
tQSQV
tQSQ
tQSQ
tLZ
tQSQ
Q0
tQSQV
tHZ
DQ
High-Z
(Output)
Q1
tAC
Q2
tAC
Q3
tAC
tOH
Note : QS is always asserted in Free Running QS mode.
- 17 -
REV. 0.11 Apr. 2003
K4C89093AF
Write Timing (Burst Length = 4)
Unidirectional DS/QS mode, Unidirectional DS/Free Running QS mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
tCH
tCL
tCK
CK
CK
tIS tIH
(after RDA)
LAL
Input
(Control &
Addresses)
DESL
tDSPSTH
tDSS
tDSP tDSPST
tDQSS
tDSPRES
tDSPREH
tDSP
tDSP
CAS latency = 4
DS
(Input)
tDSS
tDS
Preamble
tDSPRE
Postamble
tDS
tDS
tDH
Q2
tDH
tDH
Q3
DQ
Q0
Q1
tDQSS
(Input)
tDSS
tDSPSTH
tDSS
tDSP
tDSPRES
tDSP
tDSP tDSPST
tDSPREH
CAS latency = 5
DS
(Input)
Preamble
Postamble
tDSPRE
tDS
tDS
tDS
tDH
Q0
tDH
Q2
tDH
Q3
DQ
Q1
(Input)
QS
Low
(Uni-QS)
QS
(Free Runninig)
- 18 -
REV. 0.11 Apr. 2003
K4C89093AF
Write Timing (Burst Length = 4)
Unidirectional DS/QS mode, Unidirectional DS/Free Running QS mode
0
1
2
3
4
5
9
10
11
12
13
14
15
16
17
18
19
20
tCH
tCL
tCK
CK
CK
tIS tIH
(after RDA)
LAL
Input
(Control &
Addresses)
DESL
tDSS
tDQSS
tDSPSTH
tDSS
tDSP
tDSPRES
tDSPREH
tDSP
tDSP tDSPST
CAS latency = 6
DS
(Input)
Preamble
Postamble
tDSPRE
tDS
tDS
tDS
tDH
Q0
tDH
Q2
tDH
Q3
DQ
Q1
(Input)
tDSS
tDQSS
tDSPRES
tDSPREH
tDSPSTH
tDSS
tDSP
tDSP
tDSP tDSPST
CAS latency = 7
DS
(Input)
Preamble
Postamble
tDSPRE
tDS
tDS
tDS
tDH
Q0
tDH
Q2
tDH
Q3
DQ
Q1
(Input)
QS
Low
(Uni-QS)
QS
(Free Runninig)
- 19 -
REV. 0.11 Apr. 2003
K4C89093AF
tREFI, tPAUSE, Ixxxx Timing
CLK
CLK
tIS
tIH
tREFI, PAUSE, XXXX
t
I
tIS
tIH
Input
(Control &
Addresses)
Command
Command
Note. "IXXXX"means "IRC", "IRCD", "IRAS", etc.
- 20 -
REV. 0.11 Apr. 2003
K4C89093AF
Function Truth Table (Notes : 1,2,3)
Command Truth Table (Notes : 4)
•The First Command
Symbol
Function
CS
H
FN
X
BA1-BA0
A14-A9
X
A8
X
A7
X
A6-A0
X
DESL Device Deselect
X
RDA
Read with Auto-close
Write with Auto-close
L
H
BA
BA
UA
UA
UA
UA
UA
UA
WRA
L
L
UA
UA
•The Second Command (The next clock of RDA or WRA command)
Symbol
LAL
Function
Lower Address Latch
CS
H
FN
X
BA1-BA0 A14-A13 A12-A11 A10-A9 A8
A7 A6-A0
X
X
V
V
X
L
X
X
L
X
X
L
X
X
L
LA
X
LA
X
REF
Auto-Refresh
L
X
MRS
Mode Register Set
L
X
V
V
Notes :1. L=Logic Low,H=Logic High,X=eitherL or H,V=Valid(SpecifiedValue),BA=Bank Address,UA=Upper Address,
LA = Lower Address.
2. All commands are assumed to issue at a valid state.
3. All inputs for command (excluding SELFX and PDEX) are latched on the crossing point of differential clock input where
CLK goes to High.
4. Operation mode is decided by the comination of 1st command and 2nd command refer to "STATE DIAGRAM" and the
command table below.
Read Command Table
Command (Symbol)
CS
L
FN
H
BA1-BA0
A14-A9
UA
A8
UA
X
A7
UA
LA
A6-A0
UA
Notes
RDA (1st)
LAL (2nd)
BA
X
H
X
X
LA
Write Command Table
BA1-
BA0
A10~
Command (Symbol)
CS
FN
A14
A13
UA
A12
A11
A8
A7 A6-A0
A9
UA
X
WRA (1st)
LAL (2nd)
L
L
BA
X
UA
UA
X
UA
X
UA
X
UA
LA
UA
LA
H
X
VW0 VW1
Notes : 5. A14~A13 are used for Variable Write Length (VW) control at Write Operation.
VW Truth Table
Function
Write All Words
VW0
L
VW1
X
BL = 2
BL = 4
Write First One Word
Reserved
H
X
L
L
Write All Words
H
L
Write First Two Words
Write First One Word
L
H
H
H
- 21 -
REV. 0.11 Apr. 2003
K4C89093AF
Function Truth Table (Continued)
Mode Register Set Command Truth Table
Command (Symbol)
RDA (1st)
CS
L
FN
H
BA1-BA0
A14-A9
A8
X
A7
X
A6-A0
Notes
X
V
X
L
X
V
MRS (2nd)
L
X
L
V
6
Note : 6. Refer to "Mode Register Table".
Auto-Refresh Command Table
PD
Command
(Symbol)
Current
State
Function
CS
n
FN BA1-BA0 A14-A9
A8
A7
A6-A0 Notes
n-1
H
Active
Auto-Refresh
WRA(1st)
REF(2nd)
Standby
Active
H
H
L
L
L
X
X
X
X
X
X
X
X
X
X
H
X
Self-Refresh Command Table
PD
Command
Function
Current
State
BA1-
BA0
CS FN
A14-A9 A8 A7 A6-A0 Notes
(Symbol)
n-1
n
H
L
Active
WRA(1st)
REF(2nd)
-
Standby
Active
H
H
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Self-Refresh Entry
Self-Refresh Continue
Self-Refresh Exit
7, 8
9
Self-Refresh
Self-Refresh
L
X
H
SELFX
L
H
Power Down Table
PD
Command
(Symbol)
Current
State
BA1-
BA0
Function
CS FN
A14-A9 A8
A7 A6-A0 Notes
n-1
H
n
L
Power Down Entry
Power Down Continue
Power Down Exit
PDEN
-
Standby
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
8
9
Power Down
Power Down
L
L
PDEX
L
H
Notes : 7. PD has to be brought to Low within tFPDL from REF command.
8. PD should be brought to Low after DQ’s state turned high impedance.
9. When PD is brought to High from Low, this function is executed asynchronously.
- 22 -
REV. 0.11 Apr. 2003
K4C89093AF
Function Truth Table (Continued)
PD
Current State
CS
FN
Address
Command
Action
Notes
n-1
H
H
H
H
H
L
n
H
H
H
L
H
L
X
H
L
X
DESL
RDA
WRA
PDEN
-
NOP
BA, UA
Row activate for Read
Row activate for Write
Power Down Entry
Illegal
L
BA, UA
Idle
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
X
10
L
X
X
H
H
L
X
H
L
X
-
Refer to Power Down state
Begin read
H
H
H
H
L
LA
LAL
Op-Code
MRS/EMRS Access to Mode Register
PDEN Illegal
MRS/EMRS Illegal
Row Active for Read
Row Active for Write
H
L
X
L
X
X
H
H
L
X
H
L
X
-
Invalid
H
H
H
H
L
LA
LAL
Begin Write
Auto-Refresh
Illegal
X
REF
PDEN
H
L
X
L
X
REF (Self) Self-Refresh entry
X
H
H
H
L
X
H
L
X
-
Invalid
H
H
H
H
H
L
X
DESL
RDA
WRA
PDEN
-
Continue burst read to end
BA, UA
Illegal
11
11
L
BA, UA
Illegal
Read
Write
H
L
X
X
X
X
H
L
X
Illegal
L
X
Illegal
X
H
H
H
L
X
H
L
X
-
Invalid
H
H
H
H
H
L
X
DESL
RDA
WRA
PDEN
-
Data write & continue burst write to end
BA, UA
Illegal
11
11
L
BA, UA
Illegal
H
L
X
X
X
X
X
X
X
X
Illegal
L
Illegal
X
H
X
H
-
Invalid
H
DESL
NOP-> Idle after IREFC
H
H
H
H
L
H
H
L
L
L
H
L
BA, UA
RDA
WRA
PDEN
-
Illegal
BA, UA
Illegal
Auto-Refreshing
H
L
X
X
X
X
X
X
X
X
Self-Refresh entry
Illegal
12
L
X
H
X
H
-
Refer to Self-Refreshing state
Nop-> Idle after IRSC
H
DESL
H
H
H
H
L
H
H
L
L
L
H
L
BA, UA
RDA
Illegal
BA, UA
WRA
Illegal
Mode Register Accessing
H
L
X
X
X
X
X
X
X
X
X
X
X
X
PDEN
Illegal
L
-
Illegal
X
X
L
X
X
X
H
-
Invalid
H
L
-
-
Invalid
Maintain Power Down Mode
Exit Power Down Mode->Idle after tPDEX
Power Down
L
H
RDEX
L
H
L
H
X
L
L
X
X
H
X
X
X
X
X
X
X
X
-
Illegal
-
Invalid
-
Maintain Self-Refresh
Exit Self-Refresh->Idle after IREFC
Se;f-Refreshing
L
H
SELFX
L
H
L
X
X
-
Illegal
Notes : 10. Illegal if any bank is not idle.
11. Illegal to bank in specified states : Function may be Legal in the bank indicated by bank Address (BA).
12. Illegal if tFPDL is not Stisfied.
- 23 -
REV. 0.11 Apr. 2003
K4C89093AF
Mode Register Table
Regular Mode Register (Notes : 1)
Address
BA1*1
BA0*1
A7*3
A14-A8
A6-A4
A3
A2-A0
Register
0
0
0
TM
CL
BT
BL
A7
0
Test Mode (TE)
Regular (Default)
Test Mode Entry
A3
0
Burst Type (BT)
Sequential
1
1
Interleave
A6
A5
A4
CAS Latency (CL)
A2
A1
A0
Burst Length (BL)
Reserved *2
Reserved *2
Reserved *2
0
0
X
0
0
0
0
0
1
1
0
1
0
0
0
1
0
1
1
X
1
0
1
X
2
4
Reserved *2
4
1
1
0
0
0
1
Reserved *2
5
6
1
1
1
1
0
1
7
Extended Mode Register (Notes : 4)
BA1*4
BA0*4
A0*5
Address
A14-A7
A6~A5
A4-A3
A2~A1
DIC(DQ)
Register
0
1
0
SS
DIC(QS)
DS
A6
A5
Strobe Select
Reserved*2
Reserved*2
QS
DQ
A1
0
Output Driver Impedance Control
(DIC)
0
0
A4
0
A3
A2
0
0
1
0
1
Normal Output Driver
Strong Output Driver
Weak Output Driver
Reserved
0
1
0
0
1
1
1
0
1
Unidirectional DS/QS
1
1
0
Unidirectional DS/Free Running QS
1
1
1
Note : 1. Regular Mode Register Is Chosen Using the combination of BA0 = 0 and BA1 = 0.
2. "Reserved" places in Regular Mode Register should not be set.
A0
0
DLL Switch (DS)
DLL Enable
3. A7 in Regular Mode Register must be set to "0"(Low state).
Because Test Mode is specific mode for supplier.
1
DLL Disable
4. Extended Mode Register is chosen using the Combination of BA0 = 1 and BA1 = 0.
5. A0 in Extended Mode Register must be set to "0" to enable DLL for normal operation.
- 24 -
REV. 0.11 Apr. 2003
K4C89093AF
State Diagram
Self
Refresh
Power
Down
PDEX
SELFX
(PD = H)
(PD = H)
PDEN
(PD = L)
PD = L
Standby
(Idle)
PD = H
Auto-
Refresh
Mode
Register
WRA
RDA
REF
MRS
Active
(Restore)
Active
LAL
LAL
Write
(Buffer)
Read
Command Input
Automatic Return
The second command at Active
state must be issued 1clock after
RDA or WRA command input
- 25 -
REV. 0.11 Apr. 2003
K4C89093AF
Timing Diagrams
Single Bank Read Timing (CL=4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRC=5cycles
DESL
lRC=5cycles
DESL
lRC=5cycles
DESL
Command
Address
RDA
LAL
RDA
LAL
RDA
LAL
RDA
UA
lRCD=1cycle
lRAS=4cycles
lRCD=1cycle
lRAS=4cycles
lRCD=1cycle
lRAS=4cycles
UA
LA
UA
LA
UA
LA
Bank Add.
#0
#0
#0
#0
Unidirectional DS/QS mode
BL =2
DS
(Input)
QS
(Output)
Low
CL=4
CL=4
CL=4
CL=4
CL=4
CL=4
CL=4
CL=4
CL=4
Hi-Z
DQ
(Output)
Q0 Q1
Q0 Q1
Q0
BL =4
DS
(Input)
QS
(Output)
Low
Hi-Z
DQ
(Output)
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Q0
Q0
Q0
Unidirectional DS/Free Running QS mode
BL =2
DS
(Input)
QS
(Output)
Hi-Z
DQ
Q0 Q1
Q0 Q1
(Output)
BL =4
DS
(Input)
QS
(Output)
CL=4
CL=4
CL=4
Hi-Z
DQ
(Output)
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
- 26 -
REV. 0.11 Apr. 2003
K4C89093AF
Single Bank Read Timing (CL=5)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRC=6cycles
lRC=6cycles
Command
Address
RDA
LAL
DESL
RDA
LAL
DESL
RDA
LAL
LA
DESL
lRCD=1cycle
lRAS=5cycles
lRCD=1cycle
lRAS=5cycles
lRCD=1cycle
UA
LA
UA
#0
LA
UA
#0
Bank Add.
#0
Unidirectional DS/QS mode
BL =2
DS
(Input)
QS
(Output)
Low
CL=5
CL=5
Hi-Z
DQ
(Output)
Q0 Q1
Q0 Q1
BL =4
DS
(Input)
QS
(Output)
Low
Hi-Z
CL=5
CL=5
DQ
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
(Output)
Unidirectional DS/Free Running QS mode
BL =2
DS
(Input)
QS
(Output)
CL=5
CL=5
Hi-Z
DQ
(Output)
Q0 Q1
Q0 Q1
BL =4
DS
(Input)
QS
(Output)
CL=5
CL=5
Hi-Z
DQ
(Output)
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
- 27 -
REV. 0.11 Apr. 2003
K4C89093AF
Single Bank Read Timing (CL=6)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRC=7cycles
DESL
lRC=7cycles
DESL
Command
Address
RDA
LAL
RDA
LAL
RDA
LAL
lRCD=1cycle
lRAS=6cycles
lRCD=1cycle
lRAS=6cycles
lRCD=1cycle
UA
LA
UA
#0
LA
UA
#0
LA
Bank Add.
#0
Unidirectional DS/QS mode
BL =2
DS
(Input)
QS
(Output)
Low
CL=6
CL=6
Hi-Z
DQ
(Output)
Q0 Q1
Q0 Q1
BL =4
DS
(Input)
QS
(Output)
Low
Hi-Z
CL=6
CL=6
DQ
Q0 Q1 Q2 Q3
Q0 Q1 Q2
(Output)
Unidirectional DS/Free Running QS mode
BL =2
DS
(Input)
QS
(Output)
CL=6
CL=6
Hi-Z
DQ
(Output)
Q0 Q1
Q0 Q1
BL =4
DS
(Input)
QS
(Output)
CL=6
CL=6
Hi-Z
DQ
(Output)
Q0 Q1 Q2 Q3
Q0 Q1 Q2
- 28 -
REV. 0.11 Apr. 2003
K4C89093AF
Single Bank Read Timing (CL=7)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRC=8cycles
lRC=8cycles
Command
Address
RDA
LAL
DESL
RDA
LAL
DESL
lRCD=1cycle
lRAS=7cycles
lRCD=1cycle
lRAS=7cycles
UA
LA
UA
#0
LA
Bank Add.
#0
Unidirectional DS/QS mode
BL =2
DS
(Input)
QS
(Output)
Low
CL=7
CL=7
Hi-Z
DQ
(Output)
Q0 Q1
BL =4
DS
(Input)
QS
(Output)
Low
Hi-Z
CL=7
CL=7
DQ
Q0 Q1 Q2 Q3
(Output)
Unidirectional DS/Free Running QS mode
BL =2
DS
(Input)
QS
(Output)
CL=7
CL=7
DQ
(Output)
Hi-Z
Q0 Q1
BL =4
DS
(Input)
QS
(Output)
CL=7
CL=7
DQ
(Output)
Hi-Z
Q0 Q1 Q2 Q3
- 29 -
REV. 0.11 Apr. 2003
K4C89093AF
Single Bank Write Timing (CL=4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRC=5cycles
DESL
lRC=5cycles
DESL
lRC=5cycles
DESL
Command
Address
WRA
LAL
WRA
LAL
WRA
LAL
WRA
UA
lRCD=1cycle
lRAS=4cycles
lRCD=1cycle
lRAS=4cycles
lRCD=1cycle
lRAS=4cycles
UA
LA
UA
LA
UA
LA
Bank Add.
#0
#0
#0
#0
Unidirectional DS/QS mode
BL =2
DS
(Input)
QS
(Output)
Low
WL=3
WL=3
WL=3
WL=3
WL=3
WL=3
WL=3
WL=3
WL=3
WL=3
WL=3
WL=3
DQ
(Input)
D0 D1
D0 D1
D0 D1
BL =4
DS
(Input)
QS
(Output)
Low
DQ
(Input)
D0 D1 D2 D3
D0 D1 D2 D3
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
BL =2
DS
(Input)
QS
(Output)
DQ
(Input)
D0 D1
D0 D1
D0 D1
BL =4
DS
(Input)
QS
(Output)
DQ
(Input)
D0 D1 D2 D3
D0 D1 D2 D3
D0 D1 D2 D3
- 30 -
REV. 0.11 Apr. 2003
K4C89093AF
Single Bank Write Timing (CL=5)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRC=6cycles
lRC=6cycles
Command
Address
WRA
LAL
DESL
WRA
LAL
DESL
WRA
LAL
DESL
lRCD=1cycle
lRAS=5cycles
lRCD=1cycle
lRAS=5cycles
lRCD=1cycle
UA
LA
UA
LA
UA
LA
Bank Add.
#0
#0
#0
Unidirectional DS/QS mode
BL =2
DS
(Input)
QS
(Output)
Low
WL=4
WL=4
WL=4
WL=4
WL=4
WL=4
WL=4
WL=4
DQ
(Input)
D0 D1
D0 D1
BL =4
DS
(Input)
QS
(Output)
Low
DQ
(Input)
D0 D1 D2 D3
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
BL =2
DS
(Input)
QS
(Output)
DQ
(Input)
D0 D1
D0 D1
BL =4
DS
(Input)
QS
(Output)
DQ
(Input)
D0 D1 D2 D3
D0 D1 D2 D3
- 31 -
REV. 0.11 Apr. 2003
K4C89093AF
Single Bank Write Timing (CL=6)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRC=7cycles
lRC=7cycles
WRA
LAL
DESL
WRA
LAL
DESL
WRA
LAL
Command
Address
lRCD=1cycle
lRAS=6cycles
lRCD=1cycle
lRAS=6cycles
lRCD=1cycle
UA
LA
UA
#0
LA
UA
#0
LA
Bank Add.
#0
Unidirectional DS/QS mode
BL =2
DS
(Input)
QS
(Output)
Low
WL=5
WL=5
DQ
(Input)
D0 D1
D0 D1
BL =4
DS
(Input)
QS
(Output)
Low
WL=5
WL=5
DQ
(Input)
D0 D1 D2 D3
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
BL =2
DS
(Input)
QS
(Output)
WL=5
WL=5
DQ
(Input)
D0 D1
D0 D1
BL =4
DS
(Input)
QS
(Output)
WL=5
WL=5
DQ
(Input)
D0 D1 D2 D3
D0 D1 D2 D3
- 32 -
REV. 0.11 Apr. 2003
K4C89093AF
Single Bank Write Timing (CL=7)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRC=8cycles
lRC=8cycles
WRA
LAL
DESL
WRA
LAL
DESL
Command
Address
lRCD=1cycle
lRAS=7cycles
lRCD=1cycle
lRAS=7cycles
UA
LA
UA
#0
LA
Bank Add.
#0
Unidirectional DS/QS mode
BL =2
DS
(Input)
QS
(Output)
Low
WL=6
WL=6
DQ
(Output)
D0 D1
D0 D1
D0 D1
D0 D1
D0 D1
BL =4
DS
(Input)
QS
(Output)
Low
WL=6
WL=6
DQ
(Output)
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
BL =2
DS
(Input)
QS
(Output)
WL=6
WL=6
DQ
(Output)
D0 D1
BL =4
DS
(Input)
QS
(Output)
WL=6
WL=6
DQ
(Output)
D0 D1 D2 D3
- 33 -
REV. 0.11 Apr. 2003
K4C89093AF
Single Bank Read-Write Timing (CL=4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRC=5cycles
DESL
lRC=5cycles
DESL
lRC=5cycles
DESL
Command
Address
RDA
UA
LAL
LA
WRA
UA
LAL
LA
RDA
UA
LAL
LA
WRA
UA
Bank Add.
#0
#0
#0
#0
Unidirectional DS/QS mode
BL =2
DS
(input)
QS
Low
(Output)
DQ
CL=4
WL=3
CL=4
Hi-Z
Q0 Q1
D0 D1
Q0
BL =4
DS
(input)
QS
(Output)
Low
Hi-Z
CL=4
WL=3
CL=4
DQ
Q0 Q1 Q2 Q3
D0 D1 D2 D3
Q0
Q0
Q0
Unidirectional DS/Free Running QS mode
BL =2
DS
(input)
QS
(Output)
CL=4
WL=3
CL=4
Hi-Z
DQ
Q0 Q1
D0 D1
BL =4
DS
(input)
QS
(Output)
CL=4
WL=3
CL=4
Hi-Z
DQ
Q0 Q1 Q2 Q3
D0 D1 D2 D3
- 34 -
REV. 0.11 Apr. 2003
K4C89093AF
Single Bank Read-Write Timing (CL=5)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRC=6cycles
lRC=6cycles
Command
Address
RDA
UA
LAL
LA
DESL
WRA
UA
LAL
LA
DESL
RDA
UA
LAL
LA
DESL
Bank Add.
#0
#0
#0
Unidirectional DS/QS mode
BL =2
DS
(input)
QS
Low
(Output)
DQ
CL=5
WL=4
Hi-Z
Q0 Q1
D0 D1
BL =4
DS
(input)
QS
(Output)
Low
Hi-Z
CL=5
WL=4
DQ
Q0 Q1 Q2 Q3
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
BL =2
DS
(input)
QS
(Output)
CL=5
WL=4
Hi-Z
DQ
Q0 Q1
D0 D1
BL =4
DS
(input)
QS
(Output)
CL=5
WL=4
Hi-Z
DQ
Q0 Q1 Q2 Q3
Read data
D0 D1 D2 D3
Write data
- 35 -
REV. 0.11 Apr. 2003
K4C89093AF
Single Bank Read-Write Timing (CL=6)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRC=7cycles
lRC=7cycles
RDA
UA
LAL
LA
DESL
WRA
UA
LAL
LA
DESL
RDA
UA
LAL
LA
Command
Address
Bank Add.
#0
#0
#0
Unidirectional DS/QS mode
BL =2
DS
(input)
QS
Low
(Output)
DQ
CL=6
WL=5
Hi-Z
Q0 Q1
D0 D1
BL =4
DS
(input)
QS
(Output)
Low
Hi-Z
CL=6
WL=5
DQ
Q0 Q1 Q2 Q3
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
BL =2
DS
(input)
QS
(Output)
CL=6
WL=5
Hi-Z
DQ
Q0 Q1
D0 D1
BL =4
DS
(input)
QS
(Output)
CL=6
WL=5
Hi-Z
DQ
Q0 Q1 Q2 Q3
Read data
D0 D1 D2 D3
Write data
- 36 -
REV. 0.11 Apr. 2003
K4C89093AF
Single Bank Read-Write Timing (CL=7)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRC=8cycles
lRC=8cycles
RDA
UA
LAL
LA
DESL
WRA
UA
LAL
LA
DESL
Command
Address
Bank Add.
#0
#0
Unidirectional DS/QS mode
BL =2
DS
(Input)
QS
(Output)
Low
CL=7
WL=6
Hi-Z
DQ
(Output)
Q0 Q1
D0 D1
D0 D1
D0 D1
BL =4
DS
(Input)
QS
(Output)
Low
Hi-Z
CL=7
WL=6
DQ
(Output)
Q0 Q1 Q2 Q3
Unidirectional DS/Free Running QS mode
BL =2
DS
(Input)
QS
(Output)
CL=7
WL=6
Hi-Z
DQ
Q0 Q1
(Output)
BL =4
DS
(Input)
QS
(Output)
CL=7
WL=6
Hi-Z
DQ
Q0 Q1 Q2 Q3
Read data
D0 D1
(Output)
Write data
- 37 -
REV. 0.11 Apr. 2003
K4C89093AF
Multiple Bank Read Timing (CL=4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
RDA
UA
RDA
UA
LAL
LA
DESL
RDA
UA
RDA
UA
RDA
UA
RDA
UA
RDA
UA
LAL
LA
RDA
UA
Command
Address
LA
LA
LA
LA
LA
Bank
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank
"b"
Bank Add.
lRC(Bank"a")=5cycles
lRC(Bank"b")=5cycles
Unidirectional DS/QS mode
BL =2
DS
(input)
Low
QS
(Output)
CL=4
CL=4
CL=4
CL=4
CL=4
Hi-Z
DQ
(Output)
Qa0 Qa1
Qb0 Qb1
Qa0 Qa1
Qb0 Qb1
Qc0 Qc1
BL =4
DS
(input)
Low
Hi-Z
QS
(Output)
CL=4
DQ
(Output)
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Qc0 Qc1 Qc2
Unidirectional DS/Free Running QS mode
BL =2
DS
(input)
QS
(Output)
CL=4
Hi-Z
DQ
Qa0 Qa1
Qb0 Qb1
Qa0 Qa1
Qb0 Qb1
Qc0 Qc1
(Output)
BL =4
DS
(input)
QS
(Output)
CL=4
Hi-Z
DQ
(Output)
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Qc0 Qc1 Qc2
Note : lRC to the same bank must be satisfied
- 38 -
REV. 0.11 Apr. 2003
K4C89093AF
Multiple Bank Read Timing (CL=5)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
RDA
UA
RDA
UA
LAL
LA
DESL
RDA
UA
RDA
UA
RDA
UA
RDA
UA
RDA
UA
LAL
LA
Command
Address
LA
LA
LA
LA
LA
Bank
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank Add.
lRC(Bank"a")=6cycles
lRC(Bank"6")=6cycles
Unidirectional DS/QS mode
BL =2
DS
(input)
Low
QS
(Output)
CL=5
CL=5
Hi-Z
DQ
(Output)
Qa0 Qa1
Qb0 Qb1
Qa0 Qa1
Qb0 Qb1
BL =4
DS
(input)
Low
Hi-Z
QS
(Output)
CL=5
CL=5
DQ
(Output)
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2
Unidirectional DS/Free Running QS mode
BL =2
DS
(input)
QS
(Output)
CL=5
CL=5
Hi-Z
DQ
(Output)
Qa0 Qa1
Qb0 Qb1
Qa0 Qa1
Qb0 Qb1
BL =4
DS
(input)
QS
(Output)
CL=5
CL=5
Hi-Z
DQ
(Output)
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2
Note : lRC to the same bank must be satisfied
- 39 -
REV. 0.11 Apr. 2003
K4C89093AF
Multiple Bank Read Timing (CL=6)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
RDA
UA
RDA
UA
LAL
LA
DESL
RDA
UA
RDA
UA
RDA
UA
RDA
UA
RDA
UA
Command
Address
LA
LA
LA
LA
LA
Bank
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank Add.
lRC(Bank"a")=7cycles
lRC(Bank"b")=7cycles
Unidirectional DS/QS mode
BL =2
DS
(input)
Low
QS
(Output)
CL=6
CL=6
Hi-Z
DQ
(Output)
Qa0 Qa1
Qb0 Qb1
Qa0 Qa1
BL =4
DS
(input)
Low
Hi-Z
QS
(Output)
CL=6
CL=6
DQ
(Output)
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
Qa0 Qa1 Qa2
Unidirectional DS/Free Running QS mode
BL =2
DS
(input)
QS
(Output)
CL=6
CL=6
Hi-Z
DQ
(Output)
Qa0 Qa1
Qb0 Qb1
Qa0 Qa1
BL =4
DS
(input)
QS
(Output)
CL=6
CL=6
Hi-Z
DQ
(Output)
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
Qa0 Qa1 Qa2
Note : lRC to the same bank must be satisfied
- 40 -
REV. 0.11 Apr. 2003
K4C89093AF
Multiple Bank Read Timing (CL=7)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
RDA
UA
RDA
UA
LAL
LA
DESL
RDA
UA
RDA
UA
RDA
UA
RDA
UA
Command
Address
LA
LA
LA
LA
LA
Bank
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank Add.
lRC(Bank"a")=8cycles
lRC(Bank"a")=8cycles
Unidirectional DS/QS mode
BL =2
DS
(Input)
QS
(Output)
Low
Hi-Z
CL=7
CL=7
DQ
Qa0 Qa1
Qb0 Qb1
Qa0
Qa0
Qa0
Qa0
(Output)
BL =4
DS
(Input)
QS
(Output)
Low
Hi-Z
CL=7
CL=7
DQ
(Output)
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
Unidirectional DS/Free Running QS mode
BL =2
DS
(Input)
QS
(Output)
CL=7
CL=7
Hi-Z
DQ
(Output)
Qa0 Qa1
Qb0 Qb1
BL =4
DS
(Input)
QS
(Output)
CL=7
CL=7
Hi-Z
DQ
(Output)
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
- 41 -
REV. 0.11 Apr. 2003
K4C89093AF
Multiple Bank Write Timing (CL=4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
WRA
UA
WRA
UA
LAL
LA
DESL
WRA
UA
WRA
UA
WRA
UA
WRA
UA
WRA
UA
LAL
LA
WRA
UA
Command
Address
LA
LA
LA
LA
LA
Bank
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank
"b"
Bank Add.
lRC(Bank"a")=5cycles
lRC(Bank"b")=5cycles
Unidirectional DS/QS mode
BL =2
DS
(input)
Low
QS
(Output)
WL=3
WL=3
WL=3
WL=3
WL=3
DQ
(Input)
Da0 Da1
Db0 Db1
Da0 Da1
Db0 Db1
Dc0 Dc1
Dd0 Dd1
BL =4
DS
(input)
Low
QS
(Output)
WL=3
DQ
(Input)
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Dc0 Dc1 Dc2 Dc3 Dd0 Dd1
Unidirectional DS/Free Running QS mode
BL =2
DS
(input)
QS
(Output)
WL=3
DQ
(Input)
Da0 Da1
Db0 Db1
Da0 Da1
Db0 Db1
Dc0 Dc1
Dd0 Dd1
BL =4
DS
(input)
QS
(Output)
WL=3
DQ
(Input)
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Dc0 Dc1 Dc2 Dc3 Dd0 Dd1
Note : lRC to the same bank must be satisfied
- 42 -
REV. 0.11 Apr. 2003
K4C89093AF
Multiple Bank Write Timing (CL=5)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
WRA
UA
WRA
UA
LAL
LA
DESL
WRA
UA
WRA
UA
WRA
UA
WRA
UA
WRA
UA
LAL
LA
Command
Address
LA
LA
LA
LA
LA
Bank
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank Add.
lRC(Bank"a")=6cycles
lRC(Bank"b")=6cycles
Unidirectional DS/QS mode
BL =2
DS
(input)
Low
QS
(Output)
WL=4
WL=4
DQ
(input)
Da0 Da1
Db0 Db1
Da0 Da1
Db0 Db1
Dc0 Dc1
BL =4
DS
(input)
Low
QS
(Output)
WL=4
WL=4
DQ
(input)
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Dc0 Dc1
Unidirectional DS/Free Running QS mode
BL =2
DS
(input)
QS
(Output)
WL=4
WL=4
DQ
(input)
Da0 Da1
Db0 Db1
Da0 Da1
Db0 Db1
Dc0 Dc1
BL =4
DS
(input)
QS
(Output)
WL=4
WL=4
DQ
(input)
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Dc0 Dc1
Note :IRC to the same bank must be satisfied.
- 43 -
REV. 0.11 Apr. 2003
K4C89093AF
Multiple Bank Write Timing (CL=6)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
WRA
UA
WRA
UA
LAL
LA
DESL
WRA
UA
WRA
UA
WRA
UA
WRA
UA
WRA
UA
Command
Address
LA
LA
LA
LA
LA
Bank
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank Add.
lRC(Bank"a")=7cycles
lRC(Bank"a")=7cycles
Unidirectional DS/QS mode
BL =2
DS
(input)
Low
QS
(Output)
WL=5
WL=5
DQ
(input)
Da0 Da1
Db0 Db1
Da0 Da1
Db0 Db1
BL =4
DS
(input)
Low
QS
(Output)
WL=5
WL=5
DQ
(input)
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
Da0 Da1 Da2 Da3 Db0 Db1
Unidirectional DS/Free Running QS mode
BL =2
DS
(input)
QS
(Output)
WL=5
WL=5
DQ
(input)
Da0 Da1
Db0 Db1
Da0 Da1
Db0 Db1
BL =4
DS
(input)
QS
(Output)
WL=5
WL=5
DQ
(input)
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
Da0 Da1 Da2 Da3 Db0 Db1
Note :IRC to the same bank must be satisfied.
- 44 -
REV. 0.11 Apr. 2003
K4C89093AF
Multiple Bank Write Timing (CL=7)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
lRBD=2cycles
LAL
WRA
UA
WRA
UA
LAL
LA
DESL
WRA
UA
WRA
UA
WRA
UA
WRA
UA
Command
Address
LA
LA
LA
LA
LA
Bank
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank Add.
lRC(Bank"a")=8cycles
lRC(Bank"a")=8cycles
Unidirectional DS/QS mode
BL =2
DS
(Input)
Low
QS
(Output)
WL=6
WL=6
DQ
(Output)
Da0 Da1
Db0 Db1
BL =4
DS
(Input)
Low
QS
(Output)
WL=6
WL=6
DQ
(Output)
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
Unidirectional DS/Free Running QS mode
BL =2
DS
(Input)
QS
(Output)
WL=6
WL=6
DQ
(Output)
Da0 Da1
Db0 Db1
BL =4
DS
(Input)
QS
(Output)
WL=6
WL=6
DQ
(Output)
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
Note :IRC to the same bank must be satisfied.
- 45 -
REV. 0.11 Apr. 2003
K4C89093AF
Multiple Bank Read-Write Timing (BL=2)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRBD=2cycles
LAL
WRA
UA
RDA
UA
LAL
LA
DESL
WRA
UA
LAL
LA
RDA
UA
LAL
LA
DESL
WRA
UA
LAL
LA
RDA
UA
LAL
LA
DESL
WRA
UA
Command
Address
LA
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank
"b"
Bank
"c"
Bank Add.
lRC(Bank"a")
lRC(Bank"a")
Unidirectional DS/QS mode
CL =4
DS
(Input)
Low
QS
(Output)
CL=4
Da0 Da1
WL=3
Hi-Z
DQ
Qb0 Qb1
Dc0 Dc1
Qd0 Qd1
Da0 Da1
(Output)
CL =5
DS
(Input)
Low
Hi-Z
QS
(Output)
CL=5
Da0 Da1
WL=4
WL=5
WL=6
DQ
Qb0 Qb1
Dc0 Dc1
Qd0 Qd1
Da0 Da1
(Output)
CL =6
DS
(Input)
Low
Hi-Z
QS
(Output)
CL=6
DQ
Da0 Da1
Qb0 Qb1
Dc0 Dc1
Qd0 Qd1
(Output)
CL =7
DS
(Input)
Low
Hi-Z
QS
(Output)
CL=7
DQ
Da0 Da1
Qb0 Qb1
Dc0 Dc1
Qd0
(Output)
Note :IRC to the same bank must be satisfied.
- 46 -
REV. 0.11 Apr. 2003
K4C89093AF
Multiple Bank Read-Write Timing (BL=2)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRBD=2cycles
LAL
WRA
UA
RDA
UA
LAL
LA
DESL
WRA
UA
LAL
LA
RDA
UA
LAL
LA
DESL
WRA
UA
LAL
LA
RDA
UA
LAL
LA
DESL
WRA
UA
Command
Address
LA
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank
"b"
Bank
"c"
Bank Add.
lRC(Bank"a")
lRC(Bank"a")
Unidirectional DS/Free Running QS mode
CL =4
DS
(Input)
QS
(Output)
CL=4
Da0 Qa1
WL=3
WL=4
WL=5
WL=6
Hi-Z
DQ
Qb0 Qb1
Dc0 Qc1
Qd0 Qd1
Da0 Da1
(Output)
CL =5
DS
(Input)
QS
(Output)
CL=5
Da0 Da1
Hi-Z
DQ
Qb0 Qb1
Dc0 Dc1
Qd0 Qd1
Da0 Da1
(Output)
CL =6
DS
(Input)
QS
(Output)
CL=6
Hi-Z
DQ
Da0 Da1
Qb0 Qb1
Dc0 Dc1
Qd0 Qd1
(Output)
CL =7
DS
(Input)
QS
(Output)
CL=7
Hi-Z
DQ
Da0 Da1
Qb0 Qb1
Dc0 Dc1
Qd0 Qd1
(Output)
Note :IRC to the same bank must be satisfied.
- 47 -
REV. 0.11 Apr. 2003
K4C89093AF
Multiple Bank Read-Write Timing (BL=4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRBD=2cycles
LAL
WRA
UA
RDA
LAL
LA
DESL
lRWD=3cycles
WRA
UA
LAL
RDA
LAL
LA
DESL
WRA
UA
LAL
RDA
LAL
LA
Command
lWRD=1cycle
lWRD=1cycle
lRWD=3cycles
lWRD=1cycle
Address
LA
UA
LA
UA
LA
UA
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank
"b"
Bank Add.
lRC(Bank"a")
lRC(Bank"a")
Unidirectional DS/QS mode
CL =4
DS
(Input)
Low
QS
(Output)
CL=4
Da0 Da1 Da2 Da3
WL=3
Hi-Z
DQ
Qb0 Qb1 Qb2 Qb3
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
(Output)
CL =5
DS
(Input)
Low
Hi-Z
QS
(Output)
CL=5
Da0 Da1 Da2 Da3
WL=4
WL=5
WL=6
DQ
Qb0 Qb1 Qb2 Qb3
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
(Output)
CL =6
DS
(Input)
Low
Hi-Z
QS
(Output)
CL=6
DQ
Da0 Da1
Qb0 Qb1 Qb2 Qb3
Da0 Da1
Qb0 Qb1
Da2 Da3
Da2 Da3
(Output)
CL =7
DS
(Input)
Low
Hi-Z
QS
(Output)
CL=7
DQ
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
Da0 Da1 Da2 Da3
(Output)
Note :IRC to the same bank must be satisfied.
- 48 -
REV. 0.11 Apr. 2003
K4C89093AF
Multiple Bank Read-Write Timing (BL=4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRBD=2cycles
LAL
WRA
UA
RDA
LAL
LA
DESL
lRWD=3cycles
WRA
UA
LAL
RDA
LAL
LA
DESL
WRA
UA
LAL
RDA
LAL
LA
Command
lWRD=1cycle
lWRD=1cycle
lRWD=3cycles
lWRD=1cycle
Address
LA
UA
LA
UA
LA
UA
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank
"b"
Bank Add.
lRC(Bank"a")
lRC(Bank"a")
Unidirectional DS/Free Running QS mode
CL =4
DS
(Input)
QS
(Output)
CL=4
Da0 Da1 Da2 Da3
WL=3
WL=4
WL=5
WL=6
Hi-Z
DQ
Qb0 Qb1 Qb2 Qb3
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
(Output)
CL =5
DS
(Input)
UQS
(Output)
CL=5
Da0 Da1 Da2 Da3
Hi-Z
DQ
Qb0 Qb1 Qb2 Qb3
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
(Output)
CL =6
DS
(Input)
QS
(Output)
CL=6
Da0 Da1 Da2 Da3
Hi-Z
DQ
Qb0 Qb1 Qb2 Qb3
Da0 Da1 Da2 Da3
Qb0 Qb1
(Output)
CL =7
DS
(Input)
QS
(Output)
CL=7
Da0 Da1 Da2 Da3
Hi-Z
DQ
Qb0 Qb1 Qb2 Qb3
Da0 Da1 Da2 Da3
(Output)
Note :IRC to the same bank must be satisfied.
- 49 -
REV. 0.11 Apr. 2003
K4C89093AF
Write with Variable Write Length (VW) Control(CL=4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
BL=2, SEQUENTIAL MODE
WRA
LAL
DESL
WRA
UA
LAL
DESL
Command
Address
LA=#3
VW=All
LA=#1
VW=1
UA
VW0 = Low
VW1 = don’t care
VW0 = High
VW1 = don’t care
Bank
"a"
Bank
"a"
Bank Add.
DS
(Input)
DQ
(Input)
D0 D1
D0
Lower Address #3 #2
#1 (#0)
Last one data is masked.
BL=4, SEQUENTIAL MODE
WRA
LAL
DESL
WRA
UA
LAL
DESL
WRA
UA
LAL
DESL
Command
LA=#3
VW=All
LA=#1
VW=1
LA=#2
VW=2
UA
Address
VW0 = High
VW1 = Low
VW0 = High
VW1 = High
VW0 = Low
VW1 = High
Bank
"a"
Bank
"a"
Bank
"a"
Bank Add.
DS
(Input)
DQ
(Input)
D0 D1 D2 D3
Lower Address #3 #0 #1 #2
D0
D0 D1
#2 #3 (#0) (#1)
#1 (#2) (#3) (#0)
Last three data are masked.
Last two data are masked.
Note : DS input must be continued till end of burst count even if some of laster data is masked.
- 50 -
REV. 0.11 Apr. 2003
K4C89093AF
Power Down Timing (CL=4, BL=4)
Read cycle to Power Down Mode
0
1
2
3
4
5
6
7
8
9
10
n-1
n
n+1
n+2
n+3
CLK
CLK
BL=2, SEQUENTIAL MODE
RDA
or
RDA
LAL
DESL
DESL
Command
Address
WRA
IPDA
UA
LA
UA
IPD=2 cycle
tIS
tIH
PD
tQPDH
tPDEX
IRC(min), tREFI(max)
Unidirectional DS/QS mode
DS
(input)
QS
(Output)
Low
CL=4
Hi-Z
Hi-Z
DQ
(Output)
Q0 Q1 Q2 Q3
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(Output)
CL=4
Hi-Z
DC
(Output)
Hi-Z
Q0 Q1 Q2 Q3
Power Down Entry
Power Down Exit
Note :
PD must be kept "High" level until end of Burst data output.
PD should be brought to "High" within tREFI(max.) to maintain the data written into cell.
In Power Down Mode, PD "Low" and a stable clock signal must be maintained.
When PD is brought to "High", a valid executable command may be applied IPDA cycles later.
- 51 -
REV. 0.11 Apr. 2003
K4C89093AF
Power Down Timing (CL=4, BL=4)
Write cycle to Power Down Mode
0
1
2
3
4
5
6
7
8
9
10
n-1
n
n+1
n+2
n+3
CLK
CLK
IPDA
RDA
or
WRA
UA
LAL
LA
DESL
DESL
Command
Address
WRA
UA
IPD=2 cycle
tIS
tIH
PD
tPDEX
IPD=2 cycle
WL=3
IRC(min), tREFI(max)
Unidirectional DS/QS mode
DS
(input)
QS
Low
(Output)
WL=3
DC
(Output)
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(Output)
WL=3
DC
(Output)
D0 D1 D2 D3
Note :
PD must be kept "High" level until end of Burst data output.
PD should be brought to "High" within tREFI(max.) to maintain the data written into cell.
In Power Down Mode, PD "Low" and a stable clock signal must be maintained.
When PD is brought to "High", a valid executable command may be applied IPDA cycles later.
- 52 -
REV. 0.11 Apr. 2003
K4C89093AF
Mode Register Set Timing (CL=4, BL=2)
From Read operation to Mode Register Set operation
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRC=7cycles
RDA
or
RDA
UA
LAL
LA
DESL
RDA
MRS
DESL
LAL
LA
Command
A14~A0
WRA
Valid
(opcode)
UA
BA0="0"
BA1="0"
BA0, BA1
BA
BA
CL + BL/2
Unidirectional DS/QS mode
DS
(input)
QS
Low
(Output)
DC
(Output)
Q0 Q1
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(Output)
DQ
(Output)
Q0 Q1
Note : Minimum delay from LAL following RDA to RDA of MRS operation is CL+BL/2.
- 53 -
REV. 0.11 Apr. 2003
K4C89093AF
Mode Register Set Timing (CL=4, BL=4)
From Write operation to Mode Register Set operation
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRC=7cycles
RDA
or
WRA
UA
LAL
LA
DESL
RDA
MRS
DESL
LAL
LA
Command
A14~A0
WRA
Valid
(opcode)
UA
BA0="0"
BA1="0"
BA0, BA1
BA
BA
WL + BL/2
Unidirectional DS/QS mode
DS
(input)
QS
Low
(Output)
DC
(input)
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(Output)
DC
(input)
D0 D1 D2 D3
Note : Minimum delay from LAL following WRA to RDA of MRS operation is WL+BL/2.
- 54 -
REV. 0.11 Apr. 2003
K4C89093AF
Extended Mode Register Set Timing (CL=4, BL=2)
From Read operation to Extended Mode Register Set operation
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRC=7cycles
RDA
or
RDA
UA
LAL
LA
DESL
RDA
MRS
DESL
LAL
LA
Command
A14~A0
WRA
Valid
(opcode)
UA
BA0="0"
BA1="0"
BA0, BA1
BA
BA
CL + BL/2
Unidirectional DS/QS mode
DS
(input)
QS
(Output)
Low
DC
(Output)
Q0 Q1
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(Output)
DC
(Output)
Q0 Q1
Note :
Minimum delay from LAL following RDA to RDA of EMRS operation is CL+BL/2.
When DQ strobe mode is changed by EMRS, QS output is invalid for IRSC period.
DLL switch in Extended Mode Register must be set to enable mode for normal operation.
DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence.
- 55 -
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K4C89093AF
Extended Mode Register Set Timing (CL=4, BL=4)
From Write operation to Extended Mode Register Set operation
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
lRC=7cycles
RDA
or
WRA
UA
LAL
LA
DESL
RDA
MRS
DESL
LAL
LA
Command
A14~A0
WRA
Valid
(opcode)
UA
BA0="0"
BA1="0"
BA0, BA1
BA
BA
WL + BL/2
Unidirectional DS/QS mode
DS
(input)
QS
Low
(Output)
DQC
(input)
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(Output)
DQ
(input)
D0 D1 D2 D3
Note :
When DQ strobe mode is changed by EMRS, QS output is invalid for IRSC period.
DLL switch in Extended Mode Register must be set to enable mode for normal operation.
DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence.
Minimum delay from LAL following WRA to RDA of EMRS operation is WL+BL/2.
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K4C89093AF
Auto-Refresh Timing (CL=4, BL=4)
Unidirectional DS/QS mode
0
1
2
3
4
5
6
7
n-1
n
n+1
n+2
CLK
CLK
lRC=5cycles
lREFC=19cycles
DESL
RDA
or
LAL or
MRS or
REF
RDA
LAL
LA
DESL
WRA
REF
Command
WRA
Bank,
UA
Bank, Address
lRCD=1cycle
Low
lRAS=4cycles
lRCD=1cycle
QS
(output)
Low
CL=4
Hi-Z
Hi-Z
DQ
(output)
Q0 Q1 Q2 Q3
Unidirectional DS/Free Running QS mode
CLK
CLK
lRC=5cycles
lREFC=19cycles
RDA
or
LAL or
MRS or
REF
RDA
LAL
LA
DESL
WRA
REF
DESL
Command
WRA
Bank,
UA
Bank, Address
lRCD=1cycles
lRAS=4cycles
lRCD=1cycles
QS
(output)
CL=4
Hi-Z
Hi-Z
DQ
(output)
Q0 Q1 Q2 Q3
Note :
In case of CL=4, IREFC must be meet 19 clock cycles.
When the Auto-Refresh operation is perfomed, the synthetic average interval of Auto-Refresh command
specified by tREFI must be satisfied.
tREFI is average interval time in 8 Refresh cycles that is sampled randomly.
t1
t2
t3
t7
t8
CLK
WRA REF
WRA REF
WRA REF
WRA REF
WRA REF
8 Refresh cycle
t1+t2+t3+t4+t5+t6+t7+t8
8
Total time of 8 Refresh cycle
8
tREFI
=
=
tREFI is specified to avoid partly concentrated current of Refresh operation that is acivated
larger are than Read/Write operation.
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K4C89093AF
Self-Refresh Entry Timing
Unidirectional DS/Free Running QS mode
0
1
2
3
4
5
m-1
m
m+1
CLK
CLK
lRCD=1cycle
lREFC
WRA
REF
DESL
Command
PD
tFPDL (min) tFPDL (max)
Auto Refresh
Self Refresh Entry
*2
lPDV
tQPDH
lCKD
Hi-Z
Hi-Z
LQS/UQS
(output)
DQ
(output)
Qx
Note :
1.
is don’t care.
2. PD must be brought to "Low" within the timing between tFPDL(min) and tFPDL(max) to Self Refresh mode. When PD is brought to
"Low" after IPDV, K4C89183AF perform Auto Refresh and enter Power down mode. In case of PD fall between tFPDL(max) and IPDV
,
K4C89363AF will either entry self refresh mode or power down mode after auto refresh operation. It can’t be specified which mode
K4C89363AF operates.
3. It is desirable that clock input is continued at least ICKD from REF command even though PD is brought to "Low" for Self-Refresh Entry.
4. In case of self refresh entry after write operation from the LAL command following WRA to the REF command delay time is write
latency(WL) + 2 clock clycles minimum.
Self-Refresh Exit Timing
Unidirectional DS/Free Running QS mode
0
1
3
m-1
m
m+1
m+2
n-1
n
n+1
p-1
p
CLK
CLK
Command (1st)*6
lREFC
lREFC
DESL
Command (2nd)*6
DESL
lPDA=2cycles*4
WRA*5
REF*5
RDA*7
LAL*7
Command
lRCD=1cycle
lRCD=1cycle
tPDEX
PD
lLOCK
LQS/UQS
(output)
Hi-Z
DQ
(output)
Self-Refresh Exit
Note :
1.
is don’t care.
2. Clock should be stable prior to PD = "High" if clock input is suspended in Self-Refresh mode.
3. DESL command must be asserted during IREFC after PD is brought to "High"
4. lPDA is defined from the first clock rising edge after PD is brought to "High"
5. It is desirable that one Auto-Refresh command is issued just after Self-Refresh Exit before any other
operation.
6. Any command (except Read command) can be issued after lREFC
.
7. Read command (RDA +LAL) can be issued after lLOCK
.
8. QS output is invalid until DLL lock from Self-Refresh exit.
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K4C89093AF
Function Description
Network - DRAM
Network - DRAM is an acronym of Double Data Rate Network - DRAM.
Network - DRAM is competent to perform fast random core access, low latency and high-speed data transfer.
Pin Functions
Clock Inputs : CLK & CLK
The CLK and CLK inputs are used as the reference for synchronous operation. CLK is master clock input. The CS, FN and all
address input signals are sampled on the crossing of the positive edge of CLK and the negative edge of CLK. The QS and DQ output
data are aligned to the crossing point of CLK and CLK. The timing reference point for the differential clock is when the CLK and CLK
signals cross during a transition.
Power Down : PD
The PD input controls the entry to the Power Down or Self-Refresh modes. The PD input does not have a Clock Suspend function like
a CKE input of a standard SDRAMs, therefore it is illegal to bring PD pin into low state if any Read or Write operation is being per-
formed.
Chip Select & Function Control : CS & FN
The CS and FN inputs are a control signal for forming the operation commands on Network-DRAM. Each operation mode is decided
by the combination of the two consecutive operation commands using the CS and FN inputs.
Bank Addresses : BA0 & BA1
The BA0 and BA1 inputs are latched at the time of assertion of the RDA or WRA command and are selected the bank to be used for
the operation. BA0 and BA1 also define which mode register is loaded during the Mode Register Set command (MRS or EMRS).
BA0
0
BA1
0
Bank #0
Bank #1
Bank #2
Bank #3
1
0
0
1
1
1
Address Inputs : A0 to A14
Address inputs are used to access the arbitrary address of the memory cell array within each bank. The Upper Addresses with Bank
address are latched at the RDA or WRA command and the Lower Addresses are latched at the LAL command. The A0 to A14 inputs
are also used for setting the data in the Regular or Extended Mode Register set cycle.
Upper Address
Lower Address
K4C89093AF
A0 to A14
A0 to A7
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K4C89093AF
Functional Description (Continued)
Data Input/Output : DQ0 ~ DQ8
The input data of DQ0 to DQ8 are taken in synchronizing with the both edges of DS input signal.
The output data of DQ0 to DQ8 are outputted synchronizing with the both edges of QS output signal.
Data Strobe : DS or QS
Method of data strobe is chosen by Extended mode register.
(1) Unidirectional DS/QS mode
DS is input signal and QS is output signal. Both edges of DS are used to sample all DQs at Write operation. Both edges of QS
are used for trigger signal of all DQs at Read operation. During Write. Auto-Refresh and NOP cycle, QS assert always "Low"
level. QS is Hi-Z in Self-Refresh mode.
(2) Unidirectional DS/Free running QS mode
DS is input signal and QS is output signal. Both edges of DS are used to sample all DQs at Write operation. Both edges of QS
are used for trigger signal of all DQs at Read operation. QS assert always toggle signal except Self-Refresh mode. This strobe
type is easy to use for pin to pin connect application.
Power Supply : VDD, VDDQ, VSS, VSSQ
VDD and VSS are supply pins for memory core and peripheral circuits.
VDDQ and VSSQ are power supply pins for the output buffer.
Reference Voltage : VREF
VREF is reference voltage for all input signals.
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K4C89093AF
Command Functions and Operations
K4C89093AF is introduced the two consecutive command input method. Therefore, except for Power Down mode, each operation
mode decided by the combination of the first command and the second command from stand-by states of the bank to be accessed.
Read Operation (1st command + 2nd command = RDA + LAL)
Issuing the RDA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address in
a read mode. When the LAL command with Lower Addresses is issued at the next clock of the RDA command, the data is read out
sequentially synchronizing with the both edges of QS output signal (Burst Read Operation). The initial valid read data appears after
CAS latency, the burst length of read data and the burst type must be set in the Mode Register beforehand. The read operated bank
goes back automatically to the idle state after IRC
.
Write Operation (1st command + 2nd command = WRA + LAL)
Issuing the WRA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address in
a write mode. When the LAL command with Lower Addresses is issued at the next clock of the WRA command, the input data is
latched sequentially synchronizing with the both edges of DS input signal (Burst Write Operation). The data and DS inputs have to be
asserted in keeping with clock input after CAS latency-1 from the issuing of the LAL command. The DS have to be provided for a burst
length. The CAS latency and the burst type must be set in the Mode Register beforehand. The write operated bank goes back automat-
ically to the idle state after IRC. Write Burst Length is controlled by VW0 and VW1 inputs with LAL command. See VW truth table.
Auto-Refresh Operation (1st command + 2nd command = WRA + REF)
K4C89093AF is required to refresh like a standard SDRAM. The Auto-Refresh operation is begun with the REF command following to
the WRA command. The Auto-Refresh mode can be effective only when all banks are in the idle state and all DQ are in Hi-Z states. In
a point to notice, the write mode started with the WRA command is canceled by the REF command having gone into the next clock of
the WRA command instead of the LAL command. The minimum period between the Auto-Refresh command and the next command is
specified by IREFC. However, about a synthetic average interval of Auto-Refresh command, it must be careful. In case of equally distrib-
uted refresh, Auto-Refresh command has to be issued within once for every 3.9 us by the maximum In case of burst refresh or random
distributed refresh, the average interval of eight consecutive Auto-Refresh command has to be more than 400ns always. In other words,
the number of Auto-Refresh cycles which can be performed within 3.2 us (8x400ns) is to 8 times in the maximum.
Self-Refresh Operation (1st command + 2nd command = WRA + REF with PD="L")
It is the function of Self-Refresh operation that refresh operation can be performed automatically by using an internal timer. When all
banks are in the idle state and all outputs are in Hi-z states, the K4C89093AF become Self-Refresh mode by issuing the Self-Refresh
command. PD has to be brought to "Low" within tFPDL from the REF command following to the WRA command for a Self-Refresh mode
entry. In order to satisfy the refresh period, the Self-Refresh entry command should be asserted within 3.9us after the latest Auto-
Refresh command. Once the device enters Self-Refresh mode, the DESL command must be continued for IREFC period. In addition, it
is desirable that clock input is kept in ICKD period. The device is in Self-Refresh mode as long as PD held "Low". During Self-Refresh
mode, all input and output buffers except for PD are disabled, therefore the power dissipation lowers. Regarding a Self-Refresh mode
exit, PD has to be changed over from "Low" to "High" along with the DESL command, and the DESL command has to be continuously
issued in the number of clocks specified by IREFC. The Self-Refresh exit function is asynchronous operation. It is required that one Auto-
Refresh command is issued to avoid the violence of the refresh period just after IREFC from Self-Refresh exit.
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K4C89093AF
Power Down Mode( PD="L" )
When all banks are in the idle state and all DQ outputs are in Hi-Z states, the K4C89183AF become Power Down Mode by asserting
PD is "Low". When the device enters the Power Down Mode, all input and output buffers except for PD, CLK, CLK and QS. Therefore,
the power dissipation lowers. To exit the Power Down Mode, PD has to be brought to "High" and the DESL command has to be issued
for IPDA cycle after PD goes high. The Power Down exit function is asynchronous operation.
Mode Register Set (1st command + 2nd command = RDA + MRS)
When all banks are in the idle state, issuing the MRS command following to the RDA command can program the Mode Register. In a
point to notice, the read mode started with the RDA command is canceled by the MRS command having gone into the next clock of
the RDA command instead of the LAL command. The data to be set in the Mode Register is transferred using A0 to A14, BA0 and BA1
address inputs. The K4C89183AF have two mode registers. These are Regular and Extended Mode Register. The Regular or
Extended Mode Register is chosen by BA0 and BA1 in the MRS command.The Regular Mode Register designates the operation mode
for a read or write cycle. The Regular Mode Register has four function fields.
The four fields are as follows :
(R-1) Burst Length field to set the length of burst data
(R-2) Burst Type field to designate the lower address access sequence in a burst cycle
(R-3) CAS Latency field to set the access time in clock cycle
(R-4) Test Mode field to use for supplier only.
The Extended Mode Register has two function fields.
The two fields are as follows:
(E-1) DLL Switch field to choose either DLL enable or DLL disable
(E-2) Output Driver Impedance Control field.
(E-3) Data Strobe Select
Once these fields in the Mode Register are set up, the register contents are maintained until the Mode Register is set up again by
another MRS command or power supply is lost. The initial value of the Regular or Extended Mode Register after power-up is unde-
fined, therefore the Mode Register Set command must be issued before proper operation.
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K4C89093AF
• Regular Mode Register/Extended Mode Register change bits (BA0, BA1)
These bits are used to choose either Regular MRS or Extended MRS
BA1
BA0
0
A14~A0
0
0
1
Regular MRS cycle
Extended MRS cycle
Reserved
1
X
Regular Mode Register Fields
(R-1) Burst Length field (A2 to A0)
This field specifies the data length for column access using the A2 to A0 pins and sets the Burst Length to be 2 or 4
words.
A2
0
A1
0
A0
0
Burst Length
Reserved
2 words
0
0
1
0
1
0
4 words
0
1
1
Reserved
Reserved
1
X
X
(R-2) Burst Type field (A3)
This Burst Type can be chosen Interleave mode or Sequential mode. When the A3 bit is " 0", Sequential mode is
selected. When the A3 bit is "1", Interleave mode is selected. Both burst types support burst length of 2 and 4 words.
A3
0
Burst Type
Sequential
Interleave
1
• Addressing sequence of Sequential mode (A3)
A column access is started from the inputted lower address and is performed by incrementing the lower address input to
the device.
CAS Latency = 4 (Free Running QS mode)
CK
CK
Command
QS
RDA
LAL
DQ
Data 0 Data 1 Data 2 Data 3
Addressing sequence for Sequential mode
Data
Access Address
Burst Length
Data 0
Data 1
Data 2
Data 3
n
2 words (Address bits is LA0)
not carried from LA0~LA1
4 words(Address bits is LA1, LA0)
not carried from LA1~LA2
n + 1
n + 2
n + 3
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K4C89093AF
Functional Description (Continued)
• Addressing sequence of Inteleave mode
A column access is started from the inputted lower address and is performed by interleaving the address bits in the
sequence shown as the following.
Addressing sequence for Interleave mode
Data
Access Address
Burst Length
Data 0
Data 1
Data 2
Data 3
...A8 A7 A6 A5 A4 A3 A2 A1 A0
...A8 A7 A6 A5 A4 A3 A2 A1 A0
...A8 A7 A6 A5 A4 A3 A2 A1 A0
...A8 A7 A6 A5 A4 A3 A2 A1 A0
2 words
4 words
(R-3) CAS Latency field (A6 to A4)
This field specifies the number of clock cycles from the assertion of the LAL command following the RDA command to
the first data read. The minimum values of CAS Latency depends on the frequency of CLK. In a write mode, the place of
clock which should input write data is CAS Latency cycles - 1.
Addressing sequence for Interleave mode
A6
0
A5
0
A4
0
CAS Latency
Reserved
0
0
1
Reserved
0
1
0
Reserved
0
1
1
Reserved
1
0
0
4
5
6
7
1
0
1
1
1
0
1
1
1
(R-4) Test Mode field (A7)
This bit is used to enter Test Mode for supplier only and must be set to "0" for normal operation.
(R-5) Reserved field in the Regular Mode Register
• Reserved bits (A8 to A14)
These bits are reserved for future operations. They must be set to "0" for normal operation.
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K4C89093AF
Extended Mode Register Fields
(E-1) DLL Switch field (A0)
This bit is used to enable DLL. When the A0 bit is set "0", DLL is enabled.
(E-2) Output Driver Impedance Control field (A1 to A4)
This field is used to choose Output Driver Strength. Four types of Driver Strength are supported. QS and DQ Driver
Strength can be chosen separately. A2-A1 specified the DQ Driver Strength. A4-A3 specified the QS Driver Strength.
QS
DQ
Output Driver Impedance Control
A4
0
A3
0
A2
0
A1
0
Normal Output Driver
Strong Output Driver
Weaker Output Driver
Reserved
0
1
0
1
1
0
1
0
1
1
1
1
(E-3) Strobe Select (A6/A5)
Two types of strobe are supported. This field is used to choose the type of data strobe.
(1) Unidirectional DS/QS mode
Data strobe is separated DS for write strobe and QS for read strobe.
DS is used to sample write data at write operation. QS is aligned with read data at Read operation.
(2) Unidirectional DS/Free running QS mode
Data strobe is separated DS for write strobe and QS for read strobe.
DS is used to sample write data at write operation. QS is aligned with read data and always clocking
A6
0
A5
0
Strobe Select
Reserved
0
1
Reserved
1
0
Unidirectional DS/QS mode
Unidirectional DS/Free running QS mode
1
1
(E-4)Reserved fied (A7 to A14)
These bits are reserved for future operations and must be set to "0" for normal operation.
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K4C89093AF
Package Outline Drawing (FBGA 60ball, 1.0 x 1.0 mm) - will be added
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K4C89093AF
General Information
Organization
288M(x9)
G7 (800Mbps@CL7)
F6 (667Mbps@CL6)
K4C89093AF-GC(I)F6
K4C89183AF-GC(I)F6
K4C89363AF-GC(I)F6
FB (600Mbps@CL6 )
K4C89093AF-GC(I)FB
K4C89183AF-GC(I)FB
K4C89363AF-GC(I)FB
F5 (500Mbps@CL6 )
K4C89093AF-GC(I)F5
K4C89183AF-GC(I)F5
K4C89363AF-GC(I)F5
K4C89093AF-GC(I)G7
K4C89183AF-GC(I)G7
K4C89363AF-GC(I)G7
288M(x18)
288M(x36)
1
2
3
4
5
6
7
8
9
10 11
K 4 C XX XX X X X - X X XX
Memory
DRAM
Speed
Temperature & Power
Package
Small Classification
Density and Refresh
Version
Organization
Bank
Interface (VDD & VDDQ)
1. SAMSUNG Memory : K
8. Version
F : 7th Generation
2. DRAM : 4
3. Small Classification
C : Network-DRAM
9. Package
G : 144 FBGA
4. Density & Refresh
89 : 288M 8K/32ms
10. Temperature & Power
C : (Commercial, Normal)
5. Organization
I
: (Industrial, Normal)
32 : x32
36 : x36
11. Speed
G7 :800Mbps/pin (400MHz, CL=7)
F6 : 667Mbps/pin (333MHz, CL=6)
FB :533Mbps/pin (266MHz,CL=5)
F5 : 400Mbps/pin (200MHz, CL=4)
6. Bank
3 : 4 Bank
7. Interface (VDD & VDDQ)
A: SSTL-2(2.5V, 1.8V)
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相关型号：
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