K1S2816BCA-I70 [SAMSUNG]
DRAM;
SAMSUNG 
K1S2816BCA
UtRAM
128Mb (8M x 16 bit) UtRAM
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Revision 1.0
May 2006
- 1 -
K1S2816BCA
UtRAM
Document Title
8Mx16 bit Page Mode Uni-Transistor Random Access Memory
Revision History
RevisionNo.
History
Draft Date
Remark
1.0
Finalized
May 15, 2006
Final
Revision 1.0
May 2006
- 2 -
K1S2816BCA
UtRAM
Table of Contents
GENERAL DESCRIPTION...............................................................................................................................1
FEATURES & FUNCTION BLOCK DIAGRAM ................................................................................................1
PRODUCT FAMILY..........................................................................................................................................1
POWER UP SEQUENCE.................................................................................................................................2
TIMING WAVEFORM OF POWER UP(1) (CS1 controlled).......................................................................2
TIMING WAVEFORM OF POWER UP(2) (CS2 controlled).......................................................................2
FUNCTIONAL DESCRIPTION.........................................................................................................................2
ABSOLUTE MAXIMUM RATINGS...................................................................................................................3
RECOMMENDED DC OPERATING CONDITIONS.........................................................................................3
CAPACITANCE................................................................................................................................................3
DC AND OPERATING CHARACTERISTICS...................................................................................................3
AC OPERATING CONDITIONS.......................................................................................................................4
AC CHARACTERISTICS..................................................................................................................................4
TIMING WAVEFORMS ....................................................................................................................................5
TIMING WAVEFORM OF READ CYCLE(1)...............................................................................................5
TIMING WAVEFORM OF READ CYCLE(2)...............................................................................................5
TIMING WAVEFORM OF PAGE CYCLE (READ ONLY)...........................................................................5
TIMING WAVEFORM OF WRITE CYCLE(1).............................................................................................6
TIMING WAVEFORM OF WRITE CYCLE(2).............................................................................................6
TIMING WAVEFORM OF WRITE CYCLE(3).............................................................................................7
TIMING WAVEFORM OF WRITE CYCLE(4).............................................................................................7
Revision 1.0
May 2006
- 1 -
K1S2816BCA
UtRAM
8M x 16 bit Page Mode Uni-Transistor Random Access Memory
GENERAL DESCRIPTION
The K1S2816BCA is fabricated by SAMSUNG′s advanced CMOS technology using one transistor memory cell. The device sup-
ports 4 page read operation and Industrial temperature range. The device supports dual chip selection for user interface. The
device also supports internal Temperature Compensated Self Refresh mode for the standby power saving at room temperature
range.
FEATURES & FUNCTION BLOCK DIAGRAM
Clk gen.
Pre-charge circuit
• Process technology: CMOS
• Organization: 8M x 16 bit
• Power supply voltage: 1.7V~1.95V
• Internal TCSR
V
V
CC
SS
Memory
Array
Row
Row
select
Addresses
I/O Circuit
Data
cont
I/O0~I/O
7
Column Select
Data
cont
I/O8~I/O15
Data
cont
Column Address
CS2
CS1
OE
WE
UB
LB
Control Logic
PRODUCT FAMILY
Power Dissipation
Speed
Product Family
Operating Temp.
Vcc Range
PKG Type
Standby
Operating
(tRC)
(ISB1, Max.)
(ICC2P, Max.)
250µA < 85°C
135µA < 40°C
K1S2816BCA-I
Industrial(-25~85°C)
1.7~1.95V
70ns
20mA
TBD
Revision 1.0
May 2006
- 1 -
K1S2816BCA
UtRAM
POWER UP SEQUENCE
During the Power Up mode, the standby current can not be guaranteed. To get the stable standby current level, at least one cycle
of active operation should be implemented regardless of wait time duration. To get the appropriate device operation, be sure to
keep the following power up sequence.
1. Apply power.
2. Maintain stable power(Vcc min.=1.7V) for a minimum 200µs with CS1=high.or CS2=low.
TIMING WAVEFORM OF POWER UP(1) (CS1 controlled)
Min. 200µs
VCC(Min)
VCC
CS1
CS2
Power Up Mode
NormalOperation
TIMING WAVEFORM OF POWER UP(2) (CS2 controlled)
Min. 200µs
VCC(Min)
VCC
CS1
CS2
Power Up Mode
Normal Operation
FUNCTIONAL DESCRIPTION
CS1
H
X1)
X1)
L
CS2
X1)
L
OE
X1)
X1)
X1)
H
WE
LB
X1)
X1)
H
UB
X1)
X1)
H
I/O1~8
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
I/O9~16
High-Z
High-Z
High-Z
Mode
Power
Standby
Standby
Standby
Active
Active
Active
Active
Active
X1)
X1)
X1)
H
Deselected
Deselected
Deselected
X1)
X1)
H
L
X1)
High-Z
High-Z
High-Z
Dout
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
L
H
H
H
L
L
H
L
H
L
H
L
H
L
H
H
L
High-Z
Dout
L
H
L
H
L
L
Dout
X1)
X1)
X1)
L
H
L
L
H
Din
High-Z
Din
Lower Byte Write
Upper Byte Write
Word Write
Active
Active
Active
L
H
L
H
L
High-Z
Din
L
H
L
L
L
Din
1. X means "Don’t care". X should be low or high state.
Revision 1.0
May 2006
- 2 -
K1S2816BCA
UtRAM
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
VIN, VOUT
VCC, VCCQ
PD
Ratings
-0.2 to VCCQ+0.3V
-0.2 to 2.5V
Unit
V
Voltage on any pin relative to Vss
Power supply voltage relative to Vss
Power Dissipation
V
1.0
W
Storage temperature
TSTG
-65 to 150
-25 to 85
°C
°C
Operating Temperature
TA
1) Stresses greater than "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to be
used under recommended operating condition. Exposure to absolute maximum rating conditions longer than 1 second may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
Item
Symbol
VCC
Min
1.7
Typ
1.8
1.8
0
Max
1.95
1.95
0
Unit
V
Power supply voltage(Core)
Power supply voltage(I/O)
Ground
VCCQ
1.7
0
V
V
VSS, VSSQ
VCCQ+0.22)
0.4
Input high voltage
0.8 x VCCQ
-
V
VIH
VIL
-0.23)
Input low voltage
-
V
1. TA=-25 to 85°C, otherwise specified.
2. Overshoot: VCCQ +1.0V in case of pulse width ≤20ns. Overshoot is sampled, not 100% tested.
3. Undershoot: -1.0V in case of pulse width ≤20ns. Undershoot is sampled, not 100% tested.
(f=1MHz, TA=25°C)
CAPACITANCE
Item
Symbol
CIN
Test Condition
VIN=0V
Min
Max
8
Unit
pF
Input capacitance
-
-
Input/Output capacitance
CIO
VIO=0V
8
pF
DC AND OPERATING CHARACTERISTICS
Item
Symbol
ILI
Test Conditions
Min Typ Max Unit
Input Leakage Current
-1
-1
-
-
-
-
1
µA
VIN=Vss to VCCQ
Output Leakage Current
1
µA
ILO
CS=VIH, PS=VIH, OE=VIH or WE=VIL, VIO=Vss to VCCQ
2)
35
mA
ICC2
Cycle time=70ns, IIO=0mA , 100% duty, CS=VIL, PS=VIH, VIN=VIL or VIH
Average Operating
Current(Async)
2)
Cycle time=tRC+3tPC, IIO=0mA , 100% duty, CS=VIL, PS=VIH, VIN=VIL or
-
-
20
mA
ICC2P
VIH
Output Low Voltage
Output High Voltage
VOL
VOH
IOL=0.1mA
IOH=-0.1mA
-
1.4
-
-
-
-
-
0.2
-
V
V
< 40°C
< 85°C
135
250
µA
µA
CS≥VCCQ-0.2V, PS≥VCCQ-0.2V, Other inputs=Vss
or VCCQ
1)
Standby Current(CMOS)
ISB1
-
1. Internal TCSR (Temperature Compensated Self Refresh) is used to optimize Refresh cycle below 40°C.
2. IIO=0mA; This parameter is specified with the outputs disabled to avoid external loading effects.
Revision 1.0
May 2006
- 3 -
K1S2816BCA
UtRAM
AC OPERATING CONDITIONS
TEST CONDITIONS
AC Output Load Circuit
Vtt=0.5 x VCCQ
(Test Load and Test Input/Output Reference)
Input pulse level: 0.2 to VCCQ-0.2V
Input rising and falling time: 3ns
Input and output reference voltage: 0.5 x VCCQ
Output load: CL=30pF
50Ω
Dout
Z0=50
Ω
30pF
VCC:1.7V~1.95V
TA: -25°C~85°C
AC CHARACTERISTICS
Speed
Parameter List
Symbol
Units
Min
Max
Common
CS High Pulse Width
10
70
25
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCSHP(A)
tRC
Read Cycle Time
-
Page Read Cycle Time
Address Access Time
-
tPC
70
20
70
35
70
-
tAA
Page Access Time
-
tPA
Chip Select to Output
-
tCO
Output Enable to Valid Output
UB, LB Access Time
-
tOE
-
tBA
Asynch.
Read
Chip Select to Low-Z Output
UB, LB Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
UB, LB Disable to High-Z Output
Output Disable to High-Z Output
Output Hold
5
tLZ
5
-
tBLZ
tOLZ
tCHZ
tBHZ
tOHZ
tOH
5
-
0
12
12
10
-
0
0
5
Write Cycle Time
70
60
0
-
tWC
tCW
tAS
Chip Select to End of Write
Address Set-up Time to Beginning of Write
Address Valid to End of Write
UB, LB Valid to End of Write
Write Pulse Width
-
-
60
60
551)
5
-
tAW
tBW
tWP
tWHP
tWR
tDW
tDH
-
Asynch.
Write
-
WE High Pulse Width
-
Write Recovery Time
0
-
Data to Write Time Overlap
30
0
-
Data Hold from Write Time
-
1. tWP(min)=70ns for continuous write without CS toggling longer than 1.2us
2. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ x 0.5
3. The Low-Z timings measure a 100mV transition away from the High-Z level toward either VOH or VOL.
Revision 1.0
May 2006
- 4 -
K1S2816BCA
UtRAM
TIMING WAVEFORMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled, CS1=OE=VIL, CS2=WE=VIH, UB or/and LB=VIL)
tRC
Address
tAA
tOH
Data Valid
Data Out
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2)
(WE=VIH)
tRC
Address
tOH
tAA
tCO
CS1
CS2
tHZ
tBA
UB, LB
OE
tBHZ
tOE
tOLZ
tBLZ
tLZ
tOHZ
High-Z
Data out
Data Valid
TIMING WAVEFORM OF PAGE CYCLE (READ ONLY)
Valid
A22~A2
Address
Valid
Valid
Valid
Valid
A1~A0
Address Address Address
tPC
Address
tAA
CS1
CS2
tHZ
tCO
OE
tOHZ
tPA
tOE
High Z
Data
Valid
Data
Valid
Data
Valid
Data
Valid
DQ15~DQ0
(READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection.
3. tOE(max) is met only when OE becomes enabled after tAA(max).
4. If invalid address signals shorter than min. tRC are continuously repeated for over 1.2us, the device needs a normal read timing(tRC) or needs to
sustain standby state for min. tRC at least once in every 1.2us.
Revision 1.0
May 2006
- 5 -
K1S2816BCA
UtRAM
TIMING WAVEFORM OF WRITE CYCLE(1)
(WE Controlled)
tWC
tCW
Address
CS1
tWR
CS2
tAW
tBW
UB, LB
tWP
tWHP
WE
tAS
tDW
tDH
High-Z
High-Z
Data in
Data Valid
tWHZ
tOW
Data Undefined
Data out
TIMING WAVEFORM OF WRITE CYCLE(2)
(CS1 Controlled)
tWC
Address
tWR
tAS
tCW
CS1
tAW
CS2
tBW
tWP
UB, LB
WE
tDW
tDH
Data Valid
Data in
High-Z
Data out
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for sin-
gle byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high or
WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.
5. In asynchronous write cycle, Clock and ADV signals are ignored.
6. Condition for continuous write operation over 50 times : tWP(min)=70ns
Revision 1.0
May 2006
- 6 -
K1S2816BCA
UtRAM
TIMING WAVEFORM OF WRITE CYCLE(3)
(CS2 Controlled)
tWC
Address
tWR
tAS
tCW
CS1
tAW
CS2
tBW
UB, LB
tWP(1)
WE
tDW
tDH
Data Valid
Data in
Data out
High-Z
tWC
TIMING WAVEFORM OF WRITE CYCLE(4)
(UB, LB Controlled)
Address
tWR
tCW
tAW
CS1
CS2
tBW
tWP
UB, LB
tAS
WE
tDH
tDW
Data Valid
Data in
High-Z
Data out
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS1 and low WE. A write begins when CS1 goes low and WE goes low with asserting UB or LB for
single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS1 goes high
and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS1 going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS1 or WE going high.
Revision 1.0
May 2006
- 7 -
相关型号：
K1S321611C-FI700
Pseudo Static RAM, 2MX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 0.75 MM PITCH, FBGA-48
SAMSUNG
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