K1S2816BCM-I [SAMSUNG]
8Mx16 bit Page Mode Uni-Transistor Random Access Memory; 8Mx16位页面模式的Uni-晶闸管随机存取存储器
| 型号： | K1S2816BCM-I |
| 厂家： | 
SAMSUNG |
| 描述： | 8Mx16 bit Page Mode Uni-Transistor Random Access Memory |
| 文件： | 总10页 (文件大小：137K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K1S2816BCM
UtRAM
Document Title
8Mx16 bit Page Mode Uni-Transistor Random Access Memory
Revision History
Revision No. History
Draft Date
Remark
0.0
Initial Draft
April 12, 2004
Preliminary
- Design Target
0.1
Revised
July 12, 2004
Preliminary
- Updated "TIMING WAVEFORM OF WRITE CYCLE(1) (WE Con-
trolled)" in page 8 and added tWHP(WE High Pulse Width) parameter
as Min.5ns
- Added comment on standby current(ISB1) measure condition as
"Standby mode is supposed to be set up after at least one active
operation after power up. ISB1 is measured after 60ms from the time
when standby mode is set up."
- Changed ISB1 value(< 85°C) from 200µA into 250µA
1.0
Finalize
April 06, 2005
Final
- Changed tOH from 5ns to 3ns
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
Revision 1.0
April 2005
- 1 -
K1S2816BCM
UtRAM
8M x 16 bit Page Mode Uni-Transistor CMOS RAM
FEATURES
GENERAL DESCRIPTION
• Process Technology: CMOS
• Organization: 8M x16 bit
• Power Supply Voltage: 1.7~2.0V
• Three State Outputs
The K1S2816BCM is fabricated by SAMSUNG′s advanced
CMOS technology using one transistor memory cell. The device
supports 4 page read operation and Industrial temperature
range. The device supports dual chip selection for user inter-
face. The device also supports internal Temperature Compen-
sated Self Refresh mode for the standby power saving at room
temperature range.
• Compatible with Low Power SRAM
• Support 4 page read mode
• Package Type: TBD
PRODUCT FAMILY
Power Dissipation
Speed
(tRC)
Product Family
Operating Temp.
Vcc Range
PKG Type
Standby
Operating
(ISB1, Max.)
(ICC2, Max.)
130µA(<40°C)
250µA(<85°C)
K1S2816BCM-I
Industrial(-40~85°C)
1.7~2.0V
70ns
40mA
TBD
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTION
Clk gen.
Precharge circuit.
Vcc
Vss
Row
select
Row
Addresses
Memory array
I/O Circuit
Column select
Data
cont
TBD
I/O1~I/O8
Data
cont
I/O9~I/O16
Data
cont
Column Addresses
CS1
CS2
OE
Control Logic
WE
UB
LB
Name
Function
Name
Vcc
Vss
UB
Function
CS1,CS2 Chip Select Inputs
Power
OE
WE
Output Enable Input
Write Enable Input
Address Inputs
Ground
Upper Byte(I/O9~16)
Lower Byte(I/O1~8)
No Connection1)
A0~A22
LB
I/O1~I/O16 Data Inputs/Outputs
1) Reserved for future use
NC
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
Revision 1.0
April 2005
- 2 -
K1S2816BCM
UtRAM
POWER UP SEQUENCE
During the Power Up mode, the standby current can not be guaranteed. To get the stable standby current level, at least one cycle of
active operation should be implemented regardless of wait time duration. To get the appropriate device operation, be sure to keep the
following power up sequence.
1. Apply power.
2. Maintain stable power(Vcc min.=1.7V) for a minimum 200µs with CS1=high.or CS2=low.
TIMING WAVEFORM OF POWER UP(1) (CS1 controlled)
Min. 200µs
VCC(Min)
VCC
CS1
CS2
Power Up Mode
NormalOperation
POWER UP(1)
1. After VCC reaches VCC(Min.), wait 200µs with CS1 high. Then the device gets into the normal operation.
TIMING WAVEFORM OF POWER UP(2) (CS2 controlled)
Min. 200µs
VCC(Min)
VCC
CS1
CS2
Power Up Mode
Normal Operation
POWER UP(2)
1. After VCC reaches VCC(Min.), wait 200µs with CS2 low. Then the device gets into the normal operation.
Revision 1.0
April 2005
- 3 -
K1S2816BCM
UtRAM
FUNCTIONAL DESCRIPTION
CS1
H
X1)
X1)
L
CS2
OE
X1)
X1)
X1)
H
WE
X1)
X1)
X1)
H
LB
X1)
X1)
H
UB
X1)
X1)
H
I/O1~8
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
I/O9~16
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
Mode
Power
Standby
Standby
Standby
Active
Active
Active
X1)
L
Deselected
Deselected
X1)
H
H
H
H
H
H
H
H
Deselected
X1)
L
L
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
X1)
L
L
H
H
L
L
H
H
L
L
H
H
L
High-Z
Dout
Active
Active
Active
Active
Active
L
L
H
L
L
Dout
X1)
X1)
X1)
L
L
L
H
Din
High-Z
Din
Lower Byte Write
Upper Byte Write
Word Write
L
L
H
L
High-Z
Din
L
L
L
L
Din
1. X means don′t care.(Must be low or high state)
ABSOLUTE MAXIMUM RATINGS1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Symbol
VIN, VOUT
VCC
Ratings
-0.2 to VCC+0.3V
-0.2 to 2.5V
1.0
Unit
V
V
PD
W
Storage temperature
TSTG
-65 to 150
-40 to 85
°C
°C
Operating Temperature
TA
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to be used under recommended operating condition. Exposure to absolute maximum rating conditions longer than 1 second may affect reli-
ability.
Revision 1.0
April 2005
- 4 -
K1S2816BCM
UtRAM
PRODUCT LIST
Industrial Temperature Product(-40~85°C)
Part Name
Function
K1S2816BCM
70ns, 1.8V
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Symbol
Vcc
Min
1.7
Typ
Max
2.0
Unit
V
Supply voltage
Ground
1.85
Vss
0
0
-
0
V
Vcc+0.22)
0.4
Input high voltage
Input low voltage
VIH
0.8 x VCC
-0.23)
V
VIL
-
V
1. TA=-40 to 85°C, otherwise specified.
2. Overshoot: Vcc+1.0V in case of pulse width ≤20ns.
3. Undershoot: -1.0V in case of pulse width ≤20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1)(f=1MHz, TA=25°C)
Item
Input capacitance
Symbol
CIN
Test Condition
Min
Max
8
Unit
pF
VIN=0V
VIO=0V
-
-
Input/Output capacitance
CIO
10
pF
1. Capacitance is sampled, not 100% tested.
DC AND OPERATING CHARACTERISTICS
Symbol
Item
Test Conditions
Min
Max
Unit
Typ
Input leakage current
ILI
VIN=Vss to Vcc
-1
-1
-
1
µA
CS1=VIH or CS2=VIL or OE=VIH or WE=VIL or LB=UB=VIH,
VIO=Vss to Vcc
Output leakage current
ILO
-
-
1
µA
Cycle time=tRC+3tPC, IIO=0mA, 100% duty, CS1=VIL,
CS2=VIH, LB=VIL or/and UB=VIL, VIN=VIH or VIL
Average operating current
ICC2
-
40
mA
Output low voltage
Output high voltage
VOL
VOH
IOL=0.1mA
IOH=-0.1mA
-
1.4
-
-
-
-
0.2
-
V
V
Other inputs=0~Vcc
1) CS1≥VCC-0.2V, CS2≥VCC-0.2V(CS1
controlled) or
< 40°C
< 85°C
130
µA
1)
Standby Current(CMOS)
ISB1
-
-
250
µA
2) 0V ≤ CS2 ≤ 0.2V(CS2 controlled)
1. Standby mode is supposed to be set up after at least one active operation.after power up.
ISB1 is measured after 60ms from the time when standby mode is set up.
Revision 1.0
April 2005
- 5 -
K1S2816BCM
UtRAM
Vtt=0.5 x VDDQ
AC Output Load Circuit
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Test Input/Output Reference)
Input pulse level: 0.2 to Vcc-0.2V
50Ω
Input rising and falling time: 3ns
Input and output reference voltage: 0.5 x VCC
Output load (See right): CL=30pF
Dout
Z0=50Ω
30pF
AC CHARACTERISTICS (Vcc=1.7~2.0V, TA=-40 to 85°C)
Speed Bins
70ns
Parameter List
Symbol
Units
Min
70
-
Max
Read Cycle Time
tRC
tAA
-
70
70
35
70
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select to Output
tCO
tOE
-
Output Enable to Valid Output
UB, LB Access Time
-
tBA
-
Chip Select to Low-Z Output
UB, LB Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
UB, LB Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Page Cycle
tLZ
10
10
5
tBLZ
tOLZ
tHZ
-
Read
-
0
25
25
25
-
tBHZ
tOHZ
tOH
tPC
0
0
3
25
-
-
Page Access Time
tPA
20
-
Write Cycle Time
tWC
tCW
tAS
70
60
0
Chip Select to End of Write
Address Set-up Time
-
-
Address Valid to End of Write
UB, LB Valid to End of Write
Write Pulse Width
tAW
tBW
tWP
tWHP
tWR
tWHZ
tDW
tDH
60
60
551)
5
-
-
-
Write
WE High Pulse Width
-
Write Recovery Time
0
-
Write to Output High-Z
0
25
-
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
30
0
-
tOW
5
-
1. tWP(min)=70ns for continuous write operation over 50 times.
Revision 1.0
April 2005
- 6 -
K1S2816BCM
UtRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)(Address Controlled, CS1=OE=VIL, CS2=WE=VIH, UB or/and LB=VIL)
tRC
Address
tAA
tOH
Data Valid
Data Out
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2)(WE=VIH)
tRC
Address
tOH
tAA
tCO
CS1
CS2
tHZ
tBA
UB, LB
OE
tBHZ
tOE
tOLZ
tBLZ
tLZ
tOHZ
High-Z
Data out
Data Valid
TIMING WAVEFORM OF PAGE CYCLE(READ ONLY)
Valid
Address
A22~A2
Valid
Valid
Valid
Valid
Address
A1~A0
Address Address Address
tAA
tPC
CS1
CS2
tHZ
tCO
OE
tOHZ
tPA
tOE
High Z
Data
Valid
Data
Valid
Data
Valid
Data
Valid
DQ15~DQ0
(READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
3. tOE(max) is met only when OE becomes enabled after tAA(max).
4. If invalid address signals shorter than min. tRC are continuously repeated for over 4us, the device needs a normal read timing(tRC) or
needs to sustain standby state for min. tRC at least once in every 4us.
Revision 1.0
April 2005
- 7 -
K1S2816BCM
UtRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
tWC
Address
tWR
tWR
tAW
tCW
tAW
tCW
CS
tBW
tBW
UB, LB
tWHP
tAS
tWP
tWP
WE
tAS
tDH
tDH
tDW
tDW
Data in
Data Valid
Data Valid
tOW
tOW
tWHZ
tWHZ
High-Z
High-Z
Data out
Data Undefined
Data Undefined
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)
tWC
Address
tWR
tAS
tCW
tAW
CS1
CS2
tBW
UB, LB
tWP
WE
tDW
tDH
Data Valid
Data in
High-Z
Data out
Revision 1.0
April 2005
- 8 -
K1S2816BCM
UtRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)
tWC
Address
tWR
tAS
tCW
CS1
CS2
tAW
tBW
UB, LB
WE
tWP(1)
tDW
tDH
Data Valid
Data in
Data out
High-Z
TIMING WAVEFORM OF WRITE CYCLE(4) (UB, LB Controlled)
tWC
Address
CS1
tWR
tCW
tAW
CS2
tBW
UB, LB
tAS
tWP
WE
tDH
tDW
Data in
Data Valid
High-Z
Data out
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS1 and low WE. A write begins when CS1 goes low and WE goes low with asserting
UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest tran-
sition when CS1 goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS1 going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS1 or WE going high.
5. tWP(min)=70ns for continuous write operation over 50 times.
Revision 1.0
April 2005
- 9 -
K1S2816BCM
UtRAM
PACKAGE DIMENSION
TBD
Revision 1.0
April 2005
- 10 -
相关型号：
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SAMSUNG
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