K1S1616B5M-EE85T [SAMSUNG]
DRAM;
SAMSUNG 
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UtRAM
K1S1616B5M
Document Title
1Mx16 bit Uni-Transistor Random Access Memory
Revision History
Revision No. History
Draft Date
Remark
0.0
Initial Draft
May 30, 2002
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- Design target
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
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May 2002
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UtRAM
K1S1616B5M
1M x 16 bit Uni-Transistor CMOS RAM
FEATURES
GENERAL DESCRIPTION
· Process Technology: CMOS
· Organization: 1M x16 bit
The K1S1616B5M is fabricated by SAMSUNG¢s advanced
CMOS technology using one transistor memory cell. The device
supports extended temperature range and 48 ball Chip Scale
Package for user flexibility of system design. The device also
supports deep power down mode for low standby current.
· Power Supply Voltage: 1.7V~2.2V
· Three State Outputs
· Compatible with Low Power SRAM
· Deep Power Down: Memory cell data holds invalid
· Package Type: 48-TBGA
PRODUCT FAMILY
Power Dissipation
Product Family
Operating Temp.
Vcc Range
Speed
PKG Type
Standby
Operating
(ISB1, Max.)
(ICC2, Max.)
K1S1616B5M-E
Extended(-25~85°C)
1.7V~2.2V
70/85ns
60mA
25mA
48-TBGA
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
1
2
3
4
5
6
Clk gen.
Precharge circuit.
A
B
C
D
E
F
LB
OE
UB
A0
A3
A1
A4
A2
ZZ
I/O1
I/O3
Vcc
Vss
I/O7
I/O8
DNU
Vcc
Vss
I/O9
I/O10
Vss
CS
Row
select
Row
Addresses
Memory array
I/O11
I/O12
I/O13
I/O14
A19
A5
A6
I/O2
I/O4
I/O5
I/O6
WE
A11
A17
DNU
A14
A12
A9
A7
I/O Circuit
Column select
Data
cont
I/O1~I/O8
Vcc
A16
A15
A13
A10
Data
cont
I/O9~I/O16
I/O15
I/O16
A18
Data
cont
Column Addresses
G
H
A8
CS
ZZ
48-TBGA: Top View(Ball Down)
OE
WE
UB
LB
Control Logic
Name
CS
Function
Name
Vcc
Vss
UB
Function
Chip Select Input
Deep Power Down
Output Enable Input
Write Enable Input
Address Inputs
Power
ZZ
Ground
OE
Upper Byte(I/O9~16)
Lower Byte(I/O1~8)
Do Not Use1)
WE
LB
A0~A19
DNU
I/O1~I/O16 Data Inputs/Outputs
1) Reserved for future use.
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
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UtRAM
K1S1616B5M
POWER UP SEQUENCE
1. Apply power.
2. Maintain stable power(Vcc min.=1.7V) for a minimum 200ms with CS=high.
3. Issue read operation at least twice.
FUNCTIONAL DESCRIPTION
CS
H
X1)
L
ZZ
H
L
OE
X1)
X1)
X1)
H
WE
X1)
X1)
X1)
H
LB
X1)
X1)
H
UB
X1)
X1)
H
I/O1~8
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
I/O9~16
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
Mode
Power
Standby
Deep Power Down
Standby
Active
Deselected
Deselected
H
H
H
H
H
H
H
H
H
Deselected
X1)
L
L
L
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
X1)
L
L
H
H
Active
L
L
H
H
Active
L
L
H
H
L
High-Z
Dout
Active
L
L
H
L
L
Dout
Active
X1)
X1)
X1)
L
L
L
H
Din
High-Z
Din
Lower Byte Write
Upper Byte Write
Word Write
Active
L
L
H
L
High-Z
Din
Active
L
L
L
L
Din
Active
1. X means don¢t care.(Must be low or high state)
ABSOLUTE MAXIMUM RATINGS1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Symbol
VIN, VOUT
VCC
Ratings
-0.2 to VCC+0.3V
-0.2 to 2.5V
1.0
Unit
V
V
PD
W
Storage temperature
TSTG
-65 to 150
-25 to 85
°C
°C
Operating Temperature
TA
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to be used under recommended operating condition. Exposure to absolute maximum rating conditions longer than 1 second may affect reli-
ability.
STANDBY MODE STATE MACHINES
CS=VIL, UB or/and LB=VIL
Standby
ZZ=VIH
Mode
CS=VIH
Initial State
(Wait 200ms)
CS=VIH
ZZ=VIH
Power On
Active
ZZ=VIL
Read Operation Twice
ZZ=VIL
Deep Power
Down Mode
CS=VIH, ZZ=VIH
STANDBY MODE CHARACTERISTIC
Power Mode
Standby
Memory Cell Data
Standby Current(mA)
Wait Time(ms)
Valid
60
10
0
Deep Power Down
Invaild
200
Revision 0.0
May 2002
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UtRAM
K1S1616B5M
PRODUCT LIST
Extended Temperature Products(-25~85°C)
Part Name
Function
K1S1616B5M-EE70
K1S1616B5M-EE85
48-TBGA, 70ns
48-TBGA, 85ns
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Symbol
Vcc
Min
1.7V
0
Typ
1.8V
0
Max
2.2V
0
Unit
V
Supply voltage
Ground
Vss
V
VCC+0.22)
0.4
Input high voltage
Input low voltage
VIH
1.4
-
-
V
-0.23)
VIL
V
1. TA=-25 to 85°C, otherwise specified.
2. Overshoot: Vcc+1.0V in case of pulse width £20ns.
3. Undershoot: -1.0V in case of pulse width £20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1)(f=1MHz, TA=25°C)
Item
Input capacitance
Symbol
CIN
Test Condition
Min
Max
8
Unit
pF
VIN=0V
VIO=0V
-
-
Input/Output capacitance
CIO
10
pF
1. Capacitance is sampled, not 100% tested.
DC AND OPERATING CHARACTERISTICS
Symbol
ILI
Item
Test Conditions
Min
-1
Max Unit
Typ
Input leakage current
Output leakage current
VIN=Vss to Vcc
CS=VIH or OE=VIH or WE=VIL, VIO=Vss to Vcc
-
1
1
mA
mA
ILO
-1
-
-
-
Cycle time=1ms, 100% duty, IIO=0mA, CS£0.2V, VIN£0.2V or
VIN³ VCC-0.2V
ICC1
5
mA
Average operating current
ICC2
-
-
-
-
-
-
25
0.2
-
mA
V
Cycle time=Min, IIO=0mA, 100% duty, CS=VIL, VIN=VIH or VIL
Output low voltage
VOL IOL = 0.1mA
Output high voltage
Standby Current(CMOS)
VOH IOH = -0.1mA
1.4
-
V
601)
ISB1 CS³ VCC-0.2V, Other inputs=0~Vcc
mA
1. This value is valid over the entire operating temperature range.
Revision 0.0
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UtRAM
K1S1616B5M
Dout
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Test Input/Output Reference)
Input pulse level: 0.2 to Vcc-0.2V
Input rising and falling time: 5ns
CL
Input and output reference voltage: 0.5 x VCC
Output load (See right): CL=50pF
1. Including scope and jig capacitance
AC CHARACTERISTICS(Vcc=1.7~2.2V, TA=-25 to 85°C)
Speed Bins
85ns
70ns1)
Parameter List
Symbol
Units
Min
70
-
Max
Min
85
-
Max
Read Cycle Time
tRC
tAA
-
70
70
35
70
-
-
85
85
40
85
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select to Output
tCO
tOE
-
-
Output Enable to Valid Output
UB, LB Access Time
-
-
tBA
-
-
Chip Select to Low-Z Output
UB, LB Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
UB, LB Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
tLZ
10
10
5
10
10
5
Read
tBLZ
tOLZ
tHZ
-
-
-
-
0
25
25
25
-
0
25
25
25
-
tBHZ
tOHZ
tOH
tWC
tCW
tAS
0
0
0
0
5
5
70
60
0
-
85
70
0
-
Chip Select to End of Write
Address Set-up Time
-
-
-
-
Address Valid to End of Write
UB, LB Valid to End of Write
Write Pulse Width
tAW
tBW
tWP
tWR
tWHZ
tDW
tDH
60
60
50
0
-
70
70
60
0
-
-
-
Write
-
-
Write Recovery Time
-
-
Write to Output High-Z
0
20
-
0
25
-
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
30
0
35
0
-
-
tOW
5
-
5
-
1. The limitation in continuous write operation is up to 50 times. If you want to write continuously over 50 times, please refer to the technical note.
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UtRAM
K1S1616B5M
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)(Address Controlled, CS=OE=VIL, ZZ=WE=VIH, UB or/and LB=VIL)
tRC
Address
tAA
tOH
Data Valid
Data Out
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2)(ZZ=WE=VIH)
tRC1
Address
tAA
tOH
tRC2
tCO
CS
tHZ
tBA
UB, LB
tBHZ
tOE
OE
tOLZ
tBLZ
tLZ
tOHZ
High-Z
Data out
Data Valid
(READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
3. The minimum read cycle(tRC) is determined by longer one of tRC1 and tRC2.
4. tOE(max) is met only when OE becomes enabled after tAA(max).
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UtRAM
K1S1616B5M
TIMING WAVEFORM OF WRITE CYCLE(1)(WE Controlled, ZZ=VIH)
tWC
Address
tWR(4)
tCW(2)
CS
tAW
tBW
UB, LB
tWP(1)
WE
tAS(3)
tDW
tDH
High-Z
High-Z
Data in
Data Valid
tWHZ
tOW
Data Undefined
Data out
TIMING WAVEFORM OF WRITE CYCLE(2)(CS Controlled, ZZ=VIH)
tWC
Address
CS
tCW(2)
tAS(3)
tWR(4)
tAW
tBW
UB, LB
tWP(1)
WE
tDW
tDH
Data Valid
Data in
High-Z
Data out
High-Z
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UtRAM
K1S1616B5M
TIMING WAVEFORM OF WRITE CYCLE(3)(UB, LB Controlled, ZZ=VIH)
tWC
Address
tWR(4)
tCW(2)
CS
tAW
tBW
UB, LB
tAS(3)
tWP(1)
WE
tDH
tDW
Data Valid
Data in
High-Z
Data out
High-Z
(WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition
when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.
TIMING WAVEFORM OF DEEP POWER DOWN MODE
Read Operation Twice or Stay High during 300ms
200ms
0.5ms
ZZ
Wake up
Suspend
Normal Operation
Normal Operation
MODE
CS
Deep Power Down Mode
(DEEP POWER DOWN MODE)
1. When you toggle ZZ pin low, the device gets into the Deep Power Down mode after 0.5ms suspend period.
2. To return to normal operation, the device needs Wake Up period.
3. Wake Up sequence is just the same as Power Up sequence shown in next page.
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UtRAM
K1S1616B5M
TIMING WAVEFORM OF POWER UP(1)
Read Operation Twice
200ms
VCC(Min)
VCC
ZZ
CS
(POWER UP(1))
1. After VCC reaches VCC(Min.) following power application, wait 200ms with CS high and then toggle CS low and commit Read Operation
at least twice. Then you get into the normal operation.
2. Read operation should be executed by toggling CS pin low.
3. The read operation must satisfy the specified tRC.
4. ZZ pin should be kept high during whole power up sequence.
TIMING WAVEFORM OF POWER UP(2)(No Dummy Cycle)
200ms
300ms
VCC(Min)
VCC
ZZ
CS
(POWER UP(2))
1. After VCC reaches VCC(Min.) following power application, wait 200ms and wait another 300ms with CS high if you don’t want to commit
dummy read cycle. After total 500ms wait, toggle CS low, then you get into the normal mode.
2. ZZ pin should be kept high during whole power up sequence.
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UtRAM
K1S1616B5M
Unit: millimeters
PACKAGE DIMENSION
48 TAPE BALL GRID ARRAY(0.75mm ball pitch)
Top View
B
Bottom View
B
B1
6
5
4
3
2
1
A
B
#A1
C
D
E
F
G
H
B/2
Detail A
A
Side View
D
Y
C
Min
Typ
0.75
TBD
3.75
TBD
5.25
0.45
0.90
0.55
0.35
-
Max
A
B
-
-
Notes.
1. Bump counts: 48(8 row x 6 column)
2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.)
3. All tolerence are ±0.050 unless
specified beside figures.
B1
C
-
-
C1
D
-
-
4. Typ : Typical
0.40
0.50
1.00
-
5. Y is coplanarity: 0.08(Max)
E
-
E1
E2
Y
-
0.30
-
0.40
0.08
Revision 0.0
May 2002
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TNAL0201
UtRAM USAGE AND TIMING
TECHNICAL
NOTE
UtRAM USAGE AND TIMING
INTRODUCTION
DESIGN ACHIEVES SRAM SPECIFIC
OPERATIONS
The UtRAM was designed to work just like an SRAM - without
any waits or other overhead for precharging or refreshing its
internal DRAM cells. SAMSUNG Electronics(SAMSUNG) hides
these operations inside with advanced design technology -
those are not to be seen from outside. Precharging takes place
during every access, overlapped between the end of the cycle
and the decoding portion of the next cycle.
Hiding refresh is more difficult. Every row in every block must
be refreshed at least once during the refresh interval to prevent
data loss. SAMSUNG provides an internal refresh controller for
devices. When all accesses within refresh interval are directed
to one macro-cell, as can happen in signal processing applica-
tions, a more sophisticated approach is required to hide
refresh. The pseudo SRAM is sometimes used on these appli-
cations, which requires a memory controller that can hold off
accesses when a refresh operation is needed. SAMSUNG’s
unique qualitative advantage over these parts(in addition to
quantitative improvements in access speed and power con-
sumption) is that the UtRAM never need to hold off accesses,
and indeed it has no hold off signal. The circuitry that gives
SAMSUNG this advantage is fairly simple but has not previ-
ously been disclosed.
UtRAM is based on single-transistor DRAM cells. As with any
other DRAM, the data in these cells must be periodically
refreshed to prevent data loss. What makes the UtRAM unique
is that it offers a true SRAM style interface that hides all refresh
operations from the memory controller.
START WITH A DRAM TECHNOLOGY
The key point of UtRAM is its high speed and low power. This
high speed comes from the use of many small blocks such as
32Kbits each to create UtRAM arrays. The small blocks have
short word lines thus with little capacitance eliminating a major
factor of operating current dissipation in conventional DRAM
blocks.
Each independent macro-cell on a UtRAM device consists of a
number of these blocks. Each chip has one or more macro.
The address decoding logic is also fast. UtRAM performs a
complete read operation in every tRC, but UtRAM needs power
up sequence like DRAM.
Power Up Sequence and Diagram
1. Apply power.
2. Maintain stable power for a minium 200ms with CS=high.
3. Issue read operation at least 2 times.
AVOID TIMING
CS=VIL, UB or/and LB=VIL
ZZ=VIH
CS=VIH
Following figures show you an abnormal timing which is not
supported on UtRAM and its solution.
Initial State
(Wait 200ms)
Power On
Active
If your system has a timing which sustains invalid states over
4ms at read mode like Figure 1, there are some guide lines for
proper operation of UtRAM.
Read Operation(2 times)
When your system has multiple invalid address signals shorter
than tRC on the timing shown in Figure 1, UtRAM needs a nor-
mal read timing(tRC) during that cycle(Figure 2) or needs to
toggle CS once to ’high’ for about ’tRC’(Figure 3).
Figure 1.
Over 4ms
CS
WE
Less than tRC
Address
Put on read operation every 4ms
Figure 2.
Over 4ms
CS
WE
tRC
Address
SRAM PLANNING
SAMSUNG Electronics CO., LTD. reserves the right to change products or specifications without notice.
LIM-020311
Ó2002 SAMSUNG Electronics CO., LTD.
- 11 -
TNAL0201
UtRAM USAGE AND TIMING
Figure 3.
toggle CS to high every 4ms
Over 4ms
tRC
CS
WE
Address
Write operation has similar restriction to Read operation. If your
system has a timing which sustains invalid states over 4ms at
write mode and has continuous write signals with length of Min.
tWC over 4ms like Figure 4, you must toggle WE once to high
and make it stay high at least for tRC every 4ms or toggle CS
once to high for about tRC.
Figure 4.
Over 4ms
CS
tWP
WE
Address
tWC
Figure 5.
CS
toggle WE to high and make it stay high at least for tRC every 4ms
Over 4ms
tWP
WE
Address
tWC
tRC
Figure 6.
toggle CS to high every 4ms
Over 4ms
CS
tRC
tWP
WE
Address
tWC
SRAM PLANNING
SAMSUNG Electronics CO., LTD. reserves the right to change products or specifications without notice.
LIM-020311
Ó2002 SAMSUNG Electronics CO., LTD.
- 12 -
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