ML9479E_技术文档

FEDL9479E-02

Issue Date: Apr. 3, 2013

ML9479E

Static, 1/2 Duty, 1/3 Duty, 1/4 Duty 160 Outputs LCD Driver

GENERAL DESCRIPTION

The ML9479E is an LCD driver LSI, consists of a 160-bit shift register, a 640-bit data latch, 160 sets of LCD

drivers, and a common signal generation circuit.

It can directly drive an LCD up to 160 segments for static display, 320 segments for 1/2-duty display, 480

segments for 1/3-duty display, and 640 segments for 1/4-duty display.

The three-wire serial interface and I²C interface are selectable.

FEATURES





Logic power supply voltage

LCD drive power supply voltage : 4.5 to 5.5 V

Maximum number of segments

Static display

1/2-duty display

: 2.7 to 5.5 V

: 160 segments

: 320 segments

: 480 segments

: 640 segments

1/3-duty display

1/4-duty display



Interface with microcomputer :

Serial interface : DATA, CLOCK, LOAD

CLOCK transfer speed up to 1 MHz

I²C interface

: SDA, SCL, SDAACK

SCL transfer speed up to 400 kHz

Built-in CR oscillator circuit using the internal resistor or External resistor

Cascade connectable (up to eight chips)

Built-in common signal generation circuit

Built-in common output intermediate-value voltage generation circuit

Built-in POC (Power On Clear) circuit



Gold bump chip (ML9479EDVWA)

1/32

FEDL9479E-02

ML9479E

BLOCK DIAGRAM

SEG1

SEG160

VLCD

160-Dot Segment Driver

160-Ch Data Selector

Bias

Resi.

BIAS

Duty0

Duty1

160

160-Bit

Latch3

160-Bit

Latch2

160-Bit

Latch1

160-Bit

Latch4

M/S

Latch

Selector

160

I2C

LOAD

DATA (SDA)

CLOCK (SCL)

SDAACK

SA0

Command

Decoder

160-bit Shift Register

A1

A0

OSC I/E

COMON

Driver

COM1

OSC1

OSCR

OSC2

COM2

COM3

COM4

Timing

Generator

OSC

CKO

SYNCB

POCEB

POC

RESETB

TEST1

TEST2

VDD

GND

2/32

FEDL9479E-02

ML9479E

ABSOLUTE MAXIMUM RATINGS

Item

Symbol

Condition

Ta = 25°C

—

Rating

-0.3 to 6.0

– 0.3 to V_DD+ 0.3

-2.0 to +2.0

125

Unit

V

Logic power supply voltage

LCD drive power supply voltage

Input voltage

V_DD

V_LCD

V_I

V

Output short-circuit current

Chip temperature

Is

mA

°C

Tc

Storage temperature

T_STG

—

-55 to +150

Note: Do not use the ML9479E by short-circuiting one output pin to another output pin as well as to other pin

(input pin, input/output pin, or power supply pin).

RECOMMENDED OPERATION CONDITIONS

Item

Symbol

V_DD

Condition

Range

Unit

Logic power supply voltage

LCD drive power supply voltage

OSC IN clock frequency

Data clock frequency

*

—

2.7 to 5.5

4.5 to 5.5

up to 10

V

V_LCD

f_CP1

f_CP2

f_SCL

T_a

*

kHz

MHz

kHz

°C

up to 1.0

up to 400

-40 to +105

SCL clock frequency

Operating temperature

Note(*): Use at V_DD V_LCD

.

The relation between OSC IN clock frequency and frame frequency is as the equation below.

f_FRM= f_OSC/24

Recommended setting range for external component (oscillator circuit)

(V_DD= 2.7 to 5.5 V, V_LCD= 4.5 to 5.5 V, Ta= –40 to +105°C)

Item

Symbol

R_f

Condition

—

Min

423

47

TYP

470

75

Max

517

114

Unit

kΩ

Oscillation resistor

Frame frequency

f_FRM

(F1,F0)=(0,1)

Hz

The relation between oscillation resistor and frame frequency is as the equation below.

f_FRM= f_OSC/(16 x 24)

fosc = 1 / (Device coefficient x External resistor R_f)

Device coefficient = 73.8 x 10^-12± 25%

3/32

FEDL9479E-02

ML9479E

ELECTRICAL CHARACTERISTICS

DC Characteristics

(V_DD= 2.7 to 5.5 V, V_LCD= 4.5 to 5.5 V, Ta= -40 to +105°C)

Item

Symbol

V_IH

Condition

—

Min.

0.8V_DD

GND

-1.0

Typ.

—

Max.

V_DD

Unit

V

Applicable pin

(*1)

"H" input voltage

"L" input voltage

Input leakage current 1

V_IL

—

0.2V_DD

1.0

V

I_L1

V_I= V_DDor 0 V

V_I= V_DDor 0V

POCEB="H"

V_DD= 5.0V,V_I= 0 V

POCEB = "L"

I_O= -600μA

I_O= 600μA

—

μA (*1)

Input leakage current 2

Pull-up current

I_L2

I_pu

-1.0

30

—

1.0

μA RESETB

140

μA RESETB

"H" output voltage

"L" output voltage 1

"L" output voltage 2

V_OH

V_OL1

V_OL2

0.9V_DD

—

V CKO, SYNCB

V

0.1V_DD

CKO, SYNCB

SDAACK

—

Segment

Driver

V_OHS

V_LCD= 5V

—

5

15

kΩ SEG1 to SEG160

ON resistor

Common

V_OHC

V_LCD= 5V

—

5

12

kΩ COM 1 to COM4

(*1): DATA(SDA), CLOCK(SCL), LOAD, M/S, SYNCB, Duty1, Duty0, BIAS, SA0, A1, A0, OSC1, OSC I/E,

I2C, POCEB

(V_DD= 2.7 to 5.5 V, V_LCD= 4.5 to 5.5 V, Ta= -40 to +105°C)

Applicable

Item

Symbol

I_DDS

Condition

V_DD=V_LCD=5.5 V

Min.

Typ.

Max.

Unit

—

8

15

μA

VDD

Static supply

current

Input pin fixed to "H" or "L"

Oscillation stopped, output no-load

POCEB="L"

I_LCDS

—

9

15

18

μA

VLCD

VDD

V

_DD=V_LCD= 5.5 V (*2)(*3)

Clock OSC1 external input

_CP1=1.8kHz

I_DD1

I_LCD1

I_DD2

I_LCD2

I_DD3

I_LCD3

I_DD4

(*6)

10

Dynamic supply

current 1

(*7)

(*6)

(*7)

—

9

65

9

15

90

μA

VLCD

VDD

f

Dynamic supply

current 2

V_DD=V_LCD= 5.5 V (*2)(*3)

Internal oscillation

15

VLCD

VDD

V_DD=V_LCD= 5.5 V (*2)(*4)(*6)

Internal oscillation

At three-wire serial IF data input

V_DD=V_LCD= 5.5 V (*2)(*5)(*6)

Internal oscillation

200

300

Dynamic supply

current 3

—

9

230

9

15

350

15

μA

VLCD

VDD

Dynamic supply

current 4

At I²C IF data input

I_LCD4

VLCD

(*2): M/S = "H", 1/4-duty, 1/3-bias, (F1,F0) = (1,1) 95 Hz, POCEB = "L", output pin no-load.

(*3): Three-wire serial or I²C interface. Input pin fixed to "H" or "L".

(*4): Serial interface, data input frequency = 1 MHz.

(*5): I²C interface, data input frequency = 400 kHz.

(*6): Alternately inputs "0" and "1" for LCD display data (checkered display).

(*7): Inputs all "1s" for LCD display data (all illuminated).

4/32

FEDL9479E-02

ML9479E

Switching Characteristics

OSC timing

Item



(V_DD= 2.7 to 5.5 V, V_LCD= 4.5 to 5.5 V, Ta = -40 to +105°C)

Symbol

f_CP1

Condition

Min.

Typ. Max.

Unit

Applicable pin

OSC IN clock frequency

(external input)

—

1.8

—

10

—

kHz OSC1

Clock input from OSC1.

OSC2 and OSCR open.

OSC I/E = "L"

Clock pulse width

(External input)

t_WCP1

t_OSC

40

—

μs

OSC1

Clock rise and fall time

(external input)

—

(*1)

Between OSC1 and OSC2

R_f= 470kΩ

(F1,F0)=(0,1)

External Rf clock

frequency

f_OSC1

18

28.8

44

kHz OSC1, OSC2

(Internal oscillation)

OSCR open.

OSC I/E = "H"

OSC1 open.

(F1,F0)=(0,1)

OSC2 and OSCR short-circuited.

OSC I/E = "H"

Internal clock frequency

(Internal oscillation)

OSC1, OSCR,

f_OSC2

kHz

OSC2

The relation between OSC IN clock frequency and frame frequency is as the equation below.

f_FRM= f_OSC/24

(*1) t_OSCis a reference value.

The longer the clock rise and fall time, the more susceptible to extraneous noises around the threshold value.

Make the rise as steep as possible. Reference value: max=2μs.



Serial interface timing

(V_DD= 2.7 to 5.5 V, V_LCD= 4.5 to 5.5 V, Ta = -40 to +105°C)

Condition Min. Typ. Max. Unit Applicable pin

MHz CLOCK

Item

Symbol

Data clock frequency

Data clock pulse width

Data setup time

f_CP2

t_WCP2

t_SU

—

100

50

—

1

—

ns CLOCK

ns DATA

ns CLOCK

ns LOAD

Data hold time

t_HD

50

CLOCK-LOAD timing

LOAD-CLOCK timing

LOAD pulse width

t_CL

100

t_LC

t_WLD

CLOCK,DATA,

LOAD

Signal rise and fall time

tsr,tsf

—

(*2)

ns

(*2) tsr and tsf shall be reference values.

The longer the clock rise and fall time, the more susceptible to extraneous noises around the threshold value.

Make the rise as steep as possible. Reference value: max=10ns.

5/32

FEDL9479E-02

ML9479E



I²C interface timing

Item Symbol

(V_DD= 2.7 to 5.5 V, V_LCD= 4.5 to 5.5 V, Ta = -40 to +105°C)

Condition

Min. Typ. Max. Unit

Applicable pin

SCL clock frequency

Hold time (repeat)

"STATRT" condition

SCL "L" pulse width

SCL "H" pulse width

Setup time for repeat

"START" condition

Data hold time

f_SCL

—

400 kHz SCL

t_HD,STA

0.6

—

μs SCL,SDA

t_LOW

t_HIGH

1.3

0.6

—

μs SCL

t_SU,STA

0.6

—

μs SCL,SDA

t_HD,DAT

t_SU,DAT

0

—

ns SCL,SDA

Data setup time

200

Setup time for "STOP"

condition

t_SU,STO

0.6

—

μs SCL,SDA

Bus free time between

"STOP" condition and

"START" condition

Data valid acknowledge

time

t_BUF

1.3

—

μs SCL

t_VD,ACK

tir,tif

Cb

—

1.2

(*3)

400

μs SCL,SDAAACK

μs SCL,SDA

Signal rise and fall time

Data bus load

capacitance

pF SDA,SDAACK

Noise pulse width

tolerance

t_wf

—

50

ns SCL,SDA

(*3) tir and tif shall be reference values.

The longer the clock rise and fall time, the more susceptible to extraneous noises around the threshold value.

Make the rise as steep as possible. Reference value: max=0.1μs.

6/32

FEDL9479E-02

ML9479E

Timing chart (OSC1)

1/f_CP1

t_WCP1

V_IH

t_WCP1

V_IH

OSC1

(External clock)

V_IL

t_OSC

Timing chart (Serial interface)

V_IH

V_IL

t_HD

V_IH

DATA

V_IL

t_SU

t_sf

t_sr

t_WCP2

V_IH

V_IL

V_IH

CLOCK

V_IL

1/f_CP2

t_sr

t_CL

t_WLD

t_LC

t_sf

V

IH V_IH

LOAD

V_IL

t_sr

t_sf

Timing chart (I²C interface)

t_VD;ACK

V_IH

V_IL

V_IH

V_IL

V_IH

V_IL

SDA

t_f

t_BUF

t_LOW

V_IH

V_ILV_IL

V_IH

V_IL

SCL

V_IL

t_HD;STA

t_HiGH

t_HD;DAT

t_r

t_SU;DAT

V_IH

SDA

V_IL

t_SU;STA

t_SU;STO

7/32

FEDL9479E-02

ML9479E

REFERENCE DATA

Frame frequency Characteristics

VDD=5.5V/2.7V Rf=470Ω

Frame frequency f_FRM= f_OSC/(16 x 24)

fosc = 1 / (Device coefficient x External resistor R_f)

Device coefficient = 73.8 x 10^-12± 25%

Frame frequency Characteristics Rf=470k,VDD=5.5V

120

110

100

90

(F1,F0)=(1,1)

(F1,F0)=(1,0)

(F1,F0)=(0,1)

(F1,F0)=(0,0)

80

70

60

50

-60

-40

-20

0

20

40

60

80

100

120

Temp Ta[℃]

Frame frequency Characteristics Rf=470k,VDD=2.7V

130

120

110

100

90

(F1,F0)=(1,1)

(F1,F0)=(1,0)

(F1,F0)=(0,1)

(F1,F0)=(0,0)

80

70

60

50

-60

-40

-20

0

20

40

60

80

100

120

TempꢀTa[℃]

8/32

FEDL9479E-02

ML9479E

POWER ON/OFF TIMING

To turn on the power supply, raise the logic power supply first, then LCD drive power supply in order to prevent

the IC from malfunctioning.

To fall the power supply, fall the LCD drive power supply first, then the logic power supply.

For a VDD pin ranging from 0 V to VDDmin, set VDD ≥ VLCD and t1 ≥ 0 [ns].

To enable the Internal POC circuit, the VDD power supply rise time t2 range needs to be 100 [µs] t2 500 [ms].

For the VDD power supply to turn OFF then turn ON again, it is necessary to secure the POC discharge time t3

100 [ms].

Voltage

V_LCD

V_DD

0.9V_DD

t3

t1

t2

t1

Time

INITIALIZATION SIGNAL TIMING

When RESETB signal is externally input

The RESETB pin input is valid both for POCEB = "L" and "H". Usable in combination with the POC.

Keep the RESETB pin at "L" level until the VDD reaches VDDmin. (t4 ≥ 200[ns])

V_DD

V_DDmin

RESETB

VIL

t4

When Internal POC circuit is used

When using the Internal POC circuit in the initialization, set the POCEB pin to "L".

At this time, the power ON/OFF timing conditions are t1 to t3 above mentioned.

When RESETB pin POC circuit is used

If the power ON/OFF timing conditions t1 to t3 cannot be kept, the RESETB pin needs to have a capacitance

to configure the POC circuit. For this case, connect a capacitance value according to the power supply rise

time.

For the power supply rise time t2 and external capacitance value, use the following formula as a guide:

C_RST[F] > t2 [sec]／(30×10³)

9/32

FEDL9479E-02

ML9479E

PIN DESCRIPTIONS

Pad

Symbol

number

I/O

I

Description

This is the input to switch between the master and slave modes. It has a

schmitt circuit. When this pin is "H", the mode is master. When this pin is "L",

the mode is slave.

109-112

M/S

Display duty switch pins. These have schmitt circuits.

9-12

13-16

Duty0

Duty1

*1

Duty0="L", Duty1="L"

Duty0="H", Duty1="L"

Duty0="L", Duty1="H"

Duty0="H", Duty1="H"

:

Static

(COM1=COM2=COM3=COM4)

(COM1=COM3, COM2=COM4)

(COM2=COM4)

I

1/2Duty

1/3Duty

1/4Duty

:

This pin sets the LCD bias. It has a schmitt circuit.

BIAS="L": 1/3bias

BIAS="H": 1/2bias

121-124

25-28

BIAS

SA0

I

Slave address input pin. It has a schmitt circuit.

17-20

21-24

A1

A0

Sub address input pins. These have schmitt circuits.

This input selects whether to use the external clock input mode or to use the

Internal oscillation mode or external oscillation mode. It has a schmitt circuit.

When this pin is "H", the mode is the Internal or external Rf oscillation mode.

When this pin is "L", the mode is the external clock input mode.

Use the slave chip as it is connected to GND.

117-120

OSC I/E

I

These pins are for the oscillator circuit to generate common signals.

The OSC1 and OSCR pins are input pins and have a schmitt circuit.

OSC2 is an output pin. It becomes an output when the OSC I/E pin = "H" and

a high impedance when the OSC I/E pin = "L".

【In the master mode (M/S pin ="H") 】

Three types are selectable: Internal oscillation mode, external oscillation

mode, and external clock input mode.

•Internal oscillation mode: Set the OSC I/E pin to "H", short the OSCR and

OSC2 pins, and open the OSC1 pin.

•External Rf oscillation mode: Set the OSC I/E pin to "H", connect an

oscillation resistor Rf between the OSC1 and OSC2 pins, and open the

OSCR pin.

78-82

83-87

88-82

OSC1,

OSCR,

OSC2

*2

I

O

•External clock input mode: Set the OSC I/E pin to "L", open the OSCR and

OSC2 pins, and input the external clock to the OSC1 pin.

【 In the slave mode (M/S pin ="L") 】

Open the OSCR and OSC2 pins and connect the OSC1 pin to the

ML9479E's CKO pin that has been set to the master mode.

Clock output pin.

In the master mode (M/S pin = "H"), the 1/16 division signal of the oscillation

frequency is output.

In the slave mode (M/S pin = "L"), the output is fixed to "L".

For a cascade connection, connect this pin to the OSC1 pin of the chip that

has been set to the slave mode.

93-97

CKO

O

10/32

FEDL9479E-02

ML9479E

Input/output pin for common synchronization. It has a schmitt circuit.

It becomes the synchronization signal output pin in the master mode (M/S

pin = "H").

It becomes the synchronization signal input pin in the slave mode (M/S pin = "L").

For cascade connection, connect all of the involved ML9479Es' SYNC pins

by the common line.

98-102

SYNCB

I2C

I/O

Interface switching pin. It has a schmitt circuit.

When this pin is "H", the interface is I²C.

105-108

I

When this pin is "L", the interface is three-wire serial.

Display data input pin. It has a schmitt circuit.

I2C="L": Serial interface; DATA

Input the display data in the order of SEG160, SEG159, ... , SEG2, and

SEG1. The display data turns on at "H" and turns off at "L".

I2C="H": I²C interface; SDA

Input the display data in units of 8 bits. The display data turns on at "H" and

turns off at "L".

36-40

DATA

(SDA)

I

This pin has a built-in noise filter through which noises in widths up to 50 ns

are removed. This noise filter is valid only when I2C = "H".

Shift clock input pin for display data. It has a schmitt circuit.

I2C="L": Serial interface; CLOCK

The display data input to the DATA pin is serially input to the shift register at

the CLOCK signal rise.

41-45

CLOCK

(SCL)

I

I2C="H": I²C interface; SCL

The display data input to the SDA pin is serially input to the shift register at

the SCL signal rise.

This pin has a built-in noise filter through which noises in widths up to 50 ns

are removed. This noise filter is valid only when I2C = "H".

Input pin for the load signal of display data. It has a schmitt circuit.

I2C="L": Serial interface; LOAD

The display data in the shift register is transmitted as is to the segment driver

for the "H" duration. When this pin is brought into "L", the shift register is

disconnected from the segment driver. The display data in the shift register

immediately before it become "L" is held in the data latch and transmitted to

the segment driver.

46-50

LOAD

I

I2C="H": I²C interface

Use this pin as it is connected to GND.

I2C="L": Serial interface

Use this pin as it is opened.

I2C="H": I²C interface

31-35

SDAACK

POCEB

O

The I²C bus acknowledge output signal. Normally, use it as it is connected

with the SDA pin.

Connect an external pull-up resistor whenever

necessary, as it is an open drain pin. The pull-up connection destination

supply voltage shall be the V_DDsupply voltage or less.

Internal POC circuit enable pin. It has a schmitt circuit.

When this pin is "H", the POC circuit becomes OFF and the constant current

(8µA) is cut. The RESETB pin pull-up resistor is cut as well.

When this pin is "L", the POC circuit becomes ON.

113-116

73-77

I

The RESETB pin is connected to a pull-up resistor.

Reset signal input pin for initializing inside the IC. It has a schmitt circuit.

The "L" level enables the reset.

This pin has an Internal pull-up resistor. Open when POCEB = "H".

Pull-up when POCEB = "L". The power-on reset operation is available by

connecting an external capacitor.

RESETB

*3

11/32

FEDL9479E-02

ML9479E

125-128

129-132

155-234

239-318

TEST1

TEST2

Pin for testing the IC. These have Internal pull-down resistors.

Use it as it is connected to GND.

I

SEG1

SEG160

Outputs for LCD display. Connected to the segment pins on the LCD panel.

In the display off mode, all the outputs are fixed to GND.

O

Outputs for LCD display. Connected to the common pin on the LCD panel.

The output pins are located at three positions: both ends of the chip and

between SEG80 and SEG81. Each is connected inside the chip. Use the

COM pins in accordance with the panel to be used.

In the display off mode, all the outputs are fixed to GND.

When the slave is set (M/S=”L”), connecting SYNCB signals enables the

master chip to synchronize with common outputs.

143-146

235-238

326-329

COM1

COM4

O

59-65

66-72

VDD

VLCD

GND

-

Power supply pin for logic circuit.

Power supply pin for LCD driver.

51-58

29-30

103-104

7-8

133-134

1-6

Ground pin.

VDD output pin.

VDDO

GNDO

-

Use this pin when fixing the mode setting input pin to "H" on the COG.

Ground output pin.

Use this pin when fixing the mode setting input pin to "L" on the COG.

135-142

147-154

319-325

330-331

Floating pin.

DUMMY

-

At this time, avoid this pin from shorting with pins other than DUMMY in the

wiring on the COG.

*1: For details of the COM and SEG waveform when a duty is selected, refer to "Common waveform" on page

18 and "Common Segment waveform" on page 19 to 23.

*2: Oscillator circuit configuration

• When M/S = "H", OSC I/E = "H"

[Internal Rf oscillation mode]

[External Rf oscillation mode]

OSC1

OPEN

OSC1

R_ｆ

OSC2

OSCR

OPEN

OSCR

12/32

FEDL9479E-02

ML9479E

• External clock input mode when M/S = "H" and OSC I/E = "L"

External

clock

OSC1

OPEN

OSC2

OSCR

• M/S = "L", slave mode, external clock input mode

OSC1

Master CKO

OPEN

OSC2

OSCR

*3: Reset circuit configuration

• External input to RESTB when POCEB = "H"

VDD

External

input

RESETB

• POC circuit configuration when POCEB = "L"

VDD

RESETB

C_rst

13/32

FEDL9479E-02

ML9479E

DESCRIPTION

Operation description (Serial interface)

• Display data input

As described in the Data configuration section, the display data consists of the data field that corresponds to

each segment on/off and the command field that indicates the display data input.

When inputting the display data, the "F3" command is set in the command field. When the "F1" or "F2"

command is set in the command field, the display data in the data field becomes invalid.

The data input to the DATA pin is loaded to the shift register at the CLOCK pulse rise, transferred to the

display data latch during the LOAD pulse at the "H" level, then output via the segment driver.

CLOCK

D160

DATA

D1 D2 D3 D4

Data field

C0 C1 C2 C3 C4 C5 C6 C7

Command field

LOAD

Display output

New data

Old data

• Display on, Display off

The display becomes off at power-on reset. To display, write the display on command.

The display off is the command that makes all segments off. Writing the display off command, turns off the

lights regardless of the display data.

The display on is the command to release the display off. Writing the display on command returns the display

to the original state.

CLOCK

DATA

D1 D2

C6 C7

C4 C5 C6 C7

LOAD

Display ON/OFF

RESET

Display data input

Display off

command write

Display on

command write

14/32

FEDL9479E-02

ML9479E

List of Commands

Command

name

C7 C6

C5

0

C4

0

C3 C2

C1

x

C0 Operation

Disabled

F0

0

x

Frame frequency setting

(F1,F0)=(0, 0): 65Hz

(F1,F0)=(0, 1): 75Hz

(F1,F0)=(1, 0): 85Hz

(F1,F0)=(1, 1): 95Hz

(valid for Internal CR oscillation)

Display on/off

"0" : Off （COM=SEG=GND）

"1" : On

F1

(*2)

F0

(*2)

F1

F2

0

1

x

D

(*2)

1

0

1

x

Data write address setting

(Co1,Co0)=(0, 0): Corresponding to

common 1

(Co1,Co0)=(0, 1): Corresponding to

common 2

F3(*1)

SA1 SA0 A1 A0 Co1 Co0

(Co1,Co0)=(1, 0): Corresponding to

common 3

(Co1,Co0)=(1, 1): Corresponding to

common 4

SA1, SA0, A1, A0: Chip address

x: Don't care

(*1): For the I²C interface, SA0 is set at a slave address.

These bits become "Don't care".

In the ML9479E, set the SA1 address to "1".

(*2): The register is set to the following value by the RESETB = "L" input or by the power-on POC.

F1="0", F0="0", D="0"

Data configuration

• Data configuration (Serial interface)

First bit

Corresponding to SEG160

Corresponding to SEG1

C7

C6

C5

C4

C3

C2

C1

C0

D160 D159 D158

D3

D2

D1

LCD display data

Command

Note 1: The commands F1 and F2 settings become valid when the least four bits of C4 to C7 are input.

(The bits from D1 to D160 and from C0 to C3 are not necessary.)

Note 2: If the dummy bit is needed for the reason of number of transfer bits, put it on the first bit side.

Note 3: The command execution follows the contents of the C7 to C0 registers immediately before the LOAD

becomes "H".

15/32

FEDL9479E-02

ML9479E

• Data configuration (I²C interface)

Slave address

Control byte

DATA/Command

R/W

0

SA0

LSB

S

0

1

0

1

A

MSB

P

CO RS

Salve address: 0 1 1 0 0 1

CO: Consecutive control byte setting bit

0: Last control byte, 1: Consecutive control byte

RS: Command/data setting bit

0: Command data, 1: Display data

For the I²C interface, each IC is assigned with a 7-bit slave address. The first one byte in the transfer consists of

this 7-bit slave address and the R/W bit that indicates the data transfer direction. Always input "0" to the eighth

R/W bit because the ML9479E is a write-only LSI.

The eight bits next to the slave address is a control byte. The first one bit is CO: consecutive command setting bit

and the next one bit is RS: command/data setting bit (the remaining six bits are the Don't care bits).

When CO = "0": Means the last control byte.

When CO = "1": Means the control bytes are successively input.

When RS = "0": Means the data to be input next is the command data.

When RS = "1": Means the data to be input next is the display data.

The display data can be successively input.

Example of Data Setting



When inputting two commands

SA0

COMMAND

S

0

1

0

1

0

1

0

A

1

0

A

COMMAND

P



When inputting the command and display data

SA0

COMMAND

Display data

S

0

1

0

1

0

A

1

0

A

Display data

P

16/32

FEDL9479E-02

ML9479E

Data write method

• Serial interface

The data is written to the address set by the data write setting command (F3).

For the Serial interface, the data is written in units of 160 bits.

Written from D160 to SEG1, D159 to SEG2, ... , D2 to SEG159, and D1 to SEG160.

MSB

1

Segment output

72 73 74

D89 D88 D87 D86 D85 D84 D83 D82 D81

LSB

80

2

3

4

75

76

77

78

79

D160 D159 D158 D157

COM1

COM2

COM3

COM4

MSB

Segment output

LSB

81

82

83

84

152 153 154 155 156 157 158 159 160

D80 D79 D78 D77

D9

D8

D7

D6

D5

D4

D3

D2

D1

COM1

COM2

COM3

COM4

• I²C interface

The data is written to the address set by the slave address.

For the I²C interface, the data is written to the specified address starting with the LSB side in units of 8 bits.

(The data is written in the order from SEG153-160, SEG145-SEG152, ... , SEG9-16, and SEG1-SEG8.)

LSB

1

D1

Segment output

MSB

80

D8

2

3

4

72

D8

73

D1

74

D2

75

D3

76

D4

77

D5

78

D6

79

D7

D2

D3

D4

COM1

COM2

COM3

COM4

D1

D8

LSB

Segment output

MSB

81

82

83

84

152 153 154 155 156 157 158 159 160

D1

D2

D3

D4

D8

D1

D2

D3

D4

D5

D6

D7

D8

COM1

COM2

COM3

COM4

17/32

FEDL9479E-02

ML9479E

Common waveforms

(1) At static



V_LCD

COM1～4

GND

(2) At 1/2-duty

At 1/2-bias

V_LCD

COM1

COM3

V_LCD/2

GND

V_LCD

COM2

COM4

V_LCD/2

GND

At 1/3-bias

V_LCD

COM1

COM3

2V_LCD/3

V_LCD/3

GND

V_LCD

2V_LCD/3

V_LCD/3

GND

COM2

COM4

(3) At 1/3-duty

COM1

V_LCD

2V_LCD/3

V_LCD/3

GND

V_LCD

2V_LCD/3

V_LCD/3

GND

COM2

COM4

V_LCD

2V_LCD/3

V_LCD/3

GND

COM3

(4) At 1/4-duty

COM1

V_LCD

2V_LCD/3

V_LCD/3

GND

V_LCD

2V_LCD/3

V_LCD/3

GND

COM2

COM3

COM4

V_LCD

2V_LCD/3

V_LCD/3

GND

V_LCD

2V_LCD/3

V_LCD/3

GND

18/32

FEDL9479E-02

ML9479E

● Common segment output waveform

・At Static

S

E

G

1

S

E

G

2

S

E

G

3

Display example

COM1

On

Off

V_LCD

COM1

COM2

COM3

COM4

2V_LCD/3

V_LCD/3

GND

V_LCD

2V_LCD/3

V_LCD/3

GND

SEG1

SEG2

SEG3

V_LCD

2V_LCD/3

V_LCD/3

GND

V_LCD

2V_LCD/3

V_LCD/3

GND

19/32

FEDL9479E-02

ML9479E

● Common and segment output waveforms

・At 1/2Duty, 1/2bias

S

E

G

1

S

E

G

2

S

E

G

3

Display example

COM1

COM2

On

Off

V_LCD

COM1

COM3

V_LCD/2

GND

V_LCD

COM2

COM4

V_LCD/2

GND

V_LCD

SEG1

SEG2

SEG3

V_LCD/2

GND

V_LCD

V_LCD/2

GND

V_LCD

V_LCD/2

GND

20/32

FEDL9479E-02

ML9479E

●

Common segment output waveform

・At 1/2 Duty、1/3bias

S

E

G

1

S

E

G

2

S

E

G

3

Display example

COM1

COM2

On

Off

V_LCD

2V_LCD/3

V_LCD/3

GND

COM1

COM3

V_LCD

2V_LCD/3

V_LCD/3

GND

COM2

COM4

V_LCD

2V_LCD/3

V_LCD/3

GND

SEG1

SEG2

SEG3

V_LCD

2V_LCD/3

V_LCD/3

GND

V_LCD

2V_LCD/3

V_LCD/3

GND

21/32

FEDL9479E-02

ML9479E

● Common and segment output waveforms

・At 1/3Duty, 1/3bias

S

E

G

1

S

E

G

2

S

E

G

3

Display example

COM1

COM2

COM3

On

Off

V_LCD

2V_LCD/3

V_LCD/3

COM1

GND

V_LCD

2V_LCD/3

V_LCD/3

GND

COM2

COM4

V_LCD

2V_LCD/3

V_LCD/3

GND

COM3

V_LCD

2V_LCD/3

V_LCD/3

GND

SEG1

SEG2

SEG３

V_LCD

2V_LCD/3

V_LCD/3

GND

V_LCD

2V_LCD/3

V_LCD/3

GND

22/32

FEDL9479E-02

ML9479E

● Common and segment output waveforms

・At 1/4Duty, 1/3bias

S

E

G

1

S

E

G

2

S

E

G

3

Display example

COM1

COM2

COM3

COM4

On

Off

V_LCD

2V_LCD/3

V_LCD/3

GND

COM1

COM2

COM3

COM4

SEG1

SEG2

SEG3

V_LCD

2V_LCD/3

V_LCD/3

GND

V_LCD

2V_LCD/3

V_LCD/3

GND

V_LCD

2V_LCD/3

V_LCD/3

GND

V_LCD

2V_LCD/3

V_LCD/3

GND

V_LCD

2V_LCD/3

V_LCD/3

GND

V_LCD

2V_LCD/3

V_LCD/3

GND

23/32

FEDL9479E-02

ML9479E

EXAMPLE OF APPLICATION CIRCUIT

Cascade configuration 1

Serial interface

Internal CR oscillator circuit used

1/4Duty

RESETB pin + external capacitance connection to configure POC circuit

The common waveform of master and slave chip is active.

[External component]

Cp = 0.1 [µF] (bypass capacitor between power supplies)

Crst = 4.7 [µF] (capacitance for external POC circuit)

LCD panelꢀ1/4Duty × 160 Segment

LCD Panelꢀ1/4Duty × 160 Segemnet

COM1

COM2

COM3

COM4

COM2

COM3

COM4

5V

VLCD

VDD

VLCD

VDD

ML9479E

ML9479D

（Mater)

ML9479E

ML9479D

(Slave)

Cp Cp

M/S

BIAS

OSCI/E

POCEB

Duty0

Duty1

I2C

M/S

BIAS

OSCI/E

POCEB

Duty0

Duty1

I2C

OSC1

OSC2

OSCR

CKO

OPEN

OSC1

OSC2

OSCR

CKO

OPEN

SA0

A1

A0

RESETB

Crst

TEST1

TEST2

GND

TEST1

TEST2

GND

OPEN

CPU

24/32

FEDL9479E-02

ML9479E

Cascade configuration 2

II²C interface

External Rf-based CR oscillator circuit used

1/4Duty

External RESETB signal input

The common waveform of slave chip is open.

[External component]

Cp = 0.1 [µF] (bypass capacitor between power supplies),

Rf = 470 [k] (external R, resistor for CR oscillator circuit),

Rup = Resistor for SDA data bus pull-up

LCD Panelꢀ1/4Duty × 160 × n Segment

COM1

COM2

COM3

COM4

COM1

COM2

COM3

COM4

OPEN

5V

VLCD

VDD

VLCD

VDD

ML9479E

ML9479D

（Master)

ML9479D

(Slave)

Cp Cp

M/S

BIAS

OSCI/E

POCEB

Duty0

Duty1

I2C

M/S

BIAS

OSCI/E

POCEB

Duty0

Duty1

I2C

Rf

OSC1

OSC2

OSCR

CKO

OSC1

OSC2

OSCR

CKO

OPEN

SA0

OPEN

A1

A0

RESETB

TEST1

TEST2

GND

TEST1

TEST2

GND

5V

Rup

CPU

25/32

FEDL9479E-02

ML9479E

PAD CONFIGURATION

Pad layout (pattern face)

Chip size

: 8.84 mm x 0.90 mm

: 400 m ± 20 m

: 50 m

Chip thickness

Minimum bump pitch

Bump height

: 15 m ±3 m

321

152

B

Y

151

141

322

X

(0,0)

331

A

1

140

Bump and alignment mark dimensions (pattern face)

PAD No.1140

PAD No.141331

Alignment marks A and B : See below

: 35 m x 72 m

: 30 m x 84 m

[Mark A]

[Mark B]

Coordinate position

30μm

47μm

55μm

30μm

47μm

55μm

Aluminum (top metal) Passivation

Passivation

Aluminum (top metal)

X-coordinate (m)

4308.9

Y-coordinate (m)

-312.1

Alignment mark

Mark A

-4305.9

305.9

Mark B

26/32

FEDL9479E-02

ML9479E

Pad center coordinates

Pad

X-coordinate Y-coordinate

Pad

number

X-coordinate Y-coordinate

Pad name

number

Pad name

(m)

-1863

-1767.8

-1711.8

-1655.8

-1599.8

-1543.8

-1448.6

-1392.6

-1336.6

-1280.6

-1224.6

-1154.4

-1084.2

-1028.2

-972.2

-916.2

-860.2

-804.2

-748.2

-653

(m)

1

DUMMY

GNDO

Duty1

-4236.2

-4176.2

-4116.2

-4056.2

-3996.2

-3936.2

-3871

-312.1

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

DATA(SDA)

CLOCK(SCL)

LOAD

-312.1

2

3

4

5

6

7

8

-3815

LOAD

9

-3749

LOAD

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

Duty1

-3693

LOAD

Duty1

-3637

LOAD

Duty1

-3581

GND

Duty0

-3510.4

-3454.4

-3398.4

-3342.4

-3272

GND

Duty0

GND

Duty0

GND

Duty0

GND

A0

GND

A0

-3216

GND

A0

-3160

GND

A0

-3104

VDD

A1

-3033.8

-2977.8

-2921.8

-2865.8

-2795.6

-2739.6

-2683.6

-2627.6

-2557.4

-2501.4

-2406.2

-2350.2

-2294.2

-2238.2

-2182.2

-2087

VDD

-597

A1

VDD

-541

A1

VDD

-485

A1

VDD

-429

SA0

VDD

-373

SA0

VDD

-317

SA0

VLCD

-221.8

-165.8

-109.8

-53.8

SA0

VLCD

VDDO

SDAACK

DATA(SDA)

VLCD

2.2

VLCD

58.2

VLCD

114.2

209.6

265.6

321.6

377.6

433.6

503.8

RESETB

OSC1

-2031

-1975

-1919

27/32

FEDL9479E-02

ML9479E

Pad

number

79

X-coordinate Y-coordinate

Pad name

Pad number Pad name

(m)

559.8

(m)

3251.4

3321.6

3377.6

3433.6

3489.6

3559.8

3615.8

3671.8

3727.8

3798

(m)

-312.1

-232.2

-182.2

-132.2

-82.2

OSC1

OSC2

OSCR

CKO

-312.1

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

BIAS

TEST2

TEST1

GNDO

DUMMY

COM1

80

81

615.8

671.8

82

727.8

83

790.4

84

846.4

85

902.4

86

958.4

87

1014.4

1090.4

1146.4

1202.4

1258.4

1314.4

1389.8

1445.8

1501.8

1557.8

1613.8

1694

88

89

3854

90

3924.2

3984.2

4044.2

4104.2

4164.2

4224.2

4308.9

4225

91

92

93

94

CKO

95

CKO

96

CKO

97

CKO

98

SYNCB

VDDO

I2C

99

1750

COM2

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

1806

COM3

-32.2

1862

COM4

17.8

1918

DUMMY

SEG1

67.8

2004.4

2060.4

2130.6

2186.6

2242.6

2298.6

2368.8

2424.8

2480.8

2536.8

2607

117.8

167.8

217.8

267.8

308.9

I2C

4175

M/S

4125

M/S

4075

M/S

SEG2

4025

M/S

SEG3

3975

POCEB

OSCI/E

BIAS

SEG4

3925

2663

SEG5

3875

2719

SEG6

3825

2775

SEG7

3775

2845.2

2901.2

2957.2

3013.2

3083.4

3139.4

3195.4

SEG8

3725

SEG9

3675

SEG10

SEG11

SEG12

SEG13

SEG14

3625

3575

3525

BIAS

3475

BIAS

3425

28/32

FEDL9479E-02

ML9479E

Pad

number

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

259

260

261

262

X-coordinate Y-coordinate

Pad

number

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

256

257

258

304

305

306

307

X-coordinate Y-coordinate

Pad name

(m)

3375

3325

3275

3225

3175

3125

3075

3025

2975

2925

2875

2825

2775

2725

2675

2625

2575

2525

2475

2425

2375

2325

2275

2225

2175

2125

2075

2025

1975

1925

1875

1825

1775

1725

1675

1625

1575

1525

1475

1425

1375

1325

1275

1225

1175

-1125

-1175

-1225

-1275

(m)

308.9

(m)

1125

1075

1025

975

(m)

308.9

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

SEG40

SEG41

SEG42

SEG43

SEG44

SEG45

SEG46

SEG47

SEG48

SEG49

SEG50

SEG51

SEG52

SEG53

SEG54

SEG55

SEG56

SEG57

SEG58

SEG59

SEG101

SEG102

SEG103

SEG104

SEG60

SEG61

SEG62

SEG63

SEG64

SEG65

SEG66

SEG67

SEG68

SEG69

SEG70

SEG71

SEG72

SEG73

SEG74

SEG75

SEG76

SEG77

SEG78

SEG79

SEG80

COM1

925

875

825

775

725

675

625

575

525

475

425

375

325

275

225

175

125

75

COM2

25

COM3

-25

COM4

-75

SEG81

SEG82

SEG83

SEG84

SEG85

SEG86

SEG87

SEG88

SEG89

SEG90

SEG91

SEG92

SEG93

SEG94

SEG95

SEG96

SEG97

SEG98

SEG99

SEG100

SEG146

SEG147

SEG148

SEG149

-125

-175

-225

-275

-325

-375

-425

-475

-525

-575

-625

-675

-725

-775

-825

-875

-925

-975

-1025

-1075

-3375

-3425

-3475

-3525

29/32

FEDL9479E-02

ML9479E

Pad

number

263

264

265

266

267

268

269

270

271

272

273

274

275

276

277

278

279

280

281

282

283

284

285

286

287

288

289

290

291

292

293

294

295

296

297

298

299

300

301

302

303

X-coordinate Y-coordinate

Pad

number

308

309

310

311

312

313

314

315

316

317

318

319

320

321

322

323

324

325

326

327

328

329

330

331

X-coordinate Y-coordinate

Pad name

(m)

308.9

(m)

-3575

(m)

308.9

203.2

153.2

103.2

53.2

SEG105

SEG106

SEG107

SEG108

SEG109

SEG110

SEG111

SEG112

SEG113

SEG114

SEG115

SEG116

SEG117

SEG118

SEG119

SEG120

SEG121

SEG122

SEG123

SEG124

SEG125

SEG126

SEG127

SEG128

SEG129

SEG130

SEG131

SEG132

SEG133

SEG134

SEG135

SEG136

SEG137

SEG138

SEG139

SEG140

SEG141

SEG142

SEG143

SEG144

SEG145

-1325

-1375

-1425

-1475

-1525

-1575

-1625

-1675

-1725

-1775

-1825

-1875

-1925

-1975

-2025

-2075

-2125

-2175

-2225

-2275

-2325

-2375

-2425

-2475

-2525

-2575

-2625

-2675

-2725

-2775

-2825

-2875

-2925

-2975

-3025

-3075

-3125

-3175

-3225

-3275

-3325

SEG150

SEG151

SEG152

SEG153

SEG154

SEG155

SEG156

SEG157

SEG158

SEG159

SEG160

DUMMY

COM4

-3625

-3675

-3725

-3775

-3825

-3875

-3925

-3975

-4025

-4075

-4125

-4175

-4225

-4308.9

3.2

COM3

-46.8

-96.8

-146.8

-196.8

-246.8

COM2

COM1

DUMMY

30/32

FEDL9479E-02

ML9479E

REVISION HISTORY

Page

Issue Date

Description

New

Edition

FEDL9479E-01

FEDL9479E-02

May. 28,2012

Apr. 3,2013

–

Final edition 1 issued

BIAS="L": 1/2bias → BIAS="H": 1/2bias

10

31/32

FEDL9479E-02

ML9479E

NOTICE

No copying or reproduction of this document, in part or in whole, is permitted without the consent of

LAPIS Semiconductor Co., Ltd.

The content specified herein is subject to change for improvement without notice.

The content specified herein is for the purpose of introducing LAPIS Semiconductor's products (hereinafter

"Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be

obtained from LAPIS Semiconductor upon request.

Examples of application circuits, circuit constants and any other information contained herein illustrate the

standard usage and operations of the Products. The peripheral conditions must be taken into account when

designing circuits for mass production.

Great care was taken in ensuring the accuracy of the information specified in this document. However,

should you incur any damage arising from any inaccuracy or misprint of such information, LAPIS

Semiconductor shall bear no responsibility for such damage.

The technical information specified herein is intended only to show the typical functions of and examples

of application circuits for the Products. LAPIS Semiconductor does not grant you, explicitly or implicitly,

any license to use or exercise intellectual property or other rights held by LAPIS Semiconductor and other

parties. LAPIS Semiconductor shall bear no responsibility whatsoever for any dispute arising from the use

of such technical information.

The Products specified in this document are intended to be used with general-use electronic equipment or

devices (such as audio visual equipment, office-automation equipment, communication devices, electronic

appliances and amusement devices).

The Products specified in this document are not designed to be radiation tolerant.

While LAPIS Semiconductor always makes efforts to enhance the quality and reliability of its Products, a

Product may fail or malfunction for a variety of reasons.

Please be sure to implement in your equipment using the Products safety measures to guard against the

possibility of physical injury, fire or any other damage caused in the event of the failure of any Product,

such as derating, redundancy, fire control and fail-safe designs. LAPIS Semiconductor shall bear no

responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance

with the instruction manual.

The Products are not designed or manufactured to be used with any equipment, device or system which

requires an extremely high level of reliability the failure or malfunction of which may result in a direct

threat to human life or create a risk of human injury (such as a medical instrument, transportation

equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). LAPIS

Semiconductor shall bear no responsibility in any way for use of any of the Products for the above special

purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales

representative before purchasing.

If you intend to export or ship overseas any Product or technology specified herein that may be controlled

under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit

under the Law.

32/32


型号：	ML9479E
厂家：	ROHM
描述：	ML9479E由80位移位寄存器、640位数据锁存器、160组LCD驱动器、以及公共信号生成电路组成。静态显示时可直接驱动多达160段、1/2Duty显示时可直接驱动多达320段、1/3Duty显示时可直接驱动多达480段、1/4Duty显示时可直接驱动多达640段的LCD。三线串行接口和I2C接口可选。驱动 CD 锁存器驱动器移位寄存器
文件：	总33页 (文件大小：325K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ML9479E [ROHM]

相关型号：

ML9480

ML9484

ML961B8S

ML9620

ML9701A

ML974A1F

ML974A2F

ML974F11F

ML976H10

ML976H11F

ML976H6F

ML9781A