ML9480 [ROHM]
ML9480由40位移位寄存器、160位数据锁存器、40组LCD驱动器、以及公共信号生成电路组成。静态显示时可直接驱动多达40段、1/2Duty显示时可直接驱动多达80段、1/3Duty显示时可直接驱动多达120段、1/4Duty显示时可直接驱动多达160段的LCD。三线串行接口和I2C接口可选。;
| 型号： | ML9480 |
| 厂家： | 
ROHM |
| 描述： | ML9480由40位移位寄存器、160位数据锁存器、40组LCD驱动器、以及公共信号生成电路组成。静态显示时可直接驱动多达40段、1/2Duty显示时可直接驱动多达80段、1/3Duty显示时可直接驱动多达120段、1/4Duty显示时可直接驱动多达160段的LCD。三线串行接口和I2C接口可选。 驱动 CD 锁存器 驱动器 移位寄存器 |
| 文件： | 总38页 (文件大小：371K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dear customer
LAPIS Semiconductor Co., Ltd. ("LAPIS Semiconductor"), on the 1st day of October,
2020, implemented the incorporation-type company split (shinsetsu-bunkatsu) in which
LAPIS established a new company, LAPIS Technology Co., Ltd. (“LAPIS
Technology”) and LAPIS Technology succeeded LAPIS Semiconductor’s LSI business.
Therefore, all references to "LAPIS Semiconductor Co., Ltd.", "LAPIS Semiconductor"
and/or "LAPIS" in this document shall be replaced with "LAPIS Technology Co., Ltd."
Furthermore, there are no changes to the documents relating to our products other than
the company name, the company trademark, logo, etc.
Thank you for your understanding.
LAPIS Technology Co., Ltd.
October 1, 2020
FEDL9480-01
Issue Date: Oct. 1, 2012
ML9480
Static, 1/2 Duty, 1/3 Duty, 1/4 Duty 40 Outputs LCD Driver
GENERAL DESCRIPTION
The ML9480 is an LCD driver LSI, consists of a 40-bit shift register, a 160-bit data latch, 40 sets of LCD drivers,
and a common signal generation circuit.
It can directly drive an LCD up to 40 segments for static display, 80 segments for 1/2-duty display, 120
segments for 1/3-duty display, and 160 segments for 1/4-duty display.
The three-wire serial interface and I2C interface are selectable.
FEATURES
Logic power supply voltage
LCD drive power supply voltage : 4.5 to 5.5 V
Maximum number of segments
Static display
1/2-duty display
: 2.7 to 5.5 V
: 40 segments
: 80 segments
: 120 segments
: 160 segments
1/3-duty display
1/4-duty display
Interface with microcomputer :
Serial interface : DATA, CLOCK, LOAD
CLOCK transfer speed up to 1 MHz
I2C interface
: SDA, SCL, SDAACK
SCL transfer speed up to 400 kHz
Built-in CR oscillator circuit using the internal resistor or External resistor
Cascade connectable (up to sixteen chips)
Built-in common signal generation circuit
Built-in common output intermediate-value voltage generation circuit
Built-in POC (Power On Clear) circuit
Gold bump chip (ML9480DVWA)
1/37
FEDL9480-01
ML9480
BLOCK DIAGRAM
SEG1
SEG40
VLCD
40-Dot Segment Driver
40-Ch Data Selector
Bias
Resi.
BIAS
Duty0
Duty1
40
40
40
40
40-Bit
Latch4
40-Bit
Latch3
40-Bit
Latch2
40-Bit
Latch1
M/S
LATCH
SELECTOR
40
MODE
I2C
LOAD
DATA（SDA）
CLOCK（SCL）
Command
Decoder
40-bit Shift Register
SDAACK
SA1
SA0
A1
A0
OSC I/E
COM1
COM2
COM3
COM4
OSC1
OSCR
OSC2
COMMON
Driver
TIMING
GENERATOR
OSC
CKO
SYNCB
POC
Circuit
POCEB
RESETB
TEST1
VDD
GND
2/37
FEDL9480-01
ML9480
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Condition
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
—
Rating
-0.3 to 6.0
-0.3 to 6.0
– 0.3 to VDD + 0.3
-2.0 to +2.0
125
Unit
V
Logic power supply voltage
LCD drive power supply voltage
Input voltage
VDD
VLCD
VI
V
V
Output short-circuit current
Chip temperature
Is
mA
°C
°C
Tc
Storage temperature
TSTG
—
-55 to +150
Note: Do not use the ML9480 by short-circuiting one output pin to another output pin as well as to other pin
(input pin, input/output pin, or power supply pin).
RECOMMENDED OPERATION CONDITIONS
Item
Symbol
VDD
Condition
Range
Unit
Logic power supply voltage
LCD drive power supply voltage
OSC IN clock frequency
Data clock frequency
*
—
—
—
—
—
—
2.7 to 5.5
4.5 to 5.5
up to 10
V
V
VLCD
fCP1
fCP2
fSCL
Ta
*
kHz
MHz
kHz
°C
up to 1.0
up to 400
-40 to +105
SCL clock frequency
Operating temperature
Note(*): Use at VDD VLCD
.
The relation between OSC IN clock frequency and frame frequency is as the equation below.
fFRM = fOSC /24
Recommended setting range for external component (oscillator circuit)
(VDD = 2.7 to 5.5 V, VLCD = 4.5 to 5.5 V, Ta= –40 to +105°C)
Item
Symbol
Rf
Condition
—
Min
423
47
TYP
470
75
Max
517
114
Unit
kΩ
Oscillation resistor
Frame frequency
fFRM
(F1,F0)=(0,1)
Hz
The relation between oscillation resistor and frame frequency is as the equation below.
fFRM = fOSC /(16 x 24)
fosc = 1 / (Device coefficient x External resistor Rf)
Device coefficient = 73.8 x 10-12 ± 25%
3/37
FEDL9480-01
ML9480
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD = 2.7 to 5.5 V, VLCD = 4.5 to 5.5 V, Ta= -40 to +105°C)
Item
Symbol
VIH
Condition
—
Min.
0.8VDD
GND
-1.0
Typ.
—
Max.
VDD
Unit
V
Applicable pin
(*1)
(*1)
"H" input voltage
"L" input voltage
Input leakage current 1
VIL
—
—
0.2VDD
1.0
V
IL1
VI = VDD or 0 V
VI = VDD or 0V
POCEB="H"
VDD = 5.0V,VI = 0 V
POCEB = "L"
IO = -600uA
IO = 600uA
VDD=5V,
—
A (*1)
Input leakage current 2
Pull-up current
IL2
Ipu
-1.0
30
—
—
1.0
A RESETB
140
A RESETB
"H" output voltage
"L" output voltage 1
VOH
0.9VDD
—
—
—
—
V CKO, SYNCB
V
VOL1
0.1VDD
CKO, SYNCB
"L" output voltage 2
VOL2
3
—
—
mA SDAACK
VOL = 0.4V
Segment
Driver
VOHS
VOHC
VLCD = 5V
—
—
5
5
15
12
kΩ SEG1 to SEG40
kΩ COM 1 to COM4
ON resistor
Common
VLCD = 5V
(*1): DATA(SDA), CLOCK(SCL), LOAD, M/S, SYNCB, Duty1, Duty0, BIAS, SA1,SA0, A1, A0, OSC1,
OSC I/E, I2C, POCEB, MODE
(VDD = 2.7 to 5.5 V, VLCD = 4.5 to 5.5 V, Ta= -40 to +105°C)
Applicable
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
pin
VDD=VLCD=5.5 V
IDDS
—
8
15
A
VDD
Static supply
current
Input pin fixed to "H" or "L"
Oscillation stopped, output no-load
POCEB="L"
ILCDS
—
—
9
15
18
A
A
VLCD
VDD
V
DD=VLCD= 5.5 V (*2)(*3)
Clock OSC1 external input
CP1=1.8kHz
IDD1
ILCD1
IDD2
ILCD2
IDD3
ILCD3
IDD4
(*6)
10
Dynamic supply
current 1
(*7)
(*6)
(*7)
—
—
—
—
9
59
9
13
90
A
A
A
A
VLCD
VDD
f
Dynamic supply
current 2
VDD=VLCD= 5.5 V (*2)(*3)
Internal oscillation
15
VLCD
VDD
VDD=VLCD= 5.5 V (*2)(*4)(*6)
Internal oscillation
100
200
Dynamic supply
current 3
—
—
—
9
188
9
15
310
15
A
A
A
VLCD
VDD
At three-wire serial IF data input
VDD=VLCD= 5.5 V (*2)(*5)(*6)
Internal oscillation
Dynamic supply
current 4
At I2C IF data input
ILCD4
VLCD
(*2): M/S = "H", 1/4-duty, 1/3-bias, (F1,F0,FSEL) = (1,1,0) 95 Hz, POCEB = "L", output pin no-load.
(*3): Three-wire serial or I2C interface. Input pin fixed to "H" or "L".
(*4): Serial interface, data input frequency = 1 MHz.
(*5): I2C interface, data input frequency = 400 kHz.
(*6): Alternately inputs "0" and "1" for LCD display data (checkered display).
(*7): Inputs all "1s" for LCD display data (all illuminated).
4/37
FEDL9480-01
ML9480
Switching Characteristics
OSC timing
Item
(VDD = 2.7 to 5.5 V, VLCD = 4.5 to 5.5 V, Ta = -40 to +105°C)
Symbol
fCP1
Condition
Min.
Typ. Max.
Unit
Applicable pin
OSC IN clock frequency
(external input)
—
1.8
—
10
—
kHz OSC1
Clock input from OSC1.
OSC2 and OSCR open.
OSC I/E = "L"
Clock pulse width
(External input)
tWCP1
tOSC
40
—
s
s
OSC1
OSC1
Clock rise and fall time
(external input)
—
(*1)
Between OSC1 and OSC2
Rf = 470kΩ
(F1,F0)=(0,1)
External Rf clock
frequency
fOSC1
18
18
28.8
28.8
44
44
kHz OSC1, OSC2
(Internal oscillation)
OSCR open.
OSC I/E = "H"
OSC1 open.
(F1,F0)=(0,1)
OSC2 and OSCR short-circuited.
OSC I/E = "H"
Internal clock frequency
(Internal oscillation)
OSC1, OSCR,
fOSC2
kHz
OSC2
The relation between OSC IN clock frequency and frame frequency is as the equation below.
fFRM = fOSC /24
(*1) tOSC is a reference value.
The longer the clock rise and fall time, the more susceptible to extraneous noises around the threshold value.
Make the rise as steep as possible. Reference value: max=2s.
Serial interface timing
(VDD = 2.7 to 5.5 V, VLCD = 4.5 to 5.5 V, Ta = -40 to +105°C)
Condition Min. Typ. Max. Unit Applicable pin
MHz CLOCK
Item
Symbol
Data clock frequency
Data clock pulse width
Data setup time
fCP2
tWCP2
tSU
—
100
50
—
—
—
—
—
—
—
1
—
—
—
—
—
—
ns CLOCK
ns DATA
ns CLOCK
ns CLOCK
ns LOAD
ns LOAD
Data hold time
tHD
50
CLOCK-LOAD timing
LOAD-CLOCK timing
LOAD pulse width
tCL
100
100
100
tLC
tWLD
CLOCK,DATA,
LOAD
Signal rise and fall time
tsr,tsf
—
—
(*2)
ns
(*2) tsr and tsf shall be reference values.
The longer the clock rise and fall time, the more susceptible to extraneous noises around the threshold value.
Make the rise as steep as possible. Reference value: max=10ns.
5/37
FEDL9480-01
ML9480
I2C interface timing
Item Symbol
(VDD = 2.7 to 5.5 V, VLCD = 4.5 to 5.5 V, Ta = -40 to +105°C)
Condition
Min. Typ. Max. Unit
Applicable pin
SCL clock frequency
Hold time (repeat)
"STATRT" condition
SCL "L" pulse width
SCL "H" pulse width
Setup time for repeat
"START" condition
Data hold time
fSCL
—
—
400 kHz SCL
tHD,STA
0.6
—
—
s SCL,SDA
tLOW
tHIGH
1.3
0.6
—
—
—
—
s SCL
s SCL
tSU,STA
0.6
—
—
s SCL,SDA
tHD,DAT
tSU,DAT
0
—
—
—
—
ns SCL,SDA
ns SCL,SDA
Data setup time
100
Setup time for "STOP"
condition
tSU,STO
0.6
—
—
s SCL,SDA
Bus free time between
"STOP" condition and
"START" condition
Data valid acknowledge
time
tBUF
1.3
—
—
s SCL
tVD,ACK
tir,tif
Cb
—
—
—
—
—
—
1.2
(*3)
400
s SCL,SDAAACK
s SCL,SDA
Signal rise and fall time
Data bus load
capacitance
pF SDA,SDAACK
Noise pulse width
tolerance
twf
—
—
50
ns SCL,SDA
(*3) tir and tif shall be reference values.
The longer the clock rise and fall time, the more susceptible to extraneous noises around the threshold value.
Make the rise as steep as possible. Reference value: max=0.1s.
6/37
FEDL9480-01
ML9480
Timing chart (OSC1)
1/fCP1
tWCP1
VIH
tWCP1
VIH
VIH
OSC1
(External clock)
VIL
VIL
tOSC
Timing chart (Serial interface)
VIH
VIH
VIL
tHD
VIH
VIH
DATA
VIL
VIL
VIL
tSU
tsf
tsr
tWCP2
tWCP2
VIH
VIL
VIH
VIH
VIH
CLOCK
VIL
VIL
VIL
VIL
1/fCP2
tsr
tCL
tWLD
tLC
tsf
V
IH VIH
LOAD
VIL
VIL
tsr
tsf
Timing chart (I2C interface)
tVD;ACK
VIH
VIH
VIL
VIH
VIL
VIH
VIL
SDA
tf
tBUF
tLOW
VIH
VIH
VIL VIL
VIH
VIH
VIL
VIH
VIL
SCL
VIL
tHD;STA
tHiGH
tHD;DAT
tr
tSU;DAT
VIH
SDA
VIL
tSU;STA
tSU;STO
7/37
FEDL9480-01
ML9480
REFERENCE DATA
Frame frequency Characteristics
VDD=5.5V/2.7V Rf=470Ω
Frame frequency fFRM = fOSC /(16 x 24)
fosc = 1 / (Device coefficient x External resistor Rf)
Device coefficient = 73.8 x 10-12 ± 25%
Frame frequency Characteristics Rf=470k,VDD=5.5V
120
110
100
90
(F1,F0)=(1,1)
(F1,F0)=(1,0)
(F1,F0)=(0,1)
(F1,F0)=(0,0)
80
70
60
50
-60
-40
-20
0
20
40
60
80
100
120
Temp Ta[℃]
Frame frequency Characteristics Rf=470k,VDD=2.7V
130
120
110
100
90
(F1,F0)=(1,1)
(F1,F0)=(1,0)
(F1,F0)=(0,1)
(F1,F0)=(0,0)
80
70
60
50
-60
-40
-20
0
20
40
60
80
100
120
TempꢀTa[℃]
8/37
FEDL9480-01
ML9480
POWER ON/OFF TIMING
To turn on the power supply, raise the logic power supply first, then LCD drive power supply in order to prevent
the IC from malfunctioning.
To fall the power supply, fall the LCD drive power supply first, then the logic power supply.
For a VDD pin ranging from 0 V to VDDmin, set VDD ≥ VLCD and t1 ≥ 0 [ns].
To enable the Internal POC circuit, the VDD power supply rise time t2 range needs to be 100 [µs] t2 500 [ms].
For the VDD power supply to turn OFF then turn ON again, it is necessary to secure the POC discharge time t3
100 [ms].
Voltage
VLCD
VDD
VDD
0.9VDD
t3
t1
t2
t1
Time
INITIALIZATION SIGNAL TIMING
When RESETB signal is externally input
The RESETB pin input is valid both for POCEB = "L" and "H". Usable in combination with the POC.
Keep the RESETB pin at "L" level until the VDD reaches VDDmin. (t4 ≥ 200[ns])
VDD
VDDmin
RESETB
VIL
t4
When Internal POC circuit is used
When using the Internal POC circuit in the initialization, set the POCEB pin to "L".
At this time, the power ON/OFF timing conditions are t1 to t3 above mentioned.
When RESETB pin POC circuit is used
If the power ON/OFF timing conditions t1 to t3 cannot be kept, the RESETB pin needs to have a capacitance
to configure the POC circuit. For this case, connect a capacitance value according to the power supply rise
time.
For the power supply rise time t2 and external capacitance value, use the following formula as a guide:
CRST [F] > t2 [sec]／(30×103)
9/37
FEDL9480-01
ML9480
PIN DESCRIPTIONS
Pad
Symbol
number
I/O
I
Description
This is the input to switch between the master and slave modes. It has a
schmitt circuit. When this pin is "H", the mode is master. When this pin is "L",
the mode is slave.
32
M/S
Display duty switch pins. These have schmitt circuits.
Duty0
Duty1
*1
Duty0="L", Duty1="L"
Duty0="H", Duty1="L"
Duty0="L", Duty1="H"
Duty0="H", Duty1="H"
:
:
:
Static
(COM1=COM2=COM3=COM4)
(COM1=COM3, COM2=COM4)
(COM2=COM4)
3,4
I
I
1/2Duty
1/3Duty
1/4Duty
:
This pin sets the LCD bias. It has a schmitt circuit.
BIAS="L": 1/3bias
BIAS="H": 1/2bias
35
BIAS
When the static mode selection, fix this pin at “H” or “L” level.
SA1
SA0
A1
7,8
5,6
I
I
Slave address input pins. These have schmitt circuits.
Sub address input pins. These have schmitt circuits.
A0
This input selects whether to use the external clock input mode or to use the
Internal oscillation mode or external oscillation mode. It has a schmitt circuit.
When this pin is "H", the mode is the Internal or external Rf oscillation mode.
When this pin is "L", the mode is the external clock input mode.
Use the slave chip as it is connected to GND.
34
OSC I/E
I
These pins are for the oscillator circuit to generate common signals.
The OSC1 and OSCR pins are input pins and have a schmitt circuit.
OSC2 is an output pin. It becomes an output when the OSC I/E pin = "H" and
a high impedance when the OSC I/E pin = "L".
【In the master mode (M/S pin ="H") 】
Three types are selectable: Internal oscillation mode, external oscillation
mode, and external clock input mode.
•Internal oscillation mode: Set the OSC I/E pin to "H", short the OSCR and
OSC2 pins, and open the OSC1 pin.
•External Rf oscillation mode: Set the OSC I/E pin to "H", connect an
oscillation resistor Rf between the OSC1 and OSC2 pins, and open the
OSCR pin.
OSC1,
OSCR,
OSC2
*2
I
I
O
24 to 26
•External clock input mode: Set the OSC I/E pin to "L", open the OSCR and
OSC2 pins, and input the external clock to the OSC1 pin.
【 In the slave mode (M/S pin ="L") 】
Open the OSCR and OSC2 pins and connect the OSC1 pin to the
ML9480's CKO pin that has been set to the master mode.
Clock output pin.
In the master mode (M/S pin = "H", FSEL=”0”), the 1/16 division signal of the
oscillation frequency is output. In the master mode (M/S pin = "H",
FSEL=”1”), the 1/8 division signal of the oscillation frequency is output.
In the slave mode (M/S pin = "L"), the output is fixed to "L".
For a cascade connection, connect this pin to the OSC1 pin of the chip that
has been set to the slave mode.
27
CKO
O
10/37
FEDL9480-01
ML9480
Input/output pin for common synchronization. It has a schmitt circuit.
It becomes the synchronization signal output pin in the master mode (M/S
pin = "H").
It becomes the synchronization signal input pin in the slave mode (M/S pin = "L").
For cascade connection, connect all of the involved ML9480s' SYNC pins by
the common line.
28
30
SYNCB
I2C
I/O
Interface switching pin. It has a schmitt circuit.
When this pin is "H", the interface is I2C.
I
When this pin is "L", the interface is three-wire serial.
Display data input pin. It has a schmitt circuit.
I2C="L": Serial interface; DATA
Input the display data in the order of SEG40, SEG39, ... , SEG2, and SEG1.
The display data turns on at "H" and turns off at "L".
I2C="H": I2C interface; SDA
Input the display data in units of 8 bits. The display data turns on at "H" and
turns off at "L".
DATA
(SDA)
I
11
This pin has a built-in noise filter through which noises in widths up to 50 ns
are removed. This noise filter is valid only when I2C = "H".
Shift clock input pin for display data. It has a schmitt circuit.
I2C="L": Serial interface; CLOCK
The display data input to the DATA pin is serially input to the shift register at
the CLOCK signal rise.
CLOCK
(SCL)
I
12
I2C="H": I2C interface; SCL
The display data input to the SDA pin is serially input to the shift register at
the SCL signal rise.
This pin has a built-in noise filter through which noises in widths up to 50 ns
are removed. This noise filter is valid only when I2C = "H".
Input pin for the load signal of display data. It has a schmitt circuit.
I2C="L": Serial interface; LOAD
The display data in the shift register is transmitted as is to the segment driver
for the "H" duration. When this pin is brought into "L", the shift register is
disconnected from the segment driver. The display data in the shift register
immediately before it become "L" is held in the data latch and transmitted to
the segment driver.
13
LOAD
I
I2C="H": I2C interface
Use this pin as it is connected to GND.
I2C="L": Serial interface
Use this pin as it is opened.
I2C="H": I2C interface
10
SDAACK
POCEB
O
The I2C bus acknowledge output signal. Normally, use it as it is connected
with the SDA pin.
Connect an external pull-up resistor whenever
necessary, as it is an open drain pin. The pull-up connection destination
supply voltage shall be the VDD supply voltage or less.
Internal POC circuit enable pin. It has a schmitt circuit.
When this pin is "H", the POC circuit becomes OFF and the constant current
(8µA) is cut. The RESETB pin pull-up resistor is cut as well.
When this pin is "L", the POC circuit becomes ON.
33
23
I
I
The RESETB pin is connected to a pull-up resistor.
Reset signal input pin for initializing inside the IC. It has a schmitt circuit.
The "L" level enables the reset.
This pin has an Internal pull-up resistor. Open when POCEB = "H".
Pull-up when POCEB = "L". The power-on reset operation is available by
connecting an external capacitor.
RESETB
*3
11/37
FEDL9480-01
ML9480
I2C interface command table switching pin. It has a schmitt circuit.
This pin is valid only when I2C = "H".
When this pin is "L", the command table is table A.
When this pin is "H", the command table is table B.
When the three-wire serial interface mode selection, fix this pin at “H” or “L”
level.
31
36
MODE
TEST1
I
Pin for testing the IC. It has a Internal pull-down resistor.
Use it as it is connected to GND.
I
45 to 64,
69 to 88
SEG1
SEG40
Outputs for LCD display. Connected to the segment pins on the LCD panel.
In the display off mode, all the outputs are fixed to GND.
Outputs for LCD display. Connected to the common pins on the LCD panel.
The output pins are located at three positions: center and both ends of the
chip. Each is connected inside the chip. Use the COM pins in accordance
with the panel to be used.
In the display off mode, all the outputs are fixed to GND.
When the slave is set (M/S=”L”), COM1 to COM4 outputs are GND level
fixed.
O
40 to 43,
65 to 68,
90 to 93
COM1
COM4
O
14 to 16
20 to 22
17 to 19
VDD
VLCD
GND
-
-
-
Power supply pin for logic circuit.
Power supply pin for LCD driver.
Ground pin.
VDD output pin.
9,29
2,37
VDDO
GNDO
-
-
Use this pin when fixing the mode setting input pin to "H" on the COG.
Ground output pin.
Use this pin when fixing the mode setting input pin to "L" on the COG.
Floating pin.
At this time, avoid this pin from shorting with pins other than DUMMY in the
wiring on the COG.
1,38,
39,44,
89,94
DUMMY
-
*1: For details of the COM /SEG waveform when a duty is selected, refer to "Common waveform" on page 24
and "Common Segment waveform" on page 25 to 29.
*2: Oscillator circuit configuration
• When M/S = "H", OSC I/E = "H"
[Internal Rf oscillation mode]
[External Rf oscillation mode]
OSC1
OPEN
OSC1
Rｆ
OSC2
OSC2
OSCR
OPEN
OSCR
12/37
FEDL9480-01
ML9480
• External clock input mode when M/S = "H" and OSC I/E = "L"
External
clock
OSC1
OPEN
OPEN
OSC2
OSCR
• M/S = "L", slave mode, external clock input mode
OSC1
Master CKO
OPEN
OPEN
OSC2
OSCR
*3: Reset circuit configuration
• External input to RESTB when POCEB = "H"
VDD
External
input
RESETB
• POC circuit configuration when POCEB = "L"
VDD
RESETB
Crst
13/37
FEDL9480-01
ML9480
DESCRIPTION
Operation description (Serial interface)
• Display data input
As described in the Data configuration section, the display data consists of the data field that corresponds to
each segment on/off and the command field that indicates the display data input.
When inputting the display data, the "F3" command is set in the command field. When the "F1" or "F2"
command is set in the command field, the display data in the data field becomes invalid.
The data input to the DATA pin is loaded to the shift register at the CLOCK pulse rise, transferred to the
display data latch during the LOAD pulse at the "H" level, then output via the segment driver.
CLOCK
DATA
D1 D2 D3 D4
Data field
D40 C0 C1 C2 C3 C4 C5 C6 C7
Command field
LOAD
Display output
New data
Old data
• Display on, Display off
The display becomes off at power-on reset. To display, write the display on command.
The display off is the command that makes all segments off. Writing the display off command、turns off the
lights regardless of the display data.
The display on is the command to release the display off. Writing the display on command returns the display
to the original state.
CLOCK
DATA
D1 D2
C6 C7
C4 C5 C6 C7
C4 C5 C6 C7
LOAD
Display ON/OFF
RESET
Display data input
Display off
command write
Display on
command write
14/37
FEDL9480-01
ML9480
List of Commands
The ML9480 have two type command table. Command table can be selected by I2C and MODE input pins.
I2C Pin
MODE Pin
I/F
Serial
I2C
COMMAND
L
H
H
*
L
H
Command table A
Command table A
Command table B
I2C
List of Command table A
Serial interface and I2C interface (When MODE pin is "L")
Command
C7 C6
name
C5
x
C4
x
C3
x
C2
x
C1
x
C0 Operation
F0
0
0
x
x
Disabled
Frame frequency setting
(valid for Internal CR oscillation)
When FSEL =”0”
(F1,F0)=(0, 0): 65Hz
(F1,F0)=(0, 1): 75Hz
(F1,F0)=(1, 0): 85Hz
(F1,F0)=(1, 1): 95Hz
When FSEL = ”1”
0
1
F1
(*2)
F0
(*2)
FSEL
(*2)
x
x
F1
(F1,F0)=(0, 0): 130Hz
(F1,F0)=(0, 1): 150Hz
(F1,F0)=(1, 0): 170Hz
(F1,F0)=(1, 1): 190Hz
Display on/off
"0" : Off （COM=SEG=GND）
"1" : On
1
1
0
1
1
D
(*2)
x
x
x
x
F2
Data write address setting
(Co1,Co0)=(0, 0): Corresponding to common 1
(Co1,Co0)=(0, 1): Corresponding to common 2
(Co1,Co0)=(1, 0): Corresponding to common 3
(Co1,Co0)=(1, 1): Corresponding to common 4
SA1, SA0, A1, A0: Chip address
F3(*1)
SA1 SA0
A1
A0 Co1 Co0
x: Don't care
(*1): For the I2C interface, SA1 and SA0 are set at a slave address.
These bits become "Don't care".
(*2): The register is set to the following value by the RESETB = "L" input or by the power-on POC.
F1="0", F0="0", FSEL="0", D="0"
15/37
FEDL9480-01
ML9480
List of Command table B I2C interface(When MODE pin is "H")
Operation code
Command name
Initialize
C7
C
C6
1
C5
0
C4
C3
C2
C1
C0
x
D
B
M1
M0
Mode Set
D=B=M1=M2=”0”
Display RAM Address
C
C
C
C
C
0
1
1
1
1
P5
1
P4
0
P3
0
P2
A2
F1
0
P1
A1
F0
I
P0
A0
Chip Address
Frame Frequency
Select
F1=FSEL=”0”
F0=”1”
1
0
1
FSEL
O
1
1
1
Bank Select
Blink select
I=O=”0”
1
1
0
AB
BF1
BF0
AB=BF1=BF0=”0”
x: Don't care
C: Continue bit
0:last control byte in the transfer
1:control byte continue
MODE SET
C7
C
C6
1
C5
0
C4
x
C3
D
C2
B
C1
M1 M0
C0
MODE SET
D: Display ON/OFF
“0”: OFF (COM=SEG=GND)
“1”: ON
B: LCD Bias Setting
“0”: 1/3 Bias
“1”: 1/2 Bias
This command becomes effective at I2C pin =”H” and MODE pin=”H”.
M[1:0]: Duty setting
M[1:0]=(0, 1) : Static
M[1:0]=(1, 0) : 1/2Duty
M[1:0]=(1, 1) : 1/3Duty
M[1:0]=(0, 0) : 1/4Duty
This command becomes effective at I2C pin =”H” and MODE pin=”H”.
Display RAM Address
C7
C
C6
0
C5
P5
C4
P4
C3
P3
C2
P2
C1
P1
C0
P0
Display RAM
address
P[5:0]=00_0000 to 10_0111
The increment of the display RAM address is carried out automatically.
Static +8, 1/2duty +4, 1/3duty +3, 1/4duty +2
16/37
FEDL9480-01
ML9480
Chip Address
C7
C
C6
1
C5
1
C4
0
C3
0
C2
A2
C1
A1
C0
A0
Display RAM
address
A[2:0] = 111 to 000
The terminal corresponding to A2 is SA1 pin.
The terminal corresponding to A1 is A1 pin.
The terminal corresponding to A0 is A0 pin.
Frame frequency select
C7
C
C6
1
C5
1
C4
0
C3
1
C2
F1
C1
F0
C0
FSEL
Frame Frequency
Frame frequency setting.
This command becomes effective at I2C pin =”H”, MODE pin=”H”, BIAS pin =”L” and
internal CR oscillation.
When BIAS pin =”H” and internal CR oscillation, frame frequency is set to 75Hz (initialize).
When FSEL =”0”
(F1,F0)=(0, 0): 65Hz
(F1,F0)=(0, 1): 75Hz
(F1,F0)=(1, 0): 85Hz
(F1,F0)=(1, 1): 95Hz
When FSEL = ”1”
(F1,F0)=(0, 0): 130Hz
(F1,F0)=(0, 1): 150Hz
(F1,F0)=(1, 0): 170Hz
(F1,F0)=(1, 1): 190Hz
Bank Select
C7
C
C6
1
C5
1
C4
1
C3
1
C2
0
C1
I
C0
O
Bank Select
I: Input bank selection
I
Static
COM1
COM3
1/2Duty
0
1
COM1 & COM2
COM3 & COM4
This command has no effect in 1/3Duty and 1/4Duty mode.
O: Output bank selection
O
0
1
Static
COM1
COM3
1/2Duty
COM1 & COM2
COM3 & COM4
This command has no effect in 1/3Duty and 1/4Duty mode.
17/37
FEDL9480-01
ML9480
Blink Select
C7
C
C6
1
C5
1
C4
1
C3
0
C2
C1
C0
Blink Select
AB BF1 BF0
AB: Blink mode selection
“0”: Normal Blinking
“1”: Alternate RAM blinking does not apply in 1/3Duty and 1/4Duty.
BF[1:0]: Blink frequency selection
BF1
0
BF0
0
Blink Frequency
Blink OFF
65Hz/130Hz
2.03Hz
75Hz/150Hz
85Hz/170Hz
2.66Hz
95Hz/190Hz
2.97Hz
0
1
1
1
0
1
2.34Hz
1.17Hz
0.59Hz
1.01Hz
1.33Hz
1.48Hz
0.51Hz
0.66Hz
0.74Hz
Display data RAM
This is the RAM storing the data of display and has an organization of 40 x 4.
Display RAM data RAM address map
Display RAM data “1” ... Dot is displayed
Display RAM data “0” ... Dot is not displayed
Display data RAM address map
SEG SEG SEG SEG SEG
SEG SEG SEG SEG
37 38 39 40
1
2
3
4
5
COM1
COM2
COM3
COM4
・・・
・・・
・・・
・・・
Static drive ... COM1
1/2duty drive ... COM1, COM2
1/3duty drive ... COM1, COM2, COM3
1/4duty drive ... COM1, COM2, COM3, COM4
Cascade connection
When command table B is chosen (I2C pin =”H”, MODE pin =”H”), ML9480 cannot used
cascade connection.
18/37
FEDL9480-01
ML9480
Data configuration
• Data configuration (Serial interface)
First bit
Corresponding to SEG40
Corresponding to SEG1
C7
C6
C5
C4
C3
C2
C1
C0
D40
D39
D38
D3
D2
D1
LCD display data
Command
Note 1: The commands F1 and F2 settings become valid when the least four bits of C4 to C7 are input.
(The bits from D1 to D40 and from C0 to C3 are not necessary.)
Note 2: If the dummy bit is needed for the reason of number of transfer bits, put it on the first bit side.
Note 3: The command execution follows the contents of the C7 to C0 registers immediately before the LOAD
becomes "H".
19/37
FEDL9480-01
ML9480
• Data configuration (I2C interface, When MODE pin is "L")
Slave address
Control byte
R/W
0
DATA/Command
SA1 SA0
LSB
P
S
0
1
1
0
0
A
A
MSB
CO RS
Salve address: 0 1 1 0 0 1
CO: Consecutive control byte setting bit
0: Last control byte, 1: Consecutive control byte
RS: Command/data setting bit
0: Command data, 1: Display data
For the I2C interface, each IC is assigned with a 7-bit slave address. The first one byte in the transfer consists of
this 7-bit slave address and the R/W bit that indicates the data transfer direction. Always input "0" to the eighth
R/W bit because the ML9480 is a write-only LSI.
The eight bits next to the slave address is a control byte. The first one bit is CO: consecutive command setting bit
and the next one bit is RS: command/data setting bit (the remaining six bits are the Don't care bits).
When CO = "0": Means the last control byte.
When CO = "1": Means the control bytes are successively input.
When RS = "0": Means the data to be input next is the command data.
When RS = "1": Means the data to be input next is the display data.
The display data can be successively input.
Example of Data Setting
When inputting two commands
When inputting two commands
SA1 SA0
COMMAND
S
0
0
1
0
1
0
0
0
A
A
1
0
A
A
A
COMMAND
P
When inputting the command and display data
SA1 SA0
COMMAND
Display data
Display data
S
0
0
1
1
1
0
0
0
A
A
A
1
0
A
A
A
A
A
A
Display data
Display data
P
20/37
FEDL9480-01
ML9480
• Data configuration (I2C interface, When MODE pin is "H")
Slave address
1
COMMAND
DISPLAY DATA
R/W
0
MSB
SA0
LSB
A
S
0
1
1
0
0
A
C
A
P
Salve address: 0 1 1 1 0 0
C：Consecutive control byte setting bit
0：Last control byte, 1：Consecutive control byte
For the I2C interface, each IC is assigned with a 7-bit slave address. The first one byte in the transfer consists of
this 7-bit slave address and the R/W bit that indicates the data transfer direction. Always input "0" to the eighth
R/W bit because the ML9480 is a write-only LSI.
The eight bits next to the slave address is a control byte. The first one bit is CO: consecutive command setting
bit.
When CO = "0": Means the last control byte.
When CO = "1": Means the control bytes are successively input.
Data write method
• Serial interface
The data is written to the address set by the data write setting command (F3).
For the Serial interface, the data is written in units of 40 bits.
Written from D40 to SEG1, D39 to SEG2, ... , D2 to SEG39, and D1 to SEG40.
MSB
1
Segment Output
32 33 34
LSB
40
2
3
4
35
36
37
38
39
COM1
COM2
COM3
COM4
D40 D39 D38 D37
D40 D39 D38 D37
D40 D39 D38 D37
D40 D39 D38 D37
D9 D8 D7 D6 D5 D4 D3 D2 D1
D9 D8 D7 D6 D5 D4 D3 D2 D1
D9 D8 D7 D6 D5 D4 D3 D2 D1
D9 D8 D7 D6 D5 D4 D3 D2 D1
• I2C interface (When MODE pin is "L")
The data is written to the address set by the slave address.
For the I2C interface (When MODE pin is "L"), the data is written to the specified address starting with the
LSB side in units of 8 bits.
(The data is written in the order from SEG33-40, SEG25-SEG32, SEG17-SEG24, SEG9-SEG16, and
SEG1-SEG8.)
LSB
1
Segment Output
32 33 34
MSB
40
2
3
4
35
36
37
38
39
COM1
COM2
COM3
COM4
D1 D2 D3 D4
D1 D2 D3 D4
D1 D2 D3 D4
D1 D2 D3 D4
D8 D1 D2 D3 D4 D5 D6 D7 D8
D8 D1 D2 D3 D4 D5 D6 D7 D8
D8 D1 D2 D3 D4 D5 D6 D7 D8
D8 D1 D2 D3 D4 D5 D6 D7 D8
21/37
FEDL9480-01
ML9480
• I2C interface (When MODE pin is "H")
The data is written to the address set by the display RAM address.
For the I2C interface (When MODE pin is "H"), the data is written to the specified address starting with the
LSB side in units of 8 bits.
■ Static
LSB
1
Segment Output
MSB
40
2
3
4
5
6
7
8
9
37
38
39
COM1
COM2
COM3
COM4
D8 D7 D6 D5 D4 D3 D2 D1 D8
D4 D3 D2 D1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
■ 1/2Duty
LSB
1
Segment Output
MSB
40
2
3
4
5
6
7
8
9
37
38
39
COM1
COM2
COM3
COM4
D8 D6 D4 D2 D8 D6 D4 D2 D8
D7 D5 D3 D1 D7 D5 D3 D1 D7
D8 D6 D4 D2
D7 D5 D3 D1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
■ 1/3Duty
LSB
1
Segment Output
MSB
40
2
3
4
5
6
7
8
9
37
38
39
COM1
COM2
COM3
COM4
D8 D5 D2 D8 D5 D2 D8 D5 D2
D7 D4 D1 D7 D4 D1 D7 D4 D1
D2 D8 D5 D2
D1 D7 D4 D1
D6 D3
x
x
D6 D3
x
x
D6 D3
x
x
x
x
D6 D3
x
x
x
x
x
x
x
x
x
x
■ 1/4Duty
LSB
1
Segment Output
MSB
40
2
3
4
5
6
7
8
9
37
38
39
COM1
COM2
COM3
COM4
D8 D4 D8 D4 D8 D4 D8 D4 D8
D7 D3 D7 D3 D7 D3 D7 D3 D7
D6 D2 D6 D2 D6 D2 D6 D2 D6
D5 D1 D5 D1 D5 D1 D5 D1 D5
D8 D4 D8 D4
D7 D3 D7 D3
D6 D2 D6 D2
D5 D1 D5 D1
22/37
FEDL9480-01
ML9480
• RAM writing in 1/3 duty drive mode (When I2C pin is "H" and MODE pin is "H")
■ 1/3Duty（Standard RAM filling）
LSB
1
a8
a7
a6
x
Segment Output
MSB
・・・
・・・
・・・
・・・
・・・
2
3
a2
a1
x
4
5
6
b2
b1
x
7
8
9
c2
c1
x
COM1
COM2
COM3
COM4
a5
a4
a3
x
ｂ8
ｂ7
ｂ6
x
b5
b4
b3
x
c8
c7
c6
x
c5
c4
c3
x
x
x
x
■ 1/3Duty（Entire RAM filling by rewriting）
LSB
Segment Output
7
MSB
1
2
3
4
5
6
8
9
COM1
COM2
COM3
COM4
a8
a7
a6
x
a5 a2/b8 b5 b2/c8 c5 c2/d8 d5 d2/e8
a4 a1/b7 b4 b1/c7 c4 c1/d7 d4 d1/e7
a3
x
b6
x
b3
x
c6
x
c3
x
d6
x
d3
x
e6
x
23/37
FEDL9480-01
ML9480
Common waveforms
(1) At static
VLCD
COM1～4
GND
(2) At 1/2-duty
At 1/2-bias
VLCD
COM1
COM3
VLCD/2
GND
VLCD
COM2
COM4
VLCD/2
GND
At 1/3-bias
VLCD
COM1
COM3
2VLCD/3
VLCD/3
GND
VLCD
2VLCD/3
VLCD/3
GND
COM2
COM4
(3) At 1/3-duty
COM1
VLCD
2VLCD/3
VLCD/3
GND
VLCD
2VLCD/3
VLCD/3
GND
COM2
COM4
VLCD
2VLCD/3
VLCD/3
GND
COM3
(4) At 1/4-duty
COM1
VLCD
2VLCD/3
VLCD/3
GND
VLCD
2VLCD/3
VLCD/3
GND
COM2
COM3
COM4
VLCD
2VLCD/3
VLCD/3
GND
VLCD
2VLCD/3
VLCD/3
GND
24/37
FEDL9480-01
ML9480
● Common and segment output waveforms
・At Static
S
E
G
1
S
E
G
2
S
E
G
3
Display example
COM1
ON
OFF
VLCD
COM1
COM2
COM3
COM4
2VLCD/3
VLCD/3
GND
VLCD
2VLCD/3
VLCD/3
GND
SEG1
SEG2
SEG3
VLCD
2VLCD/3
VLCD/3
GND
VLCD
2VLCD/3
VLCD/3
GND
25/37
FEDL9480-01
ML9480
-
●
Common and segment output waveforms
・At 1/2 Duty、1/2bias
S
E
G
1
S
S
E
G
3
E
G
2
Display example
COM1
COM2
On
Off
VLCD
COM1
COM3
VLCD/2
GND
VLCD
COM2
COM4
VLCD/2
GND
VLCD
SEG1
SEG2
SEG3
VLCD/2
GND
VLCD
VLCD/2
GND
VLCD
VLCD/2
GND
26/37
FEDL9480-01
ML9480
Common and segment output waveforms
●
・At 1/2 Duty、1/3bias
S
S
E
G
2
S
E
G
3
E
G
Display example
1
COM1
COM2
On
Off
VLCD
2VLCD/3
VLCD/3
GND
COM1
COM3
VLCD
2VLCD/3
VLCD/3
GND
COM2
COM4
VLCD
2VLCD/3
VLCD/3
GND
SEG1
SEG2
SEG3
VLCD
2VLCD/3
VLCD/3
GND
VLCD
2VLCD/3
VLCD/3
GND
27/37
FEDL9480-01
ML9480
Common and segment output waveforms
At 1/3-duty
S
E
G
1
S
E
G
2
S
E
G
3
Display example
COM1
COM2
COM3
On
Off
VLCD
2VLCD/3
VLCD/3
COM1
GND
VLCD
2VLCD/3
VLCD/3
GND
COM2
COM4
VLCD
2VLCD/3
VLCD/3
GND
COM3
VLCD
2VLCD/3
VLCD/3
GND
SEG1
SEG2
SEG３
VLCD
2VLCD/3
VLCD/3
GND
VLCD
2VLCD/3
VLCD/3
GND
28/37
FEDL9480-01
ML9480
Common and segment output waveforms
At 1/4-duty
S
E
G
1
S
E
G
2
S
E
G
3
Display example
COM1
COM2
COM3
COM4
On
Off
VLCD
2VLCD/3
VLCD/3
GND
COM1
COM2
COM3
COM4
SEG1
SEG2
SEG3
VLCD
2VLCD/3
VLCD/3
GND
VLCD
2VLCD/3
VLCD/3
GND
VLCD
2VLCD/3
VLCD/3
GND
VLCD
2VLCD/3
VLCD/3
GND
VLCD
2VLCD/3
VLCD/3
GND
VLCD
2VLCD/3
VLCD/3
GND
29/37
FEDL9480-01
ML9480
POWER ON SEQUENCE
Start
VDD Power ON
or
VDD, VLCD Power ON at one time
VLCD Power ON
Clock Input
（when an external clock input mode）
Any Command
POWER OFF SEQUENCE
Any State
Display OFF
Wait 30ms
VLCD Power OFF
or
VDD, VLCD Power OFF at one time
VDD Power OFF
30/37
FEDL9480-01
ML9480
EXAMPLE OF APPLICATION CIRCUIT
Cascade configuration 1
Serial interface
Internal CR oscillator circuit used
1/4Duty
RESETB pin + external capacitance connection to configure POC circuit
The common outputs of the slave chip output GND-level. So Com1 to Com4 set to open.
[External component]
Cp = 0.1 [µF] (bypass capacitor between power supplies)
Crst = 4.7 [µF] (capacitance for external POC circuit)
Liquid crystal panel 1/4Duty × 40 × n Segments
COM1
COM2
COM3
COM4
COM1
COM2
COM3
COM4
OPEN
5V
5V
5V
5V
VLCD
VDD
VLCD
VDD
ML9480
（Master)
ML9480
(Slave)
Cp Cp
Cp Cp
M/S
M/S
BIAS
OSCI/E
POCEB
Duty0
Duty1
I2C
SA1
SA0
A1
A0
BIAS
OSCI/E
POCEB
Duty0
Duty1
I2C
SA1
SA0
A1
A0
OSC1
OSC2
OSCR
CKO
OPEN
OSC1
OSC2
OSCR
CKO
OPEN
OPEN
OPEN
RESETB
RESETB
MODE
MODE
TEST1
Crst
Crst
TEST1
GND
GND
OPEN
OPEN
CPU
31/37
FEDL9480-01
ML9480
Cascade configuration 2
II2C interface
External Rf-based CR oscillator circuit used
1/4Duty
External RESETB signal input
The common outputs of the slave chip output GND-level. So Com1 to Com4 set to open.
[External component]
Cp = 0.1 [µF] (bypass capacitor between power supplies),
Rf = 470 [k] (external R, resistor for CR oscillator circuit),
Rup = Resistor for SDA data bus pull-up
Liquid crystal panelꢀ1/4Duty × 40 × n
COM1
COM2
COM3
COM4
COM1
COM2
COM3
COM4
OPEN
5V
5V
5V
5V
VLCD
VDD
VLCD
VDD
ML9480
（Master)
ML9480
(Slave)
Cp Cp
Cp Cp
M/S
M/S
BIAS
OSCI/E
POCEB
Duty0
Duty1
I2C
SA1
SA0
A1
A0
BIAS
OSCI/E
POCEB
Duty0
Duty1
I2C
SA1
SA0
A1
A0
Rf
OSC1
OSC2
OSCR
CKO
OSC1
OSC2
OSCR
CKO
OPEN
OPEN
OPEN
OPEN
RESETB
RESETB
MODE
MODE
TEST1
TEST1
GND
5V
Rup
GND
CPU
32/37
FEDL9480-01
ML9480
PAD CONFIGURATION
Pad layout (pattern face)
Chip size
: 3.30 mm × 0.90mm
: 400 m ± 20 m
: 50 m
Chip thickness
Minimum bump pitch
Bump height
: 15 m ±3 m
39
94
B
Y
X
(0,0)
A
1
38
Bump and alignment mark dimensions (pattern face)
PAD No.138
PAD No.3994
: 32 m x 80 m
: 30 m x 84 m
Alignment marks A and B : See below
[Mark A]
[Mark B]
Coordinate position
Coordinate position
30m
47m
30m
30m
55m
30m
30m
30m
47m
55m
Aluminum (top metal) Passivation
Passivation
Aluminum (top metal)
Alignment Mark
Mark A
X-coordinate (m)
Y-coordinate (m)
1506
-190
-1539
309
Mark B
33/37
FEDL9480-01
ML9480
Pad center coordinates
Pad
X-coordinate Y-coordinate
Pad
number
X-coordinate Y-coordinate
Pad name
number
Pad name
(m)
(m)
(m)
(m)
DUMMY
GNDO
Duty1
Duty0
A0
-1430
-308
COM2
COM3
COM4
DUMMY
SEG1
1325
309
1
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
-1350
-1270
-1190
-1110
-1030
-950
-870
-790
-710
-630
-550
-470
-390
-310
-230
-150
-70
-308
-308
-308
-308
-308
-308
-308
-308
-308
-308
-308
-308
-308
-308
-308
-308
-308
-308
-308
-308
-308
-308
-308
-308
-308
-308
-308
-308
-308
-308
-308
-308
-308
-308
-308
-308
-308
309
1275
1225
1175
1125
1075
1025
975
925
875
825
775
725
675
625
575
525
475
425
375
325
275
225
175
125
75
309
309
309
309
309
309
309
309
309
309
309
309
309
309
309
309
309
309
309
309
309
309
309
309
309
309
309
309
309
309
309
309
309
309
309
309
309
309
309
2
3
4
5
A1
SEG2
6
SA0
SEG3
7
SA1
SEG4
8
VDDO
SDAACK
DATA(SDA)
CLOCK(SCL)
LOAD
VDD
SEG5
9
SEG6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
COM1
COM2
COM3
COM4
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
VDD
VDD
GND
GND
GND
10
VLCD
VLCD
VLCD
RESETB
OSC1
OSC2
OSCR
CKO
90
170
250
330
410
490
570
650
25
SYNCB
VDDO
I2C
730
-25
810
-75
890
-125
-175
-225
-275
-325
-375
-425
-475
-525
-575
-625
MODE
M/S
970
1050
1130
1210
1290
1370
1450
1530
1425
1375
POCEB
OSCI/E
BIAS
TEST1
GNDO
DUMMY
DUMMY
COM1
309
34/37
FEDL9480-01
ML9480
Pad
number
81
X-coordinate Y-coordinate
X-coordinate Y-coordinate
Pad name
Pad number Pad name
(m)
-675
(m)
309
309
309
309
309
309
309
309
309
309
309
309
309
309
(m)
(m)
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
DUMMY
COM4
82
83
84
85
86
87
88
89
90
91
92
93
94
-725
-775
-825
-875
-925
-975
-1025
-1075
-1125
-1175
-1225
-1275
-1325
COM3
COM2
COM1
DUMMY
35/37
FEDL9480-01
ML9480
REVISION HISTORY
Page
Previous
Document No.
FEDL9480-01
Issue Date
Description
New
Edition
Edition
Oct .1,2012
–
–
Final edition 1 issued
36/37
FEDL9480-01
ML9480
NOTICE
No copying or reproduction of this document, in part or in whole, is permitted without the consent of
LAPIS Semiconductor Co., Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing LAPIS Semiconductor's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be
obtained from LAPIS Semiconductor upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the
standard usage and operations of the Products. The peripheral conditions must be taken into account when
designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document. However,
should you incur any damage arising from any inaccuracy or misprint of such information, LAPIS
Semiconductor shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and examples
of application circuits for the Products. LAPIS Semiconductor does not grant you, explicitly or implicitly,
any license to use or exercise intellectual property or other rights held by LAPIS Semiconductor and other
parties. LAPIS Semiconductor shall bear no responsibility whatsoever for any dispute arising from the use
of such technical information.
The Products specified in this document are intended to be used with general-use electronic equipment or
devices (such as audio visual equipment, office-automation equipment, communication devices, electronic
appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While LAPIS Semiconductor always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard against the
possibility of physical injury, fire or any other damage caused in the event of the failure of any Product,
such as derating, redundancy, fire control and fail-safe designs. LAPIS Semiconductor shall bear no
responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance
with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or system which
requires an extremely high level of reliability the failure or malfunction of which may result in a direct
threat to human life or create a risk of human injury (such as a medical instrument, transportation
equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). LAPIS
Semiconductor shall bear no responsibility in any way for use of any of the Products for the above special
purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales
representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may be controlled
under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit
under the Law.
Copyright 2012 LAPIS Semiconductor Co., Ltd.
37/37
相关型号：
ML9484
ML9484由50位移位寄存器、200位数据锁存器、50组LCD驱动器、以及公共信号生成电路组成。静态显示时可直接驱动多达50段、1/2Duty显示时可直接驱动多达100段、1/3Duty显示时可直接驱动多达150段、1/4Duty显示时可直接驱动多达200段的LCD。
ROHM
©2020 ICPDF网 联系我们和版权申明