ML7631_技术文档

FEDL7631-02

Published：Nov. 18, 2019

ML7631

13.56MHz wireless charging Tx LSI

 Overview

The ML7631 is a wireless charging Tx LSI using 13.56MHz carrier frequency, which enables to feed 200mW

wirelessly to an Rx device using the ML7630. The ML7631 controls wireless charging and data communication

with the ML7630.

ML7631 is equipped with function to detect the illegal situation such as disappearance of the Rx device. This is

an ideal solution for small rechargeable devices such as headset, ear-pads and wearables.

 Features

 Power transmission control

−

Power transmission circuit embedded

Abnormaly detection by software control and hardware control(voltage and current monitoring)

 Communication control

−

Command generation function for ML7630 included

Communication speed: 212kbps (13.56MHz/64)

1kbyte data flash for storing some data contents

 Host interface(I²C slave)

−

Normal mode(100kbit/s), Fast mode(400kbit/s) available

Each internal controller and external HOST microcontroller can access register function

 General Port(PORT)

−

Input/Output port×11ch

 Reset

−

Reset by RESET_N port

Power on reset by magnetic field detection

Reset by WDT overflow

 Clock

−

Low speed clock : Built-in RC oscillation (32.768kHz) for internal timer

High speed clock : Crystal osillation(27.12MHz) 6.78MHz is used inside

 Package

WQFN 32 pin (P-WQFN32-0505-0.50)

−

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FEDL7631-02

ML7631

 Functional block structure

TEST0

P02

FLASH

Data : 1KByte

TEST1_N

VPP

Other

Circuit

P03

P05

P10

Control Logic

TEST_OUT

P16

RESET_N

P15

P06

P07

XI

OSC

27.12MHz

System Clock

XO

SRAM

256Byte

Communication

Analog

RX0

RX1

TX0

TX1

Communication

Logic

&

P01 / SCL_S

P00 / SDA_S

P04 / INT_S

Power Transmit

Host I/F

(I²C Slave)

LDO1V8

LDO1V5

WDT

Regulator

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 Pin assignment (Top view)

25

26

27

28

29

30

31

32

16

15

14

13

12

11

10

9

XO

LDO1V5

LDO1V8

VSS3

VPP

VDD_IO

VSS0

VSS1

Exposed Pad *

VSS4

TEST_OUT

RX0

P01 / SCL_S

P04 / INT_S

P10

RX1

P_EXT

* Solder the exposed pad onto the PCB

3/12

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 Pin description

● Power ∙ GND ∙ reference voltage pins

In reset

(*1)

I/O

(*2)

Active

Level

Process in

not use

PIN No.

Pin name

Description

14

13

20

28

29

15

26

27

32

21

VSS0

VSS1

VSS2

−

Ground

−

VSS3

VSS4

VDD_IO

LDO1V5

LDO1V8

P_EXT

VDD_TX_5V

−

H(A)

−

OA

−

Logic IO voltage

−

Core 1.5V voltage output

ADC 1.8V voltage output

External voltage (5V)

TX voltage (5V)

−

● Analog signal pins

In reset

(*1)

I/O

(*2)

IA

OA

Supply

Power

Active

Level

−

Process in

not use

PIN No.

Pin name

Description

RF Data receiving

RF Data transmitting

30

31

22

23

RX0

RX1

TX0

TX1

−

Z

−

VDD_TX_

5V

● Clock pins

In reset

(*1)

I/O

(*2)

I

Supply

Power

Active

Level

−

Process in

not use

PIN No.

Pin name

Description

24

25

XI

XO

I

O

LDO1V5

27.12MHz oscillation pin

−

O

−

● Reset pin

In reset

(*1)

PU

I/O

(*2)

I

Supply

Power

Active

Level

L

Process in

not use

PIN No.

6

Pin name

RESET_N

Description

Reset input

VDD_IO

Open

● General pins

Since the settings differ depending on the FW Ver., refer to the application note for details.

In reset

(*1)

I/O

(*2)

Supply

Power

Active

Level

PIN No.

Pin name

Description

Input/Output port

P00 /

SDA_S

P01 /

SCL_S

P02

17

Z

I/O

VDD_IO

−

HostIF(I²C slave) Data

Input/Output port

HostIF(I²C slave) Clock

Input/Output port

HostIF INToutput

Input/Output port

11

3

4

Z

I/O

VDD_IO

−

P03

P04 /

INT_S

P05

P06

P07

P10

P15

P16

10

Z

I/O

VDD_IO

−

5

7

8

9

19

18

Z

I/O

I_DA/O

I/O

I_DA/O

I/O

VDD_IO

−

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● Test pins

In reset

(*1)

PD

PU

−

I/O

(*2)

I/O

I

IA

O

Supply

Power

Active

Level

H

L

−

Process in

PIN No.

Pin name

Description

not use

Open

2

1

16

12

TEST0

TEST1_N

VPP

VDD_IO

−

For test/For debugger

Power supply for Flash test

Test output port

TEST_OUT

L(A)

VDD_IO

(*1)

In reset state :

Pin state

L(O)

H(O)

L(A)

H(A)

PU

:

“L” level output

“H” level output

Analog “L” level output

Analog “H” level output

Pull-Up

definition

in reset state

PD

Z

Pull-Down

Floating state

(*2)

I/O : For I/O definition, using under abbreviation

I/O definition

IA

OA

I

I/O

I_DA/O

O

:

Analog input

Analog output

Digital input

Bi-directional pin

Bi-directional pin, Input are digital and analog shared

Digital output

5/12

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 Electrical characteristics

● Absolue maximum ratings

Item

Power voltage (Digital IO)

Regulator input voltage

Tx power voltage

Core & crystal power voltage

Analog power voltage

Input voltage

Symbol

VDD_IO

P_EXT

Condition

Rating

Unit

V

mA

V

Ta=25°C

-0.3 to +6.5

-0.3 to +2.0

-0.3 to +6.5

VDD_TX_5V Ta=25°C

LDO1V5

LDO1V8

VDIN

Ta=25°C

Ta=25°C, Digital port

Ta=25°C, TX0/TX1

Ta=25°C, RX0/RX1

Ta=25°C, Digital port

Ta=25°C

-0.3 to V_{DD_IO}+0.3

6.5

12

Input current

Output voltage

Digital output current

Power dissipation

Storage temperature

Ii

-10 to +10

-0.3 to VDD_IO+0.3

-12 to +20

2

VDO

IDO

PD

Tstg

mA

W

°C

Ta=25°C

-55 to +150

● Recommended operating conditions

Item Symbol

Operating voltage

Condition

Min.

1.8

4.5

-40

Typ.

–

5.0

+25

Max.

5.5

+85

Unit

V

°C

VDD_IO

P_EXT

VDD_TX_5V Normal

Operating temperature

Ta1

Ta2

Normal

Power transmission

-10

+50

Typ

-0.05%

Typ

+0.05%

Crystal oscillator frequency

Crystal oscillator load capacitance*

f_XTL

27.12

MHz

NIHON DEMPA KOGYO

Co., Ltd.

NX2016SA(CL=6pF)

NIHON DEMPA KOGYO

Co., Ltd.

NX2016SA(CL=8pF)

KYOCERA Corporation

CX1210SB(CL=6pF)

KYOCERA Corporation

CX2016SB(CL=8pF)

TXC

C_DL

C_GL

Typ

-1%

Typ

+1%

8

pF

C_DL

C_GL

Typ

-1%

Typ

+1%

12

pF

C_DL

C_GL

C_DL

C_GL

Typ

-1%

Typ

-1%

Typ

+1%

Typ

8

pF

12

+1%

C_DL

C_GL

Typ

-1%

Typ

+1%

SMD SEAM SEALING

XTAL 2.0 × 1.6(CL=8pF)

12

pF

Typ

-10%

Typ

-10%

Typ

-10%

Typ

-10%

Typ

-10%

Typ

+10%

Typ

+10%

Typ

+10%

Typ

+10%

Typ

+10%

LDO1V5 outside Capacitor

P_EXT outside Capacitor

LDO1V8 outside Capacitor

VDD_IO outside Capacitor

VDD_TX_5V outside Capacitor

C_LDO1V5

C_PEXT

2.2

μF

C_LDO1V8

C_VDDIO

C_TX5V

0.47

0.1

2.2

*) The optimum capacitance value varies depending on the circuit board.

Please consult with the Crystal oscillation circuit manufacturer.

● Flash memory operating conditions

Item

Operating temperature (Ambience)

Operating voltage

Symbo

Condition

Range

Unit

°C

T_OP

Write/erase

–

-40 to +85

2.7 to 5.5

10,000

P_EXT

V

Write time

times

KB

ms

–

C_EPD

Erase unit

–

Sector erase

–

1

Erase time (Maximum)

Write time

100

1 word (2 byte)

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● Power transmission charactaristics

(VDD_IO=1.8 to 5.5V, VDD_TX_5V=4.5 to 5.5V, VSS=0V, Ta=-40 to +85°C)

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

TX0/TX1 output frequency

F_TX

–

13.56

–

MHz

● Oscillation characteristic

(VDD_IO=1.8 to 5.5V, P_EXT=4.5 to 5.5V, VSS=0V)

Item

Symbol

f_LCR

Condition

Min.

Typ.

Max.

Unit

Low speed embedded RC

oscillator frequency ^*1

*1 : 1024 cycle average

–

-5%

32.768

+5%

kHz

● Reset characteristics

(VDD_IO=1.8 to 5.5V, P_EXT=4.5 to 5.5V, VSS=0V, Ta=-40 to +85°C)

Item

Symbol

P_RST

Condition

Min.

Typ.

Max.

Unit

RESET_N pulse width

–

200

–

μs

RESET_N noise removal

Pulse width

P_NRST

–

0.3

μs

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ML7631

● AC characteristics (I²C bus interface: Standard mode 100 kHz)

(VDD_IO =1.8 to 5.5V, P_EXT=4.5 to 5.5V, VSS=0V, Ta=-40 to +85°C)

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

SCL_S clock frequency

f_SCL

–

100

kHz

SCL_S hold time

(start/repeated start condition)

t_HD:STA

4.0

–

μs

SCL_S "L" level time

SCL_S "H" level time

t_LOW

t_HIGH

–

4.7

4.0

–

μs

SCL_S setup time

(repeated start condition)

t_SU:STA

–

4.7

–

μs

SDA_S hold time

SDA_S setup time

t_HD:DAT

t_SU:DAT

t_SU:STO

t_BUF

–

0

–

μs

0.25

SDA_S setup time

(P: Stop condition)

–

4.0

4.7

–

μs

Bus free time

● AC characteristics (I²C bus interface: Fast mode 400 kHz)

(VDD_IO =1.8 to 5.5V, P_EXT=4.5 to 5.5V, VSS=0V, Ta=-40 to +85°C)

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

SCL_S clock frequency

f_SCL

–

400

kHz

SCL_S hold time

(start/repeated start condition)

t_HD:STA

0.6

–

μs

SCL_S "L" level time

SCL_S "H" level time

t_LOW

t_HIGH

–

1.3

0.6

–

μs

SCL_S setup time

(repeated start condition)

t_SU:STA

–

0.6

–

μs

SDA_S hold time

SDA_S setup time

t_HD:DAT

t_SU:DAT

t_SU:STO

t_BUF

–

0

–

μs

0.1

SDA_S setup time

(P: Stop condition)

–

0.6

1.3

–

μs

Bus free time

Start

condition

Repeated START

condition

Stop

condition

SDA_S

SCL_S

t_BUF

t_SU:STO

t_HD:STA

t_LOWt_HIGH

t_SU:STA

t

t_SU:DATt_HD:DAT

When connecting the I2C slave to the I2C bus common to other devices, insert a multiplexer or level shifter between

the I2C bus and ML7631.

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ML7631

● IO characteristics

(Unless otherwise specified, VDD_IO=1.8 to 5.5V, P_EXT=4.5 to 5.5V, VSS=0V, Ta=-40 to +85°C)

Item

Symbol

Condition

Min.

VDD_IO

-0.5

Typ.

Max.

Unit

VOH1

IOH=-1.0mA

–

V

Output Voltage 1

(P00-P07, P10, P15, P16)

VOL1

VOL2

IOL=+0.5mA

–

0.4

0.6

0.4

V

2.7V≤VDD_IO≤5.5V

IOL=+5.0mA

Output Voltage 2

(P00-P07, P10, P15, P16)

(LED pin)

IOL=+2.0mA

Output Voltage 3

(SCL_S,SDA_S)

(I²C pin)

Output Voltage 4

(SCL_S,SDA_S)

(I²C mode selected)

IOL3= +3mA (I²Cspec)

(VDD_IO ≥2V)

VOL3

VOL4

–

0.4

V

IOL4= +2mA (I²Cspec)

(VDD_IO <2V)

VDD_IO

×0.2

VOH=VDD_IO

(at high impedance)

VOL=VSS

(at high impedance)

IOOH1

IOOL1

Output Leakage 1

(P00-P07, P10, P15, P16,

SCL_S, SDA_S)

–

1

A

-1

–

IIH1

IIL1

IIH2

IIL2

IIH3

IIL3

VIH1=VDD_IO

–

-900

20

–

-300

300

–

1

A

Input Current 1

(RESET_N, TEST1_N)

VIL1=VSS

-20

900

–

VIH2=VDD_IO

Input Current 2

(TEST0)

VIL2=VSS

-1

VIH3=VDD_IO (In pull down)

VIL3=VSS (In pull up)

1

15

200

-1

-200

-15

Input Current 3

(P00-P07, P10, P15, P16)

VIH3=VDD_IO

(at high impedance)

VIL3=VSS

(at high impedance)

IIH3Z

IIL3Z

–

1

A

-1

–

0.7×

VDD_IO

VIH1

VIL1

–

VDD_IO

V

Input Voltage 1

(RESET_N, TEST0, TEST1_N,

P00-P07, P10, P15, P16)

0.3×

VDD_IO

0

Input pin Capacitance

f=10kHz

(RESET_N, TEST0, TEST1_N,

P00-P07, P10, P15, P16)

CIN

Vrms=50mV

Ta=25°C

–

10

–

pF

Typ. standard is at Ta=25°C, VDD_IO=3.0V

● Power supply current

(VDD_IO=1.8 to 5.5V, P_EXT=4.5 to 5.5V, VSS=0V, Ta=-40 to +85°C)

Item

Symbol

IDD1

Condition

Min.

Typ.

Max.

Unit

Power supply current

HALT*1

–

0.8

1.5

mA

CPU 6.78MHz operation

Peripherals stop

CPU 6.78MHz operation

Power transmission mode

(100Ω instead of antenna

between TX0-TX1) *2

IDD2

–

2.2

85

3.0

mA

IDD3

105

*1) CPU Stops. This status can be released by peripheral interrupt.

*2) This condition and power supply current depend on the antenna.

If load resistance is small, the power supply current increases.

It does not guarantee the current consumption when the system including the power receiving side is installed.

9/12

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ML7631

 Package dimensions

10/12

FEDL7631-02

ML7631

 Revision historys

Page

Document No.

Issue Date

Change contents

Previous Current

Edition

PEDL7631-01

FEDL7631-01

Oct. 25, 2016

Mar. 23, 2018

–

Preliminary edition 1

–

Final edition 1

Add HALT description

Revise IO-pin description

FEDL7631-02

Jan. 15, 2019























Nov. 18, 2019

Delet Unused block

Add Reset pin category

Rename Other pins to General pins

Added note for application note to general pin









Delete Sample Circuit

(Described in the application note because it

depends on the FW)





Change wording of I2C notice













Add the conditions for current consumption during

power transmission

Change notice

Change note about external crystal capacity

11/12

FEDL7631-02

ML7631

Notes

1) The information contained herein is subject to change without notice.

2) Although LAPIS Semiconductor is continuously working to improve product reliability and quality, semiconductors can

break down and malfunction due to various factors. Therefore, in order to prevent personal injury or fire arising from failure,

please take safety measures such as complying with the derating characteristics, implementing redundant and fire

prevention designs, and utilizing backups and fail-safe procedures. LAPIS Semiconductor shall have no responsibility for

any damages arising out of the use of our Products beyond the rating specified by LAPIS Semiconductor.

3) Examples of application circuits, circuit constants and any other information contained herein are provided only to illustrate

the standard usage and operations of the Products.The peripheral conditions must be taken into account when designing

circuits for mass production.

4) The technical information specified herein is intended only to show the typical functions of the Products and examples of

application circuits for the Products. No license, expressly or implied, is granted hereby under any intellectual property

rights or other rights of LAPIS Semiconductor or any third party with respect to the information contained in this

document; therefore LAPIS Semiconductor shall have no responsibility whatsoever for any dispute, concerning such rights

owned by third parties, arising out of the use of such technical information.

5) The Products are intended for use in general electronic equipment (i.e. AV/OA devices, communication, consumer systems,

gaming/entertainment sets) as well as the applications indicated in this document.

6) The Products specified in this document are not designed to be radiation tolerant.

7) For use of our Products in applications requiring a high degree of reliability (as exemplified below), please contact and

consult with a LAPIS Semiconductor representative: transportation equipment (i.e. cars, ships, trains), primary

communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and

power transmission systems.

8) Do not use our Products in applications requiring extremely high reliability, such as aerospace equipment, nuclear power

control systems, and submarine repeaters.

9) LAPIS Semiconductor shall have no responsibility for any damages or injury arising from non-compliance with the

recommended usage conditions and specifications contained herein.

10) LAPIS Semiconductor has used reasonable care to ensure the accuracy of the information contained in this document.

However, LAPIS Semiconductor does not warrant that such information is error-free and LAPIS Semiconductor shall have

no responsibility for any damages arising from any inaccuracy or misprint of such information.

11) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive.

For more details, including RoHS compatibility, please contact a ROHM sales office. LAPIS Semiconductor shall have no

responsibility for any damages or losses resulting non-compliance with any applicable laws or regulations.

12) When providing our Products and technologies contained in this document to other countries, you must abide by the

procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US

Export Administration Regulations and the Foreign Exchange and Foreign Trade Act.

13) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS Semiconductor.

2-4-8 Shinyokohama, Kouhoku-ku,

Yokohama 222-8575, Japan

http://www.lapis-semi.com/en/

12/12


型号：	ML7631
厂家：	ROHM
描述：
文件：	总13页 (文件大小：520K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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