ML7661_技术文档

FEDL-7661-01

Issue Date: Oct. 5, 2021

ML7661

13.56MHz wireless charging Tx LSI

1. Overview

ML7661 is a 13.56MHz wireless power transmission device. ML7661 realizes a wireless power supply system by

combining with the power receiving device ML7660, and can output 1W for power transmission.

The ML7661 has a communication command generation function for communicating with the power receiving device

ML7660, an external transistor control function for supplying 1W, a function for variably controlling the transmission

amount to optimize the transmission power, and a function to detect abnormalities when the ML7660 is attached/detached

or power is transmitted. All of these functions are included in the 40-pin WQFN package(6.0 mm square), and the ML7661

is the best LSI for wireless power supply of small devices.In addition, the operating voltage is 5V, and it can be driven

from a USB power source such as a mobile battery.Furthermore, ML7661 is equipped with a host interface (SPI / I²C slave)

function and a serial interface (SPI / I²C master, UART) function, and it is possible to update configuration data from an

external MCU and control various sensors.

2. Features

⚫

Charging control

― Built-in 13.56MHz power transmission control circuit

1W power transmission transistor control output

― Abnormaly detection by software and hardware control

NFC communication control

― Equipped with a command generation function for communication with ML7660

― Communication speed: 212kbps, 424kbps

― 2Kbyte data flash for storing user data

Host interface

― 1ch Serial interface (Slave), and selectable from SPI or I²C

― Register function accessible from the host MCU

― Built-in 512byte FIFO

Serial interface

― 1ch SPI interface(Master)

― 1ch I²C interface(Master)

― 1ch UART interface (2-wire, Full-duplex communication mode)

⚫

General Port(PORT)

― Input/Output×13ch

Successive approximation type A/D converter (SA-ADC)

― Resolution 10bit

Reset

― Reset by RESET_N port

― Power on reset

― Reset by WDT overflow

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ML7661

⚫

Clock

― Low speed clock

Built-in RC oscillation(32.768kHz)

― High speed clock

Crystal oscillator (27.12MHz)

⚫

Package

― WQFN40pin(P-WQFN40-0606-0.50-63)

CPU

― 16-bit RISC CPU（CPU：nX-U16/100）

― Built-in On-chip debug function

― Minimum instruction execution time



147.5ns（@6.78MHz system clock）

⚫

Internal memory

― Memory size

Flash*

SRAM

6K byte（Work RAM）

Other RAM

256 byte（For NFC）

Program：32K byte

Data：2K byte

1K byte(For debugger trace function) 512 byte (For Host interface)

*: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.

SuperFlash® is a registered trademark of Silicon Storage Technology, Inc.

⚫

Interrupt controller (INTC)

― 1 non-maskable interrupt source (Internal source: WDT)

― 26 maskable interrupt sources(Internal source: 18, External source: 8）

― Software interrupt(SWI): Max. 64 sources

― Selectable edge and sampling for external interrupt and comparator

― Four step unterrupt levels

⚫

Timer

― 8bit×8ch (16-bit configuration is possible using 2ch)

― Built-in Repeat mode, One shot mode is available

― Timer start/stop function by software

Watchdog timer(WDT)

― Non-maskable interrupt and Reset

1^stoverflow: generate interrupt, 2^ndoverflow: generate reset or host notification

― Free-run

― Overflow period: 4 selectable(125ms, 500ms, 2s, 8s) at LSCLK=32.768kHz

― Stop function

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⚫

I²C bus interface (I²C Master)

― Normal mode (100kbit/s), Fast mode (400kbit/s) available

SPI interface (SPI Master)

― Selectable from MSB/LSB first

― Selectable from 8-bit length or 16-bit length

― Selectable clock phase and polarity

⚫

UART

― Full-duplex communication mode

― Communication speed: 4800 to 115200bps

― Programable interface (Data length, Parity and Stop bit can be selected)

Power management

― Clock division function

System clock supports 6.78MHz, 3.39MHz, 1.7MHz, 848kHz, 424kHz, 212kHz and 106kHz

― Clock stop function

HALT mode to stop only CPU

HALT-H mode to stop CPU and high speed clock

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ML7661

3. Functional block structure

TEST0

VPP

Test

Circuit

FLASH

Data : 2KByte

Control Logic

P00-P06/P10-P17

AOUT

RESET_N

XI

OSC

System Clock

SRAM

27.12MHz

XO

512Byte

RX0

SCL_S/SCLK_S

SDA_S/SDI_S

Communication

Analog

Communication

Logic

Host I/F

SDO_S

(I²C Slave)

SCS_S

(SPI Slave)

INT_S

Tr Driver

&

Control

NMOS0

AIN0

AIN1

AIN2

AIN4

SRAM

256Byte

G_NMOS

MCSEL0

10bit-ADC

6ch

AIN6

AIN7

LDO1V8

Regulator

Timer

8bit x 8ch

SDI_M

SDO_M

LDO1V5

SPI Master

SCLK_M

LDO1V8_OSC

I²C Master

SCL_M

SDA_M

WDT

TXD

RXD

UART

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4. Pin assignment

WQFN 40pin

TOP VIEW

20

19

18

17

16

15

14

13

12

11

31

32

33

34

35

36

37

38

39

40

LDO1V8_OSC

XI

P11 /AIN6

P13 /AIN7

VPP

XO

LDO1V5

LDO1V8

VSS4

VDD_IO

VSS1

Exposed Pad*

VSS0

RX0

MCSEL0

AIN1

AIN4

AIN2

VSS5

P_EXT

AIN0

*Solder the exposed pad onto the PCB

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5. Pin description

5.1 Power GND reference voltage pins

In reset

(*1)

I/O

(*2)

Active

Level

Process in

not use

PIN No.

Pin name

Description

15

16

29

36

12

17

34

35

31

40

26

VSS0

VSS1

Ground

－

(VSS0 to VSS5 are connected inside the LSI,

respectively)

－

VSS3

VSS4

VSS5

VDD_IO

LDO1V5

LDO1V8

LDO1V8_OSC

P_EXT

－

H(A)

－

OA

－

Logic IO voltage

－

Core 1.5V voltage output

ADC 1.8V voltage output

27.12MHz oscillator 1.8V voltage output

External Power supply (5V)

Logic IO voltage (for host communication)

Power supply for driver (5V)

ISO_V

－

27

VDD_TX_5V

－

*

Connect ISO_V to VDD_IO on the board

5.2 Analog signal pins

In reset

(*1)

I/O

(*2)

Active

Level

－

Process in

not use

Supply power

PIN No.

37

Pin name

RX0

Description

RF Data receiving

N transistor bias output for

charging

－

PD

Z

IA

－

VDD_TX_5V

30

G_NMOS

NMOS0

OA

－

VDD_TX_5V

28

N transistor driver for charging

5.3 Clock pins

In reset

(*1)

I/O

(*2)

Active

Level

Process in

not use

Supply power

PIN No.

Pin name

Description

LDO1V8_OSC

32

33

XI

I

－

27.12MHz oscillation pin

－

XO

O

5.4 Other Pins

In reset

(*1)

I/O

(*2)

Active

Level

Process in

not use

Supply power

VDD_IO

PIN No.

5

Pin name

Description

Reset input

RESET_N

PU

I

L

Open

/For debugger

Input/Output port

P00 / SDA_S /

SDI_S

25

24

Z

I/O

ISO_V

－

HostIF(I²C slave) data input/output

HostIF(SPI slave) data input

Input/Output port

Open

P01 / SCL_S /

SCLK_S

Z

I/O

－

HostIF(I²C slave) clock input

HostIF(SPI slave) clock input

Input/Output port

Open

7

6

P02 / SCL_M

P03 / SDA_M

P04 / INT_S

Z

I/O

ISO_V

－

Open

I²C master clock output

Input/Output port

I²C master data input/output

Input/Output port

23

HostIF INT output

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In reset

(*1)

I/O

(*2)

Active

Level

Process in

not use

Supply

power

PIN No.

22

Pin name

P05 / SDO_S

P06 /SCS_S

Description

Input/Output port

HostIF(SPI slave) data output

Input/Output port

Z

I/O

ISO_V

－

Open

21

－

Open

HostIF(SPI slave) select signal

11

13

39

38

AIN0

AIN1

AIN2

AIN4

Z

I_A

VDD_IO

P_EXT

－

AD input 0

AD input 1

AD input 2

AD input 4

Open

Input/Output port

UART data input

Input/Output port

/AD input 6

Input/Output port

SPI master data input

Input/Output port

/AD input 7

Input/Output port

SPI master clock output

Input/Output port

UART data output

Input/Output port

Analog monitor output

Input/Output port

SPI master data output

1

20

8

P10 / RXD

P11 / AIN6

PU

Z

I/O

I_DA/O

I/O

VDD_IO

ISO_V

－

Open

P12 / SDI_M

P13 / AIN7

Z

ISO_V

19

10

4

Z

I_DA/O

I/O

VDD_IO

ISO_V

P14 / SCLK_M

P15 / TXD

Z

I/O

VDD_IO

3

P16 / AOUT

Z

I/O_DA

9

P17 / SDO_M

MCSEL0

Z

I/O

O

ISO_V

－

Open

14

PU

VDD_IO

Matching capacitor select signal

5.5 Test pins

In reset

(*1)

I/O

(*2)

I/O

Active

Level

L

Process in

not use

Pull-Up

Open

Supply

power

PIN No.

Pin name

Description

2

18

TEST0

VPP

Z

－

VDD_IO

－

For debugger

Power supply for Flash test

IA

－

(*1)

In reset state :

Pin state

L(O)

H(O)

L(A)

H(A)

PU

“L” level output

“H” level output

Analog “L” level output

Analog “H” level output

Pull-Up

：

definition

in reset state

PD

Z

Pull-Down

Floating state

(*2)

I/O : For I/O definition, using under abbreviation

I/O definition

IA

：

Analog input

Analog output

Digital input

OA

I

I/O

I_DA/O

I/O_DA

O

Bi-directional pin

Bi-directional pin, Input are digital and analog shared

Bi-directional pin, Output are digital and analog shared

Digital output

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6. Electrical characteristics

6.1 Absolute maximum ratings

Item

Symbol

VDD_IO

ISO_V

P_EXT

VDD_TX_5V Ta=25°C

Condition

Rating

Unit

V

Power voltage（Digital IO）

Ta=25°C

-0.3 to +6.5

-0.3 to+6.5

-0.3 to +6.5

Regulator Input voltage

Power voltage (Power transmission)

Core power voltage /

LDO1V5

Ta=25°C

-0.3 to +2.0

V

Crystal oscillator voltage

Analog power voltage

27.12MHz oscillator power voltage

Input voltage

LDO1V8

LDO1V8_OSC

VDIN

Ta=25°C

-0.3 to +6.5

-0.3 to VDD_IO+0.3

-0.3 to +6.5

-10 to +10

V

mA

V

mA

W

Ta=25°C, Digital port

Ta=25°C, RX0

Ta=25°C, Digital port

Ta=25°C

Input current

Output voltage

Digital output current

Power dissipation

Storage temperature

Ii

VDO

IDO

PD

Tstg

-0.3 to VDD_IO+0.3

-12 to +20

Ta=25°C

－

1

-55 to +150

°C

6.2 Recommended operating conditions

Item

Operating voltage

Symbol

VDD_IO

Condition

－

Connect with VDD_IO on

the board

－

Min.

1.8

Typ.

－

Max.

5.5

Unit

V

ISO_V

1.8

－

5.5

V

P_EXT

4.5

5.0

5.5

V

VDD_TX_5V

－

Communication

Charging

4.5

-40

T.B.D.

Typ

5.0

+25

5.5

+85

T.B.D.

Typ

V

°C

Operating temperature

Ta1

Ta2

Crystal oscillator frequency

Crystal oscillator load capacitance

f_XTL

27.12

MHz

-0.05%

+0.05%

NIHON DEMPA KOGYO

Co., Ltd.

NX2016SA(CL=6pF)

NIHON DEMPA KOGYO

Co., Ltd.

NX2016SA(CL=8pF)

KYOCERA Corporation

CX1210SB(CL=6pF)

KYOCERA Corporation

CX2016DB(CL=8pF)

TXC

C_DL

C_GL

Typ

-1%

Typ

+1%

8

pF

C_DL

C_GL

Typ

-1%

Typ

+1%

12

pF

C_DL

C_GL

C_DL

C_GL

Typ

-1%

Typ

-1%

Typ

+1%

Typ

8

pF

12

+1%

C_DL

C_GL

Typ

-1%

Typ

+1%

SMD SEAM SEALING

XTAL 2.0 x 1.6(CL=8pF)

12

pF

Typ

-10%

Typ

-10%

Typ

-10%

Typ

-10%

Typ

-10%

Typ

+10%

Typ

+10%

Typ

+10%

Typ

+10%

Typ

+10%

Typ

LDO1V5 outside Capacitor

P_EXT outside Capacitor

LDO1V8 outside Capacitor

LDO1V8_OSC outside Capacitor

VDD_IO outside Capacitor

C_LDO1V5

C_PEXT

－

2.2

μF

C_LDO1V8

C_LDO1V8OSC

C_VDDIO

0.47

0.1

VDD_TX_5V outside Capacitor

AIN input voltage

C_TX5V

V_AIN

－

2.2

μF

-10%

0

+10%

1.8

AIN0,AIN6,AIN7

－

V

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6.3 Flash memory operating conditions

項目

Operating temperature (Ambience)

Operating voltage

記号

T_OP

条件

範囲

-20 to +60

4.5 to 5.5

100

単位

°C

write/erase

P_EXT

C_EPD

write/erase

V

Rewrite count

times

Program Flash

times

KB

B

Data Flash

10,000

1

Erase unit

–

Sector erase (Program Flash)

Sector erase (Data Flash)

Sector erase

128

Erase time (Maximum)

Write unit

ms

–

50

Program Flash

4 bytes

1 byte

–

Data Flash

6.4 Power transmission characteristics

(VDD_IO=1.8 to 5.5V, VDD_TX_5V=4.5 to 5.5V, VSS=0V, Ta=-40 to +85°C)

Item

Symbol

F_TX

Condition

Min.

－

Typ.

13.56

Max.

－

Unit

MHz

nmos0 output frequency

－

6.5 Ocsillation characteristics

(VDD_IO=1.8 to 5.5V, P_EXT=4.5 to 5.5V, VSS=0V)

Item

Symbol

f_LCR

Condition

Min.

Typ.

Max.

Unit

Low speed embedded RC

oscillator frequency ^*1

*1 : 1024 cycle average

－

-10%

32.768

+10%

kHz

6.6 SA-ADC characteristics

(VDD_IO=1.8 to 5.5V, P_EXT=4.5 to 5.5V, VSS=0V, Ta=-40 to +85°C)

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

Resolution

n

－

–

10

–

bit

Integral non-linearity error

Differential non-linearity error

Zero scale error

INL

DNL

ZSE

FSE

RI

LDO1V8=1.8V

-6

–

+6

–

LSB

Ω

LDO1V8=1.8V

－

–

Full scale error

－

–

Input impedance

－

6k

1.8

SA-ADC reference voltage

V_REF

LDO1V8=V_REF

–

V

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6.7 Reset characteristics

(VDD_IO=1.8 to 5.5V, P_EXT=4.5 to 5.5V, VSS=0V, Ta=-40 to +85°C)

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

RESET_N pulse width

P_RST

－

2

–

ms

RESET_N noise removal

Pulse width

P_NRST

–

0.3

μs

6.8 DAC characteristics

(VDD_IO=1.8 to 5.5V, P_EXT=4.5 to 5.5V, VSS=0V, Ta=-40 to +85°C)

Item

Symbol

V_DAC

Condition

Min.

Typ.

Max.

Unit

Output voltage range

dac_level=0 to 511

–

4

–

V

Output voltage step width

V_STEP

V_temp

－

–

10

1

mV

dB

Output volrage temperature

characteristics

Max-Min

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6.9 AC characteristics (I²C Bus Interface)

● Standard Mode 100kHz

(VDD_IO=1.8 to 5.5V, P_EXT=4.5 to 5.5V, VSS=0V, Ta=-40 to +85°C)

Item

Symbol

f_SCL

Condition

Min.

Typ.

Max.

Unit

SCL_S clock frequency

–

100

kHz

SCL_S hold time

(start/repeated start condition)

t_HD:STA

4.0

–

μs

SCL_S "L" level time

SCL_S "H" level time

t_LOW

t_HIGH

–

4.7

4.0

–

μs

SCL_S setup time

(repeated start condition)

t_SU:STA

–

4.7

–

μs

SDA_S hold time

SDA_S setup time

t_HD:DAT

t_SU:DAT

t_SU:STO

t_BUF

–

0

–

μs

0.25

SDA_S setup time

(P: Stop condition)

–

4.0

4.7

–

μs

Bus free time

● Fast Mode 400kHz

(VDD_IO=1.8 to 5.5V, P_EXT=4.5 to 5.5V, VSS=0V, Ta=-40 to +85°C)

Item

Symbol

f_SCL

Condition

Min.

Typ.

Max.

Unit

SCL_S clock frequency

–

400

kHz

SCL_S hold time

(start/repeated start condition)

t_HD:STA

0.6

–

μs

SCL_S "L" level time

SCL_S "H" level time

t_LOW

t_HIGH

–

1.3

0.6

–

μs

SCL_S setup time

(repeated start condition)

t_SU:STA

–

0.6

–

μs

SDA_S hold time

SDA_S setup time

t_HD:DAT

t_SU:DAT

t_SU:STO

t_BUF

–

0

–

μs

0.1

SDA_S setup time

(P: Stop condition)

–

0.6

1.3

–

μs

Bus free time

Start

condition

Repeated START

condition

Stop

condition

SDA_S

SCL_S

t_BUF

t_SU:STO

t_HD:STA

t_LOWt_HIGH

t_SU:STA

t

If powering off this LSI, it disables communications of other devices on the I²C bus.

t_SU:DATt_HD:DAT

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6.10 AC characteristics (Host Interface：SPI slave)

(VDD_IO/ISO_V=1.8 to 5.5V, P_EXT=2.0 to 5.5V, VSS=0V, Ta=-40 to +85°C)

Item

Symbol

t_SCYC

Condition

Min.

500

Typ.

Max.

Unit

ns

SCLK_S input cycle

–

SCLK_S input pulse width

t_SW

t_CS1

t_CS2

t_CH1

t_CH2

t_CW

t_SD

–

200

80

–

ns

SCS_S setup time

–

SCS_S hold time

–

SCS_S input pulse width

SDO_S output delay time

SDI_S input setup time

SDI_S input hold time

–

240

–

t_SS

80

t_SH

–

t_SCYC

t_SWt_SW

SCLK_S

t_CS1

t_SS

t_SH

t_CS

SDI_S

t_SD

SDO_S

t_CH2

SCS_S

t_CH1

t_CW

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6.11 AC characteristics (SPI master)

(VDD_IO/ISO_V=1.8 to 5.5V, P_EXT=2.0 to 5.5V, VSS=0V, Ta=-40 to +85°C)

Item

Symbol

t_SCYC

Condition

Min.

Typ.

SCLK^*1

Max.

Unit

s

SCLK_M output cycle

–

t_SCYC

×0.4

t_SCYC

×0.5

t_SCYC

×0.6

SCLK_M output pulse width

t_SW

–

s

SDO_M output delay time

SDI_M input setup time

SDI_M input hold time

t_SD

t_SS

t_SH

–

100

–

ns

100

60

–

*1 : The Period of the internal clock selected by the interface register

t_SCYC

t_SW

SCLK_M

SDO_M

SDI_M

t_SD

t_SS

t_SH

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6.12 IO characteristics

(Unless otherwise specified,VDD_IO=1.8 to 5.5V, P_EXT=4.5 to 5.5V, VSS=0V, Ta=-40 to +85°C)

Item

Output voltage 1

Symbol

Condition

Min.

V_{DD_IO}

-0.5

Typ.

Max.

Unit

VOH1

IOH=-1.0mA

–

V

(P00-P07, P10-P17)

VOL1

VOL2

IOL=+0.5mA

–

0.4

0.6

0.4

V

2.7V ≤ VDD_IO ≤ 5.5V

IOL=+5.0mA

Output voltage 2

(P00-P07, P10-P17)

(LED mode selected)

IOL=+2.0mA

Output voltage 3

(P00-P03)

IOL3= +3mA (I²C spec)

(VDD_IO ≥ 2V)

VOL3

VOL4

–

0.4

V

(I²C mode selected)

Output voltage 4

(P00-P03)

IOL4= +2mA (I²C spec)

(VDD_IO < 2V)

V_{DD_IO}

×0.2

(I²C mode selected)

VOH=VDD_IO

(at high impedance)

VOL=VSS

(at high impedance)

IOOH1

IOOL1

–

1

A

Output leakage 1

(P00-P07, P10-P17)

-1

–

IIH1

IIL1

IIH2

IIL2

IIH3

IIL3

VIH1=VDD_IO

–

-900

–

-300

–

1

-20

1

A

Input current 1

(RESET_N, TEST1_N)

VIL1=VSS

VIH2=VDD_IO

Input current 2

(TEST0)

VIL2=VSS

-200

1

-15

15

-1

VIH3=VDD_IO (In pull down)

VIL3=VSS (In pull down)

200

-1

-200

-15

Input current 3

(P00-P07, P10-P17)

VIH3=VDD_IO

(at high impedance)

VIL3=VSS

(at high impedance)

IIH3Z

IIL3Z

–

1

A

-1

–

0.75×

V_{DD_IO}

VIH1

VIL1

–

V_{DD_IO}

V

Input voltage 1

(RESET_N, TEST0, TEST1_N,

P00-P07, P10-P17)

0.3×

V_{DD_IO}

0

Input pin capacitance

f=10kHz

(RESET_N, TEST0, TEST1_N,

P00-P07, P10-P17)

CIN

Vrms=50mV

Ta=25°C

–

10

–

pF

Typ. standard is at Ta=25°C, VDD_IO=3.0V

6.13 Current consumption

(VDD_IO=1.8 to 5.5V, P_EXT=4.5 to 5.5V, VSS=0V, Ta=-40 to +85°C)

Item

Symbol

IDD1

Condition

Min.

Typ.

Max.

23.6

2.0

Unit

HALT-H

Current consumption

–

7

uA

High speed clock stop

IDD2

IDD3

HALT

1.3

2.2

mA

CPU 6.78MHz operation

Peripherals stop

3.0

CPU 6.78MHz operation

Communication*

CPU 6.78MHz operation

Power transmission*

IDD4

IDD5

–

15

20

–

mA

* Current consumption depends on the antenna design. The smaller the load resistance, the higher the current

consumption. External Transistor is not included.

14 / 18

FEDL-7661-01

ML7661

7. Package dimensions

WQFN40 pin

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.

Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin

number, package code and desired mounting conditions (reflow method, temperature and times).

15 / 18

FEDL-7661-01

ML7661

8. Sample circuit

ML7661

R1

L1

C8

C16

AIN2

VDD_TX_5V

5V Input

C15

P_EXT

C1

C11

L3

G_NMOS

NMOS0

R3

3.3V or 5V Input

C3

C10

VDD_IO

ISO_V

C12

ANT

C14

M1

R4

C9

AIN4

MCSEL0

RX0

VDD_IO

R2

L2

M3

C13

LDO1V5

AIN0

C5

C2

C4

C6

C7

C_DL

C_GL

LDO1V8_OSC

XI

LDO1V8

Value

XO

X1

Mandatory Parts List

Parts Name

Parts Number

Size

Manufacturer

Murata

ROHM

NDK,

Description

Inductor

L1

L2

L3

1µH

22000pF

240nH

8pF

15pF, over 100V

100pF, over 100V

100pF

120pF, over 100V

0.47µF

2.2µF

560pF

1000pF, DC cut

1000pF

2016

1005

2016

1005

1220

1005

2928

2924

LQM2MPN Series

GRM155 Series

LQM2MPN Series

GRM155 Series

LTR10 Series

MCR01 Series

RQ5E035BN

RK7002BM

NX2016SA,

Capacitor

C6, C7

C12

C11

C8, C16

C10

C2, C4

C1, C3, C5

C9, C13

C14

C15

Resistor

R1

47mΩ

1MΩ

51Ω

510Ω

R2

R3

R4

MOS Transistor

Crystal

M1

M3

X1

NMOS, 30V, 3.5A, 1W

NMOS, 60V, 0.25A

27.12MHz, 8pF

-

2016

-

Kyocera,

TXC

-

CX2016DB,

SMD SEAM SEALING

-

ANT

-

16 / 18

FEDL-7661-01

ML7661

Revision history

Page

Document No.

Issue Date

Change contents

Previous Current

Edition

FEDL7661-01

2021.10.5

First edition

−

17 / 18

FEDL-7661-01

ML7661

Notes

1) The information contained herein is subject to change without notice.

2) When using LAPIS Technology Products, refer to the latest product information (data sheets, user’s manuals, application

notes, etc.), and ensure that usage conditions (absolute maximum ratings, recommended operating conditions, etc.) are

within the ranges specified. LAPIS Technology disclaims any and all liability for any malfunctions, failure or accident

arising out of or in connection with the use of LAPIS Technology Products outside of such usage conditions specified

ranges, or without observing precautions. Even if it is used within such usage conditions specified ranges, semiconductors

can break down and malfunction due to various factors. Therefore, in order to prevent personal injury, fire or the other

damage from break down or malfunction of LAPIS Technology Products, please take safety at your own risk measures such

as complying with the derating characteristics, implementing redundant and fire prevention designs, and utilizing backups

and fail-safe procedures. You are responsible for evaluating the safety of the final products or systems manufactured by you.

3) Descriptions of circuits, software and other related information in this document are provided only to illustrate the standard

operation of semiconductor products and application examples. You are fully responsible for the incorporation or any other

use of the circuits, software, and information in the design of your product or system. And the peripheral conditions must be

taken into account when designing circuits for mass production. LAPIS Technology disclaims any and all liability for any

losses and damages incurred by you or third parties arising from the use of these circuits, software, and other related

information.

4) No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of LAPIS

Technology or any third party with respect to LAPIS Technology Products or the information contained in this document

(including but not limited to, the Product data, drawings, charts, programs, algorithms, and application examples、etc.).

Therefore LAPIS Technology shall have no responsibility whatsoever for any dispute, concerning such rights owned by

third parties, arising out of the use of such technical information.

5) The Products are intended for use in general electronic equipment (AV/OA devices, communication, consumer systems,

gaming/entertainment sets, etc.) as well as the applications indicated in this document. For use of our Products in

applications requiring a high degree of reliability (as exemplified below), please be sure to contact a LAPIS Technology

representative and must obtain written agreement: transportation equipment (cars, ships, trains, etc.), primary

communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and

power transmission systems, etc. LAPIS Technology disclaims any and all liability for any losses and damages incurred by

you or third parties arising by using the Product for purposes not intended by us. Do not use our Products in applications

requiring extremely high reliability, such as aerospace equipment, nuclear power control systems, and submarine repeaters,

etc.

6) The Products specified in this document are not designed to be radiation tolerant.

7) LAPIS Technology has used reasonable care to ensure the accuracy of the information contained in this document. However,

LAPIS Technology does not warrant that such information is error-free and LAPIS Technology shall have no responsibility

for any damages arising from any inaccuracy or misprint of such information.

8) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive.

LAPIS Technology shall have no responsibility for any damages or losses resulting non-compliance with any applicable

laws or regulations.

9) When providing our Products and technologies contained in this document to other countries, you must abide by the

procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US

Export Administration Regulations and the Foreign Exchange and Foreign Trade Act..

10) Please contact a ROHM sales office if you have any questions regarding the information contained in this document or

LAPIS Technology's Products.

11) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS Technology.

(Note) “LAPIS Technology” as used in this document means LAPIS Technology Co., Ltd.

2-4-8 Shinyokohama, Kouhoku-ku, Yokohama 222-8575, Japan

https://www.lapis-tech.com/en/

18 / 18


型号：	ML7661
厂家：	ROHM
描述：
文件：	总18页 (文件大小：1532K)
中文：	中文翻译
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ML7661 [ROHM]

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