ML5232 [ROHM]
过充检测两种过充检测输出;
| 型号： | ML5232 |
| 厂家： | 
ROHM |
| 描述： | 过充检测两种过充检测输出 |
| 文件： | 总17页 (文件大小：827K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEDL5232-02
December. 1, 2020
ML5232
Overvoltage Protector for 14-Series Cell Li-ion Rechargeable Batteries
◼ General Description
The ML5232 is an overvoltage protection IC for 14-series-cell Li-ion rechargeable battery packs. It asserts the
"L" level on the N-channel open drain alarm output and the "H" level on the CMOS alarm output if overvoltage
condition is detected on any single cell.
◼ Features
• 14-series-cell high-precision overvoltage detection
Individual cell monitoring performed
Fewer cells supported by shorting cell inputs.
Overvoltage detection threshold/accuracy : 4.35 V ±20 mV (max)
Overvoltage release threshold/accuracy
:
3.90 V ±30 mV (max)
• Integrated detection delay timer
Overvoltage detection delay
Overvoltage release delay
:
:
2 sec
0.2 sec
Overvoltage detection and release delays are reduced to 0.1 sec in the customer test mode
• Dual overvoltage alarm outputs
Both the OVN pin (N-channel open-drain) and the OV pin (CMOS) are available for overvoltage alarm
output
• Externally-controlled overvoltage alarm
OVN and OV alarms enabled by the CTRL pin input
• Variety of overvoltage thresholds and detection delays can be redefined and supplied as code products
• Low current consumption
Normal operation state
Overvoltage state
:
:
2.5 µA (typ), 8µA (max)
4.5 µA (typ), 15µA (max)
• Supply voltage
:
:
:
+7 V to +80 V
-40 °C to +105 °C
20-pin TSSOP
• Operating temperature
• Package
Note) This product is not intended for automotive use and for any equipment, device, or system that requires a
specific quality or high level of reliability (e.g., medical equipment, transportation equipment, aerospace
machinery, nuclear-reactor controller, fuel-controller, various safety devices). If you are not sure whether
your application corresponds to such special purposes, please contact your local ROHM sales
representative in advance.
1/17
FEDL5232-02
ML5232
◼ Block Diagram
VDD
Voltage
Regulator
VREG
OV
V14
V13
V12
V11
Clock
Generator
V10
Clock Stop
Detector
V9
V8
V7
V6
Control
Logic
&
Delay
Timer
OVN
Reference
Voltage
Generator
V5
V4
V3
V2
V1
CTRL
Cell Voltage
Detector
Cell Voltage
Monitor
GND
◼ Pin Configuration (Top View)
1
2
3
4
20
VDD
V14
V13
V12
VREG
19
18
17
16
OV
CTRL
OVN
GND
V11 5
6
V10
V9 7
V8
15 V1
14 V2
8
V3
V4
13
12
V7 9
V6 10
11 V5
2/17
FEDL5232-02
ML5232
◼ Pin Description
Pin No.
Pin name
I/O
Description
Power supply pin.
Configure an external CR noise filter.
1
VDD
—
2
3
V14
V13
V12
V11
V10
V9
I
I
Cell 14 positive input pin.
Cell 14 negative input and Cell 13 positive input pin.
Cell 13 negative input and Cell 12 positive input pin.
Cell 12 negative input and Cell 11 positive input pin.
Cell 11 negative input and Cell 10 positive input pin.
Cell 10 negative input and Cell 9 positive input pin.
Cell 9 negative input and Cell 8 positive input pin.
Cell 8 negative input and Cell 7 positive input pin.
Cell 7 negative input and Cell 6 positive input pin.
Cell 6 negative input and Cell 5 positive input pin.
Cell 5 negative input and Cell 4 positive input pin.
Cell 4 negative input and Cell 3 positive input pin.
Cell 3 negative input and Cell 2 positive input pin.
Cell 2 negative input and Cell 1 positive input pin.
Ground pin.
4
I
5
I
6
I
7
I
8
V8
I
9
V7
I
10
11
12
13
14
15
16
V6
I
V5
I
V4
I
V3
I
V2
I
V1
I
GND
—
High voltage N-channel open drain output for overvoltage alarm.
Hi-Z output in normal state and "L" level output in the overvoltage state.
High voltage CMOS input for controlling OVN and OV status.
Assert "L" level to emulate the overvoltage state.
17
OVN
O
18
CTRL
I
Tied to "H" level (VDD level) in the normal state.
Regular voltage CMOS output for overvoltage alarm, internally pulled down
with a 25 kΩ resistor. “L” level output in normal state and "H" level (VREG
level) output in the overvoltage state.
19
20
OV
O
O
Integrated 4.3 V regulator output.
Tied to GND through a 0.1 F or larger capacitor.
VREG
Do not supply power to external circuits.
3/17
FEDL5232-02
ML5232
◼ Absolute Maximum Ratings
GND= 0 V, Ta = 25 °C
Rating Unit
Item
Symbol
VDD
Conditions
Applied to VDD pin
Supply voltage
-0.3 to +86.5
-0.3 to VDD+0.6
-0.3 to +86.5
-0.3 to +86.5
-0.3 to VREG+0.3
-0.3 to +6.5
V
V
V
V
V
V
VIN1
Applied to V14 to V1 pins
Applied to CTRL pin
Applied to OVN pin
Applied to OV pin
Input voltage
VIN2
VOUT1
VOUT2
VOUT3
Output voltage
Applied to VREG pin
Power
dissipation
PD
—
1.0
W
Short-circuit
output current
Storage
Applied to OV, OVN, and VREG
pins
IOS
10
mA
°C
TSTG
—
-55 to +150
temperature
◼ Recommended Operating Conditions
GND= 0 V
Item
Symbol
VDD
Conditions
Applied to VDD pin
—
Range
7 to 80
Unit
V
Supply voltage
Operating temperature
TOP
-40 to +105
°C
◼ Electrical Characteristics
⚫ DC Characteristics
VDD=7 V to 80 V, GND=0 V, Ta=-40 to +105 °C
Item
Symbol
VIH
Conditions
—
Min.
0.8×VDD
0
Typ.
—
Max.
VDD
Unit
V
CTRL pin "H" input voltage
CTRL pin "L" input voltage
CTRL pin "H" input current
CTRL pin "L" input current
VIL
—
—
0.2×VDD
5
V
IIH
VIH = VDD
VIL = GND
Average current
during normal
operation
—
—
µA
µA
IIL
–5
—
—
Cell monitor pins V14 to V1
input current
IINVC
–0.1
0.1
3
µA
OVN pin
"L" output voltage
OVN pin
output leakage current
OV pin
"H" output voltage
OV pin
pull-down resistance
VOL
IOLK
VOH
RPD
IOL = 100 µA
VOUT= 0 V to 80 V
IOH = -100 µA
VOL=1V
—
–5
—
—
—
25
0.2
5
V
µA
V
VREG-0.2
10
VREG
40
kΩ
VDD=7V to 64V
With a 0.5mA or
less load current
VREG pin output voltage
VREG
3.8
4.3
4.8
V
4/17
FEDL5232-02
ML5232
⚫ Supply Current Characteristics
VDD= 7 V to 64 V, GND=0 V, Ta=-40 to +105 °C
Item
Symbol
IDD1
Conditions
No output load
Ta = -40 to 60°C
No output load
Min.
Typ.
Max.
Unit
—
2.5
6
µA
Current consumption not
in overvoltage state
IDD1T
IDD2
2.5
8
µA
Current consumption in
overvoltage state
No output load
—
4.5
15
µA
⚫ Detection Threshold Characteristics (Ta = 25 °C)
VDD=56 V, GND=0 V, Ta=+25 °C
Item
Symbol
VOV
Conditions
Min.
Typ.
4.35
Max.
4.37
Unit
V
Overvoltage threshold
Overvoltage release
threshold
—
4.33
VOVR
VCON
—
3.87
3.90
2.0
3.93
2.5
V
V
V14 pin activation
threshold
V14-to-V13 voltage
1.5
⚫ Detection Threshold Characteristics (Ta = 0 to 60 °C)
VDD=56 V, GND=0 V, Ta=0 to 60 °C
Item
Symbol
VOV
Conditions
Min.
Typ.
Max.
Unit
V
Overvoltage threshold
Overvoltage release
threshold
—
4.325
4.350
4.375
VOVR
—
3.85
3.90
3.95
V
Low VREG threshold
VREG recovery threshold
VUREG
VRREG
—
—
3.0
3.4
3.4
3.8
3.8
4.2
V
V
⚫ Detection Threshold Characteristics (Ta = 105 °C)
VDD=56 V, GND=0 V, Ta=105 °C
Item
Symbol
VOV
Conditions
Min.
4.30
Typ.
4.35
Max.
4.40
Unit
V
Overvoltage threshold
Overvoltage release
threshold
—
VOVR
—
3.8
3.9
4.0
V
5/17
FEDL5232-02
ML5232
⚫ Detection Delay Time Characteristics (Ta = 25 °C)
VDD=56 V, GND=0 V, Ta=+25 °C
Item
Symbol
tOV
Conditions
Min.
1.7
Typ.
Max.
Unit
Overvoltage detection delay
time (Note)
—
2.0
2.4
sec
Overvoltage release delay
time (Note)
tOVR
tDET1
tDET2
—
0.16
320
80
0.2
400
100
0.24
480
120
sec
ms
ms
During normal state
During overvoltage
state
Cell voltage monitor cycle
Overvoltage detection delay
in quick test mode (Note)
Overvoltage release delay in
quick test mode (Note)
Quick test mode transition
time
tOVT
tOVRT
tTST
—
—
—
80
80
15
100
100
25
120
120
35
ms
ms
ms
(Note) The actual overvoltage detection and release delays may include the time lag incorporated by the cell
voltage monitor cycle.
⚫ Detection Delay Time Characteristics (Ta = 0 to 60 °C)
VDD=56 V, GND=0 V, Ta=0 to 60 °C
Item
Overvoltage detection delay
(Note)
Symbol
tOV
Conditions
Min.
1.6
Typ.
Max.
Unit
—
2.0
2.5
sec
Overvoltage release delay
(Note)
tOVR
tDET1
tDET2
—
0.14
300
75
0.2
400
100
0.26
500
125
sec
ms
ms
During normal state
During overvoltage
state
Cell voltage monitor cycle
(Note) The actual overvoltage detection and release delays may include the time lag incorporated by the cell
voltage monitor cycle.
6/17
FEDL5232-02
ML5232
◼ Timing Diagrams
⚫ During Battery Cell Connection
VDD
VDD
0V
VREG
VRREG
VREG
0V
tDET1
tDET1
tDET1 tDET1
V14-to-V13
voltage
Hi-Z
VCON
State
Normal state
Connecting battery cells
⚫ Overvoltage Detection and Release
VOV
Cell voltage
VOVR
tDET2
tDET2 tDET2
tDET2
tDET2
tDET2
tDET2
tDET2
tDET1 tDET1
tDET1 tDET1 tDET1
tDET1
tDET2 tDET2
tDET2
tDET2
tOVR
tOV
VREG
OV
0V
0V
Hi-Z
Hi-Z
OVN
0V
VDD
CTRL
State
Normal state
Overvoltage state
Normal state
7/17
FEDL5232-02
ML5232
⚫ Transition to and Return from Quick Test Mode
VDD
VDD•V14
0V
VREG
VRREG
VREG
0V
0V
tTST
VDD
CTRL
State
0V
Normal mode
Quick test mode
Normal mode
8/17
FEDL5232-02
ML5232
◼ Functional Description
⚫ Selecting Cell Count in the Battery Pack
If the serial cell count is fewer than 14, Vn pins from V1 to upward are not used. All unused pins should
be tied to GND.
⚫ OV and OVN state control with CTRL Pin
The “L” level input on the CTRL pin emulates the overvoltage state.
The following table shows the OV and OVN pin output states depending on the CTRL level.
CTRL pin input
OV pin output
OVN pin output
Remarks
"L" level
"H" level (4.3 V)
"L" level
(25 kΩ pull-down)
"L" level (0 V)
Overvoltage state
"H" level
"Hi-Z" level
Normal state
⚫ Handling VDD and V1 to V14 Pins
Since the VDD pin is power supply input, configure a noise elimination RC filter circuit in front of the
VDD input for stabilization.
The V1 to V14 pins are the monitor pins for individual cell voltages. Configure a noise elimination RC
filter circuit in front of each cell voltage input to prevent a false detection. All unused Vn pins should be
tied to GND in battery packs with fewer than 14 cells.
⚫ Handling VREG Pin
The VREG pin is the output pin of the internal regulator and also sources power to internal circuits.
Connect a 0.1 µF or larger capacitor between this pin and GND for stabilization. Do not source power to
external circuits since its current supply capacity is limited.
⚫ Unused Pins Treatment
Unused pins should be handled according to the following table.
Unused pins
Vn
Recommended treatment
Connected to GND
Connected to VDD
Open
CTRL
OV
OVN
Open
9/17
FEDL5232-02
ML5232
⚫ Overvoltage Detection Flow
Below is the operation flow chart at overvoltage detection.
Normal state (not in overvoltage state) is assumed initially.
Start
Battery cell monitor
(every 400 ms)
Individual battery cells are scanned from the
bottom to the top of cell stack every 400 ms.
No
Each cell voltage Vc is compared with the
VC > VOV
?
overvoltage detection threshold VOV
.
Yes
Overvoltage detection delay timer is started if
one or more battery cell voltage exceeds the
OV detection delay timer
started
overvoltage detection threshold VOV
.
Cell monitor cycle is reduced to 100 ms, if one or
more cell voltage exceeds the overvoltage
Battery cell monitor
(every 100 ms)
detection threshold VOV
.
No
OV-clear count is incremented if all battery cells
fall below the overvoltage detection threshold
VC > VOV
?
VOV
.
Yes
OV-clear count
increment
OV-clear count is reset if one or more battery cell
voltage exceeds the overvoltage detection
OV-clear count reset
threshold VOV
.
Overvoltage detection delay timer is updated.
OV detection delay timer update
No
OV-clear count = 2 ?
Overvoltage detection delay timer is reset if no
battery cells exceed the overvoltage detection
threshold VOV twice in a row.
Yes
No
OV detection delay
timer completed ?
Also, cell monitor cycle is extended to 400 ms.
OV detection delay
timer reset
Yes
The OV pin level is altered from "L" to "H", and
the OVN pin level is altered from "Hi-Z" to "L", if
overvoltage detection delay timer is completed.
OV pin output="H"
OVN pin output="L"
End
10/17
FEDL5232-02
ML5232
⚫ Overvoltage Release Flow
Below is the operation flow chart at overvoltage release.
Overvoltage state is assumed initially.
Start
Individual battery cells are scanned from the
bottom to the top of cell stack every 100 ms in
the overvoltage state.
Battery cell monitor
(every 100 ms)
No
Each cell voltage Vc is compared with the
VC < VOVR
?
overvoltage release threshold VOVR
.
Yes
Overvoltage release delay timer is started if all
individual cell voltages fall below the overvoltage
OV release delay timer
started
release threshold VOVR
.
Battery cell monitor
(every 100 ms)
No
Each cell voltage Vc is compared with the
overvoltage release threshold VOVR
VC < VOVR
?
.
Yes
OV release delay timer
update
Overvoltage release delay timer is updated.
Overvoltage release delay timer is reset if any
single cell voltage exceeds the overvoltage
OV release delay
timer reset
release threshold VOVR
.
No
OV release delay
timer completed ?
Yes
The OV pin level is altered from "H" to "L", and
the OVN pin level is altered from "L" to "Hi-Z", if
overvoltage release delay timer is completed.
Also, cell monitor cycle is extended to 400 ms.
OV pin output="L"
OVN pin output="Hi-Z"
End
11/17
FEDL5232-02
ML5232
⚫ V14-to-V13 Level Check
The voltage between the V14 and V13 pins is analyzed to avoid false overvoltage alarm during battery
cell assembly. Individual cell voltage monitoring is performed every 400 ms, when the VREG output
voltage exceeds the VREG recovery threshold VRREG
.
If the V14-to-V13 level is below the V14 activation threshold VCON, overvoltage detection is overridden,
ignoring all overvoltage conditions. When the V14-to-V13 level exceeds the V14 activation threshold
VCON, overvoltage alarm is triggered normally.
⚫ Reduced Cell Monitoring Cycle and Overvoltage Detection/Release Delays
The quick test mode is provided in which cell monitor cycle, overvoltage detection delay, and overvoltage
release delay are reduced to 100 ms (typ).
To enter the quick test mode, assert "L" on the CTRL pin while power is turned on and keep it for longer
than the quick test mode transition time tTST after the VREG output level has reached the VREG recovery
threshold VRREG. To exit the quick test mode, assert “H” on the CTRL pin and then pull it to "L".
The quick test mode can significantly reduce the production test time for the assembled modules.
VDD
VDD•V14
0V
VREG
VRREG
VREG
0V
0V
tTST
VDD
CTRL
State
0V
Normal mode
Quick test mode
Normal mode
⚫ Power-on/Power-off Sequence
Battery cells can be connected in any order, but the recommended connection sequence is to start with the
GND and VDD pins, followed by Vn pins from the bottom to the top of the cell stack.
If cell connection is not completed within overvoltage detection delay tOV, the overvoltage state may be
detected. To avoid such false detection, overvoltage detection is performed only after the V14-to-V13
level reaches the V14 active threshold VCON. Therefore the V14 pin should be connected in the last step of
pack assembly. Likewise, if the V14 pin stems from the VDD pin via a resistor, the highest battery cell
(the V14 and VDD pins) should be connected at the end.
There are no restrictions on the power supply voltage rise time at power-on, power-off sequence, and
power supply voltage fall time at power-off.
12/17
FEDL5232-02
ML5232
⚫ Overvoltage Detection and Release Threshold Options
Overvoltage detection and release thresholds can be defined according to the range and step specified in
the following table. Some combinations are unavailable due to conflicts. Contact us for details.
Detecting voltage
Overvoltage detection
threshold
Range
Step voltage
25 mV
4.0 V to 4.4 V
3.6 V to 4.0 V
Overvoltage release threshold
100 mV
⚫ Overvoltage Detection and Release Delay Options
Overvoltage detection and release delays can be selected from the values in the following table.
Configurable delay
Unit
Delay time
Overvoltage detection delay
Overvoltage release delay
1
2
3
4
5
1
sec
sec
0.2
0.4
0.6
0.8
13/17
FEDL5232-02
ML5232
◼ Application Circuit Example (8-cell system)
High-side
Nch-FET driver
RG
RG
RGS
Pack(+)
RUP
RVDD
1
2
3
4
5
6
20
19
18
17
VDD
V14
V13
V12
V11
V10
VREG
OV
CREG
RCELL
CVDD
CCELL
RDWN
CTRL
OVN
RO
GND 16
V1 15
V2 14
V3 13
Charge inhibit signal
RDWN
7 V9
V8
8
9 V7
V6
V4
V5
12
11
10
Pack(-)
■ Recommended Values for External Components
Recommended
Recommended
value
Component
Component
value
RVDD
CVDD
RCEL
CCEL
CREG
1 kΩ to 2 kΩ
0.1 µF or more
1 kΩ to 10 kΩ
0.1 µF or more
0.1 µF or more
RO
RUP ,RDWN
RGS
1 MΩ
100 kΩ
1 MΩ
RG
1 kΩ
(Note) The circuit examples and recommended values of external parts provided here do not guarantee the
device performance under all conditions. Full and detailed evaluations are suggested on your actual
applications before deciding your circuits and part constants.
14/17
FEDL5232-02
ML5232
◼ Package Dimensions
Caution regarding surface mount type packages
Surface mount type packages are susceptible to applied heat in solder reflow or moisture absorption during
storage. Please contact your local ROHM sales representative for the recommended mounting conditions (reflow
sequence, temperature and cycles) and storage environment.
15/17
FEDL5232-02
ML5232
◼ Revision History
Page
Before
Document No.
Issue date
Revision description
1st edition issued
After
revision
revision
FEDL5232-01
FEDL5232-02
Sep 6, 2016
Dec. 1, 2020
-
-
-
-
Changed Company name
Changed “Notes”
17
17
16/17
FEDL5232-02
ML5232
Notes
1) The information contained herein is subject to change without notice.
2) When using LAPIS Technology Products, refer to the latest product information (data sheets, user’s manuals,
application notes, etc.), and ensure that usage conditions (absolute maximum ratings, recommended operating
conditions, etc.) are within the ranges specified. LAPIS Technology disclaims any and all liability for any
malfunctions, failure or accident arising out of or in connection with the use of LAPIS Technology Products
outside of such usage conditions specified ranges, or without observing precautions. Even if it is used within such
usage conditions specified ranges, semiconductors can break down and malfunction due to various factors.
Therefore, in order to prevent personal injury, fire or the other damage from break down or malfunction of LAPIS
Technology Products, please take safety at your own risk measures such as complying with the derating
characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail-safe
procedures. You are responsible for evaluating the safety of the final products or systems manufactured by you.
3) Descriptions of circuits, software and other related information in this document are provided only to illustrate the
standard operation of semiconductor products and application examples. You are fully responsible for the
incorporation or any other use of the circuits, software, and information in the design of your product or system.
And the peripheral conditions must be taken into account when designing circuits for mass production. LAPIS
Technology disclaims any and all liability for any losses and damages incurred by you or third parties arising
from the use of these circuits, software, and other related information.
4) No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of LAPIS
Technology or any third party with respect to LAPIS Technology Products or the information contained in this
document (including but not limited to, the Product data, drawings, charts, programs, algorithms, and application
examples、etc.). Therefore LAPIS Technology shall have no responsibility whatsoever for any dispute,
concerning such rights owned by third parties, arising out of the use of such technical information.
5) The Products are intended for use in general electronic equipment (AV/OA devices, communication, consumer
systems, gaming/entertainment sets, etc.) as well as the applications indicated in this document. For use of our
Products in applications requiring a high degree of reliability (as exemplified below), please be sure to contact a
LAPIS Technology representative and must obtain written agreement: transportation equipment (cars, ships,
trains, etc.), primary communication equipment, traffic lights, fire/crime prevention, safety equipment, medical
systems, servers, solar cells, and power transmission systems, etc. LAPIS Technology disclaims any and all
liability for any losses and damages incurred by you or third parties arising by using the Product for purposes not
intended by us. Do not use our Products in applications requiring extremely high reliability, such as aerospace
equipment, nuclear power control systems, and submarine repeaters, etc.
6) The Products specified in this document are not designed to be radiation tolerant.
7) LAPIS Technology has used reasonable care to ensure the accuracy of the information contained in this document.
However, LAPIS Technology does not warrant that such information is error-free and LAPIS Technology shall
have no responsibility for any damages arising from any inaccuracy or misprint of such information.
8) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS
Directive. LAPIS Technology shall have no responsibility for any damages or losses resulting non-compliance
with any applicable laws or regulations.
9) When providing our Products and technologies contained in this document to other countries, you must abide by
the procedures and provisions stipulated in all applicable export laws and regulations, including without
limitation the US Export Administration Regulations and the Foreign Exchange and Foreign Trade Act..
10) Please contact a ROHM sales office if you have any questions regarding the information contained in this
document or LAPIS Technology's Products.
11) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS
Technology.
(Note) “LAPIS Technology” as used in this document means LAPIS Technology Co., Ltd.
Copyright 2020 LAPIS Technology Co., Ltd.
2-4-8 Shinyokohama, Kouhoku-ku, Yokohama 222-8575, Japan
https://www.lapis-tech.com/en/
17/17
相关型号：
©2020 ICPDF网 联系我们和版权申明