ML5236 [ROHM]

电池电压、电流和温度测量短路电流检测过充检测内置高边NMOS-FET驱动器内置电池均衡开关MCU接口:SPI内置外部微控制器用电源;
ML5236
型号: ML5236
厂家: ROHM    ROHM
描述:

电池电压、电流和温度测量短路电流检测过充检测内置高边NMOS-FET驱动器内置电池均衡开关MCU接口:SPI内置外部微控制器用电源

电池 开关 驱动 控制器 微控制器 驱动器
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FEDL5236-08  
1 December , 2020  
ML5236  
Analog Front-End IC for 14-Serial-Cell Lithium-Ion Rechargeable Battery Protection  
General Description  
The ML5236 is an analog front-end IC intended for 14-cell Li-ion rechargeable battery protection systems. With  
integrated individual cell voltage monitor and charge/discharge current monitor functions, it protects cell  
overvoltage, cell undervoltage, and pack over-current working with an external microcontroller (MCU).  
Also, it is equipped with the short-circuit protection function, which autonomously turns off the external  
charge/discharge Nch-FETs on the high-side power rail without the external MCU.  
Features  
5- to 14-cell high-precision cell voltage measurement function  
Built-in 12-bit successive approximation type ADC  
Cell voltage measurement precision: ±10mV (typ) at cell voltage 4V  
Cell voltage measurement time: 2ms per cell (typ)  
Charge/discharge current measurement function  
The potential differential between the ISP and ISM pins amplified by 12- or 60-fold, then digitized  
with the 12-bit ADC.  
(A single ADC module is shared in cell voltage measurement and pack current measurement.)  
Short-circuit protection function  
Variable detection threshold between ISP and ISM pins: 50mV/100mV/150mV/200mV (typ)  
Detection delay time adjustable using an external capacitor  
Built-in cell balancing switch on each cell: Switch ON resistance 6(typ)  
External charge/discharge FET control: Built-in gate driver for highside Nch-FET  
Temperature sensor measurement function: Two thermistor inputs  
Overvoltage protection function: Overvoltage protection tripped by comparing each A/D converted cell  
voltage value with the detection threshold defined in the control register  
MCU interface: SPI serial interface (mode 0)  
Dedicated power supply pin VSPI allows 5V interface  
Built-in 3.3V regulator for an external MCU: 10mA (max) output current  
Current boost circuitry configurable with an external Pch-FET  
Low current consumption  
Normal operation  
Power-save  
Power-down  
: 330A(typ), 700A (max)  
: 120A(typ), 200A (max)  
: 0.1A(typ), 1A(max)  
Power supply voltage  
Operating temperature range  
Package  
: +8V to +64V  
: -40°C to +85°C  
: 44-Pin TQFP  
Note) This product is not intended for automotive use and for any equipment, device, or system that requires a  
specific quality or high level of reliability (e.g., medical equipment, transportation equipment, aerospace  
machinery, nuclear-reactor controller, fuel-controller, various safety devices). If you are not sure whether  
your application corresponds to such special purposes, please contact your local ROHM sales  
representative in advance.  
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FEDL5236-08  
ML5236  
Block Diagram  
CPLD CPHD  
D_FET  
C_FET  
CPLC  
CFS  
CPHC  
DFS  
VDD  
Charge Pump & FET Driver  
V14  
V13  
V12  
V11  
V10  
Charger  
Detector  
PSNS  
Clock  
VDDR  
Band gap  
Reference  
Stop  
Detector  
VREG  
VREF  
Voltage  
Regulator  
V9  
V8  
1/32  
Divider  
Clock  
Generator  
V7  
VSPI  
/CS  
V6  
V5  
V4  
V3  
SCK  
MCU I/F  
SDI  
12bit A/D  
Converter  
Cell Voltage  
Level Shifter  
Control  
Logic  
SDO  
V2  
V1  
V0  
/INTO  
/PUPIN  
TEST  
Short  
Detector  
Current  
Monitor  
GND  
ISM ISP  
TEMP2 TDRV  
TEMP1  
CDLY  
Pin Configuration (Top View)  
C_FET  
CFS  
VDDR  
VDD  
V14  
1
2
3
4
5
6
7
8
9
33 CDLY  
32 TEMP2  
31 TEMP1  
30 TDRV  
29 GND  
28 /INTO  
27 SDO  
26 SDI  
V13  
V12  
V11  
V10  
V9 10  
V8 11  
25 SCK  
24 /CS  
23 VSPI  
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ML5236  
Pin Description  
Pin No.  
Pin name  
I/O  
O
Description  
Charge FET gate drive. Connected to the gate pin of the external  
Nch-FET. In the ON state, the CFS level +12V (typ) is asserted, while  
the CFS level is asserted in the OFF state.  
C_FET  
1
Reference voltage input for the C_FET drive charge pump. Connected  
to the source pin of the charge FET.  
2
3
4
CFS  
VDDR  
VDD  
I
Power supply for the internal regulator.  
Configure an external CR noise filter circuit.  
Power supply.  
Configure an external CR noise filter circuit.  
Cell 14 positive input.  
5
6
V14  
V13  
V12  
V11  
V10  
V9  
I
I
I
I
I
I
Cell 14 negative input and Cell 13 positive input.  
Cell 13 negative input and Cell 12 positive input.  
Cell 12 negative input and Cell 11 positive input.  
Cell 11 negative input and Cell 10 positive input.  
Cell 10 negative input and Cell 9 positive input.  
Cell 9 negative input and Cell 8 positive input.  
For the 5-cell applications, connected to GND.  
Cell 8 negative input and Cell 7 positive input.  
For the 5- to 6-cell application, connected to GND.  
Cell 7 negative input and Cell 6 positive input.  
For the 5- to 7-cell applications, connected to GND.  
Cell 6 negative input and Cell 5 positive input.  
For the 5- to 8-cell applications, connected to GND.  
Cell 5 negative input and Cell 4 positive input.  
For the 5- to 9-cell applications, connected to GND.  
Cell 4 negative input and Cell 3 positive input.  
For the 5- to 10-cell applications, connected to GND.  
Cell 3 negative input and Cell 2 positive input.  
For the 5- to 11-cell applications, connected to GND.  
Cell 2 negative input and Cell 1 positive input.  
For the 5- to 12-cell applications, connected to GND.  
Cell 1 negative input.  
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
V8  
V7  
V6  
V5  
V4  
V3  
V2  
V1  
I
I
I
I
I
I
I
I
V0  
19  
20  
21  
I
I
For the 5- to 13-cell applications, connected to GND.  
Ground pin.  
GND  
ISM  
Current sense negative input. Connected to the negative terminal of  
the most negative battery cell.  
Current sense positive input. The ISP pin level should be higher than  
the ISM pin level in discharge state.  
ISP  
VSPI  
/CS  
22  
23  
24  
I
I
Serial MCU interface power supply. Tied to the external MCU power  
supply.  
Serial MCU interface chip select input. Serial MCU interface is enabled  
with L-level input.  
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ML5236  
Pin No.  
25  
Pin name  
SCK  
I/O  
I
Description  
Serial MCU interface clock input. SDI input is captured at the rising  
edge of the SCK clock, while SDO output should be read at the falling  
edge of the SCK.  
SDI  
26  
27  
I
Serial MCU interface data input.  
Serial MCU interface data output. If /CS input is Hlevel, SDO is fixed  
to Hi-Z state.  
SDO  
O
Interrupt signal output to an external MCU, NMOS open drain. Should  
be pulled up externally so that Llevel is asserted when an interrupt  
occurs.  
/INTO  
28  
O
GND  
29  
30  
Ground.  
Ground for thermistors. 0V is asserted during temperature  
measurement, or fixed to the Hi-Z state otherwise.  
Thermistor inputs. Connected to TDRV through an NTC thermistor, and  
TDRV  
O
TEMP1  
TEMP2  
31  
32  
I
I
also pulled up to VREF via a resistor.  
Short circuit detection delay time configuration pin. Connected to GND  
through a capacitor.  
33  
34  
CDLY  
VREF  
IO  
O
2.5V reference level output for the internal ADC. Connected to GND  
through a 4.7F capacitor.  
Built-in 3.3V regulator output. Connected to GND through a 4.7F  
capacitor. Can power the external MCU.  
VREG  
TEST  
35  
36  
37  
O
I
Device test enable input. Should be fixed to GND.  
Power-up trigger input. The device wakes up with the Llevel input.  
/PUPIN  
I
Internally pulled up to VDD through a 1Mresistor.  
Charger presence detection input at power-down. The device is  
powered-up when the PSNS level becomes 1/2VDD or higher during  
power-down. The ADC can measure 1/32-fold voltage of the PSNS  
level.  
38  
PSNS  
I
Reference voltage input for the D_FET drive charge pump. Connected  
to the source pin of the discharge FET. The ADC can measure 1/32-fold  
voltage of the DFS level.  
DFS  
I
39  
40  
Discharge FET gate drive. Connected to the gate pin of the external  
Nch-FET. In the ON state, the DFS level +12V (typ) is asserted, while  
the DFS level is asserted in the OFF state.  
D_FET  
O
Charge pump capacitor input for D_FET drive. Connect a capacitor with  
approximately twice the gate capacitance of the discharge FET between  
the CPHD and CPLD pins.  
CPHD  
CPLD  
CPLC  
CPHC  
41  
42  
43  
44  
O
O
O
O
Charge pump capacitor input for C_FET drive. Connect a capacitor with  
approximately twice the gate capacitance of the charge FET between  
the CPHC and CPLC pins.  
4/50  
FEDL5236-08  
ML5236  
Absolute Maximum Ratings  
GND=0V, Ta=25°C  
Parameter  
Symbol  
VDD  
Condition  
Rating  
Unit  
V
Power supply voltage  
Applied to VDD and VDDR pins  
-0.3 to +86.5  
Applied to V14 to V0 pins  
Voltage difference between Vn+1 and  
Vn pins (note)  
VIN1  
-0.3 to +6.5  
V
VIN2  
VIN3  
Applied to CFS, DFS, and PSNS pins  
Applied to /PUPIN pin  
-0.3 to +86.5  
V
V
Input voltage  
-0.3 to VDD+0.3  
Applied to TEMP1, TEMP2, ISM, and  
ISP pins  
VIN4  
VIN5  
-0.3 to VREG+0.3  
-0.3 to VSPI+0.3  
VDFS-0.3 to +86.5  
V
V
V
Applied to /CS, SCK, and SDI pins  
Applied to D_FET pin  
VDFS=DFS pin voltage  
Applied to C_FET pin  
VCFS=CFS pin voltage  
Applied to /INTO ,TDRV and CDLY  
pins  
VOUT1  
VOUT2  
VCFS-0.3 to +86.5  
V
Output voltage  
VOUT3  
VOUT4  
-0.3 to +6.5  
V
V
Applied to SDO pin  
-0.3 to VSPI+0.3  
VDD=50V,  
Applied to VREG, VREF, SDO, /INTO,  
TDRV, CDLY, C_FET, and D_FET pins  
Short circuit output  
current  
IOS  
20  
mA  
Cell balancing current  
Power dissipation  
ICB  
PD  
Per cell balancing switch  
100  
1.9  
mA  
W
Ta=25°C  
Junction temperature  
TjMAX  
125  
°C  
Package thermal  
resistance  
ja  
JEDEC double-side board mounted  
50.7  
°C/W  
°C  
Storage temperature  
TSTG  
-55 to +150  
Note : When connecting and disconnecting battery cells, voltage exceeding the absolute maximum rating may be  
applied between the adjacent Vn+1 and Vn inputs, resulting in permanent damage on the LSI. Make a full  
and detailed evaluation before usage.  
Package Thermal Loss  
Package thermal loss tolerance decreases  
with increased ambient temperature Ta as in  
the left diagram. Make sure that the thermal  
loss tolerance is not exceeded especially  
when the output current on the VREG pin is  
high.  
Ambient temperature Ta [°C]  
Recommended Operating Conditions  
(GND= 0 V)  
Parameter  
Symbol  
VDD  
VSPI  
Condition  
Applied to VDD and VDDR pins  
Applied to VSPI pin  
Range  
8 to 64  
2.7 to 5.5  
-40 to +85  
Unit  
V
V
Power supply voltage  
Operating temperature  
Ta  
No VREG output load  
°C  
5/50  
FEDL5236-08  
ML5236  
Electrical Characteristics  
DC Characteristics  
VDD = 8 to 64V, VSPI = 2.7 to 5.5V, GND = 0V, Ta = -40 to +85°C, no VREG output load  
Parameter  
Digital Hinput  
voltage (*1)  
Symbol  
Condition  
Min.  
Typ.  
Max.  
Unit  
VIH  
0.8×VSPI  
VSPI  
V
Digital Linput  
voltage (*1)  
/PUPIN pin Hinput  
voltage  
/PUPIN pin Linput  
voltage  
Digital Hinput  
current (*1)  
Digital Linput  
current (*1)  
/PUPIN pin Hinput  
current  
/PUPIN pin Linput  
current  
Digital Houtput  
voltage (*2)  
Digital Loutput  
voltage (*3)  
Digital output leakage  
current (*3)  
Cell voltage monitor  
pin Input current (*4)  
Cell voltage monitor  
pin Input leakage  
current (*4)  
VIL  
VIHP  
VILP  
IIH  
0
-64  
0.2×VSPI  
V
V
0.8×VDD  
VDD  
0.2×VDD  
2
0
V
VIH = VSPI  
VIL = GND  
VIH = VDD  
VDD=64V, VIL = GND  
IOH=-100A  
IOL=1mA  
µA  
µA  
µA  
µA  
V
IIL  
2  
IIHP  
IILP  
2
128  
VSPI-0.2  
0
-32  
VSPI  
0.2  
2
VOH  
VOL  
IOLK  
IINVC  
V
VOH= VSPI  
VOL=0V  
Cell voltage being  
measured  
2  
µA  
µA  
-5  
15  
Cell voltage not being  
measured  
IILVC  
-5  
5
µA  
V
IOH=-1µA  
VDD=VS=18V to 64V  
VS: CFS and DFS pin  
voltage  
FET Houtput  
voltage (*5)  
VOHF  
VS+8  
VS+12  
VS+16  
IOL = 1µA  
FET Loutput  
voltage (*5)  
VDD=VS=18V to 64V  
VS: CFS and DFS pin  
voltage  
VOLF  
VS  
VS+0.3  
V
VDD=10V to 64V  
Output load current <  
10mA  
VDD=8V to 10V  
Output load current <  
5mA  
Ta=0 to 60°C  
Output load current <  
1mA  
Ta=-40 to 85°C  
Output load current <  
1mA  
VREG1  
VREG2  
VREF1  
VREF2  
RBL  
3.0  
3.0  
2.48  
2.45  
3
3.3  
3.3  
2.50  
2.50  
6
3.6  
3.6  
V
V
V
V
VREG output voltage  
VREF output voltage  
2.54  
2.55  
30  
Internal balancing FET  
VDS=0.6V,  
Cell balancing switch  
ON resistance  
VDD=18V to 64V  
(*1) Applied to /CS, SCK, and SDI pins.  
(*2) Applied to SDO pin.  
(*3) Applied to SDO, /INTO, and TDRV pins.  
(*4) Applied to V14 to V0 pins.  
(*5) Applied to C_FET and D_FET pins.  
6/50  
FEDL5236-08  
ML5236  
Supply Current Characteristics  
VDD = 8 to 64V, VSPI = 2.7 to 5.5V, GND = 0V, Ta = -40 to +85°C, no VREG and VREF output load  
Parameter  
Cell voltage  
Symbol  
Condition  
Min.  
Typ.  
Max.  
Unit  
measurement state  
current consumption  
Power-save state  
current consumption  
Power-down state  
current consumption  
VSPI pin  
IDD1  
No output load  
330  
700  
A  
IDD2  
IDDS  
No output load  
No output load  
120  
0.1  
200  
1.0  
µA  
µA  
No output load  
Without SPI  
static current  
IVSPI  
10  
µA  
consumption  
communication  
(Note) The above current consumption values are defined by the total current on the VDD and VDDR pins.  
Cell Voltage Measurement Characteristics  
VDD = 8 to 64V, VSPI = 2.7 to 5.5V, GND = 0V, Ta = -40 to +85°C, no VREG output load  
Parameter  
Cell voltage  
measurement range  
Symbol  
Condition  
Min.  
Typ.  
Max.  
Unit  
VVMR  
(*1)  
0.1  
4.5  
V
Cell voltage = 3.8 to  
4.3V  
VER1T  
VER2T  
VER1  
-15  
-50  
-20  
15  
50  
20  
mV  
mV  
mV  
Ta = 25°C  
When cell voltage = 1V  
Ta = 25°C  
Cell voltage  
measurement error  
(*2)  
Cell voltage = 3.8 to  
4.3V  
Ta = 0°C to 60°C  
When cell voltage = 1V  
Ta = 0°C to 60°C  
VER2  
-70  
70  
mV  
mV  
Cell voltage  
measurement step  
Cell voltage  
VLSB  
tSCAN  
tSEL  
5000/4095  
14-cell scan  
22  
28  
2
36  
ms  
ms  
measurement time  
Individual cell select  
1.6  
2.6  
(*1)  
( *2)  
The power supply voltage VDD should be greater than 8V.  
The measurement error within 1.0-to-3.8V cell voltage range is obtained by linear extrapolation.  
Cell voltage measurement timing diagram  
/CS  
SCK  
VMEAS register  
VM bit  
Hi-Z  
/INTO  
tSCAN or tSEL  
7/50  
FEDL5236-08  
ML5236  
Current Measurement Characteristics  
VDD = 8 to 64V, VSPI = 2.7 to 5.5V, GND = 0V, Ta = -40 to +85°C,  
shunt resistor=1m, no VREG output load  
Parameter  
Current measurement  
range  
Symbol  
IMR1  
Condition  
GIM bit = 0”  
Min.  
-150  
-25  
Typ.  
Max.  
Unit  
30  
A
IMR2  
GIM bit = 1”  
5
A
GIM bit = 0”  
Ta = 0°C to 60°C  
GIM bit = 1”  
Ta = 0°C to 60°C  
GIM bit = 0”  
Ta = 0°C to 60°C  
GIM bit = 1”  
GIM0  
GIM1  
11.4  
57  
12  
60  
12.6  
63  
Factor  
Factor  
Hex  
Current measurement  
amplifier gain (*1)  
VZIM1  
VZIM2  
2B84  
28F5  
3333  
3333  
3AE1  
3D70  
Current measurement  
A/D conversion value  
at zero current  
Hex  
Ta = 0°C to 60°C  
GIM bit = 0”  
IER1  
Ta = 0°C to 60°C  
-50A measurement  
GIM bit = 1”  
Ta = 0°C to 60°C  
-10A measurement  
GIM bit = 0”  
-2.5  
-0.5  
2.5  
0.5  
A
A
Current measurement  
error (*2)  
IER2  
ILSB1  
ILSB2  
3.1790  
0.6358  
mA  
mA  
Current measurement  
step  
GIM bit = 1”  
Current measurement  
setup  
stabilization time  
Current measurement  
time (*3)  
When changing GIM  
and ZERO bits  
tSTB  
2
ms  
ms  
tIM  
0.8  
1.0  
1.3  
(*1)  
(*2)  
The both ends of the shunt resistor should be tied to the ISP and ISM pins via a 1kresistor  
respectively .  
Assuming a 1mshunt resistor without resistance error, the A/D conversion value at zero current flow  
is compensated. The given values include errors in the amplification gain factor of 12- or 60-fold. (*3)  
Stabilization time for current measurement amplifier gain switching is not included.  
Current measurement timing diagram  
/CS  
SCK  
IMEAS register  
IM bit  
Hi-Z  
/INTO  
tIM  
8/50  
FEDL5236-08  
ML5236  
Temperature Sensor Measurement Characteristics  
VDD = 8 to 64V, VSPI = 2.7 to 5.5V, GND = 0V, Ta = -40 to +85°C, no VREG output load .  
Parameter  
Symbol  
Condition  
Min.  
Typ.  
Max.  
Unit  
TEMP1 and TEMP2  
pins input current  
TEMP1 and TEMP2  
pins input voltage  
measurement error  
Temperature sensor  
measurement step  
Temperature sensor  
measurement time  
ITEMP  
VIN=0V to VREG  
-2  
2
µA  
TEMP input = 0.3 to  
2.3V  
VTER  
-25  
25  
mV  
VTLSB  
tTEMP  
2500/4095  
1.0  
mV  
ms  
0.8  
1.3  
Temperature sensor measurement timing diagram  
/CS  
SCK  
MEAS_TEMP  
TM bit  
Hi-Z  
/INTO  
tTM  
Short circuit Detection and VREG Threshold Characteristics  
VDD = 8 to 64V, VSPI = 2.7 to 5.5V, GND = 0V, Ta = -40 to +85°C, no VREG output load  
Parameter  
Symbol  
Condition  
SC1 and SC0 bits =  
(0,0) Ta = 25°C  
SC1 and SC0 bits =  
(0,1), Ta = 25°C  
SC1 and SC0 bits =  
(1,0), Ta = 25°C  
SC1 and SC0 bits =  
(1,1), Ta = 25°C  
SC1 and SC0 bits =  
(0,0)  
Min.  
Typ.  
Max.  
Unit  
VS0T  
30  
50  
70  
mV  
VS1T  
VS2T  
VS3T  
VS0  
75  
120  
160  
25  
100  
150  
200  
50  
125  
180  
240  
75  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
Short circuit detection  
threshold  
SC1 and SC0 bits =  
(0,1)  
VS1  
65  
100  
150  
200  
135  
190  
260  
SC1 and SC0 bits =  
(1,0)  
VS2  
110  
140  
SC1 and SC0 bits =  
(1,1)  
VS3  
Short circuit detection  
delay time  
tSHRT  
VRD  
VRR  
CDLY=1nF  
50  
2.3  
2.5  
100  
2.45  
2.75  
180  
2.6  
2.9  
µs  
V
VREG drop threshold  
VREG recovery  
threshold  
V
9/50  
FEDL5236-08  
ML5236  
Short current detection timing diagram  
VSn  
ISP-ISM  
0V  
CDLY  
tSHRT  
Hi-Z  
/INTO  
VDFS+12V  
D-FET  
VDFS  
VCFS  
VCFS+12V  
C-FET  
PSNS-and-DFS-Pins Voltage Measurement and Charger Detection Threshold  
Characteristics  
VDD = 8 to 64V, VSPI = 2.7 to 5.5V, GND = 0V, Ta = -40 to +85°C, no VREG output load  
Parameter  
PSNS and DFS pins  
input voltage  
Symbol  
Condition  
Min.  
Typ.  
Max.  
Unit  
VERS  
Input voltage = 64V  
-5  
5
V
measurement error  
PSNS and DFS pins  
input voltage  
measurement step  
PSNS and DFS pins  
input voltage  
VSLSB  
19.536  
2.0  
mV  
ms  
tSM  
1.6  
2.6  
measurement time  
Charger detection  
PSNS pin threshold  
PSNS pull-down  
resistance  
When powered-up from  
the power down state  
PSNS pin voltage is not  
being measured  
VPC  
RPD  
RPU  
VDDX0.2  
200  
VDDX0.5  
VDDX0.8  
1000  
4
V
500  
2
KΩ  
MΩ  
DFS pin voltage is not  
being measured  
DFS pull-up resistor  
0.5  
Pull-down resistance  
during voltage  
measurement on  
PSNS and DFS pins  
Pull-down/pull-up  
resistor released  
RDM  
ILPS  
ILFS  
8
20  
50  
2
MΩ  
µA  
µA  
Pull-down resistor  
released PSNS pin  
voltage is not being  
measured  
PSNS input leakage  
current  
-2  
-2  
Pull-up resistor  
DFS input leakage  
current  
released D-FET turned  
OFF DFS pin voltage is  
not being measured  
2
10/50  
FEDL5236-08  
ML5236  
AC Characteristics  
VDD = 8 to 64V, VSPI = 2.7 to 5.5V, GND = 0V, Ta = -40 to +85°C, no VREG output load  
Parameter  
/CS-SCK setup time  
SCK-/CS hold time  
SCK Hpulse width  
SCK Lpulse width  
SCK-SDI setup time  
SCK-SDI hold time  
SCK-SDO output  
delay time  
Symbol  
tCSS  
tCSH  
tWH  
Condition  
Min.  
100  
100  
500  
500  
50  
Typ.  
Max.  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
tWL  
tDIS  
tDIH  
50  
tDOD  
tCS  
500  
1
400  
ns  
ns  
/CS Hpulse width  
/PUPIN Lpulse  
width  
tPUP  
ms  
Serial interface timing diagram  
tCSS  
tCS  
/CS  
tWH tWL  
tCSH  
SCK  
tDIH  
tDIS  
SDI  
tDOD  
Hi-Z  
Hi-Z  
SDO  
11/50  
FEDL5236-08  
ML5236  
Functional Description  
MCU Interface  
The ML5236 is equipped with the SPI interface.  
The SPI interface is enabled by asserting the /CS pin to the ”L” level. It takes in the MSB-first input data on  
the SDI pin synchronous to the rising edges of SCK clock. Output- data is supplied on the SDO pin in the  
MSB-first order synchronous to the falling edges of SCK clock. The SPI interface is disabled with the H”  
level input on the /CS pin and returns to the initial state. The /CS pin should be fixed to the Hlevel every  
time after one data write/read operation is completed.  
/CS  
SCK  
SDI  
Hi-Z  
Hi-Z  
SDO  
Configurations and controls can be done by reading/writing corresponding addresses in the control register.  
Write data is one-byte length, while read data length is specified in read commands. Set the RW bit to 0”  
for data write and 1for data read. Also, set the EC bit to 1if the CRC code for detecting a  
communication error is required, or to 0otherwise.  
1. Data Write Communication Format without CRC  
/CS  
SCK  
EC A5 A4 A3 A2 A1 A0 RW D7 D6 D5 D4 D3 D2 D1 D0  
SDI  
Control register  
write data  
address  
= 0without CRC  
= 0for write  
2. Data Read Communication Format without CRC  
/CS  
SCK  
EC A5 A4 A3 A2 A1 A0 RW D7 D6 D5 D4 D3 D2 D1 D0  
SDI  
Databytelength  
Control register  
address  
Hi-Z  
O7 O6 O5 O4  
O3 O2 O1 O0  
Hi-Z  
SDO  
= 0withoutCRC  
= 1for read  
read data  
12/50  
FEDL5236-08  
ML5236  
3. Data Write Communication Format with CRC  
/CS  
SCK  
EC A5 A4 A3 A2 A1 A0 RW D7 D6 D5 D4 D3 D2 D1 D0 C7 C6 C5 C4 C3 C2 C1 C0  
SDI  
write data  
CRC code  
Controlregisteraddress  
= 1with CRC  
= ”0” for write  
If the EC bit is enabled, 1-byte CRC (Cyclic Redundancy Code) is generated according to an X8+X2+X+1  
equation, and added at the end of each communication data. Set the /CS pin to the Hlevel to initialize  
CRC computation to the default FF [h].  
Data write is performed on the specified control register only if the result from CRC computation matches  
the received CRC. Otherwise, data write is not performed. When a CRC error is detected, the CRC error  
flag is set, allowing the interrupt signal to the external MCU to be asserted on the /INTO pin. For details,  
refer to the INT_EN and INT_REQ registers description.  
4. Data Read Communication Format with CRC  
/CS  
SCK  
EC A5 A4 A3 A2 A1 A0 RW D7 D6 D5 D4 D3 D2 D1 D0  
SDI  
Databytelength  
Controlregisteraddress  
= "1" with CRC  
Hi-Z  
O7 O6 O5 O4 O3 O2 O1 O0  
read data  
SDO  
= 1for read  
/CS  
SCK  
SDI  
O0  
C7 C6 C5 C4 C3 C2 C1 C0  
CRC code  
Hi-Z  
O7 O6 O5 O4 O3 O2 O1  
read data  
SDO  
The CRC computation is also performed for each transmitted/received data during data read operation and  
the result is appended at the end of the read data. The external MCU can detect any communication errors  
by comparing the CRC computation result and the received CRC. The CRC code is not included in the data  
byte length.  
13/50  
FEDL5236-08  
ML5236  
Control Register  
The control register map is shown below.  
Address Register name  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R
Default  
00H  
00H  
00H  
00H  
00H  
00H  
00H  
00H  
00H  
00H  
00H  
00H  
00H  
00H  
Description  
User register  
Interrupt enable 1  
Interrupt enable 2  
Interrupt request 1  
Interrupt request 2  
00H  
01H  
02H  
03H  
04H  
05H  
06H  
07H  
08H  
09H  
0AH  
0BH  
0CH  
0DH  
NOOP  
INT_EN1  
INT_EN2  
INT_REQ1  
INT_REQ2  
VMEAS  
IMEAS  
TMEAS  
SMEAS  
FET  
Cell voltage measurement control  
Current measurement control  
Temperature measurement control  
PSNS/DFS pin voltage measurement control  
FET control  
CBALL  
CBALH  
POWER  
STATUS  
Cell balancing control (lower 8 cells)  
Cell balancing control (higher 8 cells)  
Power-save/power-down control  
Status register  
Short circuit detection threshold/watchdog  
timer  
0EH  
SCWDT  
R/W  
00H  
control  
0FH  
10H  
SETOV  
R/W  
R/W  
00H  
FFH  
Overvoltage alarm control  
Overvoltage threshold  
OVDETL  
(low-order 8 bits)  
Overvoltage threshold  
(high-order 4 bits)  
Cell 1 voltage measurement result  
(low-order 8 bits)  
Cell 1 voltage measurement result  
(high-order 4 bits)  
Cell 2 voltage measurement result  
(low-order 8 bits)  
Cell 2 voltage measurement result  
(high-order 4 bits)  
Cell 3 voltage measurement result  
(low-order 8 bits)  
Cell 3 voltage measurement result  
(high-order 4 bits)  
Cell 4 voltage measurement result  
(low-order 8 bits)  
Cell 4 voltage measurement result  
(high-order 4 bits)  
Cell 5 voltage measurement result  
(low-order 8 bits)  
Cell 5 voltage measurement result  
(high-order 4 bits)  
Cell 6 voltage measurement result  
(low-order 8 bits)  
Cell 6 voltage measurement result  
(high-order 4 bits)  
Cell 7 voltage measurement result  
(low-order 8 bits)  
Cell 7 voltage measurement result  
(high-order 4 bits)  
11H  
12H  
13H  
14H  
15H  
16H  
17H  
18H  
19H  
1AH  
1BH  
1CH  
1DH  
1EH  
1FH  
OVDETH  
VCELL1L  
VCELL1H  
VCELL2L  
VCELL2H  
VCELL3L  
VCELL3H  
VCELL4L  
VCELL4H  
VCELL5L  
VCELL5H  
VCELL6L  
VCELL6H  
VCELL7L  
VCELL7H  
R/W  
R
0FH  
00H  
00H  
00H  
00H  
00H  
00H  
00H  
00H  
00H  
00H  
00H  
00H  
00H  
00H  
R
R
R
R
R
R
R
R
R
R
R
R
R
Cell 8 voltage measurement result  
(low-order 8 bits)  
Cell 8 voltage measurement result  
20H  
21H  
VCELL8L  
VCELL8H  
R
R
00H  
00H  
14/50  
FEDL5236-08  
ML5236  
Address Register name  
R/W  
Default  
Description  
(high-order 4 bits)  
Cell 9 voltage measurement result  
(low-order 8 bits)  
Cell 9 voltage measurement result  
(high-order 4 bits)  
Cell 10 voltage measurement result  
(low-order 8 bits)  
Cell 10 voltage measurement result  
(high-order 4 bits)  
Cell 11 voltage measurement result  
(low-order 8 bits)  
Cell 11 voltage measurement result  
(high-order 4 bits)  
Cell 12 voltage measurement result  
(low-order 8 bits)  
Cell 12 voltage measurement result  
(high-order 4 bits)  
Cell 13 voltage measurement result  
(low-order 8 bits)  
Cell 13 voltage measurement result  
(high-order 4 bits)  
Cell 14 voltage measurement result  
(low-order 8 bits)  
Cell 14 voltage measurement result  
(high-order 4 bits)  
22H  
23H  
24H  
25H  
26H  
27H  
28H  
29H  
2AH  
2BH  
2CH  
2DH  
VCELL9L  
VCELL9H  
VCELL10L  
VCELL10H  
VCELL11L  
VCELL11H  
VCELL12L  
VCELL12H  
VCELL13L  
VCELL13H  
VCELL14L  
VCELL14H  
R
R
R
R
R
R
R
R
R
R
R
R
00H  
00H  
00H  
00H  
00H  
00H  
00H  
00H  
00H  
00H  
00H  
00H  
Current measurement result  
(low-order 8 bits)  
Current measurement result (high-order 8 bits)  
Temperature 1 measurement result (low-order  
8 bits)  
2EH  
2FH  
30H  
CURL  
CURH  
R
R
R
00H  
00H  
00H  
TEMP1L  
Temperature 1 measurement result (high-order  
4 bits)  
Temperature 2 measurement result (low-order  
8 bits)  
Temperature 2 measurement result (high-order  
4 bits)  
PSNS/DFS measurement result (low-order 8  
bits)  
31H  
32H  
33H  
34H  
35H  
TEMP1H  
TEMP2L  
TEMP2H  
SNSL  
R
R
R
R
R
00H  
00H  
00H  
00H  
00H  
PSNS/DFS measurement result (high-order 4  
bits)  
SNSH  
15/50  
FEDL5236-08  
ML5236  
1. NOOP Register (Adrs = 00H)  
7
6
5
4
3
2
1
0
Bit name  
R/W  
NO7  
NO6  
NO5  
NO4  
NO3  
NO2  
NO1  
NO0  
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
Default  
No function is assigned to the NOOP register. Read/write access to this register does not change the  
LSI status. The written data can be read as it is.  
2. INT_EN1 Register (Adrs = 01H)  
7
6
5
4
3
2
1
0
Bit name  
R/W  
ESM  
ETM  
EIM  
EVM  
R
0
R
0
R
0
R
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
Default  
The INT_EN1 register enables or disables the interrupt signal output on the /INTO pin.  
The EVM bit enables or disables the interrupt signal output at the completion of cell voltage  
measurement.  
EVM  
Cell voltage measurement complete interrupt  
0
1
Disabled (default)  
Enabled  
The EIM bit enables or disables the interrupt signal output at the completion of current measurement.  
EIM  
0
Current measurement complete interrupt  
Disabled (default)  
1
Enabled  
The ETM bit enables or disables the interrupt signal output at the completion of temperature sensor  
measurement.  
Temperature sensor measurement complete  
ETM  
interrupt  
0
1
Disabled (default)  
Enabled  
The ESM bit enables or disables the interrupt signal output at the completion of PSNS/DFS pin voltage  
measurement.  
PSNS/DFS pin voltage measurement  
ESM  
complete interrupt  
0
1
Disabled (default)  
Enabled  
3. INT_EN2 Register (Adrs = 02H)  
7
6
5
4
3
2
1
0
Bit name  
R/W  
EWDT ECKSP ECRC  
ESC  
EOV  
R
0
R
0
R
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
Default  
16/50  
FEDL5236-08  
ML5236  
The INT_EN2 register enables or disables the interrupt signal output on the /INTO pin.  
The EOV bit enables or disables the interrupt signal output at overvoltage detection.  
EOV  
0
1
Overvoltage detection interrupt  
Disabled (default)  
Enabled  
The ESC bit enables or disables the interrupt signal output at short circuit detection.  
ESC  
0
1
Short circuit detection interrupt  
Disabled (default)  
Enabled  
The ECRC bit enables or disables the interrupt signal output at CRC error detection.  
ECRC  
CRC error interrupt  
Disabled (default)  
Enabled  
0
1
The ECKSP bit enables or disables the interrupt signal output when the internal clock is halted.  
ECKSP  
Internal clock halt interrupt  
Disabled (default)  
Enabled  
0
1
The EWDT bit enables or disables the interrupt signal output when a watchdog timer overflow occurs.  
EWDT  
WDT overflow interrupt  
Disabled (default)  
Enabled  
0
1
4. INT_REQ1 Register (Adrs = 03H)  
7
6
5
4
3
2
1
0
Bit name  
R/W  
QSM  
QTM  
QIM  
QVM  
R
0
R
0
R
0
R
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
Default  
The INT_REQ1 register contains interrupt request flags. Each request flag is set to "1" when the  
corresponding interrupt request is generated, regardless of the INT_EN1 register configuration. Only if  
the generated interrupt is enabled by the INT_EN1 register, the Llevel is asserted on the /INTO pin.  
An interrupt request flag can be cleared by writing data 0to the corresponding data bit. Since writing  
data 1is ignored, if you want to clear one specific interrupt request flag, fill in data "1" to the other  
bits. When all the enabled interrupt request flags are cleared, the /INTO pin is set to the "Hi-Z" level.  
The QVM bit indicates the interrupt request generated on completion of cell voltage measurement.  
Cell voltage measurement complete  
QVM  
interrupt request  
0
1
No interrupt request (default)  
An interrupt request is generated  
The QIM bit indicates the interrupt request generated on completion of current measurement.  
Current measurement complete interrupt  
QIM  
request  
0
1
No interrupt request (default)  
An interrupt request is generated  
The QTM bit indicates the interrupt request generated on completion of temperature measurement.  
Temperature measurement complete  
QTM  
interrupt request  
17/50  
FEDL5236-08  
ML5236  
0
1
No interrupt request (default)  
An interrupt request is generated  
The QSM bit indicates the interrupt request generated on completion of PSNS/DFS pin voltage  
measurement.  
PSNS/DFS pin voltage measurement  
QSM  
complete interrupt request  
0
1
No interrupt request (default)  
An interrupt request is generated  
18/50  
FEDL5236-08  
ML5236  
5. INT_REQ2 Register (Adrs = 04H)  
7
6
5
4
3
2
1
0
Bit name  
R/W  
QWDT QCKSP QCRC  
QSC  
QOV  
R
0
R
0
R
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
Default  
The INT_REQ2 register contains interrupt request flags. Each request flag is set to "1" when the  
corresponding interrupt request is generated, regardless of the INT_EN2 register configuration. Only if  
the generated interrupt is enabled by the INT_EN2 register, the Llevel is asserted on the /INTO pin.  
An interrupt request flag can be cleared by writing data 0to the corresponding data bit. Since writing  
data 1is ignored,if you want to clear one specific interrupt request flag, fill in data "1" to the other  
bits. When all enabled interrupt request flags are cleared, the /INTO pin is set to the "Hi-Z" level.  
The QOV bit indicates the interrupt request generated at overvoltage detection.  
QOV  
0
1
Overvoltage detection interrupt request  
No interrupt request (default)  
An interrupt request is generated  
The QSC bit indicates the interrupt request generated at short circuit detection.  
QSC  
0
1
Short circuit detection interrupt request  
No interrupt request (default)  
An interrupt request is generated  
The QCRC bit indicates the interrupt request generated at CRC error detection.  
QCRC  
CRC error interrupt request  
No interrupt request (default)  
An interrupt request is generated  
0
1
The QCKSP bit indicates the interrupt request generated when the internal clock stop is halted.  
QCKSP  
Internal clock halt interrupt request  
No interrupt request (default)  
An interrupt request is generated  
0
1
The QWDT bit indicates the interrupt request generated when a watchdog timer overflow occurs.  
QWDT  
WDT overflow interrupt request  
No interrupt request (default)  
An interrupt request is generated  
0
1
19/50  
FEDL5236-08  
ML5236  
6. VMEAS Register (Adrs = 05H)  
7
6
5
4
3
2
1
0
Bit name  
R/W  
VM  
SCAN  
VC3  
VC2  
VC1  
VC0  
R/W  
0
R
0
R
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
Default  
The VMEAS register configures the cell voltage measurement conditions.  
Configure the SCAN bit and the V0 to V3 bits to select the measurement mode and the battery cell(s)  
to measure.  
SCAN VC3 VC2 VC1 VC0  
Cell voltage measurement  
Cell 1 selected  
Cell 2 selected  
Cell 3 selected  
Cell 4 selected  
Cell 5 selected  
Cell 6 selected  
Cell 7 selected  
Cell 8 selected  
Cell 9 selected  
Cell 10 selected  
Cell 11 selected  
Cell 12 selected  
Cell 13 selected  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Cell 14 selected  
Cell 13 to cell 14 scanned  
Cell 12 to cell 14 scanned  
Cell 11 to cell 14 scanned  
Cell 10 to cell 14 scanned  
Cell 9 to cell 14 scanned  
Cell 8 to cell 14 scanned  
Cell 7 to cell 14 scanned  
Cell 6 to cell 14 scanned  
Cell 5 to cell 14 scanned  
Cell 4 to cell 14 scanned  
Cell 3 to cell 14 scanned  
Cell 2 to cell 14 scanned  
Cell 1 to cell 14 scanned  
The VM bit starts or stops cell voltage measurement operation and indicates the cell voltage  
measurement status at the same time. The cell voltage measurement results are stored in the VCELLnL  
and VCELLnH registers (12H to 2DH).  
Read  
Write  
Cell voltage  
measurement  
Stop (default)  
Start  
Cell voltage  
VM  
VM  
measurement  
Completed/stopped  
(default)  
0
1
0
1
Being measured  
20/50  
FEDL5236-08  
ML5236  
If the value “0” is written to the VM bit in the middle of cell voltage measurement, the on-going  
measurement is completed before measurement is stopped. The VM bit value continues to be 1until  
the end of measurement, and it is reset to 0when the measurement stops.  
Any changes to the SCAN and VC3 to VC0 bits are ignored during measurement (while the VM bit is  
1).  
Also, writing the value 1to the VM bit during current measurement, temperature measurement, or  
PSNS/DFS pin voltage measurement is ignored.  
7. IMEAS Register (Adrs = 06H)  
7
6
5
4
3
2
1
0
Bit name  
R/W  
IM  
ENIM  
ZERO  
GIM  
R/W  
0
R
0
R
0
R/W  
0
R
0
R
0
R/W  
0
R/W  
0
Default  
The IMEAS register controls current measurement and its conditions.  
The GIM bit selects the voltage gain of the current measurement amplifier.  
GIM  
0
1
Voltage gain GIM  
12 times (default)  
60 times  
The ZERO bit executes zero current compensation of the current measurement amplifier. Because the  
compensated values may differ for different voltage gains of the current measurement amplifier or  
different temperatures, periodic compensations are suggested for each voltage gain.  
State  
ZERO  
ISP input  
ISM input  
Current measurement  
enabled  
0
Pin input level  
Pin input level  
Zero current  
compensation enabled  
1
GND level  
GND level  
The ENIM bit runs and stops the current measurement amplifier.  
ENIM  
Current measurement amplifier  
0
1
Stop (default)  
Run  
If the value 1is written to the IM bit, current measurement is repeated for 16 times. For zero current  
compensation, if the value 1is written to both the ZERO bit and IM bit , zero current compensation  
is repeated for 16 times. When the ENIM bit is 0, writing 1to the IM bit does not execute current  
measurement or compensation.  
Current measurement status can be obtained by reading the IM bit.  
The 16-times repeated measurement results are summed up and stored as a 16-bit data to the CURL  
and CURH registers (2EH to 2FH).  
Read  
Write  
IM  
0
Current measurement  
Not being measured  
(default)  
IM  
0
Current measurement  
Completed (default)  
Being measured  
1
Start  
1
After the current measurement is started, writing 0to the IM bit does not stop the current  
measurement in progress. Also, writing 1to the IM bit during cell voltage measurement, temperature  
measurement, or PSNS/DFS pin voltage measurement is ignored.  
21/50  
FEDL5236-08  
ML5236  
8. TMEAS Register (Adrs = 07H)  
7
6
5
4
3
2
1
0
Bit name  
R/W  
TM  
TSEL  
TDRV  
R/W  
0
R
0
R
0
R
0
R
0
R
0
R/W  
0
R/W  
0
Default  
The TMEAS register controls temperature measurement and its conditions. The input voltage on the  
TEMP1 and TEMP2 pins can be measured.  
The TDRV bit specifies the TDRV pin output status.  
The temperature measurement should be performed after the input voltages on the TEMP1 and  
TEMP2 pins are stabilized.  
TDRV  
TDRV pin status  
Hi-Z (default)  
0V  
0
1
The TSEL bit selects the input pin to be measured.  
TSEL  
0
1
TEMP pin to be measured  
TEMP1 pin (default)  
TEMP2 pin  
Writing 0to the TM bit executes temperature measurement. The temperature measurement result is  
stored in the TEMPnL and TEMPnH registers (30H to 33H).  
Read  
Write  
TM  
0
TEMP pin measurement  
Not being measured  
(default)  
TM  
0
TEMP pin measurement  
Completed (default)  
Being measured  
1
Start  
1
After temperature measurement is started, writing 0to the TM bit does not stop the temperature  
measurement in progress. Also, writing 1the TM bit during cell voltage measurement, current  
measurement, or PSNS/DFS pin voltage measurement is ignored.  
9. SMEAS Register (Adrs = 08H)  
7
6
5
4
3
2
1
0
Bit name  
R/W  
SM  
ENSM  
SSEL  
PU  
PD  
R/W  
0
R
0
R
0
R/W  
0
R
0
R/W  
0
R/W  
0
R/W  
0
Default  
The SMEAS register controls voltage measurement on the PSNS and DFS pins, configures the  
pull-down resistor on the PSNS pin and the pull-up resistor on the DFS pin. The 1/32-fold voltage of  
the input levels on the PSNS and DFS pins can be measured.  
The PD bit specifies the connection of a pull-down resistor on the PSNS pin.  
PD  
0
1
PSNS pin status  
Pull-down resistor not connected (default)  
500kpull-down resistor connected  
The PU bit specifies the connection of a pull-up resistor on the DFS pin.  
PU  
0
1
DFS pin status  
Pull-up resistor not connected (default)  
2Mpull-up resistor connected  
22/50  
FEDL5236-08  
ML5236  
The SSEL bit selects the input pin to be measured.  
SSEL  
Pin to be measured  
0
1
PSNS pin (default)  
DFS pin  
The ENSM bit runs and stops the PSNS/DFS pin voltage measurement circuit.  
ENSM  
Measurement circuit  
Stop (default)  
Run  
0
1
Writing 1to the SM bit executes voltage measurement on the PSNS or DFS pin. The measurement  
result is stored in the SNSL and SNSH registers (34H to 35H). When the ENSM bit is set to 0,  
writing 1to the SM bit does not execute measurement.  
Read  
Write  
SM  
0
1
Pin voltage measurement  
Not being measured (default)  
Start  
SM Pin voltage measurement  
0
1
Completed (default)  
Being measured  
After voltage measurement is started, writing 0to the SM bit does not stop the measurement in  
progress. Also, writing 1to the SM bit during cell voltage measurement, current measurement, or  
temperature measurement is ignored.  
10. FET Register (Adrs = 09H)  
7
6
5
4
3
2
1
0
Bit name  
R/W  
CF  
DF  
R
0
R
0
R
0
R
0
R
0
R
0
R/W  
0
R/W  
0
Default  
The FET register turns on or turns off the C-FET and D-FET pins, and the C-/D-FET output status can  
be obtained by reading it.  
The DF bit specifies the D-FET pin output status. When short circuit is detected, the DF bit is  
automatically reset to 0. Note that it is not automatically set to 1even after the short circuit  
detection state is restored to the normal state. It is required to turn on the DF pin using the external  
MCU.  
DF  
0
1
Discharge-FET status  
OFF (default)  
ON  
D-FET pin output level  
DFS pin level VDFS  
VDFS+12V(typ)  
The CF bit specifies the C-FET pin output status. When short circuit is detected, the CF bit is  
automatically reset to 0. Note that it is not automatically set to 1even after the short circuit  
detection state is restored to the normal state. It is required to turn on the CF pin using the external  
MCU.  
CF  
0
1
ChargeFET status  
OFF (default)  
ON  
C_FET pin output level  
CFS pin level VCFS  
VCFS+12V(typ)  
23/50  
FEDL5236-08  
ML5236  
11. CBALL Register (Adrs = 0AH)  
7
6
5
4
3
2
1
0
Bit name  
R/W  
SW8  
SW7  
SW6  
SW5  
SW4  
SW3  
SW2  
R/W  
0
SW1  
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
Default  
The CBALL register turns ON or turns OFF the cell balancing switches for the lower 8 cells.  
Use the SW8 to SW1 bits to control the respective cells.  
SW8  
SW7  
SW6  
SW5  
SW4  
SW3  
SW2 SW1  
Switch ON/OFF  
Lower 8 cells turned OFF  
(default)  
V1-to-V0 switch turned  
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
ON  
V2-to-V1 switch turned  
ON  
V3-to-V2 switch turned  
ON  
V4-to-V3 switch turned  
ON  
V5-to-V4 switch turned  
ON  
V6-to-V5 switch turned  
ON  
V7-to-V6 switch turned  
ON  
V8-to-V7 switch turned  
ON  
Multiple switches can be turned ON simultaneously, but the following configurations are inhibited,  
because they may damage the built-in cell balancing switches.  
(1) Do not turn on adjacent cell balancing switches.  
(2) Do not turn on cell balancing switches simultaneously on both sides of a cell balancing switch  
that is turned OFF.  
OFF  
ON  
ON  
OFF  
ON  
ON  
OFF  
OFF  
The cell balancing current and the ON-resistance of cell balancing switch generate heat. Configure the  
number of turned-on switches and the turned-on duration so that the total power loss in the cell  
balancing switches does not exceed the power dissipation limit.  
24/50  
FEDL5236-08  
ML5236  
12. CBALH Register (Adrs = 0BH)  
7
6
5
4
3
2
1
0
Bit name  
R/W  
SW14  
SW13  
SW12  
SW11  
SW10  
R/W  
0
SW9  
R/W  
0
R
0
R
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
Default  
The CBALH register turns ON or turns OFF the cell balancing switches for the higher 6 cells.  
Use the SW14 to SW9 bits to control the respective cells.  
SW14 SW13 SW12 SW11 SW10 SW9  
Switch ON/OFF  
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
Higher 6 cells turned OFF (default)  
V9-to-V8 switch turned ON  
V10-to-V9 switch turned ON  
V11-to-V10 switch turned ON  
V12-to-V11 switch turned ON  
V13-to-V12 switch turned ON  
V14-to-V13 switch turned ON  
The same restrictions apply to the switch ON configurations as the CBALL register.  
13. POWER Register (Adrs = 0CH)  
7
6
5
4
3
2
1
0
Bit name  
R/W  
PUPIN  
PDWN  
PSV  
R
0
R
0
R
0
R/W  
0
R
0
R
0
R
0
R/W  
0
Default  
The POWER register controls the power-save and power-down operation states.  
The PSV bit enables the power-save state.  
PSV  
0
1
Power-save state  
Normal state (default)  
Power-save  
In the power-save state, only the circuits required for the VREG and VREF outputs are activated, and  
the measurement circuits for cell voltage or pack current are halted so as to reduce the current  
consumption. Even in the middle of measurement, the power-save state is enabled right away and halts  
the measurement in progress. Note that a measurement complete interrupt request flag is set, in this  
case. All cell balancing switches are initialized to OFF condition at the transition to the power-save  
state, while other settings are maintained in the power-save state.  
The FET drive circuit and short current detection circuit continue to operate even in the power-save  
state.  
However, operating frequency of charge pump circuit for FET drive is reduced to 1/4 of normal state  
for the purpose of saving current consumption. Therefore, in the power-save state turning on the  
C-FET or D-FET takes longer than in the normal state. It is thus recommended to turn on the FETs  
after transitioning to the normal state.  
The power-save state can be restored to the normal state by resetting the PSV bit to 0.  
The PDWN bit enables the power-down state.  
PDWN  
Power-down state  
Normal state (default)  
Power-down  
0
1
25/50  
FEDL5236-08  
ML5236  
If the PDWN bit is set to 1, a 500kpull-down resistor is automatically connected to the PSNS pin  
and all circuit operations are halted.  
Before setting the PDWN bit to “1”, both the C-FET and D-FET pins should be turned off, and  
confirm that a charger is not present by measuring the PSNS pin level. If the /PUPIN pin input is  
Llevel, the power-down state is not enabled until the /PUPIN pin input becomes Hlevel, even after  
the PDWN bit is set to “1”. As the /PUPIN pin status can be read from the PUPIN bit, check that the  
/PUPIN pin status is not “L” level before setting the PDWN bit to 1.  
PUPIN  
/PUPIN pin status  
Hlevel  
0
1
Llevel  
The power-down state is cleared with a charger detection through the PSNS pin or with the Llevel  
input on the /PUPIN pin.  
At the recovery from the power-down state, all required configurations need to be initialized after the  
VREG output becomes valid.  
14. STATUS Register (Adrs = 0DH)  
7
6
5
4
3
2
1
0
Bit name  
R/W  
INT  
CKSP  
WDT  
OV  
CBAL  
PSV  
CF  
DF  
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Default  
The STATUS register indicates status information.  
The DF bit indicates the D-FET pin output status.  
DF  
0
1
D-FET pin status  
OFF (default)  
ON  
The CF bit indicates the C-FET pin output status.  
CF  
0
1
C-FET status  
OFF (default)  
ON  
The PSV bit indicates the power-save state.  
PSV  
Power-save  
0
1
Normal operation (default)  
Power-save  
The CBAL bit indicates the ON state of cell balancing switches.  
CBAL  
Cell balancing switch ON state  
All OFF (default)  
0
1
One or more are ON  
The OV bit indicates overvoltage detection state.  
OV  
0
1
Overvoltage detection state  
Not detected (default)  
Overvoltage detected  
26/50  
FEDL5236-08  
ML5236  
The WDT bit indicates the watchdog timer overflow state.  
WDT  
0
1
WDT overflow state  
Not detected (default)  
Overflow detected  
The CKSP bit indicates the clock halt detection state.  
CKSP  
Clock halt detection state  
0
1
Not detected (default)  
Clock halted  
The INT bit indicates the /INTO pin output status.  
INT  
0
/INTO pin output state  
No interrupt (default)  
1
An interrupt signal generated  
15. SCWDT Register (Adrs = 0EH)  
7
6
5
4
3
2
1
0
Bit name  
R/W  
ENWD  
WDT1  
WDT0  
ENSC  
SC1  
SC0  
R/W  
0
R
0
R/W  
0
R/W  
0
R/W  
0
R
0
R/W  
0
R/W  
0
Default  
The SCWDT register configures the short circuit detection threshold and the watchdog timer overflow  
period, and controls operations of these functions.  
The SC0 and SC1 bits select the short circuit detection threshold corresponding to the shunt resistance.  
Do not change these values during the measurement operation.  
Short detection threshold  
(ISP-to-ISM pin voltage)  
50mV (default)  
100mV  
Equivalent current  
Shunt resistance = 1mΩ  
SC1 SC0  
0
0
1
1
0
1
0
1
50A  
100A  
150A  
200A  
150mV  
200mV  
The ENSC bit runs or stops the short circuit detection operation.  
ENSC  
Short circuit detection operation state  
0
1
Stop (default)  
Run  
Short circuit detection timing is shown in the below diagram.  
If the ISP-to-ISM pin voltage difference is equal to or larger than the short circuit detection threshold  
(VSn), the delay timer capacitor on the CDLY pin starts charging. If the CDLY pin level is equal to or  
larger than a specific threshold, the DF and CF bits of the FET register are automatically reset to 0”  
and charge/discharge is disabled. In this case, if the ESC bit of the INT_EN2 register is set to 1, the  
Llevel is asserted on the /INTO pin and a short circuit alarm is notified to the external MCU.  
27/50  
FEDL5236-08  
ML5236  
If the short circuit state is cleared while the delay timer capacitor is being charged, charge is  
discontinued, and the CDLY pin is fixed to the GND level.  
Short current detection timing diagram  
VSn  
ISP-ISM  
0V  
CDLY  
tSHRT  
Hi-Z  
/INTO  
VDFS+12V  
D-FET  
VDFS  
VCFS+12V  
C-FET  
VCFS  
The short circuit detection delay (tSHRT) depends on the charge time of the delay capacitor (CDLY) on  
the CDLY pin, which is described as follows:  
Short circuit detection delay tSC [s] = CDLY [nF] x 100  
The WDT0 and WDT1 bits configure the overflow period. Do not change these values while the  
watchdog timer is in operation.  
WDT1  
WDT0  
Overflow period  
1 second (default)  
2 seconds  
0
0
1
1
0
1
0
1
4 seconds  
8 seconds  
If writing/reading data to the control register is not performed for longer than the overflow period, the  
QWDT bit of the INT_REQ2 register is set to 1, and the Llevel is asserted on the /INTO pin.  
If WDT overflow is detected twice consecutively, the DF and CF bits of the FET register are  
automatically set to 0and charge/discharge is disabled.  
The ENWD bit runs or stops the watchdog timer.  
ENWD  
WDT operation state  
Stop (default)  
Run  
0
1
28/50  
FEDL5236-08  
ML5236  
16. SETOV Register (Adrs = 0FH)  
7
6
5
4
3
2
1
0
Bit name  
R/W  
ENOV  
SLT1  
SLT0  
CN2  
CN1  
CN0  
R/W  
0
R
0
R/W  
0
R/W  
0
R
0
R
0
R/W  
0
R/W  
0
Default  
The SETOV register configures the various overvoltage detection conditions.  
The CN0 to CN2 bits define the number of consecutive overvoltage detections in scan measurements,  
which is required to determine an overvoltage alarm. Do not change these values in the middle of  
measurement.  
Number of scan  
measurements  
CN2  
CN1  
CN0  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
16  
32  
64  
128  
Cell voltage measurements in the scan measurement mode are controlled with the VMEAS register. If  
one or more cell voltage continues to exceed the overvoltage detection threshold for more than the  
specified number of scan measurements, an overvoltage alarm is tripped, and the QOV bit of the  
INT_REQ2 register and the OV bit of the STATUS register are set with the CF bit of the FET register  
is reset to “0” for charge inhibition. Since the CF bit of the FET register is not automatically initialized  
to 1after recovery to the normal state, it is necessary to turn on the charge FET using an external  
MCU.  
The SLT0 and SLT1 bits configure the interval time between the cell voltage scan measurements in the  
power-save state. Do not change these values during the scan measurement operation.  
SLT1  
SLT0  
Interval time  
1 second (default)  
2 seconds  
0
0
1
1
0
1
0
1
4 seconds  
8 seconds  
In the power-save state, scan measurement is performed for all 14 cells including unused cells at the  
specified interval time. Fix the unused cell input pins to GND.  
The ENOV bit runs and stops overvoltage detection operation.  
ENOV  
Overvoltage detection operation state  
0
1
Stop (default)  
Run  
29/50  
FEDL5236-08  
ML5236  
17. OVDETL Register (Adrs = 10H)  
7
6
5
4
3
2
1
0
Bit name  
R/W  
OVD7  
OVD6  
OVD5  
OVD4  
OVD3  
OVD2  
OVD1  
OVD0  
R/W  
1
R/W  
1
R/W  
1
R/W  
1
R/W  
1
R/W  
1
R/W  
1
R/W  
1
Default  
The OVDETL register defines the low-order 8 bits of the overvoltage detection threshold. Set this  
value before initiating overvoltage monitor. Do not change this value in the middle of overvoltage  
monitor.  
18. OVDETH Register (Adrs = 11H)  
7
6
5
4
3
2
1
0
Bit name  
R/W  
OVD11 OVD10  
OVD9  
OVD8  
R
0
R
0
R
0
R
0
R/W  
1
R/W  
1
R/W  
1
R/W  
1
Default  
The OVDETH register defines the high-order 4 bits of the overvoltage detection threshold. Set this  
value before initiating overvoltage monitor. Do not change this value during overvoltage monitor.  
19. VCELLnL Register (Adrs = even number addresses between 12H and 2CH)  
7
6
5
4
3
2
1
0
Bit name  
R/W  
AD7  
AD6  
AD5  
AD4  
AD3  
AD2  
AD1  
AD0  
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Default  
The VCELLnL register (n = 1 to 14) stores the low-order 8-bit for the A/D conversion result of the  
individual cell voltages.  
20. VCELLnH Register (Adrs = odd number addresses between 13H and 2DH)  
7
6
5
4
3
2
1
0
Bit name  
R/W  
AD11  
AD10  
AD9  
AD8  
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Default  
The VCELLnH register (n = 1 to 14) stores the high-order 4-bit for the A/D conversion result of the  
individual cell voltages.  
30/50  
FEDL5236-08  
ML5236  
21. CURL Register (Adrs = 2EH)  
7
6
5
4
3
2
1
0
Bit name  
R/W  
AD7  
AD6  
AD5  
AD4  
AD3  
AD2  
AD1  
AD0  
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Default  
The CURL register stores the low-order 8-bit for the A/D conversion result of pack current  
measurement.  
22. CURH Register (Adrs = 2FH)  
7
6
5
4
3
2
1
0
Bit name  
R/W  
AD15  
AD14  
AD13  
AD12  
AD11  
AD10  
AD9  
AD8  
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Default  
The CURH register stores the high-order 8-bit for the A/D conversion result of pack current  
measurement.  
23. TEMPnL Register (Adrs = 30H, 32H)  
7
6
5
4
3
2
1
0
Bit name  
R/W  
AD7  
AD6  
AD5  
AD4  
AD3  
AD2  
AD1  
AD0  
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Default  
The TEMPnL register (n = 1, 2) stores the low-order 8-bit for the A/D conversion result of the TEMP1  
and TEMP2 levels  
24. TEMPnH Register (Adrs = 31H, 33H)  
7
6
5
4
3
2
1
0
Bit name  
R/W  
AD11  
AD10  
AD9  
AD8  
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Default  
The TEMPnH register (n = 1 or 2) stores the high-order 4-bit for the A/D conversion result of the  
TEMP1 and TEMP2 levels.  
31/50  
FEDL5236-08  
ML5236  
25. SNSL Register (Adrs = 34H)  
7
6
5
4
3
2
1
0
Bit name  
R/W  
AD7  
AD6  
AD5  
AD4  
AD3  
AD2  
AD1  
AD0  
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Default  
The SNSL register stores the low-order 8-bit for the A/D conversion result of the PSNS or DFS level.  
26. SNSH Register (Adrs = 35H)  
7
6
5
4
3
2
1
0
Bit name  
R/W  
AD11  
AD10  
AD9  
AD8  
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Default  
The SNSH register stores the high-order 4-bit for the A/D conversion result of the PSNS or DFS level.  
Cell Connection Table  
Cells should be connected to voltage sense pins according to the following table when the series cell count  
is 13 or less.  
Number of  
connected  
cells  
V14 to  
V9 pins  
V8  
pin  
V7  
pin  
V6  
pin  
V5  
pin  
V4  
pin  
V3  
pin  
V2  
pin  
V1  
pin  
V0  
pin  
13  
12  
11  
10  
9
8
7
6
5
Cell  
Cell  
Cell  
Cell  
Cell  
Cell  
Cell  
Cell  
Cell  
Cell  
Cell  
Cell  
Cell  
Cell  
Cell  
Cell  
Cell  
GND  
Cell  
Cell  
Cell  
Cell  
Cell  
Cell  
Cell  
GND  
GND  
Cell  
Cell  
Cell  
Cell  
Cell  
Cell  
Cell  
Cell  
Cell  
Cell  
GND  
GND  
GND  
GND  
Cell  
Cell  
Cell  
Cell  
Cell  
Cell  
GND  
GND  
GND  
GND  
GND  
GND  
Cell  
Cell  
Cell  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
Cell  
GND  
GND  
GND  
GND  
GND  
Cell  
GND  
GND  
GND  
Handling of Unused Pins  
The following table shows how to handle unused pins.  
Unused pins  
V0 to V8  
Recommended pin handling  
Tied to GND.  
TDRV  
TEMP1,TEMP2  
/INTO  
Left open or tied to GND .  
Tied to GND.  
Open  
32/50  
FEDL5236-08  
ML5236  
Handling of VDDR and VDD Power Supplies  
The VDDR pin is power supply dedicated for the built-in regulator output (VREG). If the regulator output  
current is high, the RC noise filter should be configured so that the voltage drop across the resistor is 1V or  
less.  
The VDD pin supplies power to all the other circuits except the built-in regulator.  
Supply current route  
for external circuits  
ML5236  
VDD  
VDDR  
External circuit power supply  
VREG  
GND  
The maximum output current of the built-in regulator (VREG output) is 10mA. If the consumption current  
of the external circuits exceeds 10mA, configure an external current boost circuit with Pch-FET as in the  
diagram below.  
Supply current route  
for external circuits  
ML5236  
VDD  
VDDR  
External circuit  
power supply  
VREG  
GND  
33/50  
FEDL5236-08  
ML5236  
Power-on/Power-off Sequence  
The recommended sequence of cell connection at power-on is as follows. Tie the GND pin first. Then  
connect the VDD and VDDR pins. Finally connect the cell voltage monitor pins from the most negative  
level to the most positive level.  
When this sequence is not observed, voltage exceeding the absolute maximum rating may be applied  
between the adjacent Vn+1 and Vn inputs, resulting in permanent damage on the LSI.  
The recommended sequence of cell connection at power-off is as follows. Disconnect cell voltage monitor  
pins from the most positive level to the most negative level, then disconnect the VDD, VDDR pins, and  
finally disconnect the GND pin.  
Also during tests and evaluation using a battery simulator, cell connection or disconnection sequence  
should be observed so that voltage exceeding the absolute maximum rating is not applied between the  
adjacent Vn+1 and Vn inputs.  
As shown in the below diagram, a TVS diode for protection is recommended between adjacent cell  
monitor input pins, which also requires full and detailed evaluation.  
ML5236  
Vn+1  
6.2V  
Vn  
6.2V  
Vn-1  
Battery cell should be stack in a series before connected to the Vn pins.  
Connecting separate battery cells to the Vn pins is forbidden because the input level between the adjacent  
Vn+1 and Vn pins may exceed the absolute maximum rating, resulting in permanent damage on the LSI.  
There are no restrictions on the power supply voltage rise time at power-on, power-off sequence, and power  
supply voltage fall time at power-off.  
The operation state after power-on is the normal operation state, but it may be the power-down state due to  
chattering noise during power-on sequence. Power up the LSI either by asserting a voltage greater than  
the charger detection threshold (VPC) on the PSNS pin or by asserting the Llevel on the /PUPIN pin.  
After the power-on or power-up, wait until the VREG and VREF output levels are stabilized before  
measuring cell voltages, pack current and temperature. Confirm the VREG and VREF output stabilization  
times on your actual applications because these values depend on the output load capacitance and other  
conditions.  
The following timing diagram shows the power-up operation.  
Power-up operation timing diagram  
/PUPIN  
3.3V  
tPUP  
VREG  
0V  
3V  
VREF  
0V  
Any  
Any  
Any  
SPI  
State  
Initial settings  
Power-down  
Stabilizationtime  
Resetting  
34/50  
FEDL5236-08  
ML5236  
Cell Voltage Measurement  
There are two modes in cell voltage measurement, the select mode and the scan mode. The select mode  
measures the voltage of a selected cell, while the scan mode continuously measures the voltages of selected  
multiple cells.  
The VMEAS register configures the cell voltage measurement conditions and controls measurement  
operation. For details, see the VMEAS register section.  
The following timing diagrams show the cell voltage measurement operation in each measurement mode.  
Select measurement timing diagram (Cell 1 and Cell 14 selected)  
VMEAS  
VMEAS  
INT_REQ1  
SPI  
VMEAS  
VM bit  
VCELL1L/H  
VCELL14L/H  
/INTO  
Hi-Z  
Hi-Z  
Cell 1  
Measurement  
2ms(typ)  
Cell 14  
Measurement  
2ms(typ)  
State  
Cell voltage measurement completion  
interrupt enabled  
Cell voltage measurement  
completion interrupt cleared  
Scan measurement timing diagram (Cell 13 to Cell 14 scanned)  
VMEAS  
INT_REQ1  
SPI  
VMEAS  
VM bit  
VCELL13L/H  
VCELL14L/H  
/INTO  
Hi-Z  
Hi-Z  
Cell 14  
Measurement  
2ms(typ)  
Cell 13  
Measurement  
2ms(typ)  
State  
Cell voltage measurement completion  
interrupt enabled  
Cell voltage measurement  
completion interrupt cleared  
35/50  
FEDL5236-08  
ML5236  
Current Measurement  
A shunt resistor RS is connected between the ISP and ISM pins, and the input level difference between these  
pins is amplified and supplied to the A/D converter. The circuit configuration of the current measurement  
amplifier is shown below.  
The IMEAS register configures current measurement conditions. For details, see the IMEAS register  
section.  
ML5236  
PACK(+)  
Current measurement amplifier  
2.5V  
VREF  
R1=R2×GIM  
R2  
ISM  
ISP  
R1  
R1  
RS  
ZERO  
ADC  
PACK(-)  
R2  
0.5V  
Cell voltage  
TEMP pin  
The A/D conversion result is 3333H (typ) at zero current, greater than 3333H (typ) during discharge, and less  
than 3333H (typ) during charge.  
The current value can be derived from the A/D conversion result ADIM by the following calculation formula,  
where the shunt resistor is RS, the amplifier gain GIM, and the zero current flow compensation value ADZERO  
:
Current [A] = (ADZERO - ADIM) x (2.5 / 65535) / GIM / RS  
For 12-fold gain with the current measurement result = 3600H, where the zero current compensation value =  
3300H, and the shunt resistance = 1m:  
Current [A] = (3300H - 3600H) x 2.5/65535/12/1e-3 = -768 x 2.5/65535/12/1e-3 = -2.4414[A]  
Since the current amplification gain GIM values may vary between devices, it is recommended to measure  
GIM on each device for reducing current measurement errors.  
The following timing diagram shows current measurement operation with the zero current compensation  
performed at 12-fold current amplification gain. Interrupt output on the /INTO pin is not enabled.  
Current measurement timing diagram (zero current compensation and current measurements at  
12-fold gain)  
IMEAS  
IMEAS  
IMEAS  
CURL/H  
CURL/H  
IMEAS  
SPI  
IMEAS  
ZERO bit  
IM bit  
CURL/H  
State  
Stabilization  
time  
Stabilization  
CURL/H  
read out  
time  
2ms  
Zero current  
compensation  
configurations  
CURL/H  
read out  
2ms  
Current measurement  
configurations  
Current  
Zero current  
compensation  
1ms(typ)  
measurement  
1ms(typ)  
36/50  
FEDL5236-08  
ML5236  
Temperature Sensor Measurement  
Below is an example of the temperature sensor (NTC thermistor) configuration.  
Example of TEMP input level versus temperature  
ML5236  
2.5V  
VREF  
TEMP  
RT=10kΩ  
B=3450  
R1=10kΩ  
R1  
RT  
ADC  
Cell voltage  
current  
TDRV  
Temperature [°C]  
The TMEAS register configures temperature sensor measurement conditions. For details, see the TMEAS  
register section.  
Assert 0V on the TDRV pin and wait until the TEMP1 or TEMP2 pin input level stabilizes before starting  
measurement. After temperature sensor measurement is completed, asserting the TDRV pin to the Hi-Z  
state is recommended for reducing current consumption and minimizing VREF output voltage drop.  
The following timing diagram shows the temperature sensor measurement operation.  
Temperature sensor measurement timing diagram  
TMEAS  
TMEAS  
INT_REQ1  
TMEAS  
SPI  
TMEAS  
TDRV bit  
TM bit  
VREF  
VREF  
VREF  
VREF  
TDRV pin  
0V  
TEMP1 and  
TEMP2 pins  
TEMPL/H  
/INTO  
Hi-Z  
Hi-Z  
Stabilization  
time  
State  
TEMP  
Measurement  
1ms(typ)  
TDRV pin  
=Hi-Z output  
TDRV pin  
=0V output  
Temperature sensor  
measurement completion  
interrupt being enabled  
Temperature sensor  
measurement  
completion  
interrupt cleared  
37/50  
FEDL5236-08  
ML5236  
PSNS and DFS Voltage Measurement  
The PSNS or DFS input level is divided to the 1/32-fold and is measured with the A/D converter.  
Below is the regarding voltage measurement circuit.  
PSNS  
VDD  
DFS  
ML5236  
R1: R2 = 31: 1  
R1+R2 = 20M(typ)  
2.5V  
PU  
VREF  
R1  
R1  
2M(typ)  
500k(typ)  
ADC  
R2  
R2  
PD  
Cell voltage  
current  
TEMP pin  
SSEL  
SM  
The SMEAS register configures the PSNS and DFS input voltage measurement conditions. For details, see  
the SMEAS register section.  
Writing data 1to the SM bit of the SMEAS register the 1/32-voltage dividing resistor is connected to the  
PSNS or DFS pin and A/D conversion is performed after internal voltage stabilization time of about 1ms. If  
you connect a pull-down or pull-up resistor to the PSNS or DFS pin, set the PD bit/PU bit to ”1first, then  
wait until the PSNS or DFS pin input voltage stabilizes before writing data 1to the SM bit to start  
voltage measurement. After measurement is finished, release the pull-down/pull-up resistor by configuring  
the PD/PU bits, otherwise it continues to be connected.  
The following timing diagram shows the PSNS pin voltage measurement sequence when the PSNS pin is  
pulled-down.  
PSNS pin voltage measurement timing diagram  
SMEAS  
SMEAS  
SMEAS  
SPI  
SMEAS  
PD bit  
SM bit  
PSNS pin  
SNSL/H  
State  
Stabilization  
time  
PSNS pin voltage  
measurement  
2ms(typ)  
Pull-down resistor  
released  
Pull-down resistor  
connected  
38/50  
FEDL5236-08  
ML5236  
Power-save Function  
The ML5236 is equipped with the power-save function, which reduces current consumption by halting cell  
voltage measurement circuits and others.  
The PSV bit of the POWER register controls transition to/from the power-save state.  
Write data 1to the PSV bit of the POWER register to transition to the power-save state.  
If the PSV bit is 1during measurement on cell voltages or others, the measurement in progress is canceled  
and transitions to the power-save state. In this case, invalid values may be saved to the measurement result  
registers, wait until all measurements are completed before transitioning to the power-save state.  
The following table shows the operation state of each function during the power-save state.  
Function  
VREG pin output  
VREF pin output  
Operation state during power-save  
Outputs 3.3V (typ) as the normal state.  
Outputs 2.5V (typ) as the normal state.  
Can normally read/write registers as the normal  
state, but the measurement and cell balance  
configurations are ignored.  
Halted.  
Halted.  
Halted.  
Halted.  
MCU serial interface  
Cell voltage measurement  
Pack current measurement  
Temperature sensor measurement  
PSNS and DFS voltage  
measurement  
Cell balancing  
Halted.  
Short circuit detection  
Charge/discharge control FET  
driver  
Overvoltage detection  
Watchdog timer  
Operates as the normal state.  
Operating frequency of the charge pump circuit is  
reduced to 1/4 of the normal state.  
Operates at the defined interval time.  
Halted.  
Internal clock halt detection circuit  
Operates as the normal state .  
Write data 0to the PSV bit of the POWER register to recover from the power-save state and start the  
measurement circuits . Various measurements should be conducted after 1ms (max) operation stabilization  
time.  
39/50  
FEDL5236-08  
ML5236  
Power-down Function  
The ML5236 is equipped with the power-down function, which halts all circuits to reduce the current  
consumption to zero. Write data 1to the PDWN bit of the POWER register to transition to the  
power-down state.  
Below is an example of the control flow for transitioning to the power-down state.  
START  
Write 00H toFET  
Charge/discharge FETs are turned off.  
register  
The PSNS pin is pulled-down with a 500k(typ) resistor to  
monitor release of the charger .  
SMEAS register  
Write 01H to  
Wait  
several ms  
Wait until the PSNS pin voltage stabilizes.  
The PSNS pin voltage is measured to confirm that the charger  
is released.  
Write 81H to  
SMEAS register  
The SNSL and SNSH registers are evaluated to confirm the  
PSNS pin level to be lower than 1/2 VDD. If it is higher than 1/2  
VDD, the device is powered-up again immediately after  
transitioning to the power-down state. Wait until the PSNS pin  
voltage becomes lower than 1/2 VDD.  
Charger is  
released ?  
Read from  
POWER register  
PUPIN bit  
Check the PUPIN bit to confirm that the /PUPIN pin level is H”  
If the PUPIN bit is 1, the device is powered-up again  
immediately after transitioning to the power-down state. Wait  
until the PUPIN bit becomes 0.  
PUPIN=0”  
Write 10H to  
POWER register  
Write data 1to the PDWN bit to transition to the power-down  
state. All circuits are halted and all registers are initialized.  
PSNS is internally pulled-down with a 500k(typ) resistor and  
presence of a charger is monitored.  
Power-down  
The following table shows the output level on each pin in the power-down state.  
Output level during  
Pin name  
power-down  
VREG  
0V  
VREF  
/INTO  
SDO  
0V  
Hi-Z  
Hi-Z  
C_FET  
D_FET  
CDLY  
Equals to the CFS level  
Equals to the DFS level  
0V  
The power-down state is cleared if a charger is detected through the PSNS pin, or if the Llevel is asserted  
on the /PUPIN pin.  
At recovery from the power-down state, the initial configurations should be made after the VREG and  
VREF outputs have risen.  
40/50  
FEDL5236-08  
ML5236  
Short Circuit Detection Function  
The ML5236 is equipped with the short circuit detection function, which autonomously turns off the  
charge/discharge FETs when a short circuit condition is detected. The SCWDT register configures the short  
circuit conditions. For details, see the SCWDT register section.  
Below is an example of short circuit detection configurations and the system control flow.  
START  
Configure the short circuit detection threshold with the SC0  
and SC1 bits, and set the ENSC bit to 1to start short  
Configure  
circuit monitor.  
SCWDT register  
Configure  
INT_EN2 register  
Set the ESC bit to 1to enable the short circuit detection  
interrupt.  
If the Llevel is asserted on the /INTO pin, read the INT_REQ2  
register to confirm the requested interrupt. (QSC is assumed  
here.)  
/INT=L”  
QSC=1”  
Write FDH to  
INT_REQ2 register  
Write 0to the QSC bit to clear the interrupt request.  
Set the PU bit of the SMEAS register to 1to pull-up the DFS  
pin.  
If the short circuit state is continued, the DFS pin level remains  
to be the GND level. Otherwise, it is brought up to a level close  
to VDD by the pull-up resistor.  
Configure  
SMEAS register  
To measure the DFS pin voltage, set the SSEL and SM bits of  
the SMEAS register to 1.  
Configure  
SMEAS register  
Read the SNSL and SNSH registers to confirm that the DFS  
pin level is close to VDD. If the DFS pin level is GND, it means  
that the short circuit state is continued. Wait until the DFS pin  
level reaches VDD.  
Short circuit is  
released ?  
Configure  
FET register  
If the cell voltages are in the normal range, set the DF and CF  
bits of the FET register to 1to enable charge/discharge.  
END  
41/50  
FEDL5236-08  
ML5236  
Watchdog Timer Function  
The ML5236 is equipped with the watchdog timer function, which triggers an alarm when writing/reading  
data to/from the control register is not executed for a specific time period. The SCWDT register configures  
the watchdog timer conditions. For details, see the SCWDT register section.  
Below is an example of the watchdog timer operation.  
Example of watchdog timer operation  
3.3V  
VREG  
VRR  
0V  
FET  
Any  
SPI  
WDT counter  
INT_REQ2  
QWDT bit  
Hi-Z  
/INTO pin  
0V  
FET register  
DF and CF bits  
State  
Overflow period  
Overflow period  
Reset released  
1st IRQ  
generated  
2nd IRQ generated  
Charge/discharge  
inhibited  
Charger/discharge enabled  
WDT counter cleared  
WDT counter cleared  
If writing/reading data to the control register is not performed for longer than the overflow period, the  
QWDT bit of the INT_REQ2 register is set to 1, and the Llevel is asserted on the /INTO pin. If a CRC  
error occurs during the CRC mode, the watchdog timer counter is not cleared.  
If the overflow is detected twice consecutively, the DF and CF bits of the FET register are automatically set  
to 0to disable charge/discharge. Since these bits will not be reset automatically after recovery to the  
normal state, they should be reconfigured using the external MCU.  
42/50  
FEDL5236-08  
ML5236  
Overvoltage Detection Function  
The ML5236 is equipped with the overvoltage detection function, which compares the register values of  
cell voltage measurement results with the overvoltage threshold value defined in the OVDETL/H register to  
monitor overvoltage.  
The SETOV and OVDETL/H registers configure the overvoltage detection conditions. For details, refer to  
the SETOV and OVDETL/H registers.  
The following timing diagram shows the overvoltage monitor in the normal state with the number of  
consecutive overvoltage detection delays in scan measurements being 2.  
Overvoltage detection timing diagram (normal state, number of detection delays in scan  
measurement = 2)  
VMEAS  
VMEAS  
VMEAS  
VMEAS  
INT_REQ2  
SPI  
VMEAS  
VM bit  
Normal  
Normal  
Normal  
Normal  
Normal  
Normal  
Normal  
Normal  
Normal  
VCELL1L/H  
VCELL2L/H  
Over Voltage  
Normal  
Normal  
Normal  
Normal  
Normal  
Normal  
Over Voltage  
Normal  
Normal  
VCELL13L/H  
VCELL14L/H  
Normal  
Internal OV flag  
0
0
1
2
Internal OV  
counter  
INT_REQ2  
QOV bit  
FET: CF bit  
/INTO  
Hi-Z  
Hi-Z  
State  
Scan  
measurement  
Scan  
measurement  
Scan  
measurement  
Scan  
measurement  
Overvoltage interrupt request  
cleared  
Overvoltage detected  
Charge inhibited  
Interrupt output asserted  
If any one VCELLnL/H register value is greater than the OVDETL/H register value on completion of each  
scan measurement, the internal OV flag is set, and the internal OV counter for detection delays is  
incremented.  
If an overvoltage condition is detected on a different cell at the next scan measurement, the internal OV flag  
is maintained and the OV counter is incremented.  
If the number of overcharge detection delay threshold defined in the CN0 to CN2 bits of the SETOV  
register is equal to the OV counter value, the QOV bit of the INT_REQ2 register and the OV bit of the  
STATUS register are set to 1, and the CF bit of the FET register is reset to 0for charge inhibition.  
Since the CF bit of the FET register is not automatically set to 1after recovery to the normal state, they  
should be reconfigured to turn-on condition using the external MCU.  
43/50  
FEDL5236-08  
ML5236  
While in the power-save state, all the cells from Cell 1 to Cell 14 are scanned for voltage measurement  
automatically at the interval time specified in the SLT0 and SLT1 bits of SETOV register. Since unused  
cells are scanned, tie the corresponding cell monitor pins to GND. The following timing diagram shows the  
overvoltage monitor operation in the power-save state.  
Overvoltage detection timing diagram (power-save state, number of detection delays in scan  
measurement = 2)  
POWER  
POWER  
INT_REQ2  
SPI  
VMEAS  
VM bit  
Normal  
Normal  
Normal  
Normal  
Normal  
Normal  
Normal  
Normal  
Normal  
VCELL1L/H  
VCELL2L/H  
Over Voltage  
Over Voltage  
Normal  
Normal  
Normal  
Normal  
Normal  
Over Voltage  
Normal  
Normal  
Normal  
Normal  
Normal  
Normal  
Normal  
VCELL13L/H  
VCELL14L/H  
Internal OV flag  
0
1
2
0
Internal OV  
counter  
INT_REQ2  
QOV bit  
FET: CF bit  
/INTO  
Hi-Z  
Hi-Z  
State  
Interval time  
Scan measurement  
Transition to  
power-save state  
Overvoltage detected  
interrupt cleared  
Overvoltage detected  
Charge inhibition interrupt  
asserted  
Power-save  
state released  
If a scan measurement is in progress when the PSV bit of POWER register is set to “0” to recover from the  
power-save to the normal state, the scan in progress continues until the last cell is scanned. Therefore, after  
the restoration from the power-save to the normal state, make sure that the VM bit of the VMEAS register  
is not 1.  
The scan measurement completion interrupt flag will be set during the power-save state. Reset the EVM bit  
of the INT_EN1 register to 0before transitioning to the power-save state to disable the cell voltage  
measurement completion interrupt request.  
44/50  
FEDL5236-08  
ML5236  
Interrupt Output Function  
Interrupt signal is asserted on the /INTO pin to notify the external MCU at the completed measurements and  
error detections.  
The INT_EN1 and INT_EN2 registers enables various interrupt outputs, while the INT_REQ1 and  
INT_REQ2 registers are read/written to check and clear generated interrupt requests.  
The following table shows interrupt requests, generation conditions, and states after generation.  
Interrupt request  
Interrupt generation condition  
State after interrupt  
Cell voltage  
measurement  
completion  
The VM bit of the VMEAS register is set to The measurement result  
1, subsequently the cell voltage  
is stored in the  
measurement is completed.  
VCELLnL/H register.  
Current  
measurement  
completion  
The IM bit of the IMEAS register is set to  
1, subsequently the current  
measurement is completed.  
The measurement result  
is stored in the CURL/H  
register.  
Temperature  
sensor  
measurement  
completion  
The TM bit of the TMEAS register is set to The measurement result  
1, subsequently the temperature sensor  
is stored in the TEMPnL/H  
register.  
measurement is completed.  
The count of the VCELLnL/H register  
value exceeding the OVDETL/H register  
threshold on completion of each scan,  
reaches the detection delays in scan  
measurement specified in the CN0 to CN3  
bits of the SETOV register.  
The CF bit of the FET  
register is automatically  
reset to 0.  
Overvoltage  
detection  
The ISP-to-ISM level is larger than the  
threshold specified in the SC0 and SC1  
bits of the SCWDT register, and the CDLY  
pin level reaches the predefined threshold.  
The DF and CF bits of the  
FET register are  
automatically reset to 0.  
Short circuit  
detection  
The received SPI  
communication data is  
disabled.  
The received CRC code does not match  
the calculation result.  
CRC error  
The CF and DF bits of the  
FET register are  
automatically reset to 0.  
Measurement functions  
do not operate normally.  
Internal clock  
halt detection  
Internally generated clock is not supplied  
for a specific time period.  
Writing/reading operation to/from the  
control register is not executed for longer  
than the overflow period defined in the  
WDT0 and WDT1 bits of the WDT  
register.  
The Llevel is asserted  
on the /INTO pin.  
WDT overflow  
detection  
The DF and CF bits of the  
FET register are  
Overflow is detected twice consecutively.  
automatically reset to 0.  
45/50  
FEDL5236-08  
ML5236  
Application Circuit Example 1 (7-Cell and MCU Power Supply = External 5V)  
CPUP  
PACK(+)  
RG  
RFS  
RG  
CCP  
CCP  
RFS  
CREF  
CREG  
RVDDR  
CDLY  
CVDDR  
C_FET  
CFS  
VDDR  
VDD  
V14  
1
2
3
4
5
6
7
8
9
33 CDLY  
RVDD  
32 TEMP2  
31 TEMP1  
30 TDRV  
29 GND  
28 /INTO  
27 SDO  
26 SDI  
25 SCK  
24 /CS  
23 VSPI  
CVDD  
RCEL  
CCEL  
V13  
V12  
V11  
V10  
V9 10  
V8 11  
ML5236  
RINT  
CSPI  
5V  
MCU  
CISIN  
RISIN  
PACK(-)  
RS  
Recommended Values for Externally Connected Components  
Recommended  
value  
Recommended  
value  
Recommended  
value  
Component  
Component  
Component  
RVDD  
510to 1.5kΩ  
2.2F to 10F  
100Ω  
2.2F to 10F  
150to 10kΩ  
0.1F to 10F  
1mΩ  
RISIN  
CISIN  
CREG, CREF  
RINT  
1kΩ  
0.1F  
4.7F  
51kΩ  
RG  
RFS  
CCP  
1kΩ  
1kΩ  
20nF (*2)  
(*1)  
CVDD  
RVDDR  
CVDDR  
RCEL  
CCEL  
RS  
CSPI  
CDLY  
CPUP  
0.1F  
1nF to 10nF  
0.1F  
(*1) Recommend RVDD=1.5kfor CVDD=2.2 F.  
(*2) 10nF gate capacitance of the external Nch-FET is assumed.  
(*3) In order to prevent the voltage of the Vn pin, which is connected to the lowest cells negative  
pin, from dropping below GND level, the capacitor CCEL should be connected between the  
lowest cells positive pin and the GND.  
Notice: Example of application circuit and the recommended values to parts list shall not guarantee  
performance under all conditions. Full and detailed tests are suggested on your actual  
application. e.  
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Application Circuit Example 2 (7-Cell, Isolated Charge/Discharge Path, and MCU Power  
Supply = VREG)  
CHG(+)  
RPS  
CPUP  
PACK(+)  
RG  
RFS  
RG  
CCP  
CCP  
RFS  
CREF  
CREG  
RVDDR  
CDLY  
CVDDR  
C_FET  
CFS  
VDDR  
VDD  
V14  
1
2
3
4
5
6
7
8
9
33 CDLY  
RVDD  
32 TEMP2  
31 TEMP1  
30 TDRV  
29 GND  
28 /INTO  
27 SDO  
26 SDI  
25 SCK  
24 /CS  
23 VSPI  
CVDD  
RCEL  
CCEL  
V13  
V12  
V11  
V10  
V9 10  
V8 11  
ML5236  
RINT  
CSPI  
MCU  
CISIN  
RISIN  
PACK(-)  
RS  
Recommended Values for External Components  
Recommended  
Recommended  
value  
Recommended  
value  
Component  
Component  
Component  
value  
RVDD  
510to 1.5kΩ  
2.2F to 10F  
100Ω  
2.2F to 10F  
150to 10kΩ  
0.1F to 10F  
1mΩ  
RISIN  
CISIN  
CREG, CREF  
RINT  
1kΩ  
0.1F  
4.7F  
51kΩ  
RG  
RFS  
CCP  
1kΩ  
1kΩ  
20nF (*2)  
(*1)  
CVDD  
RVDDR  
CVDDR  
RCEL  
CCEL  
RS  
CSPI  
CDLY  
CPUP  
0.1F  
1nF to 10nF  
0.1F  
(*1) Recommend RVDD=1.5kfor CVDD=2.2 F.  
(*2) 10nF gate capacitance of the external Nch-FET is assumed.  
(*3) In order to prevent the voltage of the Vn pin, which is connected to the lowest cells negative  
pin, from dropping below GND level, the capacitor CCEL should be connected between the  
lowest cells positive pin and GND.  
Notice: Example of application circuit and the recommended values to parts list shall not guarantee  
performance under all conditions. Full and detailed tests are recommended on your actual  
applications.  
47/50  
FEDL5236-08  
ML5236  
Package Dimensions  
Causion regarding surface mount type packages  
Surface mount type packages are susceptible to applied heat in solder reflow or moisture absorption during  
storage. Please contact your local ROHM sales representative for the recommended mounting conditions (reflow  
sequence, temperature and cycles) and storage environment.  
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Revision History  
Page  
Previous  
Document No.  
Issue date  
Descriptions  
First edition issued  
New  
FEDL5236-01  
FEDL5236-02  
2014.09.02  
2015.06.26  
Add it is recommended to measure the current  
amplification gain GIM values to this page.  
MCU interface: the SCK clock edge is corrected  
Power-on/Power-off Sequence: pin name is  
corrected.  
36  
12,13  
34  
FEDL5236-03  
2015.12.03  
12,13  
34  
FEDL5236-04  
FEDL5236-05  
2016.03.25  
2016.07.12  
Application Circuit example; capacitor  
connection of lowest cell is modified.  
Pin Description corrected  
46,47  
3
46,47  
3
Table of Cell connection table and Handling of  
unused pin is corrected.  
32  
32  
FEDL5236-06  
2018.06.07  
Absolute Maximum rating:  
5
5
Output voltage Vout3, short circuit output current  
IOS is applied to CDLY pin.  
FEDL5236-07  
FEDL5236-08  
2019.11.21  
2020.12.1  
Short current detection timing diagram:  
Error correction of C_FET, D_FET.  
Changed Company name  
10  
10  
-
-
50  
50  
Changed Notes”  
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Notes  
1) The information contained herein is subject to change without notice.  
2) When using LAPIS Technology Products, refer to the latest product information (data sheets, user’s manuals,  
application notes, etc.), and ensure that usage conditions (absolute maximum ratings, recommended operating  
conditions, etc.) are within the ranges specified. LAPIS Technology disclaims any and all liability for any  
malfunctions, failure or accident arising out of or in connection with the use of LAPIS Technology Products  
outside of such usage conditions specified ranges, or without observing precautions. Even if it is used within  
such usage conditions specified ranges, semiconductors can break down and malfunction due to various factors.  
Therefore, in order to prevent personal injury, fire or the other damage from break down or malfunction of  
LAPIS Technology Products, please take safety at your own risk measures such as complying with the derating  
characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail-safe  
procedures. You are responsible for evaluating the safety of the final products or systems manufactured by you.  
3) Descriptions of circuits, software and other related information in this document are provided only to illustrate  
the standard operation of semiconductor products and application examples. You are fully responsible for the  
incorporation or any other use of the circuits, software, and information in the design of your product or system.  
And the peripheral conditions must be taken into account when designing circuits for mass production. LAPIS  
Technology disclaims any and all liability for any losses and damages incurred by you or third parties arising  
from the use of these circuits, software, and other related information.  
4) No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of  
LAPIS Technology or any third party with respect to LAPIS Technology Products or the information contained  
in this document (including but not limited to, the Product data, drawings, charts, programs, algorithms, and  
application examplesetc.). Therefore LAPIS Technology shall have no responsibility whatsoever for any  
dispute, concerning such rights owned by third parties, arising out of the use of such technical information.  
5) The Products are intended for use in general electronic equipment (AV/OA devices, communication, consumer  
systems, gaming/entertainment sets, etc.) as well as the applications indicated in this document. For use of our  
Products in applications requiring a high degree of reliability (as exemplified below), please be sure to contact a  
LAPIS Technology representative and must obtain written agreement: transportation equipment (cars, ships,  
trains, etc.), primary communication equipment, traffic lights, fire/crime prevention, safety equipment, medical  
systems, servers, solar cells, and power transmission systems, etc. LAPIS Technology disclaims any and all  
liability for any losses and damages incurred by you or third parties arising by using the Product for purposes  
not intended by us. Do not use our Products in applications requiring extremely high reliability, such as  
aerospace equipment, nuclear power control systems, and submarine repeaters, etc.  
6) The Products specified in this document are not designed to be radiation tolerant.  
7) LAPIS Technology has used reasonable care to ensure the accuracy of the information contained in this  
document. However, LAPIS Technology does not warrant that such information is error-free and LAPIS  
Technology shall have no responsibility for any damages arising from any inaccuracy or misprint of such  
information.  
8) Please use the Products in accordance with any applicable environmental laws and regulations, such as the  
RoHS Directive. LAPIS Technology shall have no responsibility for any damages or losses resulting  
non-compliance with any applicable laws or regulations.  
9) When providing our Products and technologies contained in this document to other countries, you must abide  
by the procedures and provisions stipulated in all applicable export laws and regulations, including without  
limitation the US Export Administration Regulations and the Foreign Exchange and Foreign Trade Act..  
10) Please contact a ROHM sales office if you have any questions regarding the information contained in this  
document or LAPIS Technology's Products.  
11) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS  
Technology.  
(Note) “LAPIS Technology” as used in this document means LAPIS Technology Co., Ltd.  
Copyright 2020 LAPIS Technology Co., Ltd.  
2-4-8 Shinyokohama, Kouhoku-ku, Yokohama 222-8575, Japan  
https://www.lapis-tech.com/en/  
50/50  

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