BU2286FV-E2 [ROHM]
Clock Generator, CMOS, PDSO16,;
| 型号： | BU2286FV-E2 |
| 厂家： | 
ROHM |
| 描述： | Clock Generator, CMOS, PDSO16, 光电二极管 |
| 文件： | 总6页 (文件大小：52K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BU2286FV
Multimedia ICs
Clock generator IC
BU2286FV
BU2286FV is an IC that generates multiple clocks from the built-in 2ch PLL of the external crystal oscillator used for DVD
system. This IC creates six kinds of signals for video, audio, and low jitter system.
zApplications
zExternal dimensions (Unit : mm)
DVD sets
5.0±0.2
16
9
zFeatures
1) Can generate clock signals needed for DVD by a single chip
2) All output low jitter (No load 30psec)
3) Built-in PLL loop filter, No external components needed
4) 3.3V signal power supply
1
8
0.15±0.1
0.1
0.65
0.22±0.1
5) Small SSOP-B16 package
SSOP-B16
zAbsolute maximum ratings (Ta=25°C)
Parameter
Applied voltage
Symbol
Limits
−0.5 to +7.0
−0.5 to VDD+0.5
−30 to +125
450
Unit
V
VDD
Input voltage
VIN
V
Storage temperature range
Tstg
Pd
°C
mW
Power dissipation
An operation is not guaranteed.
In case it is used at Ta=25°C or more, 4.5mW is reduced at every 1°C.
Radiation resistance design is not used.
Power dissipation is measured when BU2286FV is placed on the board.
zRecommended operating conditions (Ta=25°C)
Parameter
Supply voltage
Symbol
Min.
3.0
Typ.
−
Max.
3.6
Unit
V
DD
IH
IL
V
V
Input "H" voltage range
Input "L" voltage range
Operating temperature range
Output maximum load
V
0.8VDD
0
−
VDD
V
−
0.2VDD
70
V
Topr
−10
−
−
°C
pF
CL
−
15
1/6
BU2286FV
Multimedia ICs
zBlock diagram
CLK54M
(54MHz)
1 / 4
1 / 8
XTALIN
XTAL
OSC
CLK27M
(27MHz)
PLL1
PLL2
XTALOUT
XTALIN=36.864MHz
CLK33M
(33.8688MHz)
1 / 4
1 / 8
CLK16M
(16.9344MHz)
OPEN : 36.864MHz
CLK768FS1
(33.8688MHz or 36.864MHz)
L : 33.8688MHz
FSEL
OPEN : 18.432MHz
L : 16.9344MHz
CLK384FS2
(16.9344MHz or 18.432MHz)
1 / 2
FSEL
FSEL
L
CLK768FS
33.8688
36.864
CLK384FS
16.9344
18.432
OPEN
2/6
BU2286FV
Multimedia ICs
zPin descriptions
Functions
Digtal VDD for 27.54MHz clock output
Digtal GND for 27.54MHz clock output
54MHz clock output
Pin No.
Pin name
1
2
VDD2
V
SS
2
3
CLK54M
CLK27M
AVDD
4
27MHz clock output
5
Analog VDD
6
AVSS
Analog GND
7
XTALIN
XTALOUT
384FS2
768FS1
DVSS
Standard crystal input
8
Standard crystal input
9
FSEL=OPEN : 18.432MHz, FSEL=LOW : 16.9344MHz
FSEL=OPEN : 36.864MHz, FSEL=LOW : 33.8688MHz
10
11
12
13
14
Digtal GND
Digtal VDD
DVDD
16.9344MHz clock output
Output select : with pull-up
OPEN : 18.432MHz (Pin9), 36.864MHz (Pin10)
CLK16M
FSEL
L
: 16.9344MHz (Pin9), 33.8688MHz (Pin10)
15
16
CLK33M
OE
33.8688MHz clock output
Output Enable (OPEN : enable, LOW : disable) : with pull-up
3/6
BU2286FV
Multimedia ICs
zInput output circuits
Pin No.
Equivalent circuit
Input Pin
14, 16
to inside IC
pull_up resistance
about 250kΩ
Output Pin
3, 4, 9, 10,
13, 15
from inside IC
Crystal Pin
7, 8
XTALIN
XTALOUT
to inside IC
4/6
BU2286FV
Multimedia ICs
zElectrical characteristics (Unless specified otherwise Ta=25°C, VDD=3.3V, crystal frequency=36.864MHz)
Parameter
Output "L" voltage
Output "H" voltage
Power supply current
CLK54M
Symbol
Min.
–
Typ.
–
Max.
0.4
–
Unit
V
Conditions
I
I
OL=4.0mA
V
OL
OH=−4.0mA
V
OH
2.4
–
–
V
no load
I
DD
30
50
–
mA
XTAL × 375 / 64 / 4
XTAL × 375 / 64 / 8
XTAL × 147 / 40 / 4
XTAL × 147 / 40 / 8
FSEL=OPEN, XTAL output
FSEL=L, XTAL × 147 / 40 / 4
FSEL=OPEN, XTAL / 2 output
FSEL=L, XTAL × 147 / 40 / 8
1/2VDD test
CLK54M
CLK27M
CLK33M
CLK16M
CLK768_H
CLK768_L
CLK384_H
CLK384_L
Duty
–
54
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
%
CLK27M
–
27
–
–
33.8688
16.9344
36.864
33.8688
18.432
16.9344
50
–
CLK33M
–
–
CLK16M
–
–
CLK768FS1
CLK384FS2
–
–
–
–
–
–
Duty
45
–
55
–
Jitter 1sigma
Jitter1
Jstd1
50
psec
psec
nsec
nsec
msec
dB
MIN-MAX level
Jitter2
Jstd2
–
300
–
Time between 0.2VDD to 0.8VDD
Time between 0.8VDD to 0.2VDD
1
Rise time
Fall time
Output LOCK time
S/N 27M
S/N 33M
tr
–
2.5
–
tf
–
2.5
–
tLOCK
–
–
1
2
S/N 27M
56
66
–
2
S/N 33M
50
60
–
dB
Jitter is meen value when using Time Interval Analyzer with 10000 sampling.
1) Time between voltage supply lead to 3.0V and output clock get stable. Start up time of power supply sources satisfy this rated value at every time, case.
2) Measure condition is (SPAN : 100kHz, RBW : 1kHz, VBW : 100Hz), and measure points are center of noise width at (27MHz±20kHz), (33.8688MHz±20kHz).
5/6
BU2286FV
Multimedia ICs
zApplication example
1
2
3
4
5
6
7
8
VDD 2
OE 16
CLK33M 15
FSEL 14
OPEN : Enable LOW : Disable
33.8688MHz
0.1µF
VSS 2
54MHz
27MHz
CLK54M
CLK27M
AVDD
Output select (Pin9, Pin10)
16.9344MHz
CLK16M 13
DVDD 12
DVSS 11
0.1µF
0.1µF
AVSS
33.8688MHz or 36.864MHz
16.9344MHz or 18.432MHz
XTALIN
XTALOUT
768FS1 10
384FS2
9
zOperating notes
The BU2286FV is basically placed on the board.
Decoupling capacitance (0.1µF) need to be placed between Pin5 (AVDD) and Pin6 (AVSS).
Also Decoupling capacitance (0.1µF) need to be placed between Pin1 (VDD2) and Pin2 (VSS2), Pin11 (DVSS) and Pin12
(DVDD).
To obtain accurate frequency , capacitance( pF) need to be placed between Pin7 (XTALIN) and Pin6 (AVSS),
Pin8 (XTALOUT) and Pin6 (AVSS).
Tantalum capacitance (10 ∼100µF) ,ferrite beads may need to be placed to prevent power supply drop
in certain boards case.
To reduce high frequency noise ,selected bypass capacitors (≤1Ω at problem high frequency) maybe used for power pin
as close to BU2286FV as possible.
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