BM81004MUV-ZE2 [ROHM]
Power Supply Support Circuit, Fixed, 6 Channel, VQFN-48;
| 型号： | BM81004MUV-ZE2 |
| 厂家： | 
ROHM |
| 描述： | Power Supply Support Circuit, Fixed, 6 Channel, VQFN-48 |
| 文件： | 总53页 (文件大小：2642K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet
Power supply IC series for TFT-LCD panels
12V Input Multi-Channel
System Power Supply IC
BM81004MUV
General Description
Key Specifications
BM81004MUV is a system power supply for TFT-LCD
panels used for liquid crystal TVs. This IC is
incorporated with Negative and Positive charge pump
controller and Gate Pulse Modulation (GPM) function. It
also features built-in EEPROM to contain each setting
voltage, soft start time etc.
Input voltage range：
8.6V to 14.0V
11.7V to 18.0V
2.2V to 3.7V
4.8V to 11.1V
25V to 40.5V
-10.2V to -4.0V
750kHz(Typ)
1MHz(Typ)
AVDD Output voltage range：
VIO Output voltage range：
HAVDD Output voltage range：
VGH Output voltage range：
VGL Output voltage range：
Switching Frequency：
Features
■ Step-up DC/DC converter (AVDD).
(Synchronous rectification, Built-in load switch).
■ Step-down DC/DC converter 1(VIO).
(Non-synchronous rectification).
■ Step-down DC/DC converter 2(VCORE).
■ Step-down DC/DC converter 3(HAVDD).
(Synchronous rectification).
Operating temperature range：
-40℃ to +105℃
Package
VQFN48V7070A
W(Typ) x D(Typ) x H(Max)
7.00mm x 7.00mm x 1.0mm
■ Positive charge pump controller (VGH).
■ Negative charge pump controller (VGL).
■ Gate Pulse Modulation (GPM) function.
■ High Voltage LDO (50mA)
■ 10 bit DAC-controlled Gamma Amplifier 4ch
■ 8 bit DAC-controlled VCOM Amplifier
■ Output voltage control by I2C.
■ Built-in EEPROM.
■ Switching Frequency 750kHz (AVDD, VIO).
■ Switching Frequency 1MHz (VCORE, HAVDD).
Applications
■ TFT-LCD panel
Typical Application Circuit 1
（TOP VIEW）
SW
SW
VGH
VIN
AVDD
HAVDD
SWB1
VGL
PGND2
SWB2
VDD2
VINB2
VINB1
VINB1
N.C.
PGATE
AVDDS
SWO
SWI
VCORE
AVDD
SW
VIN
SW
BM81004MUV
PGND
PGND
VL
SWB1
SWB1
AMPGND
AMP4
AMP3
VIO
COMP
AGND
CTRL
VIN
AVDD
Figure 1. Application Circuit 1
○Product structure：Silicon monolithic chip ○This chip is not designed for protection against ratio active rays.
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BM81004MUV
Typical Application Circuit 2
（TOP VIEW）
SW
SW
VGH
VIN
AVDD
HAVDD
SWB1
VGL
PGND2
SWB2
VDD2
VINB2
VINB1
VINB1
N.C.
PGATE
AVDDS
SWO
SWI
VCORE
AVDD
SW
VIN
SW
BM81004MUV
PGND
PGND
VL
SWB1
SWB1
AMPGND
AMP4
AMP3
VIO
COMP
AGND
CTRL
VIN
AVDD
Figure 2. Application Circuit 2
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BM81004MUV
Contents
General Description........................................................................................................................................................................1
Features..........................................................................................................................................................................................1
Applications ....................................................................................................................................................................................1
Typical Application Circuit 1 ............................................................................................................................................................1
Key Specifications...........................................................................................................................................................................1
Package..........................................................................................................................................................................................1
Typical Application Circuit 2 ............................................................................................................................................................2
Pin Configuration ............................................................................................................................................................................4
Pin Description................................................................................................................................................................................4
Block Diagram ................................................................................................................................................................................5
Description of each Block ...............................................................................................................................................................6
Absolute Maximum Ratings ............................................................................................................................................................7
Recommended Operating Ranges .................................................................................................................................................7
Electrical Characteristics.................................................................................................................................................................8
Typical Performance Curves.........................................................................................................................................................12
Timing Chart .................................................................................................................................................................................24
Example Application .....................................................................................................................................................................25
Protection function explanation of each block...............................................................................................................................26
Protection function list...................................................................................................................................................................29
Serial transmission .......................................................................................................................................................................30
Register Map ................................................................................................................................................................................33
Command Table 1.........................................................................................................................................................................34
Command Table 2.........................................................................................................................................................................35
Selecting Application Components ...............................................................................................................................................36
Layout Guideline .............................................................................................................................................................................41
Power Dissipation.........................................................................................................................................................................41
I/O Equivalence Circuit .................................................................................................................................................................42
Operational Notes.........................................................................................................................................................................45
Ordering Information.....................................................................................................................................................................47
Marking Diagram ..........................................................................................................................................................................47
Physical Dimension Tape and Reel Information............................................................................................................................48
Revision history ............................................................................................................................................................................49
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BM81004MUV
Pin Configuration
(TOP VIEW)
36
35
34
33
32
31
30
29
28
27
26
25
37
38
39
40
41
42
43
44
45
46
47
48
24
PGATE
PGND2
SWB2
VDD2
23 AVDDS
22
SWO
21
20
19
18
17
16
15
14
13
SWI
SW
VINB2
VINB1
VINB1
N.C.
SW
Thermal Pad
PGND
PGND
VL
SWB1
SWB1
AMPGND
AMP4
COMP
AGND
CTRL
AMP3
1
2
3
4
5
6
7
8
9
10
11
12
Figure 3. Pin Configuration
PIN No.
Pin Description
PIN No.
SYMBOL
FUNCTION
SYMBOL
FUNCTION
1
2
AMP2
AMP1
VDD1
PG
Gamma amplifier output pin 2
Gamma amplifier output pin 1
Step-down DC/DC output pin 1
Power GOOD signal output pin
Serial data input pin
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
VGL
DRVN
DRVP
VGH
Negative charge pump output pin
Negative charge pump drive pin
Positive charge pump drive pin
Positive charge pump output pin
GPM output pin
3
4
5
SDA
VGHM
RE
6
SCL
Serial clock input pin
GPM Slope adjustment pin
Power supply pin for Step-down DC/DC 3
―
7
A0
I2C address selected pin
Power supply input pin
VINB3
N.C.
8
AVIN
HVLDO
HVCC
VCOM
INN
9
High Voltage LDO output pin
VCOM and Gamma power supply pin
VCOM amplifier output pin
VCOM amplifier feedback pin
GPM control pin
SWB3
PGND3
VDD3
EN
Step-down DC/DC switching pin 3
Step-down DC/DC GND pin 3
Step-down DC/DC output pin 3
Enable pin
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CTRL
AGND
COMP
VL
PGND2
SWB2
VDD2
VINB2
VINB1
VINB1
N.C.
Step-down DC/DC GND pin 2
Step-down DC/DC switching pin 2
Step-down DC/DC output pin 2
Power supply pin for Step-down DC/DC 2
Power supply pin for Step-down DC/DC 1
Power supply pin for Step-down DC/DC 1
―
Analog GND pin
Error amplifier output pin
Internal REG output pin
Step-up DC/DC GND pin
Step-up DC/DC GND pin
Step-up DC/DC switching pin
Step-up DC/DC switching pin
Load switch input pin
PGND
PGND
SW
SW
SWB1
SWB1
AMPGND
AMP4
AMP3
Step-down DC/DC switching pin 1
Step-down DC/DC switching pin 1
Gamma amplifier GND pin
Gamma amplifier output pin 4
Gamma amplifier output pin 3
SWI
SWO
AVDDS
PGATE
Load switch output pin
Step-up DC/DC feedback pin
Load switch gate drive pin
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BM81004MUV
Block Diagram
AVDD
HVCC
HVCC
HVLDO
HVLDO
HVLDO
HVLDO
HVCC
+
COMP
OPAMP
-
VCOM
INN
PGATE
AVDDS
AVDD
HVCC
SWO
SWI
+
-
DAC
VIN
BOOST
AMP1
AMP2
AMP3
AMP4
CONVERTER
+
-
SW
PGND
+
-
VIN
VINB1
SWB1
+
-
BUCK
CONVERTER 1
VIO
AMPGND
VIN
VDD1
VINB2
VIN
INTERNAL
REGULATOR
AVIN
BUCK
CONVERTER 2
VCORE
VL
SWB2
PGND2
EEPROM
VDD2
VINB3
SWB3
BUCK
HAVDD
SDA
SCL
A0
CONVERTER 3
PGND3
I2C
INTERFACE
DAC
VDD3
DRVP
SW
VGH
SEQUENCE
CONTROL
REGULATOR
EN
PG
AVDD
SW
VGH
VGH
VGL
GPM
CTRL
VGHM
RE
AGND
VGL
DRVN
VGL
SWB1
Figure 4. Block Diagram
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BM81004MUV
Description of each Block
① BUCK CONVERTER BLOCK
2
This block generates VCORE (VDD2) voltage from Power supply voltage.
After releasing UVLO of VIN, VL starts activating. After Auto Read is operated to EEPROM, VCORE will be activated.
During operations, it is possible to prevent destruction of IC by OVP, UVP and OCP protection function.
② BUCK CONVERTER BLOCK
1
This block generates VIO (VDD1) voltage from Power supply voltage of VIO.
After completing VCORE start-up, VIO starts activating.
Power on Reset works at the time of VIN startup and the setting that is written to EEPROM will be reflected in Register.
During operations, it is possible to prevent destruction of IC by OVP, UVP and OCP protection function.
③ VGL REGULATOR BLOCK
This block generates VGL voltage.
After completing VCORE start-up, VGL starts activating.
Power on Reset works at the time of VIN startup and the setting that is written to EEPROM will be reflected in Register.
During operations, it is possible to prevent destruction of IC by UVP and OCP protection function.
④ BOOST CONVERTER BLOCK
This block generates AVDD (SWO) voltage from Power supply voltage.
It activates when EN=H, and under condition where VIO and VGL are activating.
Power on Reset works at the time of VIN startup and the setting that is written to EEPROM will be reflected in Register.
During operations, it is possible to prevent destruction of IC by OVP, UVP and OCP protection function.
⑤ BUCK CONVERTER BLOCK
3
This block generates HAVDD (VDD3) voltage from Power supply voltage.
HAVDD starts up following AVDD output voltage.
The setting voltage range of the HAVDD voltage depends on the AVDD setting voltage, and the lower limit level of the
HAVDD voltage is limited in AVDD×0.4.
Power on Reset works at the time of VIN startup and the setting that is written to EEPROM will be reflected in Register.
During operations, it is possible to prevent destruction of IC by OVP, UVP and OCP protection function.
⑥ HIGH VOLTAGE LDO BLOCK
This block generates HVLDO voltage from Power supply voltage of AVDD (HVCC).
HVLDO starts up following AVDD output voltage.
Power on Reset works at the time of VIN startup and the setting that is written to EEPROM will be reflected in Register.
During operations, it is possible to prevent destruction of IC by UVP and OCP protection function.
⑦ VCOM AMPLIFIER BLOCK
This block generates VCOM voltage from Power supply voltage of AVDD (HVCC). VCOM calibrator function is built-in.
VCOM starts up following AVDD output voltage.
Power on Reset works at the time of VIN startup and the setting that is written to EEPROM will be reflected in Register.
⑧ GAMMA AMPLIFIER BLOCK
This block generates AMP1 to 4 voltages from Power supply voltage of AVDD (HVCC).
AMP1 to 4 startup following AVDD output voltage.
Power on Reset works at the time of VIN startup and the setting that is written to EEPROM will be reflected in Register.
⑨ VGH REGULATOR BLOCK
This block generates VGH voltage from AVDD voltage.
After completing AVDD start-up, VGH starts activating.
Power on Reset works at the time of VIN startup and the setting that is written to EEPROM will be reflected in Register.
During operations, it is possible to prevent destruction of IC by OVP, UVP and OCP protection function.
⑩ GPM BLOCK
This is a switching circuit to drive a gate voltage for TFT that consist of PMOS FET.
VGHM output synchronizes with CTRL input and outputs High voltage = VGH at CTRL=H.
GPM Falling Limit voltage can be controlled by EEPROM.
※
Caution
・EN Input tolerant function is built in this IC. No need to be always EN < VIN.
・When PG pin is not used, PG pin must be connected to GND, or it should be open.
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BM81004MUV
Absolute Maximum Ratings
Limits
Parameter
Symbol
Unit
MIN
-0.3
-0.3
-0.3
-0.3
-0.3
TYP
MAX
24
20
7
AVIN, VINB1, VINB2, VINB3
-
-
-
-
-
V
V
V
V
V
Supply Voltage
Input Voltage
HVCC
SDA, SCL, A0, EN, CTRL
VL
6.5
7
COMP, PG
SW, SWI, SWO,
PGATE, AVDDS, VDD1, SWB1,
VDD2, SWB2, VDD3, SWB3
-0.3
-
24
V
Output Voltage
HVLDO, VCOM, INN
AMP1, AMP2, AMP3, AMP4
-0.3
-15
-0.3
-40
-55
-
-
20
7
V
VGL, DRVN
-
V
DRVP, VGH, VGHM, RE
-
48
V
℃
Operating Ambient
Temperature Range
Ta
-
-
105
150
150
Storage Temperature
Range
Tstg
℃
Maximum Continuous
Junction Temperature
Tjmax (*1)
Pd
-
℃
5.08
24.6
W
Power Dissipation (*2)
Θja
degC/W
*1
It shows junction temperature when stores.
*2 Derate by 40.6mW/℃ at Ta>25℃(on 4-layer 76.2mm×114.3mm×1.6mm glass epoxy board).
Recommended Operating Ranges
(Ta=-40℃～105℃)
Limits
Parameter
Symbol
Unit
MIN
8.6
-0.1
-0.1
-
TYP
MAX
14
Supply Voltage
AVIN
EN, A0, CTRL
SDA, SCL
FCLK
-
-
-
-
V
V
Functional pin voltage
2 wire serial pin voltage
2 wire serial frequency
5.5
5.5
V
400
kHz
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BM81004MUV
Electrical Characteristics
(Unless otherwise specified, Ta=25℃, AVIN,VINB1,VINB2,VINB3=12V)
Limits
Parameter
【 GENERAL 】
Symbol
Unit
Condition
MIN
TYP
MAX
8.0
7.25
155
600
800
4.9
-
8.3
7.55
175
750
1000
5
8.6
7.85
195
900
1200
5.1
V
V
VIN rising
VIN falling
VIN Under Voltage
Lockout Threshold
VIN_
UVLO
Thermal shutdown
TSD
FOSC1
FOSC2
VL
℃
Design guarantee
Internal Oscillator Frequency 1
Internal Oscillator Frequency 2
VL Voltage
kHz
kHz
V
AVDD, VIO, 0 < Ta < 50℃
VCORE, HAVDD, 0 < Ta < 50℃
Consumption Current
ICC
5.4
-
mA
Not Switching
【 LOGIC SIGNALS SDA, SCL, EN, A0, CTRL 】
High Level Input Voltage
Low Level Input Voltage
Minimum Output Voltage
Pull-Down Resistance
VIH
VIL
2
-
-
V
V
-
-
-
-
0.5
0.4
260
VSDA
RLOGIC
V
SDA, ISDA=3mA
EN, A0, CTRL
140
200
kΩ
【 BOOST CONVERTER (AVDD) 】
Output Voltage Range
AVDD
11.7
-
15.6
0
18.0
15.756
10
V
V
0.1V step
Regulation Voltage
AVDD_R
ILK_SWH
RON_SWH
ILK_SWL
RON_SWL
RON_LS
15.444
27h, 1%, 0 < Ta < 50℃
SWI=18V, SW=0V
ISW=-500mA
SW=18V
Hi-Side Leakage Current
Hi-Side SW ON-Resistance
Lo-Side SW Leakage Current
Lo-Side SW ON-Resistance
Load SW ON-Resistance
SW Current Limit
-
uA
mΩ
uA
mΩ
mΩ
A
-
100
0
200
10
-
-
100
100
5
200
200
5.75
2.8
21
ISW=500mA
ILS=500mA
-
4.25
0
5.0A – Offset(0.0A) setting
L=6.8uH, 0 < Ta < 50℃
ILIM_SW
ILIM_SET
SW Current Limit Offset
Over-Voltage Protection Rise
Over-Voltage Protection Fall
AVDD UVP Detecting Voltage
Soft Start Time
-
A
0.4A step
VOVP_AVD
D_RISE
18
-
19.5
18
V
VOVP_AVD
D_FALL
-
V
VUVP_
AVDD
AVDD
x 0.8
-
-
V
TSS_
AVDD
10
-
-
7
20
msec
A
Load Switch Current Limit
ILIM_LSW
ILIM_EXT
-
External Load Switch
Current Limit
450
-
540
10
630
-
mV
uA
PGATE_
DRV
PGATE Drive Capability
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BM81004MUV
Electrical Characteristics
(Unless otherwise specified, Ta=25℃, AVIN,VINB1,VINB2,VINB3=12V)
Limits
Parameter
Symbol
Unit
Condition
MIN
TYP
MAX
【 BUCK CONVERTER 1 (VIO) 】
Output Voltage Range
VIO
2.2
-
3.7
3.366
10
V
V
0.1V step
Regulation Voltage
VIO_R
3.234
3.3
0
0Bh, 2%, 0 < Ta < 50℃
VINB1=18V, SWB1=0V
SWB1=-500mA
ILK_
SWB1H
Hi-Side SWB1 Leak Current
Hi-Side SWB1 ON-Resistance
SWB1 Current Limit
-
-
uA
mΩ
A
RON_
SWB1H
200
3.5
300
4.2
ILIM_
SWB1
2.8
L=6.8uH, 0 < Ta < 50℃
VOVP_
VIO
VIO
x 1.03
VIO
x 1.1
VIO
x 1.17
VIO Over-Voltage Protection
VIO UVP Detecting Voltage
V
VUVP_
VIO
VIO
x 0.8
-
-
-
-
V
Frequency 1/4
Soft Start Time
TSS_VIO
3.3
msec VIO=3.3V
【 BUCK CONVERTER 2 (VCORE) 】
VCORE_
REF
VCORE Reference Voltage
0.396
0.400
0.400
0
0.404
0.406
10
V
V
1%, Ta=25℃
0.394
1.5%, 0 < Ta < 50℃
VINB2=18V, SWB2=0V
SWB2=-500mA
ILK_
SWB2H
Hi-Side SWB2 Leak Current
Hi-Side SWB2 ON-Resistance
Lo-Side SWB2 Leak Current
Lo-Side SWB2 ON-Resistance
SWB2 Current Limit
-
uA
mΩ
uA
mΩ
A
RON_
SWB2H
-
-
175
0
300
10
ILK_
SWB2L
SWB2=18V
RON_
SWB2L
-
175
3.0
300
3.6
SWB2=500mA
ILIM_
SWB2
2.4
L=6.8uH, 0 < Ta < 50℃
VCORE Over-Voltage
Protection
VOVP_
VCORE
VCORE VCORE VCORE
V
x 1.03
x 1.1
x 1.17
VUVP_
VCORE
VCORE
x 0.8
VCORE UVP Detecting Voltage
Soft Start Time
-
-
V
Frequency 1/4
TSS_
VCORE
-
3
-
msec
【 BUCK CONVERTER 3 (HAVDD) 】
Output Voltage Range
HAVDD
4.8
-
11.1
7.92
10
V
V
0.1V step
Regulation Voltage
HAVDD_R
7.68
7.8
0
1Eh, 1.5%, 0 < Ta < 50℃
VINB3=18V, SWB3=0V
SWB3=-500mA
ILK_
SWB3H
Hi-Side SWB3 Leak Current
Hi-Side SWB3 ON-Resistance
Lo-Side SWB3 Leak Current
Lo-Side SWB3 ON-Resistance
SWB3 Current Limit
-
uA
mΩ
uA
mΩ
A
RON_
SWB3H
-
-
300
0
500
10
ILK_
SWB3L
SWB3=18V
RON_
SWB3L
-
300
1.8
500
2.4
SWB3=500mA
ILIM_
SWB3
1.2
L=6.8uH, 0 < Ta < 50℃
HAVDD Over-Voltage
Protection
VOVP_
HAVDD
HAVDD
x 1.03
HAVDD
x 1.1
HAVDD
x 1.17
V
VUVP_
HAVDD
HAVDD
x 0.8
HAVDD UVP Detecting Voltage
-
-
V
Frequency 1/4
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BM81004MUV
Electrical Characteristics
(Unless otherwise specified, Ta=25℃, AVIN,VINB1,VINB2,VINB3=12V)
Limits
Parameter
Symbol
Unit
Condition
MIN
TYP
MAX
【 VGH REGULATOR 】
Output Voltage Range
VGH
25
-
40.5
V
V
0.5V step
14h, 1.5%, 0 < Ta < 50℃
Io=5mA
Regulation Voltage
VGH_R
34.47
35
-
35.53
ILIM_
DRVP
Over-Current Protection
VGH Over-Voltage Protection
VGH UVP Detecting Voltage
5
42
-
-
48
-
mA
V
VOVP_
VGH
45
VUVP_
VGH
VGH
x 0.8
V
Soft Start Time
TSS_VGH
-
7
-
msec VGH=35V
【 VGL REGULATOR 】
Output Voltage Range
VGL
-10.2
-
-4.0
V
V
0.2V step
0Ah, 1.5%, Ta=25℃
Io=5mA
Regulation Voltage
VGL_R
-6.09
-6
-5.91
0Ah, 2.0%, 0 < Ta < 50℃
Io=5mA
-6.12
-6
-5.88
V
ILIM_
DRVN
Over-Current Protection
VGL UVP Detecting Voltage
Delay Time
5
-
-
-
-
-
mA
V
VUVP_
VGL
VGL×0.8
2.5
TDLY_VGL
-
msec
【 GATE PULSE MODULATION (GPM) 】
VGH-VGHM ON-Resistance
RE-VGHM ON-Resistance
Propagation Delay
RGHH
RGHL
TGPM
-
-
3
3
5
-
Ω
Ω
150
250
350
nsec
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TSZ02201-0313AAF00420-1-2
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10/49
TSZ22111 • 15 • 001
BM81004MUV
Electrical Characteristics
(Unless otherwise specified, Ta=25℃, AVIN,VINB1,VINB2,VINB3=12V)
Limits
Parameter
Symbol
Unit
Condition
MIN
TYP
MAX
【 HIGH VOLTAGE LDO 】
LDO
11.7
15.12
15.09
-
－
15.2
18.0
15.28
15.31
-
V
V
0.1V step
23h, 0.5%
Output Voltage Range
Regulation Voltage
LDO_R
LDO_R
15.2
V
23h, 0.7%, 0 < Ta < 50℃
ILIM_
LDO
Over-Current Protection
100
mA
V
-
LDOx0.8
-
HVLDO UVP Detecting Voltage LDO_UVP
【 VCOM AMPLIFIER 】
HVLDO
X0.36
HVLDO
X0.54
－
30
V
Output Voltage Range
Slew Rate
VCOM_R
SR
-
-
-
-
-
-
V/usec No external components
Output Current Capability
Load Stability
I_VCOM
ΔVO1
RES1
LE1
±200
±15
8
mA
mV
Bit
C2h
Io=-50mA～50mA
DAC Resolution
DAC Integral Non-linearity Error
(INL)
02～FD is the allowable margin
of error against the ideal linear.
02～FD is the allowable margin
of error against the ideal
increase of 1LSB.
-1
-1
-
+1
+1
LSB
DAC Differential Non-linearity
Error (DNL)
DLE1
-
LSB
【 GAMMA AMPLIFIER 】
Output Current Capability
I_AMP
ΔVO2
RES2
30
-
-
-
-
mA
mV
Bit
Load Stability
±15
10
Io=-5mA～5mA
DAC Resolution
00F ～ 3F0 is the allowable
margin of error against the ideal
linear.
00F ～ 3F0 is the allowable
margin of error against the ideal
increase of 1LSB.
DAC Integral Non-linearity Error
(INL)
LE2
-2
-2
-
-
+2
+2
LSB
LSB
DAC Differential Non-linearity
Error (DNL)
DLE2
○This product has no designed for protection against radioactive rays.
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11/49
TSZ22111 • 15 • 001
BM81004MUV
Typical Performance Curves
(Unless otherwise specified, Ta=25℃, AVIN,VINB1,VINB2,VINB3=12V, VIO=3.3V, VCORE=1.2V,
AVDD=15.6V, HAVDD=7.8V, VGH=35V, VGL=-6.0V, HVLDO=15.2V, VCOM=6.1V, GAMMA=7.8V, RL=no load)
1500
1400
1300
1200
1100
1000
900
8
7
6
5
4
3
2
1
0
AVDD,VIO Frequency
EN=L
No Switching
800
700
VCORE,HAVDD Frequency
600
500
5
6
7
8
9
10 11 12 13 14 15
5
6
7
8
9
10 11 12 13 14 15
Input Voltage : V [V]
Input Voltage : V [V]
IN
IN
Figure 5. Input Current vs Input Voltage
(EN=L, no switching)
Figure 6. Internal Oscillator Frequency vs Input Voltage
Figure 7. Power-on (till AVDD and VGH on)
Figure 8. Power-on (after AVDD on)
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© 2014 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
TSZ02201-0313AAF00420-1-2
4.Dec.2014 Rev.002
12/49
BM81004MUV
Typical Performance Curves
(Unless otherwise specified, Ta=25℃, AVIN,VINB1,VINB2,VINB3=12V, VIO=3.3V, VCORE=1.2V,
AVDD=15.6V, HAVDD=7.8V, VGH=35V, VGL=-6.0V, HVLDO=15.2V, VCOM=6.1V, GAMMA=7.8V, RL=no load)
3
2
100
90
80
70
60
50
40
30
20
10
0
1
0
-1
-2
-3
VIN=12V
VIO=3.3V
VIN=12V
VIO=3.3V
0
200
400
600
800
1000
0
200
400
600
800 1000 1200 1400
Output Current [mA]
Output Current [mA]
Figure 9. VIO Efficiency vs Output Current
Figure 10. VIO Output Voltage vs Output Current
VIO (10mV/Div AC)
VIO (100mV/Div AC)
ΔV：6.3mV
SWB1 (10V/Div)
ISWB1 (500mA/Div)
IOUT (500mA/Div)
IOUT=500mA
IOUT=100mA
IOUT (500mA/Div)
1usec/Div
50usec/Div
Figure 11. VIO Load Transient
Figure 12. VIO Switching
(Output Current=500mA)
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13/49
TSZ22111 • 15 • 001
BM81004MUV
Typical Performance Curves
(Unless otherwise specified, Ta=25℃, AVIN,VINB1,VINB2,VINB3=12V, VIO=3.3V, VCORE=1.2V,
AVDD=15.6V, HAVDD=7.8V, VGH=35V, VGL=-6.0V, HVLDO=15.2V, VCOM=6.1V, GAMMA=7.8V, RL=no load)
3
2
100
90
80
70
60
50
40
30
20
10
0
1
0
VIN=12V
VCORE=1.2V
-1
-2
-3
VIN=12V
VCORE=1.2V
0
200
400
600
800
1000
0
200
400
600
800 1000 1200 1400
Output Current [mA]
Output Current [mA]
Figure 13. VCORE Efficiency vs Output Current
Figure 14. VCORE Output Voltage vs Output Current
VCORE (10mV/Div AC)
VCORE (100mV/Div AC)
ΔV：6.4mV
SWB2 (10V/Div)
IOUT=300mA
ISWB2 (500mA/Div)
IOUT (500mA/Div)
IOUT=10mA
IOUT (200mA/Div)
50usec/Div
1usec/Div
Figure 15. VCORE Load Transient
Figure 16. VCORE Switching
(Output Current=500mA)
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© 2014 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
TSZ02201-0313AAF00420-1-2
4.Dec.2014 Rev.002
14/49
BM81004MUV
Typical Performance Curves
(Unless otherwise specified, Ta=25℃, AVIN,VINB1,VINB2,VINB3=12V, VIO=3.3V, VCORE=1.2V,
AVDD=15.6V, HAVDD=7.8V, VGH=35V, VGL=-6.0V, HVLDO=15.2V, VCOM=6.1V, GAMMA=7.8V, RL=no load)
100
90
80
70
60
50
40
30
20
10
0
3
2
1
0
VIN=12V
-1
-2
-3
AVDD=15.6V
HAVDD=7.8V
(source)
VIN=12V
AVDD=15.6V
HAVDD=7.8V
（source)
0
200
400
600
800 1000 1200 1400
0
200
400 600
Output Current [mA]
800
1000
Output Current [mA]
Figure 17. HAVDD Efficiency vs Output Current (source)
Figure 18. HAVDD Output Voltage vs Output Current (source)
HAVDD (10mV/Div AC)
HAVDD (100mV/Div AC)
ΔV：6.8mV
SWB3 (10V/Div)
IOUT=350mA
ISWB3 (500mA/Div)
IOUT (500mA/Div)
IOUT=0mA
IOUT (300mA/Div)
200usec/Div
1usec/Div
Figure 19. HAVDD Load Transient (source)
Figure 20. HAVDD Switching (source)
(Output Current=500mA)
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© 2014 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
TSZ02201-0313AAF00420-1-2
15/49
4.Dec.2014 Rev.002
BM81004MUV
Typical Performance Curves
(Unless otherwise specified, Ta=25℃, AVIN,VINB1,VINB2,VINB3=12V, VIO=3.3V, VCORE=1.2V,
AVDD=15.6V, HAVDD=7.8V, VGH=35V, VGL=-6.0V, HVLDO=15.2V, VCOM=6.1V, GAMMA=7.8V, RL=no load)
100
90
80
70
60
50
40
30
20
10
0
3
2
1
0
VIN=12V
-1
-2
-3
AVDD=15.6V
HAVDD=7.8V
(sink)
VIN=12V
AVDD=15.6V
HAVDD=7.8V
（sink)
0
200
400
600
800 1000 1200 1400
0
200
400 600
Output Currnet [mA]
800
1000
Output Current [mA]
Figure 21. HAVDD Efficiency vs Output Current (sink)
Figure 22. HAVDD Output Voltage vs Output Current (sink)
HAVDD (10mV/Div AC)
ΔV：9.4mV
HAVDD (100mV/Div AC)
SWB3 (10V/Div)
ISWB3 (500mA/Div)
IOUT (500mA/Div)
IOUT (300mA/Div)
IOUT=350mA
IOUT=0mA
1usec/Div
200usec/Div
Figure 23. HAVDD Load Transient (sink)
Figure 24. HAVDD Switching (sink)
(Output Current=500mA)
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TSZ02201-0313AAF00420-1-2
4.Dec.2014 Rev.002
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16/49
TSZ22111 • 15 • 001
BM81004MUV
Typical Performance Curves
(Unless otherwise specified, Ta=25℃, AVIN,VINB1,VINB2,VINB3=12V, VIO=3.3V, VCORE=1.2V,
AVDD=15.6V, HAVDD=7.8V, VGH=35V, VGL=-6.0V, HVLDO=15.2V, VCOM=6.1V, GAMMA=7.8V, RL=no load)
100
90
80
70
60
50
40
30
20
10
0
3
2
1
0
VIN=12V
AVDD=15.6V
-1
-2
-3
VIN=12V
AVDD=15.6V
0
200
400
600
800 1000 1200 1400
0
200
400 600
Output Current [mA]
800
1000
Output Current [mA]
Figure 25. AVDD Efficiency vs Output Current
Figure 26. AVDD Output Voltage vs Output Current
AVDD (10mV/Div AC)
AVDD (200mV/Div AC)
SW (10V/Div )
ΔV：18.0mV
IOUT=500mA
ISW (1A/Div )
IOUT=100mA
IOUT (500mA/Div )
IOUT (500mA/Div )
50usec/Div
1usec/Div
Figure 27. AVDD Load Transient
Figure 28. AVDD Switching
(Output Current=500mA)
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TSZ02201-0313AAF00420-1-2
4.Dec.2014 Rev.002
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17/49
TSZ22111 • 15 • 001
BM81004MUV
Typical Performance Curves
(Unless otherwise specified, Ta=25℃, AVIN,VINB1,VINB2,VINB3=12V, VIO=3.3V, VCORE=1.2V,
AVDD=15.6V, HAVDD=7.8V, VGH=35V, VGL=-6.0V, HVLDO=15.2V, VCOM=6.1V, GAMMA=7.8V, RL=no load)
3
VGH (200mV/Div AC)
2
1
0
IOUT=50mA
IOUT=10mA
-1
VIN=12V
IOUT (50mA/Div)
AVDD=15.6V
VGH=35V
-2
-3
200usec/Div
10
30
50
70
Output Current [mA]
90
110
130
150
Figure 29. VGH Load Transient
Figure 30. VGH Output Voltage vs Output Current
VGH (20mV/Div AC)
ΔV：38.7mV
SW (10V/Div )
IOUT=50mA
IOUT (50mA/Div )
5usec/Div
Figure 31. VGH Ripple Voltage
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TSZ02201-0313AAF00420-1-2
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18/49
TSZ22111 • 15 • 001
BM81004MUV
Typical Performance Curves
(Unless otherwise specified, Ta=25℃, AVIN,VINB1,VINB2,VINB3=12V, VIO=3.3V, VCORE=1.2V,
AVDD=15.6V, HAVDD=7.8V, VGH=35V, VGL=-6.0V, HVLDO=15.2V, VCOM=6.1V, GAMMA=7.8V, RL=no load)
3
2
VGL (100mV/Div AC)
1
0
IOUT=50mA
IOUT=10mA
-1
VIN=12V
IOUT (50mA/Div)
VGL=-6.0V
-2
-3
200usec/Div
10
30
50
70
Output Current [mA]
90
110
130
150
Figure 32. VGL Load Transient
Figure 33. VGL Output Voltage vs Output Current
ΔV：28.2mV
SWB1 (10V/Div )
IOUT=50mA
IOUT (50mA/Div )
5usec/Div
Figure 34. VGL Ripple Voltage
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TSZ02201-0313AAF00420-1-2
4.Dec.2014 Rev.002
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19/49
TSZ22111 • 15 • 001
BM81004MUV
Typical Performance Curves
(Unless otherwise specified, Ta=25℃, AVIN,VINB1,VINB2,VINB3=12V, VIO=3.3V, VCORE=1.2V,
AVDD=15.6V, HAVDD=7.8V, VGH=35V, VGL=-6.0V, HVLDO=15.2V, VCOM=6.1V, GAMMA=7.8V, RL=no load)
CTRL (5V/Div)
VGHM (5V/Div)
CTRL (5V/Div)
VGHM (5V/Div)
Delay=255nsec
Delay=270nsec
VGH=28V
VGH=28V
No Capacitive Load
RE Resister=0Ω
No Capacitive Load
RE Resister=0Ω
500nsec/Div
500nsec/Div
Figure 35. GPM Propagation Delay (rise)
Figure 36. GPM Propagation Delay (fall)
CTRL (5V/Div)
Clamp Voltage 20V
VGHM (10V/Div)
500usec/Div
Figure 37. GPM Clamp Voltage (20V Clamp)
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4.Dec.2014 Rev.002
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20/49
TSZ22111 • 15 • 001
BM81004MUV
Typical Performance Curves
(Unless otherwise specified, Ta=25℃, AVIN,VINB1,VINB2,VINB3=12V, VIO=3.3V, VCORE=1.2V,
AVDD=15.6V, HAVDD=7.8V, VGH=35V, VGL=-6.0V, HVLDO=15.2V, VCOM=6.1V, GAMMA=7.8V, RL=no load)
3
2
1
0
-1
VIN=12V
AVDD=15.6V
HVLDO=15.2V
-2
-3
0
20
40 60
Output Current [mA]
80100
Figure 38. HVLDO Output Voltage vs Output Current
3
2
1
0
3
2
1
0
-1
-1
-2
-3
VIN=12V
VIN=12V
AVDD=15.6V
HVLDO=15.2V
GAMMA=7.8V
AVDD=15.6V
HVLDO=15.2V
VCOM=6.1V
-2
-3
-200 -150 -100 -50
0
50 100 150 20
-20 -15 -10
-5
Output Current [mA]
0
5
10
15
20
Output Current [mA]
Figure 39. VCOM Output Voltage vs Output Current
Figure 40. GAMMA Output Voltage vs Output Current
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TSZ02201-0313AAF00420-1-2
4.Dec.2014 Rev.002
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21/49
TSZ22111 • 15 • 001
BM81004MUV
Typical Performance Curves
(Unless otherwise specified, Ta=25℃, AVIN,VINB1,VINB2,VINB3=12V, VIO=3.3V, VCORE=1.2V,
AVDD=15.6V, HAVDD=7.8V, VGH=35V, VGL=-6.0V, HVLDO=15.2V, VCOM=6.1V, GAMMA=7.8V, RL=no load)
VCOM (5V/Div)
S/R = 43.6V/us
VCOM (5V/Div)
S/R = 43.3V/us
100nsec/Div
100nsec/Div
Figure 41. VCOM Slew Rate（Rise）
Figure 42. VCOM Slew Rate（Fall）
1
0.5
0
1
0.5
0
000h
0FF
000h
0FF
-0.5
-1
-0.5
-1
BIT
BIT
Figure 43. VCOM DNL vs BIT
Figure 44. VCOM INL vs BIT
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TSZ22111 • 15 • 001
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4.Dec.2014 Rev.002
22/49
BM81004MUV
Typical Performance Curves
(Unless otherwise specified, Ta=25℃, AVIN,VINB1,VINB2,VINB3=12V, VIO=3.3V, VCORE=1.2V,
AVDD=15.6V, HAVDD=7.8V, VGH=35V, VGL=-6.0V, HVLDO=15.2V, VCOM=6.1V, GAMMA=7.8V, RL=no load)
2
1
0
2
1
0
000h
3FF
000h
3FF
-1
-2
-1
-2
BIT
BIT
Figure 45. GAMMA DNL vs BIT
Figure 46. GAMMA INL vs BIT
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TSZ02201-0313AAF00420-1-2
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23/49
TSZ22111 • 15 • 001
BM81004MUV
Timing Chart
ON and OFF Sequence of this IC are shown below.
VIN_
UVLO
VIN_
UVLO
VIN
VL_
UVLO
VL
TEAR
TSS_VCORE / 3.0ms
TSS_VIO / 3.3ms
EEPROM
Auto Read
VCORE
VIO
VGL
VGL
DELAY
TDLY_VGL / 2.5ms
(internal)
EN
TSS_AVDD
TSS_LSW / 10ms
Load Swith ON
AVDD
HAVDD
TSS_VGH / 7ms
VGH
CTRL
VGHM
VGHM = RE
VGHM = VGH
Figure 47. Timing Chart
VL activates with UVLO release of VIN.
It reads EEPROM data by Auto Read operation after VL finish its activation.
After Auto Read completion, VCORE activates. The Soft Start time of VCORE is 3msec.
(TEAR=2msec)
After VCORE soft-start completion, VIO activates. The Soft Start time of VIO is 3.3msec if the setting is 3.3V.
After VIO soft-start completion, PG becomes high and VGL activates. (If SWB1 is used)
The Soft Start time of VGL depends on output voltage setting, external capacitor etc.
2.5msec after VIO soft-start completion, Load SW turns ON (10msec) because of EN=High and AVDD activates.
The Soft Start time of AVDD can be changed by register setting. (10msec or 20msec)
After AVDD started, VGH activates. The Soft Start time of VGH is 7msec if the setting is 35V.
After VGH started, CTRL rising or falling will be a trigger to activate GPM operation.
When VGHM voltage at CTRL =L reaches the GPM clamp voltage, VGHM output is high impedance.
GPM, VGH, AVDD, HAVDD shuts down when EN=Low. GPM output (VGHM) will be the same potential with RE.
All output shuts down when UVLO of VIN is detected. VGHM will be the same potential with VGH.
AVDD
HVLDO
HVLDO, HAVDD and VCOM starts up followed by
AVDD output voltage. AMP 1 to 4 startup followed by
HVLDO output voltage.
HAVDD
When EN=low, AVDD and HAVDD output become
VCOM
high impedance. HVLDO, VCOM and AMP1 to 4
output shut down followed by AVDD till AVDD is
AMP1-4
below a certain level.
EN
Figure 48. Timing Chart 2
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TSZ02201-0313AAF00420-1-2
4.Dec.2014 Rev.002
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24/49
TSZ22111・15・001
BM81004MUV
Example Application
（TOP VIEW）
SW
SW
RFP2
CFP2
CFP4
QP
CFP3
CFP1 RFP1
AVDD
VGH
VIN
C31
DFP2
DFP1
C28
RQP
RQN
QN
HAVDD
L35
C35
CFN2
R30
DFN1
SWB1
VGL
CFN1 RFN1
C39
PGND2
SWB2
VDD2
VINB2
VINB1
VINB1
N.C.
PGATE
AVDDS
SWO
SWI
C25
L39
VCORE
AVDD
R39_2 R39_1 C39_0
C40
C22
SW
VIN
SW
C41
BM81004MUV
L19
C19
PGND
PGND
VL
D45
SWB1
SWB1
AMPGND
AMP4
AMP3
L3
VIO
C3
COMP
AGND
CTRL
C54
C53
C52
C51
VIN
C9
C8
AVDD
Figure 49. Example Application
Parts
Application circuit components list
Parts
name
Value
Company
Parts Number
Value
Company
Parts Number
name
C3
C8
4x 10 [uF]
1 [uF]
MURATA
MURATA
MURATA
MURATA
MURATA
MURATA
MURATA
MURATA
MURATA
MURATA
MURATA
MURATA
MURATA
MURATA
MURATA
MURATA
MURATA
MURATA
MURATA
MURATA
MURATA
GRM21BB31A106KE18
GRM188B31E105KA75
GRM31CB31E106KA75
GRM31CB31E106KA75
GRM31CB31E106KA75
GRM188B11E682KA01
GRM188CB31E105KA75
GRM31CB31E106KA75
GRM31CB31E106KA75
GRM219B31C475KE15
GRM188B31H104KA92
GRM188B11H471KA01
GRM188B31H104KA92
GRM188B31H104KA92
GRM21BB31H105KA12
GRM188B11H222KA01
GRM31CB31H106KA12
GRM31CB31E106KA75
GRM31CB31E106KA75
GRM21BB31A106KE18
GRM188B31H104KA92
C40
C41
10 [uF]
MURATA
MURATA
MURATA
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
GRM31CB31E106KA75
GRM31CB31E106KA75
GRM188B31H104KA92
MCR03
2x 10 [uF]
0.1 [uF]
2.7 [kΩ]
300 [Ω]
330 [Ω]
120 [Ω]
2.2 [Ω]
2.2 [Ω]
100 [kΩ]
100 [kΩ]
6.8 [uH]
6.8 [uH]
6.8 [uH]
6.8 [uH]
-
C9
10 [uF]
C51-54
R15
C10
10 [uF]
C11
10 [uF]
R30
MCR25
C15
6.8 [nF]
1 [uF]
R39_1
R39_2
RFN1
RFP1-2
RQN
RQP
L19
MCR03
C16
MCR03
C19
2x 10 [uF]
4x 10 [uF]
4.7 [uF]
0.1 [uF]
470 [pF]
0.1 [uF]
0.1 [uF]
1 [uF]
MCR25
C22
MCR25
C25
MCR03
CFN1
CFN2
CFP1
CPF2
CPF3
CFP4
C28
MCR03
TAIYO YUDEN
TAIYO YUDEN
TAIYO YUDEN
TAIYO YUDEN
ROHM
NS10165T6R8N
NRS8040T6R8M
NRS8040T6R8M
NRS8040T6R8M
RSX301L-30
RB558W
L3
L35
L39
2.2 [nF]
10 [uF]
D45
DFN1
DFP1
DFP2
QN
-
ROHM
C31
10 [uF]
-
ROHM
RB558W
C35
2x 10 [uF]
4x 10 [uF]
22 [nF]
-
ROHM
RB558W
C39
PNP
ROHM
2SCR513P
C39_0
QP
NPN
ROHM
2SAR513P
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Protection function explanation of each block
1. BUCK CONVERTER BLOCK 1 (VIO)
1-1. Over Voltage Protection (OVP)
OVP function is incorporated to prevent IC or other components from malfunctioning due to rising VIO voltage.
Voltage inputted to VDD1 pin is monitored and if VIO voltage reaches VIO>110% (Typ), it is considered as unusual
condition thus, OVP function is operated. If OVP is detected, switching is stopped until OVP release voltage (100%, Typ)
falls to VIO voltage. After OVP is released, switching is re-started.
1-2. Over Current Protection (OCP)
If excessive load current (SWB1 peak current>3.5A, Typ) is present, it limits current to flow to built–in Power MOS by
controlling Switching.
1-3. Under Voltage Protection (UVP)
Timer-latch type output UVP function is built-in.
When unusual condition (VIO<80%) is detected, SWB1 frequency is divided into 1/4 and UVP timer starts.
If the unusual condition continues up to 10msec (Typ), all output will be latched in shutdown state. Power reset is needed to
remove the latch state and to re-start.
2. BUCK CONVERTER BLOCK 2 (VCORE)
2-1. Over Voltage Protection (OVP)
OVP function is incorporated to prevent IC or other components from malfunctioning due to rising VCORE voltage.
Voltage inputted to VDD2 pin is monitored and if VCORE voltage reaches VCORE>110%(Typ), it is considered as unusual
condition thus, OVP function is operated. If OVP is detected, switching is stopped until OVP release voltage (100%,Typ)
falls to VCORE voltage. After OVP is released, switching is re-started.
2-2. Over Current Protection (OCP)
If excessive load current (SWB2 peak current>3.0A, Typ) is present, it limits current to flow to built–in Power MOS by
controlling Switching.
2-3. Under Voltage Protection (UVP)
Timer-latch type output UVP function is built-in.
When unusual condition (VCORE<80%) is detected, SWB2 frequency is divided into 1/4 and UVP timer starts.
If the unusual condition continues upto 10msec (Typ), all output will be latched in shutdown state. Power reset is needed to
remove the latch state and to re-start.
3. VGL REGULATOR BLOCK
3-1. Over Current Protection (OCP)
If excessive load current (I_DRVN>5mA, Min) is present, It controls source current (Base current of NPN Tr) of DRVN.
3-2. Under Voltage Protection (UVP)
Timer-latch type output UVP function is built in.
When unusual condition is detected (VGL>80%), UVP time counter get started, and if the unusual condition continues up to
10msec (Typ), all output is latched in shutdown condition. Power reset is needed to cancel the latch state and to re-start.
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4. BOOST CONVERTER BLOCK (AVDD)
4-1. Over Voltage Protection (OVP)
OVP function is built in to prevent IC or other components from malfunctioning due to excessive rise in AVDD voltage.
The voltage inputted to SWO pin is being monitored. If the SWO pin voltage becomes 19.5V (Typ), OVP is detected. Once
OVP is detected, switching is stopped. After AVDD voltage falls below OVP detection release voltage 18V (Typ), switching
is restarted.
4-2. Over Current Protection (OCP)
If excessive load current over 5A (Typ) of SW peak current is present, OCP limits current to rush to built-in Power MOS by
controlling its output switching.
4-3. Under Voltage Protection (UVP)
Timer-latch type output UVP function is built in.
When an unusual condition is detected (AVDD<80%), UVP timer starts. If the unusual condition continues upto 10msec
(Typ), all output is latched in shutdown condition. Power reset is needed to remove the latch state and to re-start.
4-4. Load Switch Over Current Protection (LSW_OCP)
If excessive load current (7A, Typ) is present, It controls current of load switch.
5. BUCK CONVERTER BLOCK 3 (HAVDD)
5-1. Over Voltage Protection (OVP)
OVP function is incorporated for preventing IC or other components from malfunctioning due to rising HAVDD voltage.
Voltage inputted to VDD3 pin is being monitored and if HAVDD voltage reaches HAVDD>110% (Typ), it is considered as
unusual condition thus, OVP function is operated. If OVP is detected, switching is stopped until OVP release voltage (100%,
Typ) falls to HAVDD voltage. After OVP release, switching is re-started.
5-2. Over Current Protection (OCP)
If excessive load current is demanded (SWB3 peak current>1.5A, Typ), it limits current to flow to built–in Power MOS by
controlling Switching.
5-3. Under Voltage Protection (UVP)
Timer-latch type output UVP function is built-in.
When the unusual condition (HAVDD<80%) is detected, SWB3 frequency is divided into 1/4 and UVP timer starts.
If the unusual condition continues up to 10msec(typ.), all output will be latched with shutdown state. Power reset is needed
to remove the latch state and to re-start.
6. HIGH VOLTAGE LDO BLOCK
6-1. Over Current Protection (OCP)
If excessive load current (I_HVLDO>100mA, typ.) is present, It controls source current of HVLDO.
6-2. Under Voltage Protection (UVP)
Timer-latch type output UVP function is built in.
When an unusual condition is detected (HVLDO<80%), UVP timer starts. If unusual condition continues up to 10msec (Typ),
all output is latched in shutdown condition. Power reset is needed to remove the latch state and to re-start.
7. VGH REGULATOR BLOCK
7-1. Over Voltage Protection (OVP)
OVP function is incorporated to prevent IC or other components from malfunctioning due to rising VGH voltage.
Voltage inputted to VGH pin is being monitored and if VGH voltage reaches VGH>38V (Typ), it is considered as unusual
condition so that OVP function is operated. If OVP is detected, limit DRVP current until OVP release voltage (35V, Typ) falls
to VGH voltage. After OVP release, switching is re-started.
7-2. Over Current Protection (OCP)
If excessive load current (I_DRVP>5mA, Min) is present, It controls sink current (Base current of PNP Tr ) of DRVP.
7-3. Under Voltage Protection (UVP)
Timer-latch type output UVP function is built-in.
When an unusual condition is detected (VGH<80%), UVP timer starts. If the unusual condition continues up to 10msec
(Typ), all output is latched in shutdown condition. Power reset is needed to remove the latch state and to re-start.
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8. GENERAL
8-1. Thermal shutdown
All outputs will shut down when the IC temperature exceeds 175℃ (Typ). After the temperature falls below 150℃ (Typ),
the operation re-starts.
8-2. VIN Under Voltage Lock Out
VIN Under Voltage Lock Out prevents the circuit malfunction below the UVLO voltage. If VIN voltage is below the UVLO
voltage (8.3V / 7.55V), it enters the standby state.
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Protection function list
Protective
BLOCK
Working Condition
Action
Protective removal
VIO<100%
Function
OVP
VIO>110%
I_SWB1>3.5A
VIO<80%
Stops switching.
BUCK
CONVERTER
1
OCP
UVP
Control switching pulse duty to not over current limit.
Frequency becomes 1/4
I_SWB1<3.5A
VIO>80%
IC shutdown if UVP status maintains during 10msec.
IC restart
OVP
OCP
UVP
VCORE>110%
I_SWB2>3.0A
VCORE<80%
Stops switching.
VCORE<100%
BUCK
CONVERTER
2
Control switching pulse duty to not over current limit.
Frequency becomes 1/4
I_SWB2<3.0A
VCORE>80%
IC restart
IC shutdown if UVP status maintains during 10msec.
Limit DRVN current.
OCP
UVP
OVP
OCP
UVP
OCP
I_DRVN>5mA
VGL<80%
I_DRVN<5mA
IC restart
VGL
REGULATOR
IC shutdown if UVP status maintains during 10msec.
Stops switching
AVDD>19.5V
I_SW>5A
AVDD<18V
I_SW<5A
BOOST
CONVERTER
Control switching pulse duty to not over current limit.
IC shutdown if UVP status maintains during 10msec.
Control switching pulse duty to not over current limit.
AVDD<80%
I_SWO>7.0A
IC restart
LOAD SW
IC restart
OVP
OCP
UVP
HAVDD>110%
I_SWB3>1.5A
HAVDD<80%
Stops switching.
HAVDD<100%
BUCK
CONVERTER
3
Control switching pulse duty to not over current limit.
Frequency becomes 1/4
I_SWB3<1.5A
HAVDD>80%
IC restart
IC shutdown if UVP status maintains during 10msec.
Limit HVLDO current.
HIGH
VOLTAGE
LDO
OCP
UVP
OVP
OCP
UVP
TSD
I_HVLDO>100mA
HVLDO<80%
VGH>45V
I_HVLDO<100mA
IC restart
IC shutdown if UVP status maintains during 10msec.
DRVP current limit to 0mA
VGH<42V
VGH
REGULATOR
I_DRVP>5 mA
VGH<80%
Limit DRVP current.
I_DRVP<5mA
IC restart
IC shutdown if UVP status maintains during 10msec.
IC shutdown
Tj>175℃
Tj<150℃
GENERAL
UVLO
VIN<7.55V
IC shutdown
VIN>8.3V
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Serial transmission
Use I2C BUS control for command interface with Host.
Writing or reading by specifying 1 byte Register address besides Slave address.
I2C BUS slave mode format is shown below.
Slave Address
Register Address
Select Register Address (8bit)
Register Address
DATA
8bit DATA
DATA
R/W A
A
0
A
0
Write operation Start
Read operation Start
Stop
Stop
0
0
1
1
0
0
0
0
0
A0
A0
0
0
Slave Address
R/W A
A
0
A
0
Select Register Address (8bit)
8bit DATA
0
0
0
1
0
Start
Slave Address
:
:
Start condition
Send 7 bit data in all with bit of Read Mode (H) or Write Mode (L).
(MSB First)
A0 are selectable (1/0) with the slave address select pin.
Acknowledge
ACK
:
Sending or receiving data includes acknowledge bit per byte.
If the data is sent and received properly, ‘L’ is sent and received.
If ‘H’ is sent and received, it means there is no Acknowledge.
Use 1 byte select address.
Data byte. Sending and Receiving data (MSB First)
Stop condition
Register Address
Data
STOP
:
:
:
For writing mode from I2C BUS to register, there are Single mode and Multi-mode.
On single mode, write data to one designated register.
On multi-mode, as a start address register specified in the second byte, writing data can be performed continuously, by
entering multiple data.
Single mode or multi-mode setting can be configured by having or not having ‘stop bit’.
①Single Mode Timing Chart
start
Slave Address
Write Ackn
Resister Address
Ackn
Data
Ackn
Stop
SCL
SDA_in
A6
A6
A5
A5
A4
A4
A3
A3
A2
A2
A1
A1
A0 R/W Ackn R7
A0 R/W Ackn R7
R6
R6
R5
R5
R4
R4
R3
R3
R2
R2
R1
R1
R0 Ackn D7
R0 Ackn D7
D6
D6
D5
D5
D4
D3
D3
D2
D2
D1
D1
D0 Ackn
D0 Ackn
D4
Device_Out
②Multi-Mode Timing Chart
start
Slave Address
Write Ackn
Resister Address (Ex.01h)
Ackn
Data (to Resister 01h)
Ackn
Data (to Resister 02h)
Ackn
・・・
・・・
・・・
SCL
SDA_in
A6
A6
A5
A5
A4
A4
A3
A3
A2
A2
A1
A1
A0 R/W Ackn R7
A0 R/W Ackn R7
R6
R6
R5
R5
R4
R4
R3
R3
R2
R2
R1
R0 Ackn
R0 Ackn
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0 Ackn
D0 Ackn
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0 Ackn
D0 Ackn
D7
R1
D7
Device_Out
Data(toResister05h)
Ackn
Data(toResister06h)
Ackn
Stop
・・・
・・・
・・・
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0 Ackn D7
D0 Ackn D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0 Ackn
D0 Ackn
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I2CTiming Diagram
tR
tHIGH
tF
70%
30%
SCL
tLOW
tPD
tHD:STA
tSU;DAT
tHD;DAT
70%
30%
SDA
(IN)
tBUF
tDH
70%
30%
SDA
(OUT )
70%
SCL
SDA
tHD;STA
tSU;STA
tSU;STO
70%
30%
tl
S：START bit
P：STOP bit
S
P
Figure 50. I2C Timing Diagram
NORMA LMODE
・Timing standard values
FAST MODE
TYP
Parameter
Symbol
Unit
MIN
TYP
MAX
MIN
MAX
SCL frequency
SCL high time
ｆSCL
tHIGH
tLOW
-
4.0
4.7
-
-
-
100
-
-
0.6
1.2
-
-
-
400
-
kHz
us
us
us
us
us
us
ns
ns
us
us
us
us
us
SCL low time
-
-
-
-
Rise Time
tR
-
1.0
-
0.3
Fall Time
tF
-
-
0.3
-
-
0.3
Start condition hold time
Start condition setup time
SDA hold time
tHD；STA
tSU；STA
tHD；DAT
tSU；DAT
tPD
4.0
4.7
200
200
-
-
-
0.6
0.6
100
100
-
-
-
-
-
-
-
-
-
-
-
SDA setup time
-
-
-
-
-
-
Acknowledge delay time
Acknowledge hold time
Stop condition setup time
Bus release time
Noise spike width
0.9
0.9
tDH
-
0.1
-
-
-
-
-
-
0.1
-
-
-
-
-
tSU；STO
tBUF
4.7
4.7
-
0.6
1.2
-
-
-
Tl
0.1
0.1
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Command Interface
EEPROM transmission format for data sent and received is shown below.
I2C Write format
Slave Address
Register Address
00h to 0Ch
DATA
R/W
0
A
0
A
0
A
0
Start
Stop
N-bytes DATA
0
1
0
0
0
0 A0
It can enter further Register from 3 byte by entering data continuously.
DATA after 0Dh is invalid.
Inputted Data reflect to the Register at the ACK output timing.
I2C Read format
1. Read data from DAC Register
Slave Address
Start
Register Address
R/W
0
A
0
A
0
00h to 0Ch
DATA
0
1
0
0
0
0
0
A0
A0
Slave Address
R/W
1
A
0
A
0
Repeated
Start
Stop
N-bytes DATA
0
1
0
0
0
EEPROM Write Format
EEPROM (DAC Register) transmission format for write is shown below.
EEPROM Write format
Slave Address
Register Address
DATA
R/W
0
A
0
A
A
0
Start
Stop
0
1
0
0
0
0
A0
1
1
1
1
1
1
1
1
0
1
X
X
X
X
X
X
X
D6 to D0 : Don’t care
Automatic EEPROM Read Function at Start-up
Upon BM81110MUW start-up, a reset signal is generated and each register is initialized.
After VL activation is finished, data which is stored in the EEPROM is copied to the registers.
The automatic EEPROM read function at start-up is further explained by the flow chart below.
VL ACTIVE
EEPROM READ
TRANSFER DATA
REGISTER
START OPERATION
Figure 51. Automatic EEPROM Read Function at Start-up
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Content of EEPROM setting
Register
Bits
Function
Default(*1)
Resolution
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
6
6
3
1
4
6
5
2
5
6
Channel Disable Register
AVDD output voltage setting[5:0]
AVDD OCP offset setting[2:0]
AVDD soft start time setting[0]
VIO output voltage setting[3:0]
HAVDD output voltage setting[5:0]
VGH output voltage setting[4:0]
GPM clamp voltage setting[1:0]
VGL output voltage setting[4:0]
HVLDO output voltage setting[5:0]
00h
-
15.6V [27h]
1.6A [04h]
10msec [00h]
3.3V [0Bh]
7.8V [1Eh]
35V [14h]
0.1V [11.7V to 18.0V]
0.4A [0A to 2.8A]
10msec [10msec or 20msec]
0.1V [2.2V to 3.7V]
0.1V [4.8V to 11.1V]
0.5V [25V to 40.5V]
5V [15V to 30V]
20V [01h]
-6.0V [0Ah]
15.2V [23h]
0.2V [-10.2V to -4.0V]
0.1V [11.7V to 18.0V]
HVLDOx0.18/256
[HVLDOx0.36 to HVLDOx0.54]
8
VCOM output voltage setting[7:0]
6.103V[C5h]
0Ah
10
10
10
10
8
AMP1 output voltage setting[9:0]
AMP2 output voltage setting[9:0]
AMP3 output voltage setting[9:0]
AMP4 output voltage setting[9:0]
7.808V[1F2h]
7.808V[1F2h]
HVLDO/1024[0V to HVLDO]
HVLDO/1024[0V to HVLDO]
HVLDO/1024[0V to HVLDO]
HVLDO/1024[0V to HVLDO]
0Bh[7:6], 0Ch
0Bh[5:4], 0Dh
0Bh[3:2], 0Eh
0Bh[1:0], 0Fh
FFh
7.808V[1F2h]
7.808V[1F2h]
Control Register[7:0]
*1 Factory value.
*2 Value of default voltage setting. The Soft start time of each output changes depending on a setting voltage.
Channel Disable Register
Register Address = 00h
[7]
-
[6]
-
[5]
[4]
[3]
[2]
[1]
[0]
VCORE
HAVDD
VGH
VGL
GPM
AVDD_EXT
0：Enable 1：Disable
AVDD_EXT 1：AVDD external mode
Control Register
Register
Address
DATA
[BIN]
Function
Write to EEPROM from DAC Register data.
FFh
1xxx_xxxx
x：Don’t care bit
Register Map
Resister
D7
D6
D5
D4
D3
D2
D1
D0
Default
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
FFh
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
VCORE
HAVDD
VGH
VGL
GPM
AVDD_EXT
00h
27h
04h
00h
0Bh
1Eh
14h
01h
0Ah
23h
C5h
55h
F2h
F2h
F2h
F2h
―
AVDD[5:0]
―
―
―
―
―
―
―
―
AVDD OCP offset[2:0]
―
―
AVDD SS
VIO [3:0]
HAVDD [5:0]
―
―
―
VGH [4:0]
―
―
―
GPM clamp [1:0]
AMP4[9:8]
VGL [4:0]
HVLDO[5:0]
VCOM [7:0]
AMP1[9:8]
AMP2[9:8]
AMP3[9:8]
AMP1[7:0]
AMP2[7:0]
AMP3[7:0]
AMP4[7:0]
（ Control Register ）
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Command Table 1
Register Address
01
[5:0]
02
[2:0]
AVDD
OCP
offset
[A]
0.0
0.4
0.8
1.2
03
[0]
04
[3:0]
05
[5:0]
06
[4:0]
07
[1:0]
08
[4:0]
09
[5:0]
AVDD
soft
start
[msec]
10
GPM
clamp
[V]
DATA
(HEX)
AVDD
[V]
VIO
[V]
HAVDD
[V]
VGH
[V]
VGL
[V]
HVLDO
[V]
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
11.7
11.8
11.9
12.0
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
12.9
13.0
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
13.9
14.0
14.1
14.2
14.3
14.4
14.5
14.6
14.7
14.8
14.9
15.0
15.1
15.2
15.3
15.4
15.5
15.6
15.7
15.8
15.9
16.0
16.1
16.2
16.3
16.4
16.5
16.6
16.7
16.8
16.9
17.0
17.1
17.2
17.3
17.4
17.5
17.6
17.7
17.8
17.9
18.0
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
6.0
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7.0
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
8.0
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
9.0
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
10.0
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
11.0
11.1
25.0
25.5
26.0
26.5
27.0
27.5
28.0
28.5
29.0
29.5
30.0
30.5
31.0
31.5
32.0
32.5
33.0
33.5
34.0
34.5
35.0
35.5
36.0
36.5
37.0
37.5
38.0
38.5
39.0
39.5
40.0
40.5
15
20
25
30
-4.0
-4.2
-4.4
-4.6
-4.8
-5.0
-5.2
-5.4
-5.6
-5.8
-6.0
-6.2
-6.4
-6.6
-6.8
-7.0
-7.2
-7.4
-7.6
-7.8
-8.0
-8.2
-8.4
-8.6
-8.8
-9.0
-9.2
-9.4
-9.6
-9.8
-10.0
-10.2
11.7
11.8
11.9
12.0
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
12.9
13.0
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
13.9
14.0
14.1
14.2
14.3
14.4
14.5
14.6
14.7
14.8
14.9
15.0
15.1
15.2
15.3
15.4
15.5
15.6
15.7
15.8
15.9
16.0
16.1
16.2
16.3
16.4
16.5
16.6
16.7
16.8
16.9
17.0
17.1
17.2
17.3
17.4
17.5
17.6
17.7
17.8
17.9
18.0
20
1.6
2.0
2.4
2.8
: Default Value
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Command Table 2
Register Address
Register Address
0A
[7:0]
0B[7:6], 0C
[9:0]
0B[5:4], 0D
0B[3:2], 0E
[9:0]
0B[1:0], 0F
[9:0]
[9:0]
DATA
(HEX)
VCOM
[V]
DATA
(HEX)
AMP1
[V]
AMP2
[V]
AMP3
[V]
AMP4
[V]
00
01
02
HVLDOx0.18x(3 - 0/256)
HVLDOx0.18x(3 - 1/256)
HVLDOx0.18x(3 - 2/256)
000
001
002
HVLDOx(1 - 0/1024)
HVLDOx(1 - 1/1024)
HVLDOx(1 - 2/1024)
HVLDOx(1 - 0/1024)
HVLDOx(1 - 1/1024)
HVLDOx(1 - 2/1024)
HVLDOx(1 - 0/1024)
HVLDOx(1 - 1/1024)
HVLDOx(1 - 2/1024)
HVLDOx(1 - 0/1024)
HVLDOx(1 - 1/1024)
HVLDOx(1 - 2/1024)
…
…
…
…
…
…
…
FD
FE
FF
HVLDOx0.18x(3 - 253/256)
HVLDOx0.18x(3 - 254/256)
HVLDOx0.18x(3 - 255/256)
3FD
3FE
3FF
HVLDOx(1 - 1021/1024) HVLDOx(1 - 1021/1024) HVLDOx(1 - 1021/1024) HVLDOx(1 - 1021/1024)
HVLDOx(1 - 1022/1024) HVLDOx(1 - 1022/1024) HVLDOx(1 - 1022/1024) HVLDOx(1 - 1022/1024)
HVLDOx(1 - 1023/1024) HVLDOx(1 - 1023/1024) HVLDOx(1 - 1023/1024) HVLDOx(1 - 1023/1024)
・In case of HVLDO=15.2[V]
Register Address
Register Address
0A
[7:0]
0B[7:6], 0C
[9:0]
0B[5:4], 0D
[9:0]
0B[3:2], 0E
[9:0]
0B[1:0], 0F
[9:0]
DATA
(HEX)
VCOM
[V]
DATA
(HEX)
AMP1
[V]
AMP2
[V]
AMP3
[V]
AMP4
[V]
00
01
02
8.208
8.197
8.187
000
001
002
15.200
15.185
15.170
15.200
15.185
15.170
15.200
15.185
15.170
15.200
15.185
15.170
…
…
…
…
…
…
…
C5
6.103
1F2
7.808
7.808
7.808
7.808
…
…
…
…
…
…
…
FD
FE
FF
5.504
5.493
5.483
3FD
3FE
3FF
0.045
0.030
0.015
0.045
0.030
0.015
0.045
0.030
0.015
0.045
0.030
0.015
step幅
0.011
step幅
0.015
0.015
0.015
0.015
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Selecting Application Components
1. Buck Converter
1-1. Selecting the Output LC Constant
IL
IL
⊿
IOMAX+
should not exceed the rated value
ILR
2
I
OMAXMean current
t
Figure 52. Inductor Current Waveform (Buck Converter).
The output inductance (L) is decided by the rated current (ILR)and maximum input current (IOMAX)of the inductance.
Adjust so that IOMAX+ΔIL / 2 does not exceed the rated current value.
ΔIL can be obtained by the following equation.
1
L
VO
VIN
1
f
ΔI
=
× (VIN - VO) ×
×
[A]
L
where f is the switching frequency
Set with sufficient margin because the inductance value may have a dispersion of ±30%.
If the coil current exceeds the rated current (ILR), the IC may be damaged.
1-2. Selecting the Input/Output capacitor
The output capacitor (CO) smoothens the ripple voltage at the output. Select a capacitor that will regulate the output ripple voltage
within the specifications.
Output ripple voltage can be obtained by the following equation.
ΔI
L
VO
VIN
1
f
ΔVPP = ΔI × R
ESR
＋
×
×
L
2 Co
However, since the aforementioned conditions are based on a lot of factors, verify the results using the actual product.
Since the peak current flows between the input and output at the DC/DC converter, a capacitor is required to install at the
Input side. For the reason, the low ESR capacitor is recommended as an input capacitor which has the value more than
10μF and less than 100mΩ ESR. If an out of range capacitor is selected, the excessive ripple voltage is superimposed on
the input voltage, thus, it may cause the malfunction of the IC.
However these conditions may vary according to the load current, input voltage, output voltage, inductance and switching
frequency. Be sure to perform margin check using the actual product.
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1-3. Selecting the Output rectifier diode
A schottky barrier is recommended as rectifier diode to be used at the output stage of the DC/DC converter. Select carefully
in consideration of the maximum inductor current, maximum output voltage and power supply voltage.
ΔI
L
Maximum inductor current I
＋
＜
＜
Diode Maximum Absolute Current
Diode Maximum Absolute Voltage
OMAX
IN
2
Maximum input voltage
V
Provide sufficient design margins for a tolerance of 30% to 40 for each parameter.
2. Boost Converter
2-1. Selecting the Output LC Constant
IL
IL
⊿
IOMAX+
should not exceed the rated value
level.
2
ILR
I
OMAX mean current
t
Figure 53. Inductor Current Waveform (Boost Converter).
The output inductance (L) is decided by the rated current (ILR)and maximum input current (IINMAX)of the inductance.
Adjust so that IINMAX+ΔIL / 2 does not exceed the rated current value.
ΔIL can be obtained by the following equation.
1
VO VIN
1
Δ I
VIN
[A]
L
L
VO
f
where f is the switching frequency
Set with sufficient margin because the inductance value may have a dispersion of ±30%.
If the coil current exceeds the rated current (ILR), the IC may be damaged.
2-2. Selecting the Output capacitor
The output capacitor (CO) smoothens the ripple voltage at the output. Select a capacitor that will regulate the output ripple voltage
within the specifications.
Output ripple voltage can be obtained by the following equation.
ΔI
1
VIN
VO
L
ΔV
PP
= Ｉ
LMAX
× R
ESR
＋
×
×
I
－
LMAX
f × CO
2
However, since the aforementioned conditions are based on a lot of factors, verify the results using the actual product.
Since the peak current flows between the input and output at the DC/DC converter, a capacitor is required to install at the
Input side. For the reason, the low ESR capacitor is recommended as an input capacitor which has the value more than
10μF and less than 100mΩ ESR. If an out of range capacitor is selected, the excessive ripple voltage is superimposed on
the input voltage, thus, it may cause the malfunction of the IC.
However these conditions may vary according to the load current, input voltage, output voltage, inductance and switching
frequency. Be sure to perform the margin check using the actual product.
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2-3. Setting phase compensation
Phase setting procedure.
Stable negative feedback condition is achieved as follows:
・When the gain is set to 1 (0 dB), phase delay should not be more than 150°.Consequently, phase margin should not be
less than 30°.
Also, since DC/DC converter applications are sampled according to the switching frequency, the whole system GBW should
be set to not more than 1/10 of the switching frequency. The target characteristics of the applications can be summarized
as follows:
・When the gain is set to 1 (0 dB), the phase delay should not be more than 150°.
And phase margin should not be less than 30°.
・The frequency when the gain is set to 0 dB should not be more than 1/10 of the switching frequency.
The responsiveness is determined by the GBW limitation. Consequently, to increase the circuit response, higher switching
frequencies are required.
AVDD is in current mode control. The current mode control is a two-pole single-zero system. The poles are formed by the
error amplifier and load while added zero is for phase compensation.
By placing poles appropriately, the circuit can maintain good stability and transient load response.
Bode plot diagram of general DC/DC converter is described below. At point (a), gain starts falling via the output impedance
of the error amplifier and forms a pole by capacitor Ccp. When point (b) is reached, a zero is formed by resistor Rpc and
capacitor Ccp to cancel the pole by loading and balance variation of Gain and phase.
The GBW (i.e., frequency when the gain is 0 dB) is determined by phase compensation capacitor connected to the error
amplifier. If GBW is to be reduced, increase the capacitance of the capacitor.
(a)
-20dB/decade
Vo
A
0
R3
C1
R1
R2
Gain
[dB]
GBW(b)
f
-
+
COMP
Rcp
Ccp
A
0
Phase
[deg]
-90°
Phase margin
-90
-180°
-180
f
Figure 54. Setting phase compensation.
Formed Zero (fz1) by Rcp resistor and Ccp Capacitor are shown by using the following equation.
And also, Feed-forward capacitor C1 and R1 resistor both create Formed Zero (fz2) and it is used as boosting phase
margin in the limited frequency area.
1
Phase lead fZ1 =
Phase lead fZ2 =
[Hz]
2πCcpRcp
1
[Hz]
2πC1R1
The formed zero fz2 phase compensation is built into the IC.
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3. Positive Charge Pump : VGH
3-1. Selecting the Output rectifier diode
Select carefully in consideration of the maximum load current, maximum output voltage and power supply voltage.
Maximum output current
I
＜
Diode Maximum Absolute Current
OMAX
Maximum output voltage AVDD
＜
Diode Maximum Absolute Voltage
Provide sufficient design margins for a tolerance of 30%~40 for each parameter.
3-2. Selecting the Output PNP transistor
Select carefully in consideration of the maximum load current, maximum output voltage and power supply voltage.
AVDD－VIN
Boost Converter Duty
D =
AVDD
I
OMAX
D
Maximum Output current
＜Transistor Maximum Absolute Current
Power supply voltage
DC gain
AVDD x 2
IOMAX / IBASE
＜Transistor Maximum Absolute Voltage
＜Transistor hfe
Power dissipation (Doubler Mode)
Power dissipation (Tripler Mode)
Maximum DRVP current
( 2 x AVDD – VGH – 2 x Vf ) x IOUT
( 3 x AVDD – VGH – 4 x Vf ) x IOUT
IBASE（5mA）
＜Transistor Power dissipation
＜Transistor Power dissipation
Provide sufficient design margins for a tolerance of 30%~40 for each parameter.
3-3. Selecting the base emitter resistor
100kΩ base-emitter resistor used to ensure proper operation.
3-4. Selecting the flying capacitor and the switch node resistor
A 0.1uF to 0.47uF flying capacitor and 1Ω to 20Ω resistor are appropriate for most applications.
3-5. Selecting the output capacitor
A 10uF ceramic capacitor is appropriate for most applications. More capacitor can be added to improve the load transient
response.
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4. Negative Charge Pump : VGL
4-1. Selecting the Output rectifier diode
Select carefully in consideration of the maximum load current, maximum output voltage and power supply voltage.
Maximum output current
I
＜
Diode Maximum Absolute Current
OMAX
VIN
Maximum switching voltage
＜
Diode Maximum Absolute Voltage
Provide sufficient design margins for a tolerance of 30%~40 for each parameter.
4-2. Selecting the Output NPN transistor
Select carefully in consideration of the maximum load current, maximum output voltage and power supply voltage.
VIN－VIO
Converter Duty
D =
VIN
I
OMAX
D
Maximum Output current
＜Transistor Maximum Absolute Current
Power supply voltage
DC gain
VIN
＜Transistor Maximum Absolute Voltage
＜Transistor hfe
IOMAX / IBASE
Power dissipation (Doubler Mode)
Maximum DRVN current
(VIN - ∣ VGL ∣ – 2 x Vf ) x IOUT
IBASE（5mA）
＜Transistor Power dissipation
Provide sufficient design margins for a tolerance of 30%~40 for each parameter.
4-3. Selecting the base emitter resistor
100kΩ base-emitter resistor used to ensure proper operation.
4-4. Selecting the flying capacitor and the switch node resistor
A 0.1uF to 0.47uF flying capacitor and 1Ω to 20Ω resistor are appropriate for most applications.
4-5. Selecting the output capacitor
A 10uF ceramic capacitor is appropriate for most applications. More capacitor can be added to improve the load transient
response.
5. High Voltage LDO : HVLDO
5-1. Selecting the output capacitor
A 4.7uF to10uF ceramic capacitor is appropriate for most applications.
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Layout Guideline
DC/DC converter switching line must be as short and thick as possible to reduce line impedance. If the wiring is long,
ringing caused by switching would increase and this may exceed the absolute maximum voltage ratings. If the parts are
located far apart, consider inserting a snubber circuit.
The thermal Pad on the back side of IC has the great thermal conduction to the chip. So using the GND plain as broad and
wide as possible can help thermal dissipation. And a lot of thermal via for helping the spread of heat to the different layer is
also effective. When there is unused area on PCB, please arrange the copper foil plain of DC nodes, such as GND, VIN
and VOUT for helping heat dissipation of IC or circumference parts.
Power Dissipation
6
(2) 5.08W
5
(1) 4.01W
4
3
2
1
0
0
25
50
75
100
125
150
AMBIENT TEMPERATURE : Ta [℃]
VQFN48V7070A Package
On 4-layer 114.3mm×74.2mm×1.6mm glass epoxy PCB
(1) 2-layer board (Backside copper foil area 74.2 mm ×74.2 mm)
(2) 4-layer board (The 2nd, 3rd layers and backside copper foil area 74.2 mm ×74.2 mm)
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I/O Equivalence Circuit
1, 2, 47, 48. AMP1~4
3. VDD1
4.PG
HVCC
HVCC
VINB1
PG
AMPx
VDD1
5.SDA
6.SCL
7.A0
Internal reg.
Internal reg.
AVIN
Internal reg.
SCL
SDA
A0
8. AVIN
9.HVLDO
10. HVCC
AVIN
HVCC
HVCC
HVLDO
11.VCOM
12. INN
13. CTRL
HVCC
Internal reg.
HVCC
CTRL
INN
VCOM
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I/O Equivalence Circuit - continued
15.COMP
16.VL
19, 20.SW
SWO
Internal reg.
AVIN
SWI
SW
VL
COMP
21.SWI
22.SWO
23.AVDDS
SWO
SWO
SWO
SWO
SWI
SW
SWI
SW
AVDDS
24.PGATE
25.VGL
26.DRVN
SWI
SWI
VL
VL
VL
Internal reg.
PGATE
DRVN
VGL
27.DRVP
28.VGH
29.VGHM
VGH
VGH VGH
VGH
DRVP
VGHM
RE
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I/O Equivalence Circuit - continued
30.RE
31.VINB3
33. SWB3
VGH
VGH VGH
VINB3
VINB3
VGHM
RE
SWB3
35. VDD3
36. EN
38. SWB2
Internal reg.
VINB3
VDD3
SWB2
39. VDD2
40. VINB2
41, 42.VINB1
VINB2
VINB2
VINB1
VDD2
44, 45. SWB1
―
―
VINB1
SWB1
―
―
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Operational Notes
1.
2.
Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power
supply pins.
Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the
digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog
block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and
aging on the capacitance value when using electrolytic capacitors.
3.
4.
Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5.
Thermal Consideration
Should by any chance the power dissipation rating be exceeded the rise in temperature of the chip may result in
deterioration of the properties of the chip. In case of exceeding this absolute maximum rating, increase the board size
and copper area to prevent exceeding the Pd rating.
6.
7.
Recommended Operating Conditions
These conditions represent a range within which the expected characteristics of the IC can be approximately
obtained. The electrical characteristics are guaranteed under the conditions of each parameter.
Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush
current may flow instantaneously due to the internal powering sequence and delays, especially if the IC
has more than one power supply. Therefore, give special consideration to power coupling capacitance,
power wiring, width of ground wiring, and routing of connections.
8.
9.
Operation Under Strong Electromagnetic Field
Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.
Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may
subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply
should always be turned off completely before connecting or removing it from the test setup during the inspection
process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during
transport and storage.
10. Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment)
and unintentional solder bridge deposited in between pins during assembly to name a few.
11. Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the
power supply or ground line.
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Operational Notes – continued
12. Regarding the Input Pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should
be avoided.
Resistor
Transistor (NPN)
Pin A
Pin B
Pin B
B
E
C
Pin A
B
C
E
P
P+
P+
N
P+
P
P+
N
N
N
N
N
N
N
Parasitic
Elements
Parasitic
Elements
P Substrate
GND GND
P Substrate
GND
GND
Parasitic
Elements
Parasitic
Elements
N Region
close-by
Figure 55. Example of monolithic IC structure
13. Ceramic Capacitor
When using a ceramic capacitor, determine the dielectric constant considering the change of capacitance with
temperature and the decrease in nominal capacitance due to DC bias and others.
14. Area of Safe Operation (ASO)
Operate the IC such that the output voltage, output current, and power dissipation are all within the Area of Safe
Operation (ASO).
15. Thermal Shutdown Circuit(TSD)
This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always
be within the IC’s power dissipation rating. If however the rating is exceeded for a continued period, the junction
temperature (Tj) will rise which will activate the TSD circuit that will turn OFF all output pins. When the Tj falls below
the TSD threshold, the circuits are automatically restored to normal operation.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from
heat damage.
16. Over Current Protection Circuit (OCP)
This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This
protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should
not be used in applications characterized by continuous operation or transitioning of the protection circuit.
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TSZ02201-0313AAF00420-1-2
4.Dec.2014 Rev.002
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TSZ22111・15・001
BM81004MUV
Ordering Information
B M 8 1 0 0 4 M U V
ZE2
Part number
Package
MUV:VQFN48V7070A
Packaging and forming specification
ZE2: Embossed tape and reel
Marking Diagram
VQFN48V7070A (TOP VIEW)
Part Number Marking
8 1 0 0 4
LOT Number
1PIN MARK
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TSZ02201-0313AAF00420-1-2
4.Dec.2014 Rev.002
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BM81004MUV
Physical Dimension Tape and Reel Information
Package Name
VQFN48V7070A
ZE2
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© 2014 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
TSZ02201-0313AAF00420-1-2
4.Dec.2014 Rev.002
48/49
BM81004MUV
Revision history
Date
Revision
001
Contents
2014.09.16
2014.12.04
New release
Page 8/49 TSD: MIN, MAX added
002
Page 9/49 VOVP_VIO, VOVP_VCORE and VOVP_HAVDD: MIN, MAX added
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TSZ02201-0313AAF00420-1-2
4.Dec.2014 Rev.002
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TSZ22111・15・001
Notice
Precaution on using ROHM Products
1. Our Products are designed and manufactured for application in ordinary electronic equipments (such as AV equipment,
OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you
intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note 1), transport
equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car
accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or
serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.
Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific
Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅣ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅢ
2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3. Our Products are designed and manufactured for use under standard conditions and not under any special or
extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any
special or extraordinary environments or conditions. If you intend to use our Products under any special or
extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of
product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4. The Products are not subject to radiation-proof design.
5. Please verify and confirm characteristics of the final or mounted products in using the Products.
6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7. De-rate Power Dissipation (Pd) depending on Ambient temperature (Ta). When used in sealed area, confirm the actual
ambient temperature.
8. Confirm that operation temperature is within the specified range described in the product specification.
9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-GE
Rev.003
© 2013 ROHM Co., Ltd. All rights reserved.
Precautions Regarding Application Examples and External Circuits
1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2. You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
QR code printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since our Products might fall under controlled goods prescribed by the applicable foreign exchange and foreign trade act,
please consult with ROHM representative in case of export.
Precaution Regarding Intellectual Property Rights
1. All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data. ROHM shall not be in any way responsible or liable
for infringement of any intellectual property rights or other damages arising from use of such information or data.:
2. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the information contained in this document.
Other Precaution
1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4. The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-GE
Rev.003
© 2013 ROHM Co., Ltd. All rights reserved.
Daattaasshheeeett
General Precaution
1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.
ROHM shall not be in an y way responsible or liable for failure, malfunction or accident arising from the use of a ny
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s
representative.
3. The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or
liable for any damages, expenses or losses incurred by you or third parties resulting from inaccuracy or errors of or
concerning such information.
Notice – WE
Rev.001
© 2015 ROHM Co., Ltd. All rights reserved.
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