BM28723AMUV_技术文档

Datasheet

Middle Power Class-D Speaker Amplifier series

17W+17W

Full Digital Speaker Amplifier

with built-in DSP

BM28723AMUV

General Description

Features

BM28723AMUV is a 17W+17W Class D stereo Speaker

Amplifier with built-in DSP designed for TVs specifically

for space-saving and low-power consumption.

BM28723AMUV features BCD (Bipolar, CMOS, DMOS)

process technology to achieve high efficiency. In addition,

BM28723AMUV is packaged in a compact back surface

heatsink type power package to attain low power

consumption, low heat generation without external

heatsink. The package Max output power is only

17W+17W (When R_L=8Ω) as compared to 20W+20W

(When R_L=8Ω) Max output power of package with

external heat-sink.



Built-in DSP (Digital Sound Processor) for Audio

Signal Processing for TVs

12-Band/ch BQ, 3-Band DRC, Pre-Scaler, Channel

Mixer, Fine Master Volume, Hard Clipper, Level

Meter, etc.



Single Input System for Digital Audio Interface (No

Master Clock Required)

- I²S/LJ/RJ Format

- LRCLK: 32kHz/44.1kHz/48kHz

- BCLK: 32fs/48fs/64fs

- SDATA: 16bit/20bit/24bit



Single Output System for Digital Audio Interface

The product satisfies all needs for drastic downsizing,

low-profile structures and powerful high quality playback

of sound systems.

- I²S Format

- SDATA: 16bit/20bit/24bit



No Snubber Circuit Required (V_CCP1, V_CCP2≤22V)

because of Slew Rate Control

Output Feedback Circuit which prevents decrease of

sound quality caused by change of power supply

voltage, achieves low noise and low distortion, so no

large electrolytic-capacitors for V_CCbypass is

required.

Key Specifications

 Supply voltage range

(V_CCP1, V_CCP2

10V to 24V

17W+17W (Typ)

0.08[%] (Typ)

)

 Speaker output power

(V_CCP1, V_CCP2=18V, R_L=8Ω)

 THD+N



Wide Range of Power Supply Input Voltage

The monaural output reduces the number of

external parts needed.

Applications



High Efficiency and Low Heat Dissipation allowing

Miniaturization, Slim Design, and also Power Saving

of the System

Eliminates pop-noise generated during the power

supply ON/OFF. High quality muting performance is

achieved using the soft-muting technology.

Built-in with Various Protection Functions for Highly

Reliability Design

 TVs (LCD, OLED)

 Home Audio

 Desktop PC

 Amusement Equipment

 Electronic Music Equipment, etc.

Typical Application Circuit

- High Temperature Protection

- Under Voltage Protection

SP ch1

(Lch)

SP ch2

(Rch)

- Output Short Protection

- DC Voltage Protection for speaker

- Clock Stop Protection



Small Package, it reduces surface mount area

Package

VQFN032V5050

W(Typ) x D(Typ) x H(Max)

5.00mm x 5.00mm x 1.00mm

Digital

Audio

Source

μ -con

Figure 1. Typical Application Circuit

VQFN032V5050

〇Product structure: Silicon integrated circuit 〇This product has no designed protection against radioactive rays

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Pin Configuration and Block Diagram

32

31

30

29

28

27

26

25

BSP1P OUT1P

REG_G

NC

REG_G

Control

I/F

1

2

3

4

5

6

7

8

2 wire I/F

24

23

22

21

20

19

18

17

ADDR

BCLK

VCCP1

Driver

FET 1P

GNDP1

BSP1N

I²S/LJ/RJ

I/F

Driver

FET 1N

LRCLK

SDATA

8 Times

Over-

Sampling

Digital

Filter

OUT1N

OUT2P

PWM

Modulator

Audio

DSP

TEST1

Driver

FET 2P

PLL

BSP2P

PLL

REG15

Driver

FET 2N

GNDP2

VCCP2

Protection

DGND

DVDD

10

TEST2

9

TEST3 SDATAO

11 12

BSP2N OUT2N

15 16

NC

14

13

Figure 2. Pin Configurations and Block Diagram (Top View)

Pin Description

No.

1

Name

ADDR

BCLK

I/O

No.

9

Name

TEST2

DVDD

I/O

I

No.

17

18

19

20

21

22

23

24

Name

VCCP2

GNDP2

BSP2P

OUT2P

OUT1N

BSP1N

GNDP1

VCCP1

I/O

-

No.

25

26

27

28

29

30

31

32

Name

OUT1P

BSP1P

REG_G

NC

I/O

I

O

2

I

10

11

12

13

14

15

16

-

I

O

-

3

LRCLK

SDATA

TEST1

PLL

TEST3

SDATAO

ERRORX

NC

I

4

I

O

-

O

I

5

I

RSTX

MUTEX

SCL

I

6

I/O

O

-

I

7

REG15

DGND

BSP2N

OUT2N

I

-

I

8

O

-

SDA

I/O

I: input, O: output, -: others

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I/O Equivalence Circuits

Caution: The numerical value of I/O equivalence circuit is typical value, not guaranteed.

No.

1

Voltage

0V

Pin Name

ADDR

Pin Explanation

I/O Equivalence Circuit

2 wire Bus control slave address select pin

10

Select LSB data of slave address for 2 wire Bus

control.

Input High level to set LSB=1.

Input Low level to set LSB=0.

1

Select pull-down resistor after DVDD is applied.

8

2

BCLK

3.3V

Digital audio signal input pin

10

Input bit clock of digital audio signal.

Select pull-up resistor after DVDD is applied.

2

8

3

4

LRCLK

SDATA

Digital audio signal input pin

10

Input LR clock of digital audio signal to LRCLK.

Input data of digital audio signal to SDATA.

Select pull-up resistor after DVDD is applied.

3,4

8

5

9

11

TEST1

TEST2

TEST3

-

Test pin

10

Connect to DGND.

5,9,11

8

6

PLL

1V

PLL filter pin

10

Connect filter circuit for PLL.

6

8

7

REG15

1.5V

Internal power supply pin for digital circuit

Connect capacitor.

10

Caution: The REG15 of BM28723AMUV should not be used

as an external supply and cannot support voltage load from

external source. Therefore, do not connect anything except

capacitor for stabilization.

7

8

10

DGND

DVDD

0V

3.3V

GND pin for Digital I/O

Power supply pin for Digital I/O.

Connect capacitor.

-

12

SDATAO

3.3V

Digital audio signal output pin

10

Output data of digital audio signal.

Select pull-up resistor after DVDD is applied.

12

8

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I/O Equivalence Circuits – continued

No.

13

Pin Name

ERRORX

Pin Voltage

3.3V

Pin Explanation

I/O Equivalence Circuit

Error flag pin

Connect pull-up resistor.

High: Normal operation

Low: Error

500Ω

13

Caution: An error flag is indicated when Output Short

Protection, DC Voltage Protection for speaker, and High

Temperature Protection are activated. The flag shows the LSI

condition during operation.

8

Don’t use for the protection except this product.

14

28

15

NC

-

No-Connection Pin

Don’t connect anything.

Boot strap pin, CH2 negative

Connect a capacitor from pin to OUT2N.

PWM output pin, CH2 negative

-

BSP2N

OUT2N

-

17

27

16

V_CCP2to 0V

Connect pin to output LPF.

15, 19

16, 20

Caution 1: If this pin is shorted to GND, the LSI may break.

Caution 2: When Reset ON or Mute ON, all output transistors

are OFF and output pins are pulled down by 10kΩ (Typ).

17

18

19

VCCP2

GNDP2

BSP2P

V_CCP2

0V

Power supply pin for CH2

Power GND pin for CH2

Boot strap pin, CH2 positive

18

-

Connect a capacitor from pin to OUT2P.

PWM output pin, CH2 positive

20

OUT2P

V_CCP2to 0V

Connect pin to output LPF.

Caution 1: If this pin is shorted to GND, the LSI may break.

Caution 2: When Reset ON or Mute ON, all output transistors

are OFF and output pins are pulled down by 10kΩ (Typ).

21

OUT1N

V_CCP1to 0V

PWM output pin, CH1 negative

Connect pin to output LPF.

24

27

Caution 1: If this pin is shorted to GND, the LSI may break.

Caution 2: When Reset ON or Mute ON, all output transistors

are OFF and output pins are pulled down by 10kΩ (Typ).

22, 26

21, 25

22

23

24

25

BSP1N

GNDP1

VCCP1

OUT1P

-

0V

Boot strap pin, CH1 negative

Connect a capacitor from pin to OUT1N.

Power GND pin for ch1

V_CCP1

Power supply pin for ch1

23

V_CCP1to 0V

PWM output pin, CH1 positive

Connect to output LPF.

Caution 1: If this pin is shorted to GND, the LSI may break.

Caution 2: When Reset ON or Mute ON, all output transistors

are OFF and output pins are pulled down by 10kΩ (Typ).

26

BSP1P

-

Boot-strap pin of ch1 positive

Connect a capacitor from pin to OUT1P.

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I/O Equivalence Circuits - continued

No.

27

Voltage

5.7V

Pin Name

REG_G

Pin Explanation

I/O Equivalence Circuit

24

Internal power supply pin for gate driver

Connect capacitor

Caution: The REG_G pin of BM28723AMUV should not be used

as an external supply and cannot support voltage load from external

source. Therefore, do not connect anything except capacitor for

stabilization.

27

350kΩ

23

29

30

31

RSTX

MUTEX

SCL

0V

-

Reset pin for Digital circuit

High: Reset OFF

Low: Reset ON

Select pull-down resistor after DVDD is applied.

Speaker output mute control pin

High: Mute OFF

10

29,30

Low: Mute ON

8

Select pull-down resistor after DVDD is applied.

2 wire Bus control transmit clock input pin

Input the transmit clock to this pin for 2 wire Bus

control.

31

Caution: This pin is not corresponding to threshold tolerance of 5V.

Refer to Absolute Maximum Ratings, Input voltage 1

8

32

SDA

-

2 wire Bus control data input/output pin

Input the transmit data to this pin for 2 wire Bus

control.

32

Caution: This pin is not corresponding to threshold tolerance of

5V.Refer to Absolute Maximum Ratings, Input voltage 1

8

-

EXP-PAD

There is no problem when EXP-PAD is left

unconnected. However, connecting it to ground is

recommended because the radiation performance

will be degraded.

-

The connection to any place except for the ground is

prohibited.

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Absolute Maximum Ratings (Ta=25°C)

Parameter

Supply Voltage

Symbol

V_CCMAX

V_DVDDMAX

Limit

30

4.5

Unit

V

Conditions

Pin 17, 24^{(Note 1) (Note 2)}

Pin 10^{(Note 1)}

-0.3 to

Input Voltage 1

Pin Voltage 1

Pin Voltage 2

V_IN1

V_PIN1

V_PIN2

V

Pin 1 to 5, 9, 11, 29 to 32^{(Note 1)}

Pin 27^{(Note 1)}

V_DVDD+0.3^{(Note 2)}

-0.3 to +7.0

-0.3 to

Pin 16, 20, 21, 25^{(Note 1) (Note 4)}

+V_CCMAX

-0.3 to V_OUT1P+7

-0.3 to V_OUT1N+7

-0.3 to V_OUT2P+7

-0.3 to V_OUT2N+7

-0.3 to +2.1

-0.3 to +7.0

-25 to +85

Pin 26^{(Note 1) (Note 5)}

Pin 22^{(Note 1) (Note 5)}

Pin Voltage 3

V_PIN3

V

Pin 19^{(Note 1) (Note 5)}

Pin 15^{(Note 1) (Note 5)}

Pin 7^{(Note 1)}

Pin Voltage 4

V_PIN4

V_ERR

Topr

Tstg

Tj

V

°C

Open-drain Pin Voltage

Operating Temperature Range

Storage Temperature Range

Junction Temperature Range

Pin 13^{(Note 1)}

-55 to +150

-40 to +150

Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit

between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is

operated over the absolute maximum ratings.

Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the

properties of the chip. In case of exceeding this absolute maximum rating, design a PCB with thermal resistance taken into consideration by

increasing board size and copper area so as not to exceed the maximum junction temperature rating.

(Note 1) The voltage that can be applied reference to GND (Pin 8, 18, 23).

(Note 2) Do not exceed Tj=150°C.

(Note 3) Refer to Recommended Operating Ratings for V_DVDD

.

(Note 4) This LSI should be used within AC peak limits at all conditions. Overshoot should be ≤30V with reference to GND.

Undershoot should be ≤10ns and ≤30V with reference to V_CCP1and V_CCP2. (Refer to Figure 3-1)

(Note 5) This LSI should be used in lower than this rating by all means.

Undershoot should be ≤10ns and ≤ (V_OUT1Por V_OUT1Nor V_OUT2Por V_OUT2N) +7V. (Refer to Figure 3-2)

Overshoot to OUT1P or

OUT1N or OUT2P or OUT2N

7V (Max)

VCCP1,

VCCP2

Overshoot to

GND

30V (Max)

Undershoot to Vcc

30V(Max)

BSP1P

BSP1N

BSP2P

BSP2N

Undershoot to OUT1P or

OUT1N or OUT2P or OUT2N

7V (Max)

OUT1P

OUT1N

OUT2P

OUT2N

GND

≦10ns

Figure 3-1

Figure 3-2

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Thermal Resistance^{(Note 6)}

Thermal Resistance (Typ)

Parameter

Symbol

Unit

1s^{(Note 8)}

2s2p^{(Note 9)}

VQFN032V5050

Junction to Ambient

Junction to Top Characterization Parameter^{(Note 7)}

θ_JA

138.9

11

39.1

5

°C/W

Ψ_JT

(Note 6) Based on JESD51-2A (Still-Air)

(Note 7) The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside

surface of the component package.

(Note 8) Using a PCB board based on JESD51-3.

(Note 9) Using a PCB board based on JESD51-5, 7.

Layer Number of

Measurement Board

Material

FR-4

Board Size

Single

114.3mm x 76.2mm x 1.57mmt

Top

Copper Pattern

Thickness

Footprints and Traces

70μm

Thermal Via^{(Note 10)}

Layer Number of

Measurement Board

Material

FR-4

Board Size

114.3mm x 76.2mm x 1.6mmt

2 Internal Layers

Pitch

Diameter

4 Layers

1.20mm

Φ0.30mm

Top

Copper Pattern

Bottom

Thickness

Copper Pattern

Thickness

Copper Pattern

Thickness

70μm

Footprints and Traces

70μm

74.2mm x 74.2mm

35μm

74.2mm x 74.2mm

(Note 10) This thermal via connects with the copper pattern of all layers.

Recommended Operating Conditions (Ta=-25°C to +85°C)

Parameter

Supply voltage

Symbol

V_CCP1

V_CCP2

Limit

10 to 24

Unit

V

Conditions

Pin 24^{(Note 1) (Note 2)}

Pin 17^{(Note 1) (Note 2)}

V_DVDD

Pin 10 ^{(Note 1)}

3.0 to 3.6

6.4

V

Ω

21V<V_CCP1, V_CCP2≤24V^{(Note 2)}

14V<V_CCP1, V_CCP2≤21V^{(Note 2)}

V_CCP1, V_CCP2≤14V^{(Note 2)}

Minimum load impedance

R_L

4.8

3.6

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Electrical Characteristics

(Unless otherwise specified Ta=25°C, V_CCP1, V_CCP2=18V, V_DVDD=3.3V, V_RSTX=3.3V, V_MUTEX=3.3V, f=1kHz, fs=48kHz, R_L=8Ω,

DSP: Through, Driver Gain (G_DRV) =26dB, LC Filter: L=10μH, C_g=0.47μF, Without Snubber circuit)

Limit

Typ

Parameter

Total Circuit

Symbol

Unit

Conditions

Min

Max

Pin 17, 24, -infinity dBFS input,

No load

I_CC1

I_DD1

I_CC2

-

45

9

90

19

mA

μA

Circuit Current 1

(Normal mode)

Pin 10, -infinity dBFS input, No load

Pin 17, 24, -infinity dBFS input,

No load, V_RSTX=0V, V_MUTEX=0V

Pin 10, -infinity dBFS input, No load

V_RSTX=0V, V_MUTEX=0V

110

400

Circuit Current 2

(Reset mode)

I_DD2

-

2.5

7.0

mA

Open-drain Pin

V_ERR

-

0.8

V

Pin 13, I_OUT=0.5mA

Low Level Voltage

High Level Input Voltage

Low Level Input Voltage

Input Pull-up Resistance

Input Pull-down Resistance

Input Current

V_IH

V_IL

R_UP

R_DN

2.5

0

22

31

-

33

47

3.3

0.8

-

V

kΩ

Pin 1 to 5, 9, 11, 29 to 32

Pin 2 to 4, V_IN=0V

-

Pin 1, 29, 30, V_IN=3.3V

I_IL

-1

0

-

μA

Pin 31, 32, V_IN=0V

(SCL, SDA pin)

Input Current

(SCL, SDA pin)

I_IH

-

0

1

μA

Pin 31, 32, V_IN=3.3V

Speaker Amplifier Output

V_CCP1, V_CCP2=13V,

THD+N=10%

V_CCP1, V_CCP2=16V,

THD+N=10%

Maximum Output Power 1^{(Note 11)}

P_O1

P_O2

-

10

15

-

W

Maximum Output Power 2^{(Note 11)}

V_CCP1, V_CCP2=12V, P_O=1W,

BW=AES17 (20Hz -22kHz)

With snubber circuit

P_O=1W, 1kHz BPF

Total Harmonic Distortion^{(Note 11)}

THD

-

0.08

-

%

Crosstalk^{(Note 11)}

CT

PSRR

V_NO

60

-

90

60

-

dB

V_ripple=1V_rms, f=1kHz

PSRR^{(Note 11)}

-Infinity dBFS input, BW=A-Weight

Output Noise Voltage^{(Note 11)}

-

150

μVrms

f_PWM1

f_PWM2

f_PWM3

-

256

352.8

384

-

kHz

f_S=32 kHz

f_S=44.1 kHz

f_S=48 kHz

PWM (Pulse Width Modulation)

Frequency

(Note 11) These Parameters show the typical performance of device and depend on board layout, parts, and power supply.

The standard value is in mounting device and parts on surface of ROHM’s board directly.

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Typical Performance Curves

Unless otherwise specified Ta=25°C, V_CCP1, V_CCP2=18V, V_DVDD=3.3V, V_RSTX=3.3V, V_MUTEX=3.3V, f=1kHz, fs=48kHz, R_L=8Ω,

DSP: Through, Driver Gain (G_DRV) =26dB

Measured by ROHM designed 4 layers board^{(Note 12)}

180

160

140

120

100

80

60

50

40

30

20

10

0

V_RSTX=V_MUTEX=0V

R_L=8Ω

No Signal

V_RSTX=3.3V

R_L=8Ω

No Signal

V_MUTEX=3.3V

60

40

V_MUTEX=0V

20

0

8

10 12 14 16 18 20 22 24 26

Supply Voltage: V_CCP1, V_CCP2[V]

8

10 12 14 16 18 20 22 24 26

Supply Voltage: V_CCP1,V_CCP2[V]

Figure 4. Circuit Current vs Supply Voltage

Figure 5. Circuit Current vs Supply Voltage

100

90

80

70

60

50

40

30

20

10

0

2.5

2.0

1.5

1.0

0.5

0.0

R_L=8Ω

R_L=6Ω

R_L=4Ω

R_L=8Ω

R_L=8Ω,6Ω : V_CCP1,V_CCP2=18V

R_L=4Ω

: V_CCP1,V_CCP2=14V

R_L=4Ω

: V_CCP1,V_CCP2=14V

0

5

10

15 20

0

5

10

Output Power [W/CH]

15

20

Output Power [W/CH]

Figure 6. Efficiency vs Output Power

Figure 7. Circuit Current vs Output Power

(Note 12) 100mmx100mmx1.6mm FR4 4-layer glass epoxy board Cu Thickness 35μm/70μm/70μm/35μm For Application Evaluation Board

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Typical Performance Curves - continued

Unless otherwise specified Ta=25°C, V_CCP1, V_CCP2=18V, V_DVDD=3.3V, V_RSTX=3.3V, V_MUTEX=3.3V, f=1kHz, fs=48kHz, R_L=8Ω,

DSP: Through, Driver Gain (G_DRV) =26dB

Measured by ROHM designed 4 layers board^{(Note 12)}

R_L=8Ω

Po=1W

R_L=8Ω

Po=1W

20ms/div

2ms/div

Speaker output

MUTEX(2V/div)

Figure 8. Waveform at soft start

Figure 9. Waveform at soft mute

2.5

2.0

1.5

1.0

0.5

0.0

25

20

15

10

5

R_L=8Ω

V_CCP1,V_CCP2=18V

V_CCP1,V_CCP2=12V

THD+N=10%

THD+N=1%

V_CCP1,V_CCP2=24V

0

10

12

14

16

18

20

22

24

0

5

10

15

20

Supply Voltage: V_CCP1,V_CCP2[V]

Output Power [W/CH]

Figure 10. Output Power vs Supply Voltage

Figure 11. Circuit Current vs Output Power

Caution 1: Dotted line means exceeding maximum junction temperature.In that case heat dissipation measures such as the heat sink are necessary separately.

Caution 2: Use this LSI in 20W or less output power even with heat dissipation measures.

(Note 12) 100mmx100mmx1.6mm FR4 4-layer glass epoxy board Cu Thickness 35μm/70μm/70μm/35μm For Application Evaluation Board

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Typical Performance Curves - continued

Unless otherwise specified Ta=25°C, V_CCP1, V_CCP2=18V, V_DVDD=3.3V, V_RSTX=3.3V, V_MUTEX=3.3V, f=1kHz, fs=48kHz,

DSP: Through, Driver Gain (G_DRV) =26dB

Measured by ROHM designed 4 layers board^{(Note 12)}

30

25

20

15

10

5

2.5

2.0

1.5

1.0

0.5

0.0

R_L=6Ω

V_CCP1,V_CCP2=18V

R_L=6Ω

V_CCP1,V_CCP2=12V

THD+N=10%

THD+N=1%

V_CCP1,V_CCP2=21V

0

10

12

14

16

18

20

22

0

5

10

15

20

Output Power [W/CH]

Figure 13. Circuit Current vs Output Power

Supply Voltage: V_CCP1,V_CCP2[V]

Figure 12. Output Power vs Supply Voltage

Caution 1: Dotted line means exceeding maximum junction temperature.In that case heat dissipation measures such as the heat sink are necessary separately.

Caution 2: Use this LSI in 20W or less output power even with heat dissipation measures.

2.5

2.0

1.5

1.0

0.5

0.0

20

18

16

14

12

10

8

R_L=4Ω

V_CCP1,V_CCP2=12V

V_CCP1,V_CCP2=14V

THD+N=10%

THD+N=1%

6

4

2

0

5

10

15

20

10

12

14

16

Supply Voltage: V_CCP1,V_CCP2[V]

Output Power [W/CH]

Figure 14. Output Power vs Supply Voltage

Figure 15. Circuit Current vs Output Power

Caution 1: Dotted line means exceeding maximum junction temperature.In that case heat dissipation measures such as the heat sink are necessary separately.

Caution 2: Use this LSI in 15W or less output power even with heat dissipation measures.

(Note 12) 100mmx100mmx1.6mm FR4 4-layer glass epoxy board Cu Thickness 35μm/70μm/70μm/35μm For Application Evaluation Board

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Typical Performance Curves - continued

Unless otherwise specified Ta=25°C, V_CCP1, V_CCP2=18V, V_DVDD=3.3V, V_RSTX=3.3V, V_MUTEX=3.3V, f=1kHz, fs=48kHz, R_L=8Ω,

DSP: Through, Driver Gain (G_DRV) =26dB

Measured by ROHM designed 4 layers board^{(Note 12)}

0

-20

30

28

26

24

22

20

Po=1W

B.W. none

R_L=8Ω

No Signal

B.W. none

R_L=8Ω

OUT1

OUT2

-40

-60

OUT1

OUT2

-80

-100

-120

-140

10

100

1k

10k

100k

10

100

1k

Frequency [Hz]

10k

100k

Frequency [Hz]

Figure 16. Noise FFT vs Frequency

Figure 17. Voltage Gain vs Frequency

10

1

10

B.W. 20Hz to 22kHz

Po=1W

R_L=8Ω

1

f=6kHz

f=1kHz

0.1

0.01

0.1

OUT1

z

OUT2

f=100Hz

0.01

0

1

10

100

10

100

1k

10k

100k

Frequency [Hz]

Output Power [W]

Figure 18. THD+N vs Output Power

Figure 19. THD+N vs Frequency

(Note 12) 100mmx100mmx1.6mm FR4 4-layer glass epoxy board Cu Thickness 35μm/70μm/70μm/35μm For Application Evaluation Board

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Typical Performance Curves - continued

Unless otherwise specified Ta=25°C, V_CCP1, V_CCP2=18V, V_DVDD=3.3V, V_RSTX=3.3V, V_MUTEX=3.3V, f=1kHz, fs=48kHz, R_L=8Ω,

DSP: Through, Driver Gain (G_DRV) =26dB

Measured by ROHM designed 4 layers board^{(Note 12)}

120

Po=1W

R_L=8Ω

OUT1 to OUT2

100

OUT2 to OUT1

80

60

40

20

0

10

100

1k

10k

100k

Frequency [Hz]

Figure 20. Crosstalk vs Frequency

(Note 12) 100mmx100mmx1.6mm FR4 4-layer glass epoxy board Cu Thickness 35μm/70μm/70μm/35μm For Application Evaluation Board

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Typical Performance Curves - continued

Unless otherwise specified Ta=25°C, V_CCP1, V_CCP2=18V, V_DVDD=3.3V, V_RSTX=3.3V, V_MUTEX=3.3V, f=1kHz, fs=48kHz, R_L=6Ω,

DSP: Through, Driver Gain (G_DRV) =26dB

Measured by ROHM designed 4 layers board^{(Note 12)}

0

-20

30

28

26

24

22

20

Po=1W

B.W. none

R_L=6Ω

No Signal

B.W. none

R_L=6Ω

OUT1

OUT2

-40

-60

OUT1

OUT2

-80

-100

-120

-140

10

100

1k

10k

100k

10

100

1k

10k

100k

Frequency [Hz]

Figure 21. Noise FFT vs Frequency

Figure 22. Voltage Gain vs Frequency

10

1

10

1

B.W. 20Hz to 22kHz

Po=1W

R_L=6Ω

f=6kHz

0.1

0.01

0.1

0.01

OUT1

z

f=1kHz

OUT2

f=100Hz

0

1

10

100

10

100

1k

10k

100k

Output Power [W]

Frequency [Hz]

Figure 23. THD+N vs Output Power

Figure 24. THD+N vs Frequency

(Note 12) 100mmx100mmx1.6mm FR4 4-layer glass epoxy board Cu Thickness 35μm/70μm/70μm/35μm For Application Evaluation Board

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Typical Performance Curves - continued

Unless otherwise specified Ta=25°C, V_CCP1, V_CCP2=18V, V_DVDD=3.3V, V_RSTX=3.3V, V_MUTEX=3.3V, f=1kHz, fs=48kHz, R_L=6Ω,

DSP: Through, Driver Gain (G_DRV) =26dB

Measured by ROHM designed 4 layers board^{(Note 12)}

120

OUT1 to OUT2

Po=1W

R_L=6Ω

100

OUT2 to OUT1

80

60

40

20

0

10

100

1k

10k

100k

Frequency [Hz]

Figure 25. Crosstalk vs Frequency

(Note 12) 100mmx100mmx1.6mm FR4 4-layer glass epoxy board Cu Thickness 35μm/70μm/70μm/35μm For Application Evaluation Board

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Typical Performance Curves - continued

Unless otherwise specified Ta=25°C, V_CCP1, V_CCP2=18V, V_DVDD=3.3V, V_RSTX=3.3V, V_MUTEX=3.3V, f=1kHz, fs=48kHz, R_L=4Ω,

DSP: Through, Driver Gain (G_DRV) =26dB

Measured by ROHM designed 4 layers board^{(Note 12)}

30

28

26

24

22

20

0

-20

Po=1W

B.W. none

R_L=4Ω

No Signal

B.W. none

R_L=4Ω

OUT1

OUT2

-40

-60

OUT1

OUT2

-80

-100

-120

-140

10

100

1k

Frequency [Hz]

10k

100k

10

100

1k

10k

100k

Frequency [Hz]

Figure 26. Noise FFT vs Frequency

Figure 27. Voltage Gain vs Frequency

10

B.W. 20Hz to 22kHz

Po=1W

R_L=4Ω

1

0.1

1

0.1

f=6kHz

OUT1

z

f=1kHz

OUT2

f=100Hz

0.01

0.1

1

10

100

10

100

1k

10k

100k

Output Power [W]

Frequency [Hz]

Figure 28. THD+N vs Output Power

Figure 29. THD+N vs Frequency

(Note 12) 100mmx100mmx1.6mm FR4 4-layer glass epoxy board Cu Thickness 35μm/70μm/70μm/35μm For Application Evaluation Board

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Typical Performance Curves - continued

Unless otherwise specified Ta=25°C, V_CCP1, V_CCP2=18V, V_DVDD=3.3V, V_RSTX=3.3V, V_MUTEX=3.3V, f=1kHz, fs=48kHz, R_L=4Ω,

DSP: Through, Driver Gain (G_DRV) =26dB

Measured by ROHM designed 4 layers board^{(Note 12)}

120

OUT1 to OUT2

Po=1W

R_L=4Ω

100

80

60

40

20

0

OUT2 to OUT1

10

100

1k

10k

100k

Frequency [Hz]

Figure 30. Crosstalk vs Frequency

(Note 12) 100mmx100mmx1.6mm FR4 4-layer glass epoxy board Cu Thickness 35μm/70μm/70μm/35μm For Application Evaluation Board

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Description of Function

1

DSP Block Functional Overview

No. Function

Specification

1

Pre-Scaler

•Lch/Rch become same set point.

•+48dB to -79dB (0.5dB step), -infinity dB

•It is able to set mixing of Left and Right channel which are inputted digital signal

to Audio DSP

2

Channel Mixer

•Selectable in L, (L+R) /2, L-R, R, MUTE

3

12 Band BQ

•12 Band Bi-quad (BQ) type filter.

•Only 5 coefficients are required. (b0, b1, b2, a1, a2)

•Lch/Rch dependent or independent.

•The Filter types which can be attained are

Peaking/Low-shelf/High-shelf/Low-pass/High-pass/All-pass/Notch.

•There is soft transition function.

4

5

Fine Master Volume

3 Band DRC

•Lch/Rch become same set point or independent set.

•+24dB to -103dB (0.125dB step), -infinity dB

•There are soft transition and soft mute functions.

•There are 3 band DRC.

•It is possible to set the slope of compression level.

6

7

Post-scaler

•Lch/Rch become same set point.

•+48dB to -79dB (0.5dB step), -infinity dB

•Lch/Rch become independent set point.

•+0.7dB to -0.8dB (0.1dB step)

Fine Post-scaler

8

9

DC cut HPF

Hard Clipper

•1^storder HPF

•Cut OFF frequency fc: 1Hz

•Lch/Rch become same set point.

•Clip level: 0dB to -22.5dB (-0.1dB step)

I²S

LJ

RJ

Fine

post

scaler/

ch

Fine

Master

Volum

e/ch

Pre

Scaler

Chanel

Mixer

DC cut

HPF

Hard

Clipper

3Band

DRC

Post

Scaler

12Band

/ch BQ

Input1

Main

Figure 31. DSP Block Diagram

About description of the register setting the register value is written at hex.

Also, the value with blue background is initial value.

2

RSTX Pin^{(Note 13) (Note 14)}, MUTEX Pin Function

RSTX

(29pin)

MUTEX

(30pin)

Speaker Output

DSP Block

Reset ON

(OUT1P, OUT1N, OUT2P, OUT2N)

High-Z_low^{(Note 15)}

Low

(Low power consumption)

High-Z_low^{(Note 15)}

Normal operation

(Mute ON)

High

(Mute ON) ^{(Note 16)}

Normal operation

(Mute OFF)

Normal operation

High

Low

High

(Mute OFF)

Don’t use.

(Note 13) When RSTX is set to low, internal registers are initialized.

(Note 14) If V_DVDDis under 3V, RSTX is set to low once for 10ms (Min), and set to high again. Then DSP is needed to set parameter again.

(Note 15) This means that all output transistors are OFF and output pins are pulled down by 10kΩ (Typ).

(Note 16) Speaker output becomes High-Z_low after elapse of PWM stop time after setting MUTEX Low.

Refer to PWM Sampling Frequency in next page for PWM stop time.

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Description of Function - continued

3

PWM Sampling Frequency

PWM sampling frequency of speaker output, Soft mute time, Soft start time and PWM stop time depend on sampling

frequency (f_S) of the digital audio signal. These transition times are changed by sending the data to select address 0x15[1:0].

Default=0x3

Sampling

PWM Sampling

Frequency

0x15[1:0]

Value

Soft Mute

Time

Soft Start

Time

PWM Stop

Time

frequency (f_S)

0x0

0x1

0x2

0x3

0x0

0x1

0x2

0x3

0x0

0x1

0x2

0x3

10.7ms

21.4ms

42.7ms

85.4ms

11.7ms

23.3ms

46.5ms

92.9ms

16.1ms

32.1ms

64.1ms

128.1ms

10.7ms

11.7ms

16.1ms

86ms

106ms

125ms

162ms

93ms

48kHz

384kHz

352.8kHz

256kHz

113ms

135ms

177ms

116ms

148ms

178ms

241ms

44.1kHz

32 kHz

4

Setting Driver Gain (G_DRV

)

It can change the driver gain of the output FET driver part.

Set it depending on speaker used because the maximum output level changes by speaker load impedance value.

When set the driver gain, change after setting MUTEX pin to Low (>PWM stop time).

Pop noise may be occurred if the driver gain is set while MUTEX=High.

Default=0x03

Driver Gain

Select Address

Value

G_DRV(BTL)

26dB (Typ)

32dB (Typ)

0xF3[7:0]

0x03

0x0B

Regarding 0xF3 address,

Prohibit to set except data 0x03 and 0x0B to address 0xF3.

The setting value is fixed by transmitting 0xF8=0x01. If the setting value of address 0xF3 is changed, certainly set

0xF8=0x01 again. In addition, wait time more than 10ms is necessary after 0xF8=0x01 setting.

5

Setting of When Monaural output

When monaural output setting is applied as shown in Application Circuit Example3, set 0xF2 register during start-up (Refer

to P.62 “20. The wake-up Procedure of power-up”).

Setting 0xF2=0x0A, DC voltage protection function at the speaker of OUT2 side can be disabled, therefore it is possible to

use Application Circuit Example3.

Default=0x02

Select Address

0xF2[7:0]

Value

0x02

0x0A

PWM Output

Stereo

Monaural

0xF2[7:0]

Regarding 0xF2 address,

Prohibit to set except data 0x02 and 0x0A to address 0xF2.

The setting value is fixed by transmitting 0xF8=0x01. If the setting value of address 0xF2 is changed, certainly set

0xF8=0x01 again. In addition, wait time more than 10ms is necessary after 0xF8=0x01 setting.

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Description of Function - continued

6

Level Diagram

V

_ING





^DSP

(1)DSPGain 10^^

G







20

DRV



(2)DriverGain(BTL) 10^^

20



R_L

r_DS r_DC

(3)Loss 

2





 R_L

(1)

(2)

(3)

Feedback

V_CCP1

V_CCP2

r_DS

ON

OFF

ON

LPF

r_DC

R_L

C

Feedback

driver

V_IN

DSP

(G_DSP

PWM

Modulator

FET

)

r_DS

(G_DRV

)

OFF

Cg

V_CCP1,V_CCP2

The Duty ratio of

PWM output is

different from ｔｈat

of the DSP output.

V_DVDD

0V

PWM output

from DSP

PWM output

at FET

V_CCP1,V_CCP2

V_DVDD

V_{O_DSP}

0V

V_{O_SP}

0V

DSP output signal

(It converts it into the analog signal. )

FET output signal

(It converts it into the

analog signal. )

-(V_CCP1,V_CCP2

)

Speaker output signal

(BTL output)

V_IN

G_DSP

G_DRV

: I²S input level [dBFS]

: DSP gain [dB]

: Feedback driver gain [dB]

V

_ING





^DSP

V_{O _ DSP}10^^

[Vrms]

20



V_CCP1,V_CCP2: Power supply voltage for power amp [V]

V_DVDD

R_L

r_DS

: Power supply voltage for DSP [V]

: Speaker load resistance [Ω]

: Output FET on resistance [Ω]

(Typ=0.23Ω)

G





DRV

V_{O _ SP} V_{O _ DSP}10^^

^^

R_L

r_DS r_DC R_L

20

[Vrms]

2





r_DC

: Direct current resistance of coil [Ω]

V

_ING

20

G

DRV









^DSP



²





10^^

^10^^

^^

R_L

r_DS r_DC

20

2





 R





_L

[W]

P



O(THD1%)

R_L

P

_O(THD10%)=P

×1.25

O(THD1%)

[W]

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Description of Function - continued

7

2 Wire Bus Control Signal Specification

7.1 Electrical Characteristics and Timing of Bus Line and I/O Stage

SDA

t^t^B_B^U_UF^F

t

t_F

F

t

HD;STA

t

^tLOW

t_R

R

t_LOW

SCL

t

^tHD;DAT

t

^tHIGH

^tSU;DAT

^tSU;STA

^tSU;STO

t_HD;STA

HD;STA

t_SU;STA

t_HIGH

t_SU;DAT

t_HD;STO

HD;DAT

P

S

Sr

P

Figure 32

SDA and SCL bus line characteristics^{(Note 18)}(Unless otherwise specified Ta=25°C, V_DVDD=3.3V)

High Speed Mode

Parameter

SCL Clock Frequency

Bus Free Time between a STOP and START Condition

Hold Time (repeated) START Condition.

After this period, the first clock pulse is generated.

Low Period of the SCL Clock

High Period of the SCL Clock

Set-up Time for a Repeated START Condition

Data Hold Time

Symbol

Unit

Min

0

1.3

Max

400

-

1

2

f_SCL

t_BUF

kHz

μs

3

t_HD;STA

0.6

-

μs

4

5

6

7

8

t_LOW

t_HIGH

t_SU;STA

t_HD;DAT

t_SU;DAT

t_R

t_F

t_SU;STO

Cb

1.3

0.6

-

μs

ns

μs

pF

0.6

-

0^{(Note 17)}

250

Data Set-up Time

9

Rise Time of both SDA and SCL Signals

Fall Time of both SDA and SCL Signals

Set-up Time for STOP Condition

20+0.1Cb

0.6

300

-

10

11

12

Capacitive Load for each Bus Line

-

400

Caution: The above-mentioned numerical values are all the values corresponding to V_IHminand the V_ILmaxlevel.

(Note 17) To exceed an undefined area on the fall-edge of SCL (Refer to V_IHmin of the SCL signal) , the transmitting set like SoC should internally offer the

holding time of 300ns or more for the SDA signal.

(Note 18) SCL and SDA pin is not corresponding to threshold tolerance of 5V.

Use it within Input voltage 1 of the absolute maximum rating.

7.2 Command Interface

2 wire Bus Control is used for command interface between host CPU. It not only writes but also it is possible to read it

excluding a part of register. In addition to Slave Address, set and write 1 byte of Select Address to read out the data. 2 wire

bus Slave mode format is illustrated below.

MSB

Slave Address

LSB

MSB

Select Address

LSB

MSB

LSB

S

A

Data

A

P

Figure 33

S:

Start Condition

Slave Address:

Data of 8bit in total is sent with a bit of Read mode (High) or Write mode (Low) after slave

Address (7bit) set by ADDR pin. (MSB first)

A:

Acknowledge-bit will be added byte per byte in the data that acknowledge is sent and received.

Low will be sent and received when the data is correctly sent and received.

There was no acknowledgement for High.

Select Address:

Use 1byte of select address. (MSB first)

Data:

P:

Sent and received data-byte data. (MSB first)

Stop Condition

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Command Interface - continued

MSB

6

5

LSB

SDA

SCL

Start Condition

Stop Condition

SDA↓ SCL=High

SDA↑ SCL=High

Figure 34

7.3 Slave Address

•While ADDR Pin is Low

MSB

LSB

A6

1

A5

0

A4

A3

0

A2

0

A1

0

A0

0

R/W

1/0

0

•While ADDR Pin is High

MSB

LSB

A6

1

A5

0

A4

0

A3

0

A2

0

A1

0

A0

1

R/W

1/0

Figure 35

7.4 Writing of Data

•Basic format

S

Slave Address

A

Select Address

A

Data

A

P

: Master to Slave,

: Slave to Master

•Auto-increment format

Slave Address

S

Select Address

A

Data 1

Data 2

A

Data 3…N

A

P

: Master to Slave,

Figure 36

: Slave to Master

7.5 Reading of Data

First of all, the address (0x20 in the example) for reading is written in the register of the 0xD0 address at the time of reading.

In the following stream, data is read after the slave address. Do not return the acknowledge when ending the reception.

S

Slave Address

0x80

A

Req_Addr

0xD0

A

Select Address

0x20

A

P

(ex.)

S

Slave Address

0x81

Data 1

0x**

A

Data 2

0x**

A

Data N

0x**

Ā

P

(ex.)

: Master to Slave,

: Slave to Master, A: With Acknowledge, Ā: Without Acknowledge

Figure 37

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Description of Function - continued

8

Format of Digital Audio Signal

•LRCLK: It is L/R Clock Input Signal

It is available of 32kHz/44.1kHz/48kHz with those clocks (f_S) that are same to the sampling frequency (f_S).

The data of the left channel and the right channel for one sample is input to this section.

•BCLK: It is Bit Clock Input Signal

It is used for the latch of data in everyone bit by sampling frequency’s 32 times frequency (32f_S) or 48 times frequency

(48f_S) or 64 times sampling frequency (64f_S). However, if the 32f_Sis selected, the data length is held static of 16bit.

•SDATA: It is Data Input Signal

It is amplitude data. Word length is different according to the resolution of the input digital audio signal.

It is available of 16bit/20bit/24bit.

The digital input format is available of I²S, Left-justified and Right-justified formats.

The figure below shows the timing chart of each transmission mode.

•SDATAO: Audio Data Output After DSP Processing

This output syncs with inputted LRCLK and BCLK.

Output format is available of I²S format only.

BCLK Clock 64f_S

I²S 64fs Format

LRCLK

Left Channel Right Channel

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

1

BCLK

MSB

S 141312 1110 9 8

LSB

1 0

MSB LSB

S 141312 1110 9 8 7 6 5 4 3 2 1 0

SDATA

7

6 5 4 3

2

16bit Mode

20bit Mode

24bit Mode

16bit Mode

20bit Mode

24bit Mode

Left-Justified 64fs Format

LRCLK

Left Channel Right Channel

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

1

BCLK

MSB

SDATA S 14 131211 10 9 8 7

LSB

0

LSB

MSB

S 14 131211 10 9 8 7 6 5 4 3 2 1 0

6

5 4 3 2

1

16bit Mode

20bit Mode

24bit Mode

16bit Mode

20bit Mode

24bit Mode

Right-Justified 64fs Format

LRCLK

Left Channel Right Channel

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

1

BCLK

MSB

S 1413 1211 10 9 8

LSB

1 0

MSB LSB

S 1413 1211 10 9 8 7 6 5 4 3 2 1 0

7

6 5 4 3

2

SDATA

16bit Mode

20bit Mode

24bit Mode

16bit Mode

20bit Mode

24bit Mode

Figure 38

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8

Format of Digital Audio Signal - continued

BCLK Clock 48f_S

I²S 48fs Format

LRCLK

Left Channel

Right Channel

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 1

BCLK

MSB

S 1413121110 9

LSB

MSB

LSB

8

7

6

5

4

3

2

1

0

S 1413121110 9 8 7 6 5 4 3 2 1 0

SDATA

16bit Mode

20bit Mode

24bit Mode

16bit Mode

20bit Mode

24bit Mode

Left-Justified 48fs Format

LRCLK

Left Channel

Right Channel

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

BCLK

MSB

S 1413121110 9

LSB

MSB

LSB

8

7

6

5

4

3

2

1

0

S 1413121110 9 8 7 6 5 4 3 2 1 0

SDATA

16bit Mode

20bit Mode

24bit Mode

16bit Mode

20bit Mode

24bit Mode

Right-Justified 48fs Format

LRCLK

Left Channel

Right Channel

1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

BCLK

MSB

S 1413121110 9

LSB

MSB

LSB

8

7

6

5

4

3

2

1

0

S 1413121110 9 8 7 6 5 4 3 2 1 0

SDATA

16bit Mode

20bit Mode

24bit Mode

16bit Mode

20bit Mode

24bit Mode

Figure 39

BCLK Clock 32f_S

I²S 32fs Format

LRCLK

Left Channel

Right Channel

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1

BCLK

MSB

S 1413121110 9

LSB MSB

LSB

8

7

6

5

4

3

2

1

0

S 1413121110 9 8 7 6 5 4 3 2 1 0

SDATA

16bit Mode

Left-Justified 32fs Format

LRCLK

Left Channel

Right Channel

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

BCLK

MSB

S 1413121110 9

LSB MSB

LSB

8

7

6

5

4

3

2

1

0

S 1413121110 9 8 7 6 5 4 3 2 1 0

SDATA

16bit Mode

Right-Justified 32fs Format

LRCLK

Left Channel

Right Channel

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

BCLK

MSB

S 1413121110 9

LSB MSB

LSB

8

7

6

5

4

3

2

1

0

S 1413121110 9 8 7 6 5 4 3 2 1 0

SDATA

16bit Mode

Figure 40

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Description of Function - continued

9

Format Setting for Digital Audio Signal

Set BCLK clock fs, word length and data format by transmitting command according to the inputted digital audio signal.

SDATAO output word length is able to be set independently of input word length.

It is available of I²S format only.

BCLK Clock

Default=0x0

Select Address

0x03[5:4]

Value

0x0

Explanation of Operation

64f_S

0x1

0x2

0x3

48f_S

32f_S

Don't use

Data Format

Default=0x0

Select Address

0x03[3:2]

Value

0x0

I²S format

0x1

0x2

0x3

Left-justified format

Right-justified format

Don't use

Word Length

Default=0x2

Select Address

0x03[1:0]

Value

0x0

16 bit

0x1

0x2

0x3

20 bit

24 bit

Don't use

SDATAO Output Word Length

Default=0x2

Select Address

0x78[1:0]

Value

0x0

16 bit

0x1

0x2

0x3

20 bit

24 bit

Don't use

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Description of Function - continued

10 Audio Interface Format and Timing

Electrical characteristics and timing of BCLK, LRCLK and SDATA

1/f_LRCLK

V_IH

LRCLK

V_IL

T_r

T_f

1/f_BCLK

V_IH

V_IL

BCLK

T_r

T_f

Figure 41. Clock Timing

T_HLRCLK

V_IH

V_IL

LRCLK

T_LLRCLK

t_HD;LR

t_SU;LR

T_HBCLK

V_IH

V_IL

BCLK

T_LBCLK

t_SU:SD

t_HD:SD

V_IH

V_IL

SDATA

LRCLK DUTY=f_LRCLKx (T_HLRCLKor T_LLRCLK

)

BCLK DUTY =f_BCLKx (T_HBCLKor T_LBCLK

)

Figure 42. Audio Interface Timing

Limit

No.

Parameter

LRCLK Frequency

BCLK Frequency

Symbol

f_LRCLK

f_BCLK

Unit

kHz

Min

32

-10%

2.048

-10%

20

40

Max

48

+10%

3.072

1

2

MHz

+10%

3

4

5

6

7

8

Setup Time, LRCLK^{(Note 19)}

Hold Time, LRCLK^{(Note 19)}

Setup Time, SDATA

Hold Time, SDATA

LRCLK, DUTY Ratio

BCLK, DUTY Ratio

LRCLK, BCLK,

t_SU;LR

t_HD;LR

t_SU;SD

t_HD;SD

d_LRCLK

d_BCLK

-

60

ns

%

40

%

9

T_r,T_f

-

12

ns

Rise Time, Fall Time

(Note 19) This regulation is to keep rising edge of LRCLK and rising edge of BCLK from overlapping.

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Description of Function - continued

11 Power Supply Start-up Sequence

① Power up VCCP1, VCCP2 simultaneously.

The setup order of VCCP1

(and VCCP2) and DVDD does

VCCP1,VCCP2

DVDD

VCCP1

VCCP2

DVDD

not have the constraint

3V

t

Keep RSTX to low during the

section which LRCLK,BCLK is

unstable in.

Input stable LRCLK,BCLK in the technical limit

range to show in P.26 after RSTX =high .

Take measures to show it in P.63 when input of

BCLK,LRCLK becomes unstable.

After DVDD

rises, Input

BCLK and

LRCLK.

BCLK

LRCLK

SDATA

Set RSTX to high after input more than

1ms in stable LRCLK,BCLK in the

technical limit range to show to P.26

② After DVDD

rises and 10 or

more ms

More than

10ms

passes, Input

stable LRCLK

and BCLK.

where after set

RSTX to high.

RSTX

t

More than

1ms

③ After set

RSTX to high

and 1 or more

ms passes,

please send 2

wire command.

SDA

SCL

t

Data

transmis

sion

Data

transmi

ssion

Refer to

P.62

Refer to

P.62

(No.3 to

(No.5 to

No.17)

No.4)

More than 100ms

MUTEX

④ Set MUTEX to high.

t

T_WAIT: Refer to P.74

OUT1P

OUT1N

OUT2P

OUT2N

t

Soft start time

Speaker

BTL output

(After LC filter)

t

Figure 43. Power Supply Start-up Sequence

Caution 1: Refer to P.62 “20. The wake-up Procedure of power-up”.

Caution 2: Make sure to input Low to RSTX pin from external at the time power up DVDD.

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Description of Function - continued

12 Power Supply Shut-down Sequence

③ Power down VCCP1, VCCP2 simultaneously.

VCCP1, VCCP2

VCCP1

VCCP2

DVDD

t

After PWM stop time, please stop I²S signal.

BCLK

LRCLK

SDATA

t

① SetꢀMUTEX＝low.

MUTEX

t

SCL

SDA

t

Wait Time

② After PWM stop time, set RSTX=low

RSTX

t

PWM stop

time(Refer to

P.19)

OUT1P

OUT1N

OUT2P

OUT2N

t

Soft mute time

t

Speaker

BTL output

(After LC filter)

Figure 44. Power Supply Shut-down Sequence

Caution: When power supply shut-down sequence is executed, before doing RSTX Highy → Low, set MUTEX High → Low and hold Wait time > PWM stop

time.

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Description of Function - continued

13 Protection Function

About ERRORX pin (Pin 13)

If LSI detects Output short protection or DC voltage protection or high temperature protection, LSI informs abnormality with

ERRORX pin as Low level in the protection function operation. This is a function indicating the abnormal condition of this

product.

ERRORX pin does not become Low in the case of detecting Under voltage protection or Clock stop protection.

Protection

Function

Speaker

ERRORX

Detecting & Releasing Condition

PWM Output Output^{(Note 20)}

Detecting current=10A (Typ)/5A (Min, Tj=85°C)

/3.9A (Min, Tj=150°C)

Output Short

Protection

Detecting

condition

High-Z_low

Low

(Latch)

(Latch) ^{(Note 21)}

DC Voltage

Protection

Detecting PWM output Duty ratio=0% or 100%

High-Z_low

Low

(Latch)

condition

for 42ms (Typ, f_S=48kHz) and over

(Latch) ^{(Note 21)}

Detecting

condition

Chip temperature to be more than 150°C (Min)

High-Z_low

High

Temperature

Protection

Low

Releasing

condition

Normal

operation

Chip temperature to be less than 120°C (Min)

Detecting Power supply voltage to be below

condition 7.0V (Typ)/6.0V (Min)/8.0V (Max)

High-Z_low

Under Voltage

Protection

High

Releasing Power supply voltage to be above

Normal

condition

7.5V (Typ)/6.5V (Min)/8.5V (Max)

operation

BCLK signal has stopped more than constant period

of time.

LRCLK signal has stopped more than constant period

of time.

BCLK frequency becomes lower than constant

frequency speed.

BCLK frequency becomes higher than constant

frequency speed.

Detecting

condition

High-Z_low

Clock Stop

Protection

Clock stop protection is detected if any of the

condition described above happens.

Refer to P.58 to P.61.

High

LRCLK has not stopped more than constant period

of time. And BCLK frequency keeps between the

Releasing constant frequency speed more than maximum

condition 60ms. Refer to P.58 to P. 61.

Normal

operation

(Note 20) The ERRORX pin is Nch open-drain output. The ERRORX output pin should be pulled-up by external resistor.

(Note 21) Once LSI is latched, the circuit will not be released automatically even after the abnormal condition has been removed.

The following procedure is available for recovery.

To let LSI return from latch state, set MUTEX pin to Low once for more than PWM stop time and then return it back to high.

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13 Protection Function - continued

13.1 Output Short Protection (Short to the Power Supply)

This LSI has the output short protection circuit that mutes the PWM output when the PWM output is short-circuited to the

power supply unintentionally.

Detecting condition - It will detect when MUTEX pin is set high and the current that flows in the PWM output pin

becomes over 10A (Typ) more than 0.3μs (Typ). The PWM output immediately transition to the

state of High-Z_low if detected, and LSI does the latch.

Releasing method - Set MUTEX pin to low once for more than PWM stop time (Refer to P.19) and then return it back

to high.

Short to VCC

Release from short to VCC

OUT1P (25pin)

OUT1N (21pin)

OUT2P (20pin)

OUT2N (16pin)

t

Normal operation after released

from Latch state.

PWM out： IC latches

with High-Z_low.

Over current

10A(Typ)

t

PWM stop time

ERRORX (13pin)

t

0.3µs(Typ)

MUTEX(30pin)

Latch release

Figure 45. Output Short Protection (Short to the power supply) Sequence

13.2 Output Short Protection (Short to GND)

This LSI has the output short protection circuit that mutes the PWM output when the PWM output is short-circuited to

GND unintentionally.

Detecting condition - It will detect when MUTEX pin is set high and the current that flows in the PWM output pin

becomes over 10A (Typ) more than 0.4μs (Typ). If Output short protection is detected, the

PWM output immediately transition to the state of High-Z_low, and LSI latches the stop state.

Releasing method - Set MUTEX pin to low once for more than PWM stop time (Refer to P.19) and then return it back

to high.

Short to GND

Release from short to GND

OUT1P (25pin)

OUT1N (21pin)

OUT2P (20pin)

OUT2N (16pin)

t

Normal operation after released

from latch state.

PWM out: IC latches with High -

Z_low state.

Over current

10A(Typ)

t

PWM stop time

ERRORX (13pin)

t

0.4µs(Typ)

MUTEX（30pin）

Latch release

t

Figure 46. Output Short Protection (Short to GND) Sequence

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13 Protection Function – continued

13.3 DC Voltage Protection for Speaker

When the DC voltage is applied to the speaker unintentionally, the embedded DC Voltage Protection circuit mute the

PWM output circuit for preventing the speaker from destruction.

Detecting condition - It will detect when MUTEX pin is set to high and PWM output Duty ratio=0% or 100% over

42ms (fs=48kHz). The PWM output immediately transition to the state of High-Z_low if detected,

and LSI does the latch.

Releasing method - Set MUTEX pin to low once for more than PWM stop time (Refer to P.19) and then return it back

to high.

Abnormal state release

PWM out locked duty=100% abnormal state.

OUT1P (25pin)

OUT1N (21pin)

OUT2P (20pin)

OUT2N (16pin)

PWM out: IC latches with High -Z_low state

t

.

Normal operation after released latch state

Speaker

BTL Output

(After LC Filter)

t

Soft start

Protection starts by a DC

voltage having been

applied to a speaker

more than 42ms

PWM stop time

ERRORX(13pin)

t

MUTEX(30pin)

Latch release

t

Figure 47. DC Voltage Protection in the Speaker Sequence

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13 Protection Function – continued

13.4 High Temperature Protection

This LSI has the high temperature protection circuit that prevents from thermal runaway under an abnormal state for

the temperature of the chip to exceed Tj=150°C(Min).

Detecting condition - It will detect when MUTEX pin is set to high and the temperature of the chip becomes 150°C

(Min) or more. The speaker output immediately transitions to the state of High-Z_low.

Releasing condition - It will release when MUTEX pin is set to high and the temperature of the chip becomes 120°C

(Min) or less. If this protection is released, the PWM output pin return to output PWM signal

state (Auto recovery).

Temparature of

IC chip junction (℃)

150 °C(Min)

120°C(Min)

t

OUT1P (25pin)

OUT1N (21pin)

OUT2P (20pin)

OUT2N (16pin)

PWM out: High-Z_low

t

Speaker

BTL output

(After LC filter)

t

ERRORX (13pin)

t

Figure 48. High Temperature Protection Sequence

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13 Protection Function – continued

13.5 Under Voltage Protection

This LSI has under voltage protection circuit that makes PWM output mutes when extreme drop of the power supply

voltage is detected.

Detecting condition - It will detect when MUTEX pin is set to high and the power supply voltage becomes lower than

7.0V (Typ). The speaker output immediately transitions to the state of High-Z_low when

detected.

Releasing condition - It will be released when MUTEX pin is set to high and the power supply voltage becomes

more than 7.5V (Typ). If this protection is released, the PWM output pin return to output PWM

signal state (Auto recovery).

VCCP1 (24pin)

VCCP2 (17pin)

7.5V(Typ)

7.0V(Typ)

t

OUT1P (25pin)

OUT1N (21pin)

OUT2P (20pin)

OUT2N (16pin)

PWM output : High-Z_low

t

Speaker

BTL output

(After LC filter)

t

ERROR(13pin)

t

Figure 49. Under Voltage Protection Sequence

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13 Protection Function – continued

13.6 Clock Stop Protection

This LSI has the clock stop protection circuit that makes PWM output mutes when the BCLK and LRCLK frequency of

the digital audio signal are stopped or become high frequency or become low frequency more than given period.

Detecting condition - If BCLK frequency is stop or high or low, LRCLK frequency is stop.

The speaker output immediately transitions to the state of High-Z_low when detected.

Releasing condition - If BCLK and LRCLK are normal input over 60ms (Max) and more.

After 60ms (Max) from releasing, the PWM output pin return to output PWM signal state after

soft start (Auto recovery).

High/Low frequency or stop

Normal input

BCLK

LRCLK

60ms(Max)

Internal

Error

flag

t

OUT1P

OUT1N

PWM output : High-Z_low

OUT2P

OUT2N

t

Soft start time

Speaker

BTL output

(After LC filter)

t

Figure 50. Clock Stop Protection Sequence

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Description of Function - continued

14 Digital Sound Processing (DSP)

The digital sound processing (DSP) part of BM28723AMUV is composed of special hardware which is optimal for TV and

Mini/Micro Component System. BM28723AMUV does the following processing using this special DSP.

Pre-Scaler, Channel mixer, 12 Band BQ, Fine Master Volume, 3 Band DRC, Fine Post-scaler,

DC Cut HPF, Hard Clipper

The outline and signal flow of the DSP part

Data width:

Machine cycle:

Multiplier:

32 bit (DATA RAM)

20.3ns (1024f_S, fs=48kHz)

32x24 → 56 bit

Data

RAM

In

MUX

Adder:

Data RAM:

56+56 → 56 bit

512x32 bit

0

Coef

RAM

Coefficient RAM:

Sampling frequency:

512x24 bit

fs=32k, 44.1k, 48kHz

MUX

Decorder

ADD

Acc

Out

I²S

LJ

RJ

Fine

post

scaler/

ch

Fine

Pre

Scaler

Chanel

Mixer

DC cut

HPF

Hard

Clipper

3Band

DRC

Post

Scaler

12Band

/ch BQ

Input1

Main

Master

Volum

e/ch

Figure 51

Digital signal from 16bit to 24bit is inputted to the DSP but extends 8bit (+48dB) as the overflow margin to the MSB side.

When the processing is over this range, it will be clip processing inside DSP. Note that in case of commonly used second

IIR-type (BQ) filter is the digital filter, output of the internal multiplier and adder will consume a lot of overflow margin.

The output of multipliers and the adder might exceed +48dB by the

coefficient of a1, a2, b0, b1, and b2. In that case, data becomes

saturation output. Therefore, the output of the filter cannot obtain

the aimed characteristic.

X[n]

Y[n]

b0

b1

b2

Z^-1

X[n-1]

a1

a2

Y[n-1]

Z^-1

X[n-2]

Y[n-2]

-1 is multiplied by the coefficient of a1 and a2.

Considering efficiency of calculation at DSP.

Direct form 1

Figure 52

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14 Digital Sound Processing (DSP) - continued

The management of audio data and coefficient data is as follows by each block.

Decimal point

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Extension bit Data[22:0]

Decimal point

9

1

8

0

7

6

5

4

3

2

1

0

S

Audio data

Data of DSP part

23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

S

EXT. bit

Coefficient data[20:0] for BQ etc.

Coefficient data of DSP part

Coefficient data

Figure 53

14.1 Bypass

There are commands to bypass selected DSP functions. This bypass can be set even the setting values are remained for

each function; therefore, it is easy to check ON/OFF of the sound effect.

There are three bypass options, which are 12Band BQ, 3Band DRC or the whole DSP except Hard Clipper.

I²S

LJ

RJ

Fine

Master

Volum

e/ch

Fine

post

scaler/

ch

12Ban

d

/ch BQ

Pre

Scaler

Chanel

Mixer

Post

Scaler

DC cut

HPF

3Band

DRC SW2

Hard

Clipper

Input1

Main

SW3

SW1

Figure 54

Default=0x0

Select Address

0x02[2:0]

bit

2

Explanation of Operation

Bypass of 12 Band BQ (SW1) 0: Normal 1: Bypass

Bypass of 3 Band DRC (SW2) 0: Normal 1: Bypass

1

Bypass of DSP (SW3)

(Except Hard Clipper)

0: Normal 1: Bypass

0

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14 Digital Sound Processing (DSP) - continued

14.2 Pre-Scaler

To overflow when the level sometimes is full scale entry in case of the digital signal which is inputted to the sound DSP and

does surround and equalizer processing, it adjusts an entry gain with Pre-Scaler. The adjustable-range can be set from

+48dB to -79dB with the 0.5dB step. (Lch/Rch dependent control)

Pre-Scaler does not have the soft transition function.

Default=0x60

Select Address

0x16[7:0]

Explanation of Operation

Value

0x00

0x01

Gain

+48dB

+47.5dB

0x60

0x61

0x62

0dB

-0.5dB

-1dB

0xFE

0xFF

-79dB

-∞

14.3 Channel Setup with a Phase Inversion Function Channel Mixer 1

This function mixes the sound on the left channel and the right channel of the digital signal which was inputted to the DSP.

Here, it changes stereo signal to monaural. In addition, the phase-inversion, the mute on each channel can be set.

Channel Mixer

L

±1

Lch

(L+R)/2

1/2

Input

I²S

LJ

RJ

L-R

Pre-

Scaler

-

R

±1

Rch

Mute

0

Figure 55

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14.3 Channel Setup with a Phase Inversion Function Channel Mixer 1- continued

DSP Input: The data inputted into Lch of DSP is inverted.

Default=0x0

Select Address

0x17[7]

Value

Explanation of Operation

0x0

Normal

Invert

0x1

DSP Input: The data inputted into Lch of DSP is mixed.

Default=0x1

Select Address

0x17[6:4]

Value

Explanation of Operation

0x0

Mute

0x1

0x2

0x3

0x4

Lch data input

Rch data input

(Lch+Rch)/2 data input

Lch-Rch data input

DSP input: The data inputted into Rch of DSP is inverted.

Default=0x0

Select Address

0x17[3]

Value

Explanation of Operation

0x0

Normal

Invert

0x1

DSP Input: The data inputted into Rch of DSP is mixed.

Default=0x2

Select Address

0x17[2:0]

Value

Explanation of Operation

0x0

Mute

0x1

0x2

0x3

0x4

Lch data input

Rch data input

(Lch+Rch)/2 data input

Lch-Rch data input

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14 Digital Sound Processing (DSP) - continued

14.4 Bi-quad Type Filter

This LSI has the following blocks that have a feature of the Bi-quad type filter:

12 Band BQ, Crossover filter of 3Band DRC block and BQ of the soft transition.

The shapes that can be used are peaking filter, low shelf filter, high shelf filter, low pass filter, high pass filter, all path filter

and notch filter.

Setting the coefficient of the digital filter (b0, b1, b2, a1, a2) in the LSI by transmitting to the coefficient RAM via command.

12 Band BQ have the soft transition function. Note that the detailed order of the parameter setting refers to the following

BQ setting method.

Select of BQ independent or dependent setting

Default=0x0

Select Address

0x60[4]

Value

0x0

Explanation of Operation

L/R dependent setting

0x1

L/R independent setting

0x60[4] setting note.

Reset all the Bi-quad type filters when you change the setting of 0x60[4].

The Bi-quad type filters for which the re-setting is necessary are 18 BQs of BQ1-12, DRC1,DRC2 and DRC3 (Each DRC

has 2 band).

Select the destination of BQ soft transition

Default=0x00

Select Address

Explanation of Operation

0x51[4:0]

Destination

12BAND(1)

12BAND(2)

12BAND(3)

12BAND(4)

12BAND(5)

12BAND(6)

12BAND(7)

12BAND(8)

12BAND(9)

12BAND(10)

Destination

12BAND(11)

12BAND(12)

Value

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

Value

0x0A

0x0B

Select of soft transition

Default=0x0

Select Address

0x53[6]

Value

0x0

Explanation of Operation

Use soft transition

0x1

Not use soft transition

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14.4 Bi-quad Type Filter – continued

Select the destination channel of soft transition

Default=0x0

Select Address

0x53[5:4]

Value

Explanation of Operation

Lch and Rch

0x0

0x1

0x2

0x3

Lch

Rch

Don't use

Setting of soft transition time

Default=0x3

Select Address

0x53[3:2]

Value

0x0

Explanation of Operation

2.7ms

0x1

0x2

0x3

5.3ms

10.7ms

21.3ms

Setting of transition filter wait time

Default=0x0

Select Address

0x53[1:0]

Value

0x0

2.7ms

0x1

0x2

0x3

5.3ms

10.7ms

21.3ms

Setting of soft transition start

Default=0x0

Select Address

0x58[0]

Value

0x0

Stop the soft transition operation

Start the soft transition operation (After the transition is completed, it

becomes 0x0 by the automatic operation)

0x1

This register is write only.

Read-out soft transition status

Read only

Select Address

Explanation of Operation

0x59[0]

0x1 is read at the time of executing soft transition

0x0 is read at the time of except executing soft transition

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14 Digital Sound Processing (DSP) - continued

14.5 Volume Setting

Volume is from +24dB to -103dB, and can be selected by the step of 0.125dB. And it is also possible to be set to -infinity

dB. L/R independent or L/R dependent can be selected by 0x10[7]. At the time of switching of Volume, soft transition is

executed. Soft transition duration is optional with the command.

It becomes the following formula at the transition from AdB to BdB. C is soft transition duration selected by 0x15[7:6]

command.

A

B

20













_^









20

10 ^10^

C





Transition time =

[ms]





Setting of soft transition time

Default=0x0

Select Address

Value

0x0

Explanation of Operation

0x15[7:6]

21.3ms

42.7ms

85.3ms

Don't use

0x1

0x2

0x3

Lch/dependent volume setting

Default=0xFF

Select Address

0x11[7:0]

Explanation of Operation

Value

0x00

0x01

Gain

+24dB

+23.5dB

0x30

0x31

0x32

0dB

-0.5dB

-1dB

0xFE

0xFF

-103dB

-∞

Fine volume setting function becomes effective by sending the following command.

When using this command, it is possible to set a volume in 0.125dB step.

When L/R dependent volume setting, 0x11[7:0] is enable.

When L/R independent volume setting, 0x11[7:0] is the volume setting of Lch.

Lch/dependent fine volume setting

It is possible to use with the 0.5dB step in changing only 0x11[7:0] when 0x10[1:0]=0x0.

Default=0x0

Select Address

0x10[1:0]

Value

0x0

Explanation of Operation

0dB

0x1

0x2

0x3

-0.125dB

-0.25dB

-0.375dB

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14.5 Volume Setting - continued

The Lch/Rch independent volume setting and the dependent volume setting can be selected by 0x10[7] command.

When Lch/Rch independent volume set, the volume setting of Lch is the setting of 0x10[1:0] and 0x11, and the volume

setting of Rch is the settings of 0x10[5:4] and 0x12.

Setting of Lch/Rch independent volume

Default=0x0

Select Address

0x10[7]

Value

0x0

Explanation of Operation

Lch/Rch dependent volume setting

Lch/Rch independent volume setting

0x1

Setting of volume (Setting of Rch volume, It is enable only to set an independent volume. )

Default=0xFF

Select Address

0x12[7:0]

Explanation of Operation

Value

0x00

0x01

Gain

+24dB

+23.5dB

0x30

0x31

0x32

0dB

-0.5dB

-1dB

0xFE

0xFF

-103dB

-∞

Fine volume setting function becomes effective by sending the following command.

When using this command, it is possible to set a volume in 0.125dB step.

Setting of fine volume (Setting of Rch fine volume, It is enable only to set an independent volume. )

It is possible to use with the 0.5dB step in changing only 0x12[7:0] when 0x10[5:4]=0.

Default=0x0

Select Address

0x10[5:4]

Value

0x0

Explanation of Operation

0dB

0x1

0x2

0x3

-0.125dB

-0.25dB

-0.375dB

It is possible to use with the 0.125dB step in setting both 0x10[1:0] and 0x11[7:0].

In case of 0x10[1:0]=0x0, it becomes the set value of 0x11[7:0].

In case of 0x10[1:0]=0x1, it becomes the -0.125dB set value of 0x11[7:0].

In case of 0x10[1:0]=0x2, it becomes the -0.25dB set value of 0x11[7:0].

In case of 0x10[1:0]=0x3, it becomes the -0.375dB set value of 0x11[7:0].

Since the transfer of 0x11 fixes it in any case, the soft transition can be beforehand begun in the set value for the direct

following of the purpose in setting 0x11 after setting in 0x10.

0x10[5:4] is the same function as 0x10[1:0], 0x12 is the same function as 0x11 when Lch/Rch independently set for Rch.

0x11

0x10→0x11

0x11

0x10→0x11

Volume

When use 0.5dB steps

When use 0.125dB steps

Figure 56

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14 Digital Sound Processing (DSP) - continued

14.6 3 Band DRC

This DRC is used in order to prevent speaker protection and the clip output of a large audio signal.

There are three kinds of DRC (DRC1, DRC2, and DRC3) , and no clip can be output to each three BAND.

DRC1, DRC2 and DRC3 can set up two threshold levels. Moreover, it is possible to also change one slope.

3 Band DRC block diagram

Cross over

AGC_TH1, Slope α

Filters

DRC4

DRC3

HPF

Input

Output

AGC_TH1, Slope α

DRC1

LPF

AGC_TH1, Slope α

DRC2

APF

Figure 57

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14.6 3 Band DRC - continued

DRC transition figure

Input

A_TIME

AGC_TH

Volume

Level

Output

AGC_TH

R_TIME

A_RATE

R_RATE

A_TIME

In here A_TIME is the time for detecting time before gain starts to decrease. And A_RATE decides the slope of gain

compression.

On the other hand, R_TIME is the time for detecting before starting to release gain operation. And R_RATE decides slope

of release gain.

Figure 58

DRC1, DRC2, DRC3 can be set 2 types of threshold (AGC_TH1 and AGC_TH2) as shown below. If output is in between

AGC_TH1 and AGC_TH2, a slant for output gain can be made. If input become bigger and output over AGC_TH2, output

gain doesn’t have slant and become constant level. Slope setting (α) is calculated by AGC_TH1, AGC_TH2 and the value

of input gain to DRC block for reaching AGC_TH2 (xdB).

The operation between AGC_TH1 and AGC_TH2 is named as DRC1_slopeand DRC2_slopeand DRC3_slope

.

And the operation over AGC_TH2 is named as DRC1_compand DRC2_compand DRC3_comp

.

Each operation can be set ON/OFF, A_TIME, A_RATE, R_TIME, R_RATE respectively.

For example, DRC1 do not have slope curve when setting DRC1_slopeOFF and DRC1_compON.

DRC4 can be set only AGC_TH2 therefore DRC4 do not have slope function.

DRC input-and-output gain characteristics

[dB]

V_O

The formula which asks for Slope α is described below.

α changes into 8bit Hex data of the complement of 2 the value

α =0x00

calculated by calculation.

10₂^y₀10₂^x₀

α

AGC_TH2

y=-6dB

 

128

10^TH10₂^x₀

20

AGC_TH1

-12dB

α =0x80

TH is AGC_TH1. x is input level. y is output level.

Ex) It asks for α at the time of AGC_TH1 = -12dB, x = 0dB y = -6dB

10^610₂⁰₀

Slope function Compressor

Area Area

20

 

128

10^₂¹₀²10₂⁰₀

  85 .266

V_Oinf

→ 0x55

0x55calculated is setto command0x29, 0x31 or 0x39.

-12dB

x=0dB

V_Iinf

V_I

Figure 59

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14.6 3 Band DRC - continued

Volume Curve

Volume

Level

Linear

Curve

Linear

Curve

Exponential

Curve

Exponential

Curve

AGC_TH

A_RATE

R_RATE

Time

Figure 60

DRC1_slopeON/OFF setting

OFF is through output.

Default=0x1

Select Address

0x20[7]

Value

0x0

Explanation of Operation

OFF

0x1

ON

DRC1_compON/OFF setting

OFF is through output.

Default=0x1

Select Address

0x20[6]

Value

0x0

OFF

ON

0x1

DRC2_slopeON/OFF setting

OFF is through output.

Default=0x1

Select Address

0x20[5]

Value

0x0

OFF

ON

0x1

DRC2_compON/OFF setting

OFF is through output.

Default=0x1

Select Address

0x20[4]

Value

0x0

Explanation of Operation

OFF

ON

0x1

DRC3_slopeON/OFF setting

OFF is through output.

Default=0x1

Select Address

0x20[3]

Value

0x0

Explanation of Operation

OFF

ON

0x1

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14.6 3 Band DRC - continued

DRC3_compON/OFF setting

OFF is through output.

Default=0x1

Select Address

0x20[2]

Value

0x0

Explanation of Operation

OFF

ON

0x1

DRC4 ON/OFF setting

OFF is through output.

Default=0x0

Select Address

0x3F[4]

Value

0x0

Explanation of Operation

OFF

ON

0x1

The volume curve at the time of an attack (A_RATE) is selected.

Default=0x1

Select Address

0x21[7]

Value

0x0

Linear curve

0x1

Exponential curve

The volume curve at the time of a release (R_RATE) is selected.

Default=0x1

Select Address

0x21[6]

Value

0x0

Linear curve

0x1

Exponential curve

Initial setting of DRC cross over filter is 1 Band.

To set the crossover filter (HPF, LPF and APF) which divides the frequency band of 3 Band DRC, therefore, it is referred to

the 14.4 Bi-quad Type Filter.

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14.6 3 Band DRC - continued

Slope (α) setting of DRC1_slope, DRC2_slope, and DRC3_slope

Each DRC can be set individually.

Default=0x80

Select Address

Explanation of Operation

[dB]

V_O

The formula which asks for Slope α is described below.

changes into 8bit Hex data of the complement of 2 the value

calculated by calculation.

DRC1_slope0x29[7:0]

α =0x00

α

DRC2_slope0x31[7:0]

y

20

x

20

y

x

α

10²⁰10²⁰

10 -10

DRC3_slope0x39[7:0]

AGC_TH2

y=-6dB

 

128

× 128

x

α

=

TH

x

20

TH

20

10 ²⁰10²⁰

10 -10

AGC_TH1

-12dB

α =0x80

TH is AGC_TH1. x is input level. y is output level.

Ex) It asks for α at the time of AGC_TH1 = -12dB, x = 0dB y = -6dB

-6

0

20

6

0

20

Slope function Compressor

Area Area

10 -10

₌10²⁰10

α

²×⁰128

 

128

0

-12

0

20

12

20

10 -10

10 ²⁰10²⁰

α

= 85.266 → 0x55

V_Oinf

0x55calculated is setto command0x29, 0x31 or 0x39.

-12dB

x=0dB

V_Iinf

V_I

AGC_TH1 setting of DRC1_slope, DRC2_slope, and DRC3_slope

Please set this value is smaller than the value of AGC_TH2.

Each DRC can be set individually.

Default=0x40

Select Address

Explanation of Operation

DRC1_slope0x28[6:0]

DRC2_slope0x30[6:0]

DRC3_slope0x38[6:0]

Threshold

Value

0x00

…

-32dB

…

0x3F

0x40

0x41

-0.5dB

0dB

+0.5dB

…

0x58

…

+12dB

AGC_TH2 setting of DRC1_comp, DRC2_comp, DRC3_comp, and DRC4

Each DRC can be set individually.

Default=0x40

Select Address

Explanation of Operation

DRC1_comp0x2C[6:0]

DRC2_comp0x34[6:0]

DRC3_comp0x3C[6:0]

Threshold

Value

0x00

…

-32dB

…

DRC4

0x40[6:0]

0x3F

0x40

0x41

-0.5dB

0dB

+0.5dB

…

0x58

…

+12dB

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A_RATE setting of DRC1_slope, DRC2_slope, DRC3_slope, DRC1_comp, DRC2_comp, DRC3_comp, DRC4

(Transition time setting for attack function)

Each DRC can be set individually.

Default=0x3

Select Address

Explanation of Operation

DRC1_slope0x2A[6:4]

DRC2_slope0x32[6:4]

DRC3_slope0x3A[6:4]

DRC1_comp0x2E[6:4]

DRC2_comp0x36[6:4]

DRC3_comp0x3D[6:4]

Value

0x0

0x1

0x2

0x3

A_RATE

1ms

2ms

3ms

4ms

Value

0x4

0x5

0x6

0x7

A_RATE

5ms

10ms

20ms

40ms

DRC4

0x41[6:4]

R_RATE setting of DRC1_slope, DRC2_slope, DRC3_slope, DRC1_comp, DRC2_comp, DRC3_comp, DRC4

(Transition time setting for release function)

Each DRC can be set individually.

Default=0xB

Select Address

Explanation of Operation

DRC1_slope0x2A[3:0]

DRC2_slope0x32[3:0]

DRC3_slope0x3A[3:0]

DRC1_comp0x2E[3:0]

DRC2_comp0x36[3:0]

DRC3_comp0x3D[3:0]

Value

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

R_RATE

0.125s

0.1825s

0.25s

0.5s

Value

0x8

0x9

0xA

0xB

0xC

0xD

0xE

0xF

R_RATE

2s

2.5s

3s

4s

0.75s

1s

5s

6s

DRC4

0x41[3:0]

1.25s

1.5s

7s

8s

A_TIME setting of DRC1_slope, DRC2_slope, DRC3_slope, DRC1_comp, DRC2_comp, DRC3_comp, DRC4

(Detection time setting for attack function)

Each DRC can be set individually.

Default=0x1

Select Address

Explanation of Operation

DRC1_slope0x2B[7:4]

DRC2_slope0x33[7:4]

DRC3_slope0x3B[7:4]

DRC1_comp0x2F[7:4]

DRC2_comp0x37[7:4]

DRC3_comp0x3E[7:4]

Value

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

A_TIME

0ms

Value

0x8

0x9

0xA

0xB

0xC

0xD

0xE

0xF

A_TIME

6ms

0.5ms

1ms

7ms

8ms

1.5ms

2ms

9ms

10ms

20ms

30ms

40ms

3ms

DRC4

0x42[7:4]

4ms

5ms

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R_TIME setting of DRC1_slope, DRC2_slope, DRC3_slope, DRC1_comp, DRC2_comp, DRC3_comp, DRC4

(Detection time setting for release function)

Each DRC can be set individually.

Default=0x3

Select Address

Explanation of Operation

DRC1_slope0x2B[2:0]

DRC2_slope0x33[2:0]

DRC3_slope0x3B[2:0]

DRC1_comp0x2F[2:0]

DRC2_comp0x37[2:0]

DRC3_comp0x3E[2:0]

Value

0x0

0x1

0x2

0x3

R_TIME

Value

0x4

0x5

0x6

0x7

R_TIME

100ms

200ms

300ms

400ms

5ms

10ms

25ms

50ms

DRC4

0x42[2:0]

14.7 Post-scaler

Post-scaler is used to adjust the gain of post DSP processing data.

The adjustable-range can be set from +48dB to -79dB with the 0.5dB step. (Lch/Rch dependent control)

Pre-Scaler does not have a soft transition function.

Default=0x60

Select Address

0x13[7:0]

Explanation of Operation

Value

0x00

0x01

Gain

+48dB

+47.5dB

0x60

0x61

0x62

0dB

-0.5dB

-1dB

0xFE

0xFF

-79dB

-∞

14.8 Fine Post-scaler

This function block is located after Post-scaler. An adjustable range can be set up from +0.7dB to –0.8dB at 0.1dB step.

Fine Post-scaler does not have a soft transition function.

(Independent control of Lch/Rch.)

Default=0x8

Select Address

Lch 0x14[7:4]

Rch 0x14[3:0]

Explanation of Operation

Value

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

Gain

Value

0x8

Gain

-0.8dB

-0.7dB

-0.6dB

-0.5dB

-0.4dB

-0.3dB

-0.2dB

-0.1dB

0dB

0x9

+0.1dB

+0.2dB

+0.3dB

+0.4dB

+0.5dB

+0.6dB

+0.7dB

0xA

0xB

0xC

0xD

0xE

0xF

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14 Digital Sound Processing (DSP) - continued

14.9 Hard Clipper

Measure the rated output power (practical maximum output power) of TV or any audio products at the 10% of Total

Harmonic Distortion (THD+N). It can be made to clip with any output amplitude by using a clipper function. For example,

the rated output of 10W or 5W can be gained using the amplifier of 15W output.

Hard clip

Clip level： 0dB

Clip level： -3dB

+3dB

0dB

+3dB

0dB

+3dB

0dB

-3dB

-6dB

-3dB

-6dB

-3dB

-6dB

Figure 61

Clipper setting

Default=0x1

Select Address

0x1A[0]

Value

0x0

Explanation of Operation

Not use Clipper function

Use Clipper function

0x1

Clip level selection

Default=0xE1

Select Address

0x1B[7:0]

Explanation of Operation

Value

0x00

0x01

Gain

-22.5dB

-22.4dB

0xE0

0xE1

-0.1dB

0dB

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14 Digital Sound Processing (DSP) - continued

14.10 DC Cut 1^storder HPF

DC offset element of the digital signal from audio DSP is cut by this HPF.

The cutoff frequency fc of HPF uses the 1Hz filter, and the degree uses the first-order filter.

Default=0x1

Select Address

0x18[0]

Value

0x0

Explanation of Operation

Not use DC Cut HPF

Use DC Cut HPF

0x1

14.11 RAM Clear

The data RAM of DSP and coefficient RAM are cleared.

40μs or more is required until all the data is cleared.

After RAM Clear state keeps 40µs or more, change the mode RAM Clear to Normal.

Clear of the data RAM

Default=0x1

Select Address

0x01[7]

Value

0x0

Explanation of Operation

Normal

0x1

Clear operation

Clear of coefficient RAM

Default=0x1

Select Address

0x01[6]

Value

0x0

Normal

0x1

Clear operation

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14 Digital Sound Processing (DSP) - continued

14.12 Audio Output Level Meter

It is possible to output the peak level of the PCM data inputted into a PWM processor.

A peak value can be read using the 2-wire command interface as 16 bit data of an absolute value.

The interval holding a peak value can be selected from six steps (50ms step) from 50ms to 300ms.

A peak hold result can be selected from L channel, R channel, and a monaural channel {(Lch+Rch)/2}.

Audio Output Level Meter block diagram

I²S

DSP

Peak Hold

(Lch)

Peak Hold

(Rch)

0.5

Selector

0x75 METER_LOAD [1:0]

Level Output Register

0x76, 0x77 OUT_LEVEL [15:0]

Figure 62

Setting of the peak level hold time interval of Audio Output Level Meter

Default=0x00

Select Address

0x74[2:0]

Explanation of Operation

Hold time

50ms

Value

0x0

0x1

0x2

0x3

0x4

0x5

100ms

150ms

200ms

250ms

300ms

Specify the read-target signal of Audio Level Meter.

A value will be taken into a read-only register if a setting value is written in.

In order to update this register value, it is necessary to write in a setting value again.

Write only

Select Address

0x75[1:0]

Value

0x0

Explanation of Operation

The peak level of L channel

0x1

0x2

The peak level of R channel

The peak level of monaural channel {(Lch+Rch)/2}

Read-back of Audio Output Level

0x76 (upper 8 bits) and a 0x77 (lower 8 bits) commands are read for the maximum within the period appointed by the

command 0x74 using the 2-wire interface.

(Example)

When 0xFFFF is read, mean 1.0 (0dBFS).

When 0x8000 is read, mean 0.5 (-6dBFS).

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Description of Function - continued

15 Setting and Reading Method of BQ

It explains a detailed sequence of the setting method and the reading method of BQ separately for usage.

15.1 BQ coefficient setting

BQ consists of Bi-quad filter as follows. Each coefficient b0, b1, b2, a1, and a2 of BQ can be written directly.

It is S2.21 format, and setting range is -4≤x<+4.

Moreover, the coefficient address is shown in Table 1.

The output of multipliers and the adder might exceed +48dB by the

coefficient of a1, a2, b0, b1, and b2. In that case, data becomes

saturation output. Therefore, the output of the filter cannot obtain

the aimed characteristic.

X[n]

Y[n]

b0

b1

b2

Z^-1

X[n-1]

a1

a2

Y[n-1]

Z^-1

X[n-2]

Y[n-2]

-1 is multiplied by the coefficient of a1 and a2.

Considering efficiency of calculation at DSP.

Direct form 1

Figure 63

15.2 Writing sequence (Set in numerical order)

1. Address setting (0x61) Refer to Table 1.

2. 24bit coefficient upper [23:16] bit setting (0x62[7:0])

3. 24bit coefficient middle [15:8] bit setting (0x63[7:0])

4. 24bit coefficient lower [7:0] bit setting (0x64[7:0])

5. The writing of coefficients is performed. (0x65[0]=0x1)

Caution 1: After completion of writing coefficients this register is cleared automatically.

It is not necessary to write 0x65[0]=0x0. Coefficient writing takes about 100μs.

Caution 2: 100μs should not change an address setup and 24-bit coefficient setup after coefficient write-in execution.

(ex) When 0x3DEDE7 is written, same L/Rch, 12band BQ1 b0

1. 0x61=0x00 (12band BQ1 b0 is appointed)

2. 0x62=0x3D (Upper [23:16] is setting)

3. 0x63=0xED (Middle [15:8] is setting)

4. 0x64=0xE7 (Lower [7:0] is setting)

5. 0x65=0x01 (Coefficient transfer)

6. 100μs or more wait

15.3 Read-back sequence (Set in numerical order)

1. Address setting (0x61) Refer to Table 1.

2. Setting of a read-back register address (0xD0) Refer to P.22 “5 Reading of Data”

3. Read-back of the 24bit coefficient upper [23:16] bit (0x66[7:0])

4. Read-back of the 24bit coefficient middle [15:8] bit (0x67[7:0])

5. Read-back of the 24bit coefficient lower [7:0] bit (0x68[7:0])

15.4 When the coefficient of BQ is set up directly and a soft transition is performed

1. Set BQ coefficient to soft transition addresses. The addresses are 0x50 to 0x54. Please refer to Table1.

Since in the case of 0x60[4]=0x1 (Enable L/R independent setting) and 0x53[5:4]=0x0 a soft transition is carried out

and it is set to LR simultaneously, please write a coefficient in both LR address.

In the case of 0x53[5:4]=0x1, coefficient is set to only Lch address.

In the case of 0x53[5:4]=0x2, coefficient is set to only Rch address.

2. Select BQ Band that is performed soft transition by setting 0x51[4:0] address.

(Refer to chapter 14.4 Bi-quad Type Filter)

3. 0x58[0]=0x1, Start soft transition (After the completion of soft transition this register is automatically cleared 0x0.)

4. Wait soft transition completion, or read command 0x59[0], and wait until it 0x59[0] cleared (0x0).

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15 Setting and Reading Method of BQ- continued

Table1. Specified Coefficient

0x61[6:0]

Value

0x61[6:0]

Value

0x61[6:0]

Value

Select Coefficient

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

0x22

12BandBQ1 b0

12BandBQ1 b1

12BandBQ1 b2

12BandBQ1 a1

12BandBQ1 a2

12BandBQ2 b0

12BandBQ2 b1

12BandBQ2 b2

12BandBQ2 a1

12BandBQ2 a2

12BandBQ3 b0

12BandBQ3 b1

12BandBQ3 b2

12BandBQ3 a1

12BandBQ3 a2

12BandBQ4 b0

12BandBQ4 b1

12BandBQ4 b2

12BandBQ4 a1

12BandBQ4 a2

12BandBQ5 b0

12BandBQ5 b1

12BandBQ5 b2

12BandBQ5 a1

12BandBQ5 a2

12BandBQ6 b0

12BandBQ6 b1

12BandBQ6 b2

12BandBQ6 a1

12BandBQ6 a2

12BandBQ7 b0

12BandBQ7 b1

12BandBQ7 b2

12BandBQ7 a1

12BandBQ7 a2

0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x30

0x31

0x32

0x33

0x34

0x35

0x36

0x37

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

0x40

0x41

0x42

0x43

0x44

0x45

12BandBQ8 b0

12BandBQ8 b1

12BandBQ8 b2

12BandBQ8 a1

12BandBQ8 a2

12BandBQ9 b0

12BandBQ9 b1

12BandBQ9 b2

12BandBQ9 a1

12BandBQ9 a2

12BandBQ10 b0

12BandBQ10 b1

12BandBQ10 b2

12BandBQ10 a1

12BandBQ10 a2

12BandBQ11 b0

12BandBQ11 b1

12BandBQ11 b2

12BandBQ11 a1

12BandBQ11 a2

12BandBQ12 b0

12BandBQ12 b1

12BandBQ12 b2

12BandBQ12 a1

12BandBQ12 a2

DRC1_1 b0

0x46

0x47

0x48

0x49

0x4A

0x4B

0x4C

0x4D

0x4E

0x4F

0x50

0x51

0x52

0x53

0x54

0x55

0x56

0x57

0x58

0x59

0x5A

0x5B

0x5C

0x5D

0x5E

DRC2_1 b0

DRC2_1 b1

DRC2_1 b2

DRC2_1 a1

DRC2_1 a2

DRC2_2 b0

DRC2_2 b1

DRC2_2 b2

DRC2_2 a1

DRC2_2 a2

Smooth BQ b0

Smooth BQ b1

Smooth BQ b2

Smooth BQ a1

Smooth BQ a2

DRC3_1 b0

DRC3_1 b1

DRC3_1 b2

DRC3_1 a1

DRC3_1 a2

DRC3_2 b0

DRC3_2 b1

DRC3_2 b2

DRC3_2 a1

DRC3_2 a2

DRC1_1 b1

DRC1_1 b2

DRC1_1 a1

DRC1_1 a2

DRC1_2 b0

DRC1_2 b1

DRC1_2 b2

DRC1_2 a1

DRC1_2 a2

Caution: When L/R independent, Lch: 0x61[7]=0x0, Rch: 0x61[7]=0x1.When L/R dependent, 0x61[7] is not reflected.

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Description of Function - continued

16 Mute Function by MUTEX Pin

BM28723AMUV can mute output by setting the MUTEX pin to Low.

Transition time setting at the time of mute is as follows.

Soft transition mute time setting

The transition time when changing to a mute state is selected.

The soft transition time at the time of mute release is 10.7ms fixed.

Default=0x3

Select Address

0x15[1:0]

Value

0x0

Explanation of Operation

10.7ms (fs=48kHz)

21.4ms (fs=48kHz)

42.7ms (fs=48kHz)

85.4ms (fs=48kHz)

0x1

0x2

0x3

0x15[1:0] Mute time setting

It is only operated to mute by MUTEX terminal.

XdB

Mute state

Audio output data

T_A

T_B

0x15[1:0] setting

Value

0x0

T_A

T_B

10.7ms

21.4ms

42.7ms

85.4ms

10.7ms

0x1

0x2

0x3

Figure 64

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16 Mute Function by MUTEX Pin- continued

Soft start delay time setting

It is the delay time from detecting mute release to begin soft start actually.

Default=0x0

Select Address

Value

0x0

Explanation of Operation

0ms

0x15[5:4]

0x1

0x2

0x3

100ms

200ms

300ms

Operation of Soft start delay 0x15[5:4]

MUTEX

Value

00x0

T_M

Audio output data

0ms

0x1

100ms

200ms

300ms

0x2

T_M

0x3

Figure 65

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Description of Function

17 Small Signal Input Detecting Function

There is a function which detects the audio data input of a non-signal or a small signal. This function is used in order to reduce

the standby power consumption of an audio set.

If the signal below a setting detection level continues in both L channel and R channel, a small signal detection flag will

become High. A detection result can be read from command 0x72[0].

The point which acts as a monitor of the small signal becomes input data of audio DSP block.

I²S

DSP

Peak Detector

(Lch)

Peak Detector

(Rch)

Counter

Flag

0x72 [0]

NOSIG_DET_FLAG

Figure 66. Block Diagram of Small Signal Input Detecting

Detection level setting

Default=0x00

Select Address

0x70[4:0]

Explanation of Operation

Level

-103dB

-93dB

-91dB

-87dB

-84dB

-80dB

-79dB

-78dB

Level

-77dB

-76dB

-75dB

-74dB

-73dB

-72dB

-71dB

-70dB

Level

-69dB

-68dB

-67dB

-66dB

-65dB

-64dB

-62dB

-60dB

Value

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

Value

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

Value

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

Detection time setting

Default=0x0

Select Address

0x71[1:0]

Value

0x0

Explanation of Operation

42.7ms

85.4ms

170.7ms

341.4ms

0x1

0x2

0x3

Caution: Sampling frequency is value of f_S=48kHz. In the case of f_S=44.1kHz, it will be about 1.09 times the setting value.

Detection flag read-back (Read Only)

Select Address

0x72[0]

Value

0x0

Explanation of Operation

Not detecting

Detecting

0x1

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Description of Function - continued

18 Clock Stop Detection and detection of high speed and low speed or detection of out of sync

18.1 Clock Stop Detection

BM28723AMUV generates internal clock using for audio data processing from inputted several clocks.

By stopping these clock sources, the clocks that is used for audio data processing also stop (Or if that clock does not reach

the frequency speed needed).

Therefore, the detection circuit is needed to avoid that situation.

State of BCLK and LRCLK are detected by using internal clock.

If valid flag is detected, output is muted (Immediate mute).

Internal

frequency

generator

Judge

OK/NG

Clock stop

detecion

circuit

BCLK

Register Read

& Output Stop

LRCLK

Figure 67

Each clock stop is detected when inputted clock stop during the time that is set by command. Detection result can be read

back by command.

In addition, once stop flag is detected, these flags cannot be cleared until clear command is send even though the clock

speed becomes normal.

LRCLK stop detection time

Default=0x2

Select Address

LRCLK 0x07[2:0]

Value

0x0

Explanation of Operation

10μs to 20μs

0x1

0x2

0x3

0x4

0x5

0x6

0x7

20μs to 40μs

50μs to 100μs

100μs to 200μs

200μs to 400μs

300μs to 600μs

400μs to 800μs

500μs to 1000μs

Caution: Detection time has the above-mentioned variation within the limits

BCLK stop detection time

Default=0x0

Select Address

BCLK 0x08[6:4]

Value

0x0

Explanation of Operation

10μs to 20μs

0x1

0x2

0x3

0x4

0x5

0x6

0x7

20μs to 40μs

50μs to 100μs

100μs to 200μs

200μs to 400μs

300μs to 600μs

400μs to 800μs

500μs to 1000μs

Caution: Detection time has the above-mentioned variation within the limits.

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18.1 Clock Stop Detection - continued

Stop detection flag read back register (Read Only)

Select Address

0x09[5]

Value

Explanation of Operation

0x0

Normal

0x1

0x0

0x1

Detection of LRCLK stop flag

Normal

0x09[4]

Detection of BCLK stop flag

Stop detection flag clear register (Write Only)

Select Address

0x09[1]

Explanation of Operation

LRCLK stop detection flag is cleared by writing 0x1.

BCLK stop detection flag is cleared by writing 0x1.

0x09[0]

Caution: When using Auto recovery from clock error function (P.62) , the above-mentioned flag is cleared automatically.

LRCLK stop flag valid or invalid selection

Default=0x1

Select Address

0x07[3]

Value

0x0

Explanation of Operation

Valid

0x1

Invalid

BCLK stop flag valid or invalid selection

Default=0x0

Select Address

0x08[7]

Value

0x0

Valid

0x1

Invalid

18.2 Out of sync Detection

As for out of sync detecting function, it detects as out of sync error when it counts between the rising edges of LRCLK with

internal clock (49.152MHz), and it shifts more than the definite value, and whether PLL is normally locked is judged.

Input Sampling Frequency

32kHz, 44.1kHz, 48kHz

1023

Count value (Start of counting from 0)

As for the detection result, reading from the register is possible. As a result of the judgment as out of sync once, it is not

cleared until a clear command is transmitted even if the state of the clock returns normally. Moreover, out of sync count

setting is also possible, and if the error is detected more than the number of times set by the command, the flag (0x06[1])

becomes 0x1.

Out of sync flag reading register (Read Only)

Select Address

0x06[1]

Value

Explanation of Operation

0x0

Normal

Synchronous blank detects

0x1

Out of sync flag clear register (Write Only)

Select Address

0x06[0]

Explanation of Operation

When 0x1 is written, the out of sync flag is cleared.

Caution: When using Auto recovery from clock error function (P.62), the above-mentioned flag is cleared automatically.

Out of sync count setting

Default=0x2

Select Address

0x06[6:4]

Explanation of Operation

Set more than 0x1 (Set 0x1 to 0x7).

When the actual detection count of out of sync exceeds the setting,

Select Address 0x07[1] becomes 0x1.

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Description of Function - continued

18.3 BCLK High or Low Speed Detection function

BCLK high or low speed detection function counts the period of BCLK rising edge by using internal clock (12MHz to 25MHz) ,

and if the count value go beyond a constant value, it judge that abnormal speed of clock is occurred such as BCLK speed

become high or low.

When using a BCLK speed detection, speed failure detection can be more correctly performed by making a command set

reflect about an input sampling rate.

When you validate sampling rate setting, be sure to set up the sampling rate inputted with 0x0C [1:0] command. A high

speed and the low speed detection flag can set up validity and the invalidity respectively. If valid flag is detected, output is

muted (immediate mute).

Valid or invalid frequency value setting up by 0x0C[1:0] command.

Default=0x0

Select Address

0x0A[3]

Value

Explanation of Operation

0x0

Valid

0x1

Invalid

Setting of input sampling rate

Default=0x0

Select Address

0x0C[1:0]

Value

0x0

Explanation of Operation

48kHz

44.1kHz

32kHz

0x1

0x2

The setting of constraints of a high speed or a low speed detection condition

Default=0x0

Select Address

Value

Explanation of Operation

0x0A[2]

0x0

±10%

It can check detection result by reading back.

The result judged that is once unusual is not cleared until it transmits a clear command, even if the condition of a clock

returns to normal. It is possible to set the number of judging count of high speed flag detection and low speed flag detection

by the command. If the error more than the predetermined number is detected, the flag (0x0A[1], 0x0B[1]) becomes 0x1.

BCLK high speed flag (Read Only)

Select Address

0x0A[1]

Value

0x0

Explanation of Operation

Normal

High speed detection flag

0x1

BCLK low speed flag (Read Only)

Select Address

Value

0x0

Explanation of Operation

0x0B[1]

Normal

Low speed detection flag

0x1

High speed detection clears register (Write Only)

Select Address

0x0A[0]

Explanation of Operation

If 0x1 writes in, a high speed detection flag will be cleared.

Caution: When using Auto recovery from clock error function (P.62) , the above-mentioned flag is cleared automatically.

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18.3 BCLK High or Low Speed Detection function - continued

Low speed detection clear register (Write Only)

Select Address

0x0B[0]

Explanation of Operation

If 0x1 is written, a low speed detection flag will be cleared.

Caution: When using Auto recovery from clock error function (P.62) , the above-mentioned flag is cleared automatically.

A constraint of the count of judging with high speed flag detection

Default=0x2

Select Address

Explanation of Operation

Set over 0x1. (0x1 to 0x7 are set up) it become 0x0A[1]=0x1 if the BCLK high

speed condition more than the count of setting up is detected continuously.

0x0A[6:4]

A constraint of the count of judging with low speed flag detection

Default=0x2

Select Address

Explanation of Operation

0x0B[6:4]

Set over 0x1. (0x1 to 0x7 are set up) it become 0x0B[1]=0x1 if the BCLK low

speed condition more than the count of setting up is detected continuously.

High speed detection flag valid or invalid

Default=0x0

Select Address

0x0A[7]

Value

0x0

Explanation of Operation

Valid

0x1

Invalid

Low speed detection flag valid or invalid

Default=0x0

Select Address

0x0B[7]

Value

0x0

Explanation of Operation

Valid

0x1

Invalid

The frequency range of BCLK by which high speed detection or low speed detection is carried out is as follows.

Low Speed Detection

Lowest Frequency

(MHz)

High Speed Detection

Highest Frequency

(MHz)

Setting1

Setting2

48kHz (0x0C[1:0]=0x0)

44.1kHz (0x0C[1:0]=0x1)

32kHz (0x0C[1:0]=0x2)

48kHz (0x0C[1:0]=0x0)

44.1kHz (0x0C[1:0]=0x1)

32kHz (0x0C[1:0]=0x2)

48kHz (0x0C[1:0]=0x0)

44.1kHz (0x0C[1:0]=0x1)

32kHz (0x0C[1:0]=0x2)

1.28

1.21

0.88

0.96

0.91

0.66

0.64

0.60

0.44

7.13

6.55

4.76

5.35

4.92

3.57

3.56

3.28

2.38

64fs BCLK (0x03[5:4]=0x0)

48fs BCLK (0x03[5:4]=0x1)

32fs BCLK (0x03[5:4]=0x2)

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Description of Function – continued

19 Auto Recovery of Clock Error Function

Establishment of Clock stop detection flag or BCLK high speed detection flag or BCLK low speed detection flag makes PWM

output mute (Immediate mute).

In that case, if the Auto Recovery of Clock Error Function is enabled, when it returns to a normal input, a mute condition will

be cancelled automatically.

When Auto Recovery of Clock Error Function is cancelled, it is necessary to control a series of operations called a mute-on

and flag clear command transmission, an internal RAM data clear and mute release from an external microcomputer. Since

it is invalid immediately after a wake-up, 0x0D[6]=0x1 is set up before mute release, and it is recommended to enable this

function.

Valid or invalid auto recover from clock error

Default=0x0

Select Address

0x0D[6]

Value

Explanation of Operation

0x0

Invalid

Valid

0x1

Each error flag can be read from the following addresses. When 0x1 is read from a read address, the error flag establishes.

Moreover, a flag is not cleared until it writes 0x0 in the target address, even if error status will be canceled, once a flag leaves.

Error flag read register

Select Address

0x0E[6]

Explanation of Operation

Synchronous error flag

0x0E[4]

0x0E[3]

0x0E[2]

0x0E[1]

LRCLK stop flag

BCLK stop flag

BCLK high speed detection flag

BCLK low speed detection flag

20 The Wake-up Procedure of Power-up

It has to start power-up in the following procedures.

0x**=0x** means writing data to register. (For example) 0x10=0x00 It means writing data 0x00 to select address 0x10.

1. Power-up (VCCP1, VCCP2, DVDD)

Input BCLK and LRCLK

Wait over 10ms

Input stable BCLK and LRCLK in the specification

Wait over 1ms

2. Release reset (RSTX=High)

Wait over 1ms

3. 0x0C=0x00

: Sampling rate setting

(Set 48kHz: 0x00, 44.1kHz: 0x01, 32kHz: 0x02 to 0x0C address)

: Clock initialization

4. 0xE9=0x10

Wait over 100ms

5. 0x01=0x00: Set RAM clear OFF

6. 0x0D=0x40

: Valid auto recover from clock error

7. 0x0E=0x00: Clear error flag

8. 0x92=0x1D

: PWM setting1

9. 0x93=0x1B: PWM setting2

10. 0x94=0x0F

11. 0x95=0x11

12. 0x90=0x40

13. 0xF4=0x14

14. 0xF3=0x03

15. 0xF2=0x02

16. 0xF8=0x01

Wait over 10ms

: PWM setting3

: PWM setting4

: PWM setting5

: Protect function initialization

: Driver Gain setting (0x03: 26dB, 0x0B: 32dB)

: Stereo application setting (0x02: Stereo, 0x0A: Monaural)

: 0xF4, 0xF3, 0xF2 setting value is fixed

17. Set up DSP function such as volume, BQ, DRC, and Pre-Scaler etc.

18. MUTEX=High : Release mute

(Order from 8 to 12 and 17 can be interchanged.)

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Description of Function - continued

21 The Operating Procedure in a Status with an Unstable Clock

In the period there is the possibility that inputted I²S, BCLK, LRCLK and SDATA, may become unstable, set MUTEX=Low to

mute output.

BCLK,LRCLK unstable period

BCLK,LRCLK

AUDIODATA

PWM stop time

MUTEX

Refer to “7．The Wake-up Procedure of Power-up” of P.62

More than 1ms

RSTX

OUTxx

PWM STOP

A

B

C

D

E F

G

Figure 68. The Operating Procedure in a Status with an Unstable Clock

Caution: When clock stop was detected, mute release procedure will follow the clock stop error release sequence.

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Description of Function – continued

22 I²S Data Output Select

Capable of output I²S format digital audio data from SDATAO (pin12).

That signal synchronizes to inputted LRCK and BCK signal.

And enable to select output SDATA signal as shown below.

The Point of selected data is shown below diagram.

Whatever output is selected, hard clip is processed.

SDATAO output select

Default=0x0

Select Address

0x78[6:4]

Value

0x0

Explanation of Operation

DSP output (Point1)

DSP input (Point2)

0x1

0x2

0x3

0x4

0x5

0x6

0x7

Pre-Scaler output (Point3)

Mixer output (Point4)

12Band BQ output (Point5)

Fine master volume output (Point6)

Don't use

Fine Post-Scaler output (Point7)

I²S

LJ

RJ

Fine

post

scaler/

ch

Fine

Master

Volume

/ch

Pre

Chanel

Mixer

DC cut

HPF

Hard

Clipper

3Band

DRC

Post

Scaler

12Band

/ch BQ

Input1

Main

Scaler

Point7

Point1

Point2 Point3 Point4 Point5 Point6

Figure 69

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Register Map

Address

0x01

Initial Value

Recommended value

0x00^{(Note 22)}

Description

Function

0xE0

RAM clear

Bypass

RAM clear setting

0x02

0x03

0x06

0x07

0x08

0x09

0x0A

0x0B

0x00

0x02

0x20

0x8A

0x00

-

Select bypass blocks

0x02

Digital audio input 1

I²S input format setting

0x20

Synchronous error 2

Synchronous error setting

LRCLK stop detection setting

BCLK stop detection setting

Read/Clear stop detection

0x8A

LRCLK,BCLK stop detection 1

LRCLK,BCLK stop detection 2

LRCLK,BCLK stop detection 3

0x00

Read/Write Only

0x20

BCLK Measurement of velocity 1 BCLK fast detection setting

BCLK Measurement of velocity 2 BCLK slow detection setting

0x20

0x00 (48kHz sampling)

0x0C

0x00

Sampling frequency setting

(Note 22)

0x0D

0x0E

0x00

0x40^{(Note 22)}

0x00^{(Note 22)}

Auto return 1

Auto return 2

Auto return setting

Auto return monitor

Read Only

Fine volume setting/

Independent volume setting

Lch/dependent Volume setting

(0dB: 0x30)

Rch volume setting

(0dB: 0x30)

0x10

0x11

0x12

0x13

0x00

0xFF

0x60

0x00

0xFF

0x60

Volume, Balance, Post-scaler 1

Volume, Balance, Post-scaler 2

Volume, Balance, Post-scaler 3

Volume, Balance, Post-scaler 4

Post-scaler setting

(0dB: 0x60)

0x14

0x15

0x88

0x03

0x88

0x00

Volume, Balance, Post-scaler 5

Mute function

L/R fine postscaler setting

Mute transition time setting

Pre-Scaler setting

(0dB: 0x60)

0x16

0x60

Pre-Scaler

0x17

0x18

0x1A

0x1B

0x20

0x21

0x28

0x29

0x2A

0x2B

0x2C

0x2E

0x2F

0x12

0x01

0xE1

0xFC

0xC0

0x40

0x80

0x3B

0x13

0x40

0x3B

0x13

0x12

0x01

0xE1

0xFC

0xC0

0x40

0x80

0x3B

0x13

0x40

0x3B

0x13

Channel mixer

Channel mixer setting

DC cut HPF setting

DC Cut HPF

Hard Clipper 1

Hard Clipper setting

Hard Clipper 2

Hard Clip level setting

DRC select setting

DRC common 1

DRC common 2

Transition form setting

Threshold setting

AGC_TH1 setting of DRC1

Slope (α) setting of DRC1

RATE setting of DRC1

TIME setting of DRC1

AGC_TH2 setting of DRC1

RATE setting of DRC1

TIME setting of DRC1

Slope setting

A_RATE and R_RATE setting

A_TIME and R_TIME setting

Threshold setting

A_RATE and R_RATE setting

A_TIME and R_TIME setting

(Note 22) It must be set at the time of start-up. Refer to P.62 “20. The wake-up Procedure of power-up”.

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Register Map - continued

Address Initial Value Recommended value

Description

Function

Threshold setting

0x30

0x31

0x32

0x33

0x34

0x36

0x37

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

0x40

0x41

0x42

0x51

0x53

0x40

0x80

0x3B

0x13

0x40

0x3B

0x13

0x40

0x80

0x3B

0x13

0x40

0x3B

0x13

0x00

0x40

0x3B

0x13

0x00

0x0C

0x40

0x80

0x3B

0x13

0x40

0x3B

0x13

0x40

0x80

0x3B

0x13

0x40

0x3B

0x13

0x00

0x40

0x3B

0x13

0x00

0x0C

AGC_TH1 setting of DRC2

Slope (α) setting of DRC2

RATE setting of DRC2

TIME setting of DRC2

AGC_TH2 setting of DRC2

RATE setting of DRC2

TIME setting of DRC2

AGC_TH1 setting of DRC3

Slope (α) setting of DRC3

RATE setting of DRC3

TIME setting of DRC3

AGC_TH2 setting of DRC3

RATE setting of DRC3

TIME setting of DRC3

DRC4 ON

Slope setting

A_RATE and R_RATE setting

A_TIME and R_TIME setting

Threshold setting

A_RATE and R_RATE setting

A_TIME and R_TIME setting

Threshold setting

Slope setting

A_RATE and R_RATE setting

A_TIME and R_TIME setting

Threshold setting

A_RATE and R_RATE setting

A_TIME and R_TIME setting

ON/OFF setting

AGC_TH2 setting of DRC4

RATE setting of DRC4

TIME setting of DRC4

Bi-quad type filter1

Threshold setting

A_RATE and R_RATE setting

A_TIME and R_TIME setting

Select of BQ soft transition Band

Setting of transition time and wait time

Bi-quad type filter2

Soft transition start, 0x0: Stop 0x1:

Start

0x58

0x59

0x60

Write Only

Read Only

0x00

-

Bi-quad type filter3

-

Bi-quad type filter4

Soft transition flag

Select of BQ independence or

synchronous setting

0x00

The coefficient is written directly. 1

0x61

0x62

0x63

0x64

0x00

The coefficient is written directly. 2 Coefficient address bit7 to bit0

The coefficient is written directly. 3 Coefficient data bit23 to bit16

The coefficient is written directly. 4 Coefficient data bit15 to bit8

The coefficient is written directly. 5 Coefficient data bit7 to bit0

The writing of coefficients is

The coefficient is written directly. 6

performed

0x65

Write Only

-

0x66

0x67

0x68

0x70

0x71

0x72

Read Only

0x00

-

The coefficient is written directly. 7 Coefficient reading bit23 to bit16

The coefficient is written directly. 8 Coefficient reading bit15 to bit8

The coefficient is written directly. 9 Coefficient reading bit7 to bit0

-

0x00

-

Small signal detection1

Small signal detection2

Small signal detection3

Small signal detection level setting

Small signal detection time setting

Small signal detection flag read-back

0x00

Read Only

Setting of the peak level hold time

interval

0x74

0x75

0x76

0x00

Level meter1

Level meter2

Level meter3

Write Only

Read Only

-

0x0: Lch 0x1: Rch 0x2: (Lch+Rch) /2

Level reading

(16bit high position 8bit)

Level reading

(16bit subordinate position 8bit)

0x77

0x78

Read Only

0x02

-

Level meter4

SDATAO

0x02

SDATAO select

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Register Map - continued

Address Initial Value Recommended value

Description

Function

0x90

0x92

0x93

0x94

0x95

0xE9

0xF2

0xF3

0xF4

0x00

0x01

0x04

0x05

0x01

0x02

0x03

0x04

0x40^{(Note 22)}

0x1D^{(Note 22)}

0x1B^{(Note 22)}

0x0F^{(Note 22)}

0x11^{(Note 22)}

PWM setting 5

PWM initialization

PWM delay

PWM setting 1

PWM setting 2

PWM setting 3

PWM setting 4

PWM delay

0x10 (normal) ^{(Note 22)}DSP clock setting

0x02 (Stereo) ^{(Note 22)}Stereo/Mono

DSP clock initialization

DC voltage protection setting for Stereo / Mono

Driver Gain setting (26dB or 32dB)

0x03 (26dB) ^{(Note 22)}

0x14 ^{(Note 22)}

Driver Gain

Protection initialization Protection initialization

The decision of 0xF2,

Decided by sending 0x01

0xF3 and 0xF4

0xF8

0x00

0x01^{(Note 22)}

(Note 22) It must be set at the time of start-up. Refer to P.62 “20. The wake-up Procedure of power-up”.

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Application Circuit Example1 (Stereo BTL output, R_L=8Ω, V_CCP1, V_CCP2≤22V)

μ-con

L25

10μH

GNDP1

DVDD DVDD

10μ F

C27

3.3μ F

C26

10kΩ

R32

10kΩ

R31

32

31

30

29

28

27

26

25

REG_G BSP1P OUT1P

NC

0.47μ F

SP ch1

(Lch)

C25A

I²C BUS

Address

Select

REG_G

DVDD

VSS

GNDP1

VCCP1

Control

I/F

1

2

3

4

5

6

7

8

2 wire I/F

24

23

22

21

20

19

18

17

ADDR

VCCP1

10μ F

C24

Driver

FET 1P

0.47μF

C21A

BCLK

LRCLK

SDATA

R2 0Ω

GNDP1

BSP1N

I²S/LJ/RJ

I/F

LRCLK

Driver

FET 1N

Digital

Audio

Source

R3 0Ω

3.3μ F

C22

10μH

L21

SDATA

8 Times

Over-

Sampling

Digital

Filter

OUT1N

OUT2P

R40Ω

PWM

Modulator

Audio

DSP

TEST1

VSS

L20

10μH

C19

3.3μF

C6B

0.027μF

R6

Driver

FET 2P

1.5kΩ

PLL

BSP2P

PLL

VSS

C6A

C7

GNDP2

2700pF

REG15

VSS

REG15

C20A

0.47μF

Driver

FET 2N

1μF

GNDP2

VCCP2

C17

10μ F

Protection

VSS

LRCLK

VCCP2

DGND

GNDP2

BCLK

SP ch2

(Rch)

DVDD

C16A

0.47μF

TEST2

TEST3 SDATAO

BSP2N OUT2N

15 16

NC

14

9

10

11

12

13

C15

3.3μF

0Ω

R12

R13

VSS

1μF

L16

C10

DVDD(3.3V)

10μH

μ-con

VSS

10kΩ

DVDD

SDATAO

ERRORX

Figure 70

Parts

Qty

Parts No.

Description

Inductor

4

1

2

4

1

L16, L20, L21, L25

10μH / 3.8A / (±20%)

R6

R31, R32

R2, R3, R4, R12

R13

1.5kΩ / 1/16W / F(±1%)

10kΩ / 1/16W / J(±5%)

0Ω / 1/10W / J(±5%)

Resistor

10kΩ / 1/16W / J(±5%)

2700pF / 6.3V / B(±10%)

0.027μF / 6.3V / B(±10%)

C6A

C6B

C16A, C20A,

C21A, C25A

4

2

4

0.47μF / 50V / B(±10%)

10μF / 35V / B(±10%)

3.3μF / 16V / B(±10%)

Capacitor

C17, C24

C15, C19,

C22, C26

2

1

C7, C10

C27

1.0μF / 10V / B(±10%)

10μF / 16V / B(±10%)

Caution 1: If the impedance characteristics of the speakers at high-frequency range increase rapidly, the LSI might not have stable operation in the resonance

frequency range of the LC filter. Therefore, consider adding damping-circuit, etc., depending on the impedance of the speaker.

Caution 2: Though this LSI has a short protection function, when short to VCC or GND after the LC filter, over-current occurs during short protection function

operation. Be careful about over/undershoot which exceeds the maximum standard ratings because back electromotive force of the inductor will occur

which sometimes leads to LSI destruction.

The Inductor must be used to the coil with large margin of rated DC current (saturation current). When the short-circuit of the speaker output (after the

LC filter) to VCC or GND occurs when the coil with small rated DC current is used, LSI destruction might be caused. Because the coil causes the magnetic

saturation behavior, it instantaneously passes the heavy-current to LSI.

Caution 3: Overshoot of output PWM differs according to the board or coupling capacitor of V_CC, and etc. Check to ensure that it is lower than absolute maximum

ratings.

If it exceeds the absolute maximum ratings, snubber circuit must need to be added.

Caution 4: When it is used at V_CCP1, V_CCP2>22V, snubber circuit must need to be added, and must change LC filter value to suppress the influence of the LCR

resonance.

Caution 5: This circuit constant is value with ROHM evaluation board, and adjustment of the constant may be necessary for the application board. Must carry out

enough evaluations.

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Application Circuit Example2 (Stereo BTL output, R_L=8Ω, 22V<V_CCP1, V_CCP2≤24V)

μ-con

L25

15μH

GNDP1

DVDD DVDD

10μF

C27

3.3μF

C26

10kΩ

R31

10kΩ

R32

680pF

C25B

32

31

30

29

28

27

26

25

REG_G BSP1P OUT1P

NC

5.6Ω

R25

0.47μF

SP ch1

(Lch)

C25A

I²C BUS

Address

Select

REG_G

DVDD

VSS

GNDP1

VCCP1

Control

I/F

1

2

3

4

5

6

7

8

2 wire I/F

24

23

22

21

20

19

18

17

ADDR

VCCP1

10μF

C24

Driver

FET 1P

0.47μF

C21A

BCLK

5.6Ω

BCLK

LRCLK

SDATA

R2 0Ω

R21

GNDP1

BSP1N

GNDP1

680pF

I²S/LJ/RJ

I/F

C21B

LRCLK

Driver

FET 1N

Digital

Audio

Source

R3 0Ω

3.3μF

C22

15μH

L21

SDATA

8 Times

Over-

Sampling

Digital

Filter

OUT1N

OUT2P

R40Ω

PWM

Modulator

Audio

DSP

TEST1

VSS

R6

L20

15μH

C19

3.3μF

C6B

0.027μF

Driver

FET 2P

1.5kΩ

PLL

BSP2P

PLL

C20B

VSS

C6A

2700pF

680pF

C7

GNDP2

R20

5.6Ω

REG15

VSS

REG15

C20A

0.47μF

Driver

FET 2N

1μF

GNDP2

VCCP2

C17

10μF

Protection

VSS

LRCLK

VCCP2

DGND

GNDP2

BCLK

SP ch2

(Rch)

DVDD

C16A

0.47μF

TEST2

TEST3SDATAO

R16

5.6Ω

BSP2N OUT2N

15 16

NC

14

9

10

11

12

13

C16B

680pF

C15

3.3μF

0Ω

R12

R13

VSS

1μF

C10

VSS

L16

DVDD(3.3V)

15μH

μ-con

10kΩ

DVDD

SDATAO

ERRORX

Figure 71

Parts

Qty

4

Parts No.

Description

Inductor

L16, L20, L21, L25

15μH / 2.9A / (±20%)

1.5kΩ / 1/16W / F(±1%)

10kΩ / 1/16W / J(±5%)

0Ω / 1/10W / J(±5%)

1

R6

R31, R32

R2, R3, R4, R12

R16, R20, R21, R25

R13

2

Resistor

4

5.6Ω / 1/4W / J(±5%)

10kΩ / 1/16W / J(±5%)

2700pF / 6.3V / B(±10%)

0.027μF / 6.3V / B(±10%)

1

C6A

1

C6B

C16B, C20B,

C21B, C25B

C16A, C20A,

C21A, C25A

4

680pF / 50V / CH(±5%)

4

2

4

0.47μF / 50V / B(±10%)

10μF / 35V / B(±10%)

3.3μF / 16V / B(±10%)

Capacitor

C17, C24

C15, C19,

C22, C26

2

1

C7, C10

C27

1.0μF / 10V / B(±10%)

10μF / 16V / B(±10%)

Caution 1: If the impedance characteristics of the speakers at high-frequency range increase rapidly, the LSI might not have stable operation in the resonance

frequency range of the LC filter. Therefore, consider adding damping-circuit, etc., depending on the impedance of the speaker.

Caution 2: Though this LSI has a short protection function, when short to VCC or GND after the LC filter, over-current occurs during short protection function

operation. Be careful about over/undershoot which exceeds the maximum standard ratings because back electromotive force of the inductor will occur

which sometimes leads to LSI destruction.

The Inductor must be used to the coil with large margin of rated DC current (saturation current). When the short-circuit of the speaker output (after the

LC filter) to VCC or GND occurs when the coil with small rated DC current is used, LSI destruction might be caused. Because the coil causes the magnetic

saturation behavior, it instantaneously passes the heavy-current to LSI.

Caution 3: Overshoot of output PWM differs according to the board or coupling capacitor of VCC, and etc. Check to ensure that it is lower than absolute maximum

ratings.

If it exceeds the absolute maximum ratings, snubber circuit must need to be added.

Caution 4: When it is used at V_CCP1, V_CCP2>22V, snubber circuit must need to be added, and must change LC filter value to suppress the influence of the LCR

resonance.

Caution 5: This circuit constant is value with ROHM evaluation board, and adjustment of the constant may be necessary for the application board. Must carry out

enough evaluations.

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(Note 23)

Application Circuit Example3 (Monaural BTL output

, R_L=4Ω, V_CCP1, V_CCP2≤14V)

μ-con

L25

10μH

GNDP1

DVDD DVDD

10μF 3.3μF

C27

10kΩ

R32

10kΩ

R31

C26

32

31

30

29

28

NC

27

26

25

REG_G BSP1P OUT1P

1μF

C25A

SP ch1

(Lch)

I²C BUS

Address

Select

REG_G

DVDD

VSS

GNDP1

VCCP1

Control

I/F

1

2

3

4

5

6

7

8

2 wire I/F

24

23

22

21

20

19

18

17

ADDR

VCCP1

10μF

C24

Driver

FET 1P

1μF

C21A

BCLK

LRCLK

SDATA

R2 0Ω

GNDP1

BSP1N

GNDP1

I²S/LJ/RJ

I/F

LRCLK

Driver

FET 1N

Digital

Audio

Source

R3 0Ω

3.3μF

C22

10μH

L21

SDATA

8 Times

Over-

Sampling

Digital

Filter

OUT1N

OUT2P

R40Ω

PWM

Modulator

Audio

DSP

TEST1

VSS

R6

C6B

0.027μF

Driver

FET 2P

1.5kΩ

PLL

BSP2P

PLL

VSS

C6A

C7

GNDP2

2700pF

REG15

VSS

REG15

Driver

FET 2N

1μF

GNDP2

VCCP2

Protection

VSS

LRCLK

DGND

BCLK

DVDD

TEST2

TEST3SDATAO

BSP2N OUT2N

15 16

NC

14

9

10

11

12

13

0Ω

R12

R13

VSS

1μF

C10

DVDD(3.3V)

μ-con

VSS

10kΩ

DVDD

SDATAO

ERRORX

Figure 72

Description

Parts

Qty

Parts No.

Inductor

2

1

2

4

1

2

1

2

1

L21, L25

R6

10μH / 3.8A / (±20%)

1.5kΩ / 1/16W / F(±1%)

10kΩ / 1/16W / J(±5%)

0Ω / 1/10W / J(±5%)

10kΩ / 1/16W / J(±5%)

R31, R32

R2, R3, R4, R12

R13

Resistor

C6A

2700pF / 6.3V / B(±10%)

0.027μF / 6.3V / B(±10%)

1.0μF / 50V / B(±10%)

10μF / 35V / B(±10%)

3.3μF / 16V / B(±10%)

1.0μF / 10V / B(±10%)

10μF / 16V / B(±10%)

C6B

C21A, C25A

C24

Capacitor

C22, C26

C7, C10

C27

Caution 1: If the impedance characteristics of the speakers at high-frequency range increase rapidly, the LSI might not have stable operation in the resonance

frequency range of the LC filter. Therefore, consider adding damping-circuit, etc., depending on the impedance of the speaker.

Caution 2: Though this LSI has a short protection function, when short to VCC or GND after the LC filter, over-current occurs during short protection function operation.

Be careful about over/undershoot which exceeds the maximum standard ratings because back electromotive force of the inductor will occur which

sometimes leads to LSI destruction.

The Inductor must be used to the coil with large margin of rated DC current (saturation current). When the short-circuit of the speaker output (after the LC

filter) to VCC or GND occurs when the coil with small rated DC current is used, LSI destruction might be caused. Because the coil causes the magnetic

saturation behavior, it instantaneously passes the heavy-current to LSI.

Caution 3: Overshoot of output PWM differs according to the board or coupling capacitor of VCC, and etc. Check to ensure that it is lower than absolute maximum

ratings. If it exceeds the absolute maximum ratings, snubber circuit must need to be added.

Caution 4: This circuit constant is value with ROHM evaluation board, and adjustment of the constant may be necessary for the application board. Must carry out

enough evaluations.

(Note 23) Register setting of 0xF2=0x0A and 0xF8=0x01 is necessary at the time of start-up (in state of MUTEX=Low).

(Refer to “Monaural output setting”.)

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Selection of Components Externally Connected

1 Output LC Filter Circuit

An output filter is required to eliminate radio-frequency components exceeding the audio-frequency region supplied to a load

(speaker). Because this LSI uses sampling frequency 384kHz (f_S=48kHz) in the output PWM signals, the high-frequency

components must be appropriately removed.

This section takes an example of an LC type LPF shown below, in which coil L and capacitor C_gcompose a differential filter

with an attenuation property of -12dB/oct.

L

OUT1P

OUT2P

C_g

R_L

C_g

OUT1N

OUT2N

L

Figure 73. Output LC Filter

Following presents output LC filter constants with typical load impedances.

R_L

L

C_g

Note

4Ω

10μH

15μH

10μH

15μH

1μF

V_CCP1, V_CCP2≤14V

V_CCP1, V_CCP2≤22V

V_CCP1, V_CCP2>22V

V_CCP1, V_CCP2≤22V

V_CCP1, V_CCP2>22V

0.68μF

0.47μF

6Ω

8Ω

Use coils with a low direct-current resistance and a sufficient margin of allowable currents. In addition, select a closed

magnetic circuit type product in normal cases to prevent unwanted emission. A high direct-current resistance causes power

losses.

When the short-circuit of the speaker output (After the LC filter) to VCC or GND occurs when the coil with small rated DC

current is used, LSI destruction might be caused. Because thecoil causes the magnetic saturation behavior, it instantaneously

passes the heavy-current to LSI.

When using at V_CCP1, V_CCP2>22V, the coil of the rated DC current: 7.2A or more will be recommended.

And, f_CL(LC resonance frequency) of the LC filter should be lowered and decrease the influence of LC resonance.

Use capacitors with low equivalent series resistance and good impedance characteristics at high frequency ranges.

Also, select the parts with the margin of the ratings enough.

2 The Value of the LC Filter Circuit Computed Equation

The output LC filter circuit of BM28723AMUV is as it is shown in Figure 74. The LC filter circuit of Figure 74 is thought to

substitute it like Figure 75 on the occasion of the computation of the value of the LC filter circuit.

L

OUT1P

OUT2P

L

OUT1P

C_g

OUT1N

OUT2P

OUT2N

R=R_L/2

R_L

C_g

OUT1N

OUT2N

L

Figure 74. Output LC Filter 1

Figure 75. Output LC Filter 2

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2 The Value of the LC Filter Circuit Computed Equation - continued

The transfer function H(s) of the LC filter circuit of Figure 75. becomes the following.

1

LC

ω²

g

H



s





1

LC

ω

s ²



s



s ²



s 

ω²

Cg

R

g

Q

The ω and Q become the followings here.

1

LC

1

ω²



ω



2πf_CL

f_CL

g

2π LC

g

C

L

g

1

2

C

L

g

Q



R



R_L

Therefore, L and C_gbecome the followings.

1

ω²C

R_L

4πf_CLQ

Q

L



Cg



g

ωR πf_CLR_L

The R_Land L should be made known, and f_CLis set up, and C_gis decided.

3 The Settlement of the Inductance Value of the Coil

A standard for selection of the L value of a coil to use is to take the following consideration except for the factor such as a low

cost, miniaturization and thin.

1.When the inductance value was made small

•Circuit electric currents increase without a signal. Efficiency in the low output power gets bad.

•Direct current resistance value of the coil becomes small.

Therefore, maximum output power becomes bigger.

Rated DC current and Temperature rise current of the coil become high.

2.When the inductance value was made large

•Circuit electric current is decrease without a signal. Efficiency in the low output power improves.

•Direct current resistance value of the coil becomes big.

Therefore, maximum output power becomes smaller.

Rated DC current and Temperature rise current of the coil becomes low.

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Selection of Components Externally Connected - continued

4 Snubber Circuit Constant

When overshoot of PWM Output exceeds absolute maximum rating, and when V_CCP1, V_CCP2>22V, or when overshoot of PWM

output negatively affects EMI, or when ringing deteriorates the audio characteristic of the PWM output, snubber circuit is used

as shown below.

1. Measure the ringing resonance frequency f₁of PWM output waveform (when rising) by using low capacitance Probe

(e.g. FET probe) at the OUT pin. (Figure 76)

Shorten GND lead of FET probe and monitor as near as possible to output pin.

2. Measure the resonance frequency f₂of the ringing as the snubber-circuit Rsnb=0Ω

(capacitor is connected to GND)

Adjust the value of the capacitor C until it becomes half of f₁(2f₂=f₁).

The value of C that becomes (2f₂=f₁) is 3 times of the parasitic capacity C_pthat a ringing is formed. (C=3C_p)

3. Parasitic inductance L_pis calculated using the next formula.

1

L_p





2ππ₁²C _p

4. The characteristics impedance Z of resonance is calculated from the parasitic capacity C_pand the parasitic inductance L_p

using the next formula.

L_p

Z



C _p

5. Set snubber circuit R_snbsame as the character impedance Z.

Set snubber circuit C_snb4 to 10 times of the parasitic capacity C_p(C_snb=4C_pto 10C_p).

If C_snbvalue is set large, switching current will possibly increase.

Therefore, please decide it by the trade-off with the characteristic.

VCCP1

VCCP2

Snubber

LC Filter

Ringing resonance

frequency

Driver

OUT1N

OUT1P

OUT2N

OUT2P

C_snb

R_snb

5ns/div

GNDP1

GNDP2

Figure 76. PWM Output Waveform

Figure 77. Snubber Schematic

(Measure of spike resonance frequency)

Following presents Snubber filter constants with the recommendation value at 22V<V_CCP1, V_CCP2≤24V, R_L=8Ω,

Po=10W+10W, ROHM 4 layer board^{(Note 12).}

C_snb

R_snb

680pF 50V CH (±5%)

5.6Ω 1/4W J (±5%)

Following presents Snubber filter constants with the recommendation value at V_CCP1, V_CCP2≤22V, R_L=8Ω,

Po=10W+10W, ROHM 4 layer board^{(Note 12).}

C_snb

R_snb

470pF 50V CH (±5%)

0Ω or 5.6Ω 1/8W J (±5%)

(Note 12) 100mmx100mmx1.6mm FR4 4-layer glass epoxy board Cu Thickness 35μm/70μm/70μm/35μm For Application Evaluation Board

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Selection of Components Externally Connected - continued

5 Operating Condition with the Application Component

Limit

Parameter

Parts No.

C17, C24

C27

Unit

µF

Conditions

B characteristics

Ceramic type capacitor

recommended

B characteristics, 16V

Ceramic type capacitor

recommended

B characteristics, 10V

Ceramic type capacitor

recommended

B characteristics, 16V

Ceramic type capacitor

recommended

B characteristics, 16V

Ceramic type capacitor

recommended

Min

Typ

Max

-

Coupling Capacitor for Power

Supply

1^{(Note 24)}

10

Capacitor for REG_G

Capacitor for REG15

1^{(Note 24)}

10

1.0

3.3

4.7

13.5^{(Note 26)}

1.35^{(Note 26)}

4.5^{(Note 26)}

C7

0.4^{(Note 24)}

2.0^{(Note 24)}

(Note 25)

C15, C19,

C22, C26

Capacitor for BSP

2.0^{(Note 24)}

6.3^{(Note 26)}

(Note 25)

(Note 27)

(Note 24) Should use the capacity of the capacitor not to be less than a minimum in consideration of temperature characteristics and dc-bias characteristics.

(Note 25) Minimum value to guarantee Speaker output operating range (20Hz to 20kHz, sin wave, THD+N ≤ 10%)

(Note 26) Use it within this rating. (Capacitance±10%, Capacitance change ratio±22%)

(Note 27) Influence it at the RSTX → MUTEX Wait time (T_WAIT: Refer to P.27) at the time of the Power Supply Start-up. Use it within this rating.

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Operational Notes

1. Reverse Connection of Power Supply

Connecting the power supply in reverse polarity can damage the LSI. Take precautions against reverse polarity when

connecting the power supply, such as mounting an external diode between the power supply and the LSI’s power

supply pins.

2. Power Supply Lines

Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the

digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog

block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and

aging on the capacitance value when using electrolytic capacitors.

3. Ground Voltage

Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition. However,

pins that drive inductive loads (e.g. motor driver outputs, DC-DC converter outputs) may inevitably go below ground

due to back EMF or electromotive force. In such cases, the user should make sure that such voltages going below

ground will not cause the LSI and the system to malfunction by examining carefully all relevant factors and conditions

such as motor characteristics, supply voltage, operating frequency and PCB wiring to name a few.

4. Ground Wiring Pattern

When using both small-signal and large-current ground traces, the two ground traces should be routed separately but

connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal

ground caused by large currents. Also ensure that the ground traces of external components do not cause variations

on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.

5. Recommended Operating Conditions

These conditions represent a range within which the expected characteristics of the LSI can be approximately obtained.

The electrical characteristics are guaranteed under the conditions of each parameter.

6. Inrush Current

When power is first supplied to the LSI, it is possible that the internal logic may be unstable and inrush current may

flow instantaneously due to the internal powering sequence and delays, especially if the LSI has more than one power

supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and

routing of connections.

7. Testing on Application Boards

When testing the LSI on an application board, connecting a capacitor directly to a low-impedance output pin may

subject the LSI to stress. Always discharge capacitors completely after each process or step. The LSI’s power supply

should always be turned OFF completely before connecting or removing it from the test setup during the inspection

process. To prevent damage from static discharge, ground the LSI during assembly and use similar precautions during

transport and storage.

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Ordering Information

2

3

A M U

V

B M 2

8

7

-

E 2

Part Number

Package

MUV:

Packaging and forming specification

E2: Embossed tape and reel

VQFN032V5050

The tape of BM28723AMUV-E2 is a dry pack.

Marking Diagram

VQFN032V5050 (TOP VIEW)

Part Number Marking

2 8 7 2 3 A

LOT Number

Pin 1 Mark

Figure 79

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Physical Dimension and Packing Information

Package Name

VQFN032V5050

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Revision History

Date

Revision

001

Changes

31.Aug.2018

New release

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Notice

Precaution on using ROHM Products

1. Our Products are designed and manufactured for application in ordinary electronic equipment (such as AV equipment,

OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you

intend to use our Products in devices requiring extremely high reliability (such as medical equipment ^{(Note 1)}, transport

equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car

accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or

serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.

Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any

damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific

Applications.

(Note1) Medical Equipment Classification of the Specific Applications

JAPAN

USA

EU

CHINA

CLASSⅢ

CLASSⅣ

CLASSⅡb

CLASSⅢ

2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor

products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate

safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which

a failure or malfunction of our Products may cause. The following are examples of safety measures:

[a] Installation of protection circuits or other protective devices to improve system safety

[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure

3. Our Products are designed and manufactured for use under standard conditions and not under any special or

extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way

responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any

special or extraordinary environments or conditions. If you intend to use our Products under any special or

extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of

product performance, reliability, etc, prior to use, must be necessary:

[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents

[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust

[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,

H2S, NH3, SO2, and NO2

[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves

[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items

[f] Sealing or coating our Products with resin or other coating materials

[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of

flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning

residue after soldering

[h] Use of the Products in places subject to dew condensation

4. The Products are not subject to radiation-proof design.

5. Please verify and confirm characteristics of the final or mounted products in using the Products.

6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,

confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power

exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect

product performance and reliability.

7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in

the range that does not exceed the maximum junction temperature.

8. Confirm that operation temperature is within the specified range described in the product specification.

9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in

this document.

Precaution for Mounting / Circuit board design

1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product

performance and reliability.

2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must

be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,

please consult with the ROHM representative in advance.

For details, please refer to ROHM Mounting specification

Notice-PGA-E

Rev.003

Precautions Regarding Application Examples and External Circuits

1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the

characteristics of the Products and external components, including transient characteristics, as well as static

characteristics.

2. You agree that application notes, reference designs, and associated data and information contained in this document

are presented only as guidance for Products use. Therefore, in case you use such information, you are solely

responsible for it and you must exercise your own independent verification and judgment in the use of such information

contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses

incurred by you or third parties arising from the use of such information.

Precaution for Electrostatic

This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper

caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be

applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,

isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).

Precaution for Storage / Transportation

1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:

[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2

[b] the temperature or humidity exceeds those recommended by ROHM

[c] the Products are exposed to direct sunshine or condensation

[d] the Products are exposed to high Electrostatic

2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period

may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is

exceeding the recommended storage time period.

3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads

may occur due to excessive stress applied when dropping of a carton.

4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of

which storage time is exceeding the recommended storage time period.

Precaution for Product Label

A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.

Precaution for Disposition

When disposing Products please dispose them properly using an authorized industry waste company.

Precaution for Foreign Exchange and Foreign Trade act

Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign

trade act, please consult with ROHM in case of export.

Precaution Regarding Intellectual Property Rights

1. All information and data including but not limited to application example contained in this document is for reference

only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any

other rights of any third party regarding such information or data.

2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the

Products with other articles such as components, circuits, systems or external equipment (including software).

3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any

third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM

will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to

manufacture or sell products containing the Products, subject to the terms and conditions herein.

Other Precaution

1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.

2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written

consent of ROHM.

3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the

Products or this document for any military purposes, including but not limited to, the development of mass-destruction

weapons.

4. The proper names of companies or products described in this document are trademarks or registered trademarks of

ROHM, its affiliated companies or third parties.

Notice-PGA-E

Rev.003


型号：	BM28723AMUV
厂家：	ROHM
描述：	BM1050AF是组合了应对高次谐波的功率因数校正（Power Factor Correction）转换器（以下简称PFC部）与DC/DC转换器（以下简称DC/DC部）的复合LSI。DC/DC部采用准谐振方式动作，有助于实现低EMI。BM1050AF内置650V耐压启动电路。PFC部、DC/DC部均外接开关MOSFET及电流检测电阻，可实现自由度高的电源设计。PFC部采用峰值电流控制。利用带AC电压过低补偿电路的乘法器、应对负载变动的电路、最大功率补偿电路等各种保护电路，提供合适的应用方案。此外，内置跳频功能，有助于实现低EMI。DC/DC部的准谐振方式为软开关动作，有助于实现低EMI。内置脉冲串模式，可降低轻负载时的功耗。内置了软启动功能、脉冲串功能、逐周期过电流限制、过电压保护、过负荷保护等各种保护功能。与微控制器间设有通信控制用端子、外部停止端子，可提供适用于各种应用的系统方案。通信开关控制器微控制器软启动脉冲功率因数校正转换器
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中文：	中文翻译
下载：	下载PDF数据表文档文件

BM28723AMUV [ROHM]

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