BM29F04-12AI [WINBOND]
Flash, 512KX8, 120ns, PQCC32;
| 型号： | BM29F04-12AI |
| 厂家： | 
WINBOND |
| 描述： | Flash, 512KX8, 120ns, PQCC32 内存集成电路 |
| 文件： | 总29页 (文件大小：196K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BRIGHT
Microelectronics
Inc.
Preliminary BM29F040
4 MEGABIT (512K ´ 8)
5 VOLT SECTOR ERASE CMOS FLASH MEMORY
GENERAL DESCRIPTION
The BM29F040 is a 4 Megabit, 5.0 Volts only Flash memory device organized as 512K ´ 8 bits each.
The BM29F040 is offered in an Industry standard 32-pin package which is backward compatible to 1
Megabit and also pin compatible to EEPROMs. The device is offered in PDIP, PLCC and TSOP
packages. The device is designed to be programmed and erased in system with the standard system
5 Volt Vcc supply. An external 12.0 Volts Vpp is not required for program and erase operation. The
device can also be reprogrammed in standard EPROM programmers.
The BM29F040 offers access times between 70 to 150 nS. The device has separate chip enable
(CE), write enable (WE ) and output enable (OE ) controls to eliminate bus contention.
BMI flash memory technology reliably stores memory information even after 100,000 erase and
program cycles. The BMI proprietary cell technology enhances the programming speeds and
™
eliminates over erase problems seen in the classical ETOX type of Flash cell technologies. The
combination of cell technology and internal circuit design techniques give reduced internal electrical
fields and this provides improved reliability and endurance. The BM29F040 is entirely pin and
command set compatible to the JEDEC standard 4 Megabit EEPROM. The commands are written to
the Command State machine using standard microprocessor write timings. The internal Programming
and Erase Algorithms are automatically implemented based on the input commands.
The BM29F040 is programmed by executing the program command sequence. This will start the
internal automatic program Algorithm that times the program pulse width and also verifies the proper
cell margin. Erase is accomplished by executing the erase command sequence. The internal Power
Switching State Machine automatically executes the algorithms and generates the necessary voltages
and timings for the erase operation. The program and erase verify is also done internally and proper
margin testing is automatically performed. This scheme unburdens the microprocessor or
microcontroller from generating the program and erase algorithms by controlling all the necessary
timings and voltages. The entire memory is typically erased in 1.5 seconds. No preprogramming is
necessary in this technology.
The BM29F040 also features a sector erase architecture. It is divided into 8 sectors of 64K bytes
each. Each sector can be erased individually without affecting the data in other sectors or they can be
erased in a random combination of groups. This multiple sector erase capability or full chip erase
makes it very flexible to alter the data in BM29F040. To protect the data from accidental program or
erase the device also has a sector protect or multiple sector protect function.
The device features a single 5 Volt power supply for read, program and erase operation. Internally
generated and well regulated voltages are provided for the program and erase operation. A low Vcc
detector inhibits write operations during power transitions. The end of program or erase is detected by
Data polling of DQ7 or by the Toggle Bit feature on DQ6. Once the program or erase cycle has been
successfully completed, the device internally resets to Read mode.
A Winbond Company
Publication Release Date: June 1999
Revision A1
- 1 -
BRIGHT
Microelectronics
Inc.
Preliminary BM29F040
FEATURES
· 5.0 V +/- 10% Program and Erase
- Minimizes system power consumption
- Simplifies the system design
· Sector Erase architecture
- 8 Equal sectors of 64K bytes each
- Any combination of multiple Sector Erase
- Full Chip Erase
· Compatible with JEDEC standard commands
· Sector Protection
- Uses same software commands as
EEPROMs
- Any number of sectors can be protected from
Program and Erase operation
· Compatible with JEDEC-standard byte wide
pinout
· Low Power Consumption
· Typically 100,000 Program/Erase cycles
· Erase Suspend and Resume
- 32 pin PLCC/TSOP
- 32 pin DIP
· Automated sector/chip Erase Algorithms
- Suspend the Sector Erase Operation to
allow a READ in another sector
- No programming before Erase needed
- Internal program and Erase Margin Check
· Low Vcc Write inhibit < 3.2 volts
· Single Cycle reset command
· Data Polling and Toggle Bit
- useful for detection of Program and Erase
cycle completion
Product Selection Guide
FAMILY PART NO.
-75*
70
-90
90
90
-120
120
120
-150
150
150
Maximum Access Time (nS)
70
CE (E) Access time (nS)
OE (G) Access time (nS)
30
35
50
60
Table 1
*This speed is available with Vcc = 5V +/- 5% variation
- 2 -
BRIGHT
Microelectronics
Inc.
Preliminary BM29F040
PIN CONFIGURATIONS
DIP Top View
A18
A16
A15
A12
A7
Vcc
WE
A17
A14
A13
A8
A6
A5
A9
A4
A11
OE
A3
A2
A10
CE
A1
A0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ0
DQ1
DQ2
GND
PLCC Top View
A12 A16 Vcc A17
A15 A18 WE
3
4
2
1
31 30
32
A14
A13
A8
5
6
29
28
27
26
25
24
23
22
21
A7
A6
7
A5
A9
8
9
10
11
12
13
A4
A11
OE
A3
A2
A10
CE
A1
A0
DQ7
DQ0
14 15 16 17 18 19 20
I/O's 1 2
3 4 5 6
GND
TSOP Top View
TYPE 1
OE
A11
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A10
CE
A9
2
A8
3
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A13
A14
A17
WE
Vcc
A18
A16
A15
A12
A7
4
5
6
7
8
9
10
11
12
13
14
15
16
A1
A6
A2
A5
A3
A4
A Winbond Company
Publication Release Date: June 1999
Revision A1
- 3 -
BRIGHT
Microelectronics
Inc.
Preliminary BM29F040
Flexible Sector-erase Architecture:
64K bytes per sector
Individual sector, multiple sector or bulk erase capability.
Individual or multiple-sector protection is user definable.
Table 2. Sector Definition
64K byte sector
64K byte sector
64K byte sector
64K byte sector
64K byte sector
64K byte sector
64K byte sector
64K byte sector
70000H-7FFFFH
60000H-6FFFFH
50000H-5FFFFH
40000H-4FFFFH
30000H-3FFFFH
20000H-2FFFFH
10000H-1FFFFH
00000H-0FFFFH
PIN DESCRIPTION
SYMBOL
TYPE
NAME AND FUNCTION
A0 - A18
I
ADDRESS INPUTS: for memory addresses. Addresses are internally
latched during a write cycle.
A9
I
ADDRESS INPUT: When A9 is at 12 Volts the ID mode is accessed. During
this mode A0 decodes between the manufacturer and device ID¢s.
DQ0-DQ7
I/O
DATA INPUTS / OUTPUTS: Inputs array data on the fourth
and WE
CE
cycle during a program command. Inputs commands WE to the Command
register when and WE are active. Data is internally latched during the
CE
program cycles. Outputs are from Array and Intelligent Identifier
information. The output pins float to tri-state when the chip is deselected or
the outputs are disabled.
I
I
CHIP ENABLE: Activates the device's control logic, input buffers, decoders
CE
OE
and sense amplifiers.
is active low control;
high deselects the
CE
CE
memory device and reduces power consumption to standby levels.
OUTPUT ENABLE: is active low control signal. This pin gates the
OE
’ s
device outputs through the data buffers during a read cycle. When
is
CE
low and
is high the outputs are tri-state.
OE
I
WRITE ENABLE: Controls writes to the Command state Machine and
memory array. WE is active low signal. Addresses and Data are latched
during the rising edge of the WE pulse.
WE
Vcc
DEVICE POWER SUPPLY: Main power source to the device. It¢s value is
5V ± 10% or 5V ± 5%.
GND
GROUND: The device ground for the internal circuitry.
Table 3
- 4 -
BRIGHT
Microelectronics
Inc.
Preliminary BM29F040
BLOCK DIAGRAM
0
7
DQ - DQ
Vcc
GND
Erase Voltage
Generator
Input / output
Buffers
WE
State
Control
Command
Register
Program Voltage
Generator
Data
latch
Chip Enable
Output Enable
Logic
CE
OE
Vcc Detect
Timer
A
d
d
Y-Decode
Y-MUX / SENSING
r
e
s
s
L
a
t
X-decode
ARRAY
A 0 - A 18
c
h
Figure 1
BUS OPERATION
Operation
A0
A1
A6
A9
I/O
WE
H
H
H
X
CE
L
OE
L
Auto select Manufacturers ID (1)
Auto select Device ID (1)
Read
L
H
L
L
L
L
VID
VID
A9
X
Code
Code
Dout
L
L
L
L
A0
X
A1
X
A6
X
Standby
H
L
X
High Z
High Z
Din (2)
X
Output Disable
H
H
VID
L
H
L
X
X
X
X
Write
L
A0
X
A1
X
A6
X
A9
VID
VID
Enable Sector Protect
Verify Sector Protect (3)
L
L
L
H
L
H
L
Code
Table 4
Notes:
1. LEGENDS: L = VIL, H = VIH, X = don't care, VID = +12V.
2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to table 6 for
Command definitions.
3. Refer to Table 4 for valid Din during a write operation.
4. Refer to the section on sector protection.
A Winbond Company
Publication Release Date: June 1999
Revision A1
- 5 -
BRIGHT
Microelectronics
Inc.
Preliminary BM29F040
Autoselect Codes
Code
(Hex)
7
6
5
4
3
16
6
1
0
DQ DQ DQ DQ DQ
DQ DQ DQ
A
A
A
A
2
1
0
TYPE
18
17
A
A
Vil
0
0
1
0
Manufacturer Code
X
X
Vil Vil ADH
1
0
0
1
1
0
0
0
1
0
X
1
0
X
X
X
Vil Vil Vih
40H
01H
BM29F040 Device code
Sector Protection (1)
0
0
0
1
0
0
0
0
Sector Addresses
Vil Vih
Vil
Table 5
PRODUCT FAMILY PRINCIPLES OF OPERATION
Flash memory devices are electrically alterable non-volatile memory products. The BM29F040
augments this feature by not requiring an additional Vpp power supply. The 4 Megabit flash family
uses a Command register and internally generated voltages and timing algorithms to make program
and erase operations simple. The user need not worry about generating tightly controlled high
voltages on board or tying up the microcontroller to generate program and erase algorithms.
The Command register allows for 100% TTL-level control inputs, and maximum compatibility with the
Flash memory functions.
The device provides standard EPROM read, standby and output disable operations. Manufacturer
Identification and Device Identification data can be accessed through the Command register or
through the standard EPROM ²A9² high voltage access (VID) for PROM programming equipment.
A Command register and Power Switching State Machine are built inside the device. Their purpose is
to completely automate the program and erase operation. The command register receives the
commands given by the user and internally controls the power switching state machine.
Read Mode
The BM29F040 has three control pins and they should all be logically active to obtain valid data at the
outputs. Chip-Enable (CE) is the device selection control. Output Enable (OE ) is the data
input/output control. This pin when high (VIH) brings the output drivers to the tristate and allows data
into the device. Data input is then controlled by WE . When the OE pin is low (VIL) it enables the
output buffers and valid array data becomes available at the output pins. The Write Enable (WE ) pin
has to be high during the READ mode.
Standby Mode
The BM29F040 has two standby modes: a CMOS standby mode (CE input = Vcc +0.5V) when the
current consumed is less than 100 mA; and a TTL standby mode (CE is held at VIH) when the current
consumed is approximately 1 mA. In the standby mode the outputs are in a high impedance state
independent of the OE input.
If the device is deselected during erasure or programming, the device will draw active current until the
erase or programming operation is complete.
- 6 -
BRIGHT
Microelectronics
Inc.
Preliminary BM29F040
Autoselect Mode
The Autoselect mode allows access to the manufacturers and the device code. This mode can be
enabled by either taking the address pin A9 to VID (11.5 to 12.5 volts) or by giving the Autoselect
Command sequence as shown in Table 5. Once the Autoselect mode is enabled two identifier bytes
can be read on the device outputs by toggling A0 from VIL to VIH. Byte 0 (A0 = VIL) represents the
manufacturers code (ADH for BMI). Byte 1 (A0 = VIH) represents the device identifier and this is 40H
for the BM29F040. A READ command must be written to the Command register to return to the Read
mode after the Autoselect mode.
Write Operations
The on-chip state machines control the Chip Erase, Sector Erase and byte Write operations. This
frees the system processor to do other tasks. All the Programming and Erase voltages are generated
internally. The Write and Erase timings and algorithms are also built into the device. The byte write/
sector erase or Chip Erase Command Interface provides additional data protection to avoid
accidental Write or Erase.
Commands are written to the Command register using standard microprocessor write timings. The
Command register recognizes Read mode, Autoselect mode, Chip Erase, Sector Erase (64K bytes
per sector) and Program commands. The Command register does not occupy an addressable
memory location. The interface register is a latch used to store the command and address and data
information needed to execute the command.
Command Definitions
Device operations are selected by writing specific address and data sequences into the Command
register. Table 6 defines these Command sequences.
Read/ Reset Command
The read or reset operation is initiated by writing the read/reset command sequence to the command
register. Processor read cycles retrieve the data from the memory. The device remains enabled for
reads until the command register contents are changed.
The device will automatically power-up in the read/reset mode. In this case, a command sequence is
not needed to read the memory data. This default power up to read mode ensures that no spurious
changes of the data can take place during power-up. As shown in this data sheet, the timing
parameters and A.C. read waveforms should be referenced.
A single cycle reset is also available as shown in table.
A Winbond Company
Publication Release Date: June 1999
Revision A1
- 7 -
BRIGHT
Microelectronics
Inc.
Preliminary BM29F040
Table 6. Command Definitions
Bus
First Bus
Write
cycle
Second
Third Bus Fourth Bus Fifth Bus
Sixth Bus
Write
cycle
Write
Bus Write Write cycle Write cycle Write
Command
Sequence
cycles
cycle
cycle
Address Data
Address Data
Address Data
Address Data Address Data Address
Data
required
XXXXH
5555H
5555H
F0H
AAH
AAH
1
4
4
Read /Reset
Read /Reset
Auto Select
2AAAH
2AAAH
55H
55H
5555H
5555H
F0H
90H
RA
00H
01H
SA
RD
ADH
40H
00
5555H
AAH
2AAAH
55H
5555H
90H
4
Auto Select
Sector
X02
PA
01
Protect
Verify
5555H
AAH
2AAAH
55H
5555H
A0H
PD
4
Byte
Program
5555H
5555H
XXXXH
AAH
AAH
B0H
2AAAH
2AAAH
55H
55H
5555H
5555H
80H
80H
5555H AAH 2AAAH 55H 5555H
5555H AAH 2AAAH 55H SA
10H
30H
6
6
1
Chip Erase
Sector Erase
Sector Erase
Suspend
XXXXH
30H
1
Sector Erase
Resume
Notes:
1. Address bit A15, A16, A17 and A18 = X = don¢t care for all address commands except for Program
address (PA) and sector address (SA).
2. Bus operations are defined in Table 4.
3. RA = Address of the memory location to be read. PA = Address of the memory location to be programmed.
Addresses are latched on the falling edge of WE. SA = Address of the sector to be erased. The combination
of A16, A17 and A18 will uniquely select the sector.
4. RD = Data from the selected address location (RA) during read operation. PD = Data to be programmed at the
selected memory location (PA). Data is latched at the falling edge of /WE.
5. Auto select command can be used to evaluate whether a block is protected or not by using at the fourth address 02H.
This is similar to placing A9 to High Voltage.
Auto Select Command
The BM29F040 contains two different procedures for the autoselect mode. One is the traditional
PROM programmer methodology (by taking Address pin A9 to VID) and the other is by writing the
Auto Select command sequence into the command register. Following the third bus cycle write
command, a read cycle from Address 00H retrieves the BMI manufacturer code ADH, and a read
cycle at 01H retrieves the device code of 40H. Scanning the sector addresses (A16, A17, A18) while
(A6, A1, A0) = (0, 1, 0) will produce a logical at device output DQ0 for a protected sector. See table 5
for more details.
To terminate this operation, it is necessary to write the read/ reset command to the command
register.
- 8 -
BRIGHT
Microelectronics
Inc.
Preliminary BM29F040
Byte Write or Byte program
The BM29F040 is programmed one byte at a time. Programming is a four bus cycle operation. There
are two "unlock" write cycles which are followed by a program set-up command and data write cycles.
Addresses are latched on the falling edge of WE and data is latched on the rising edge of WE . The
rising edge of WE begins programming. During the execution of the embedded program algorithm
the host system is not required to provide any other controls or timings. The device also provides
adequate program margin and all the necessary voltages and timings. When completed, the
automatic programming will provide the equivalent of the written data on DQ7. After a successful
programming
operation the device returns back to read mode. Data polling must be performed at the memory
location which is being programmed.
Figure 3 illustrates the Embedded Programming Algorithm and the waverforms are shown in figures 9
and 10.
Chip Erase
Chip erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by
writing the ²setup² command. Two more "unlock" write cycles are then followed by the chip erase
command.
Chip erase does not require the user to program the device prior to erase. BM29F040's technology is
immune to overerase and it does not need any internal programming algorithm before erase. This can
save erase time in many applications.
The automatic Chip erase begins on the rising edge of the last WE pulse in the command sequence
and terminates when the data on DQ7 is "1", and which time the device returns back to the read
mode.
Figure 4 illustrates the Auto Erase Algorithm and the Erase Waveforms are shown in Figure 11.
Sector Erase
Sector erase is a six bus cycle operation. There are two "unlock" write cycles followed by writing the
sector erase setup command. Two more "unlock" write cycles are then followed by the sector erase
confirm command. The sector address is latched on the failing edge of WE , and the command data
is latched on the rising edge of WE . An 80 mS time-out from the rising edge of WE of the last sector
erase command is initiated. The actual sector erase starts 100 uS after the last rising edge of WE .
Multiple sectors can be erased simultaneously. After writing the six bus cycle command for sector
erase additional sector address and sector erase command can be inserted within the 80 uS time-out
period. The timer is reset every time and additional sector erase command is inserted. The sectors
can be added to be erased in any random sequence. Any command other than the sector erase
command or Erase Suspend command during the time-out period will reset the device to the read
mode and ignoring the previous command string. During the execution of the Sector Erase command,
only the Erase Suspend and Erase Resume commands are allowed. All other commands will reset
the device to the Read mode. Once the device resets to the Read mode due to command error during
Sector Erase, the data in this sector has lost its integrity. The sector should be properly erased again.
Sector erase does not require the user to program the sector before erase. When erasing a sector or
multiple sectors the data in the unselected sectors remains unchanged. After the sector erase
A Winbond Company
Publication Release Date: June 1999
Revision A1
- 9 -
BRIGHT
Microelectronics
Inc.
Preliminary BM29F040
operation is completed the data on DQ7 becomes "1", and the device returns to the read mode. Data
polling must be performed at an address within any of the sectors being erased.
Figure 4 shows the Embedded Erase Algorithm and Figure 11 shows the Sector Erase Waveforms.
Erase Suspend and Resume
The Erase suspend command allows the user to interrupt the sector erase function and then read
data from the other sectors which were not being erased. This command is not applicable during the
Chip erase operation or during the program mode. The Erase suspend command (B0H) will terminate
the Sector erase operation and it may require form 0.1 mS to 70 mS to suspend the erase operation
and go into the read mode (pseudo read mode). The user must use the toggle bit to determine if the
chip has entered the erase suspended read mode, at which time the toggle bit will stop toggling. An
address of a sector not being erased must be used to read the toggle bit. The user must keep the
information whether the device is in pseudo read mode or read mode. Every time an Erase suspend
command followed by an Erase resume command is written the internal counters are reset. The erase
suspend command is allowed during the 100 mS time out window before the actual sector erase
operation starts. The Erase resume command will start the erase operation immediately and there is
no time out window during erase resume. Note that any other command during the time out will reset
the device to read mode.
To resume the Sector erase operation after pseudo read mode the Resume command (30H) should
be written. The sector erase will start immediately. Another Erase suspend command can be written
after the chip has resumed the erase operation. Note that a data "0" can not be programmed back to
"1." Attempting to do so may give erroneous results or may hang up the device. Only an erase
operation can change the data from a "0" to "1".
The system may also write the Autoselect Command during the Erase Suspend mode. This allows the
host system to correctly read the autoselect codes during Erase Suspend since this data is not stored
in the memory array.
Sector Protection
The BM29F040 has a hardware sector protection. This feature will disable both Program and Erase
operation of the protected sector or group of sectors. The device is shipped with all sectors
unprotected.
To verify if a sector is protected, the programming equipment must force VID on the address pin A9,
and A6 = CE = OE = VIL and WE = VIH. Reading the device at a particular sector address (A16,
A17 and A18) and XXX2H will produce 01H at the data outputs for a protected sector. See Figure 14
for the AC Waveforms and Figure 16 for the algorithm.
Please use the appropriate approved Programmer or contact Bright for the BM29F040 Programmers
Guide for the specification for protecting individual sectors.
Sector Unprotection
The BM29F040 also features a sector unprotect mode, so that a protected sector may be
unprotected. All sectors are unprotected at the same time. Please use the appropriate approved
Programmer or contact Bright for the BM29F040 Programmers Guide for the specification to
unprotect the sectors.
It is also possible to determine if a sector is unprotected in the system by writing the autoselect
command and A6 is set to VIH. Performing a read operation at XXX2H and the sector address
(defined by A16, A17 and A18) will produce 00H at the Data outputs for an unprotected sector.
- 10 -
BRIGHT
Microelectronics
Inc.
Preliminary BM29F040
Table 7 Sector Address Table
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
A18
0
A17
0
A16
0
Address Range
00000H - 0FFFFH
10000H - 1FFFFH
20000H - 2FFFFH
30000H - 3FFFFH
40000H - 4FFFFH
50000H - 5FFFFH
60000H - 6FFFFH
70000H - 7FFFFH
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Data Flags
DQ7 Data polling
The BM29F040 features Data polling to indicate to the host system that the Embedded Algorithms are
in progress or completed. During the Embedded Program Algorithm, an attempt to read the device
will produce the complement of the Data last written to DQ7. Upon completion of the Embedded
Programming Algorithm an attempt to read the device will produce the true data last written to DQ7.
Data polling is valid after the rising edge of the fourth WE pulse in the four write pulse sequence.
During the Embedded Erase Algorithm, DQ7 will be "0" until the Erase operation is completed. Upon
completion of Erase the data at DQ7 is "1". For sector erase, the Data polling is valid after the last
rising edge of the sector erase WE pulse. For Chip erase, the Data polling is valid after the last rising
edge of the sixth Chip erase WE pulse. Data polling must be performed at a sector address within
any of the sectors being erased and not a protected sector. Once the Embedded operation is close to
being completed, the BM29F040 data pins (DQ7) may change asynchronously while the OE pin is
asserted low. This means that the device is driving status information on DQ7 at one time and bytes
of valid data at other times. Depending on when the system samples the DQ7 output it may read the
status or it may read the valid data.
See Figure 12 for the Data polling timing diagram.
DQ6 Toggle Bit
The BM29F040 also features the "Toggle Bit" as a method to indicate to the host system that the
Embedded Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read data from the
device will result in DQ6 toggling between "1" and "0". Once the Embedded Program or Erase
algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on successive
attempts. During programming the toggle bit is valid after the rising edge of the fourth WE pulse in
the four write pulse sequence. During Chip and Sector Erase, the toggle bit is valid after the rising
edge of the sixth WE pulse in the six write pulse sequence.
A Winbond Company
Publication Release Date: June 1999
Revision A1
- 11 -
BRIGHT
Microelectronics
Inc.
Preliminary BM29F040
In programming, if the sector being written to is protected, the toggle bit may toggle for about 2 mS
and then will stop toggling without the data being changed. During erase the device will erase all the
sectors except the sector being protected. If all the sectors are protected the chip will toggle the
toggle bit for about 2 mS and then drop back to read mode without changing the data.
Either CE or OE toggling will cause the DQ6 to toggle. The toggle bit is valid in the time out period
during sector erase.
See Figure 13 for the Toggle bit timing diagrams.
DQ5 Exceeded The Timing Limits
DQ5 indicates if the program or erase time has exceeded the specified timing limits. Under these
conditions DQ5 will produce a "1". This is a failure condition which indicates that the program or erase
cycle was not successfully completed. Data polling is the only operating function of the device under
this condition. The CE circuit will partially power down the device under these conditions. The OE
and WE pins will control the output disable function as shown in Table 4.
If this failure condition occurs during the sector erase operation, it indicates that the particular sector
is bad and may not be reused. The other sectors are still functioning properly and can be used. The
device must be reset to use the other good sectors. To reset the device, write the Reset command
sequence to the device. This will allow the system to use the other active sectors in the device.
If this failure condition occurs during chip erase, it indicates that the entire chip is bad or many sectors
are bad.
If this condition occurs during byte write it indicates that the sector containing this byte is bad.
This failure condition can also occur if the user tries to program a non-blank location without erasing.
In this case the device locks out and never completes the operation. Please note that this is not a
device failure.
DQ3 Sector Erase Timer
After the completion of the Sector erase command sequence the sector erase time-out begins. DQ3
will remain low until the time-out is complete. Data polling and the Toggle bit are valid after the initial
sector erase command sequence.
If Data polling or the Toggle bit indicates the device has been written with a valid erase command,
DQ3 may be used to determine if the sector erase timer window is still open. If DQ3 is "1" the
internally controlled erase cycle has begun. If DQ3 is "0" the device will accept additional sector erase
commands. To ensure that the command has been accepted, the user should check the status of
DQ3 prior to and following each sector erase command. If DQ3 is "1" on the second status check, the
command may not be accepted.
Once the internal erase cycle begins the device will not accept any other command until the internal
erase cycle is completed.
The BM29F040 is designed to offer protection against accidental programming or erasure. During
power-up the device automatically resets to the read mode. The multi-bus command sequences also
provide data protection for accidental write. The device also provides additional features to prevent
inadvertent write operations during power-up and power-down transitions or system noise.
- 12 -
BRIGHT
Microelectronics
Inc.
Preliminary BM29F040
DQ2 Toggle Bit II
The BM29F040 also features the "Toggle Bit II" as a method to indicate to the host system whether a
specific sector is actively erasing or whether the sector is erase-suspended. The Toggle Bit II is valid
after the rising edge of the final WE pulse in the command sequence.
DQ2 toggles when the host system reads addresses within a sector that have been selected for erase.
The system may use OE or WE to control the read cycles. But, DQ2 can not distinguish between a
sector erasing or erase-suspended. However, Toggle Bit DQ6 can be used to determine if a sector is
actively erasing or erase-suspended. As a result, both Toggle Bits are required for the host system to
determine the current mode information. Refer to Table 7 for a further comparison of DQ6 and DQ2.
Whenever the host system begins to read the erase status using the toggle bits, they must be read at
least twice in a row. Typically, the system would store the first value and compare it to the second. If
the bits are still toggling, the system should also check DQ5(see the DQ5 description).
If DQ5 is high, the system should re-check the toggle bits since toggling may have just finished. If the
toggle bits have stopped toggling, the device has successfully completed the erase. If the toggle bits
are still toggling, the device has not successfully completed the erase operation and the host should
issue a Reset Command to the device before continuing.
If DQ5 is low, the host system should continue to monitor the toggle bits and DQ5 or issue an erase
suspend command if performing a single or multiple sector erase command.
Write Operation Status
Status
Auto-Programming
DQ7
____
DQ7
0
DQ6
DQ5
DQ3
DQ2
Standard
Toggle
0
N/A
No Toggle
Auto-Erase
Toggle
0
0
1
Toggle
Toggle
Erase
Reading an Erase
Suspended Sector
Reading a Non-Erase
Suspended Sector
Auto-Programming
Erase Suspend
No Toggle
N/A
1
Suspend
Data
Data
Data
Data
N/A
1
Data
N/A
____
DQ7
____
DQ7
0
Toggle
Toggle
Toggle
0
1
1
Exceeded
Auto-Programming
Reserved for
Future use
Time Limits
Auto-Erasing
1
Table 8. Hardware Sequence Flags
Low Vcc Write Inhibit
During Vcc power-up or power-down, a write cycle is inhibited for Vcc values of less than 3.2 Volts
(3.8 Volts typical). If Vcc < Vlko (Vlko = lock out Voltage) the command register is disabled and all
internal program/erase circuits are disabled. Under this condition the device will reset to the read
mode. If a write command is given during Vcc < Vlko, the writes will be ignored. It is the users
responsibility to ensure that the control pins are logically correct to prevent unintentional writes when
Vcc > Vlko.
A Winbond Company
Publication Release Date: June 1999
Revision A1
- 13 -
BRIGHT
Microelectronics
Inc.
Preliminary BM29F040
Write Pulse Glitch Protection
Noise pulses of less than 5 nS on OE , WE or CE will not initiate a write cycle.
Power-up Wtire Inhibit
Power-up of the device with WE = CE = VIL and OE = VIH will not accept commands at the rising
edge of WE . The internal state machine is automatically reset to the read mode on power-up.
Logical Inhibit
Writing is inhibited by holding any one of the control pins to OE = VIL, WE = VIH or CE = VIH. To
initiate a write cycle, CE and WE must be logical "0" and OE must be logical "1".
Sector Protect
Sectors of the BM29F040 may be hardware protected by the user. The protection circuitry will disable
both program and erase functions for the protected sectors. The program and erase commands will
be ignored if given to the protected sectors. The Chip erase command will also not erase the
protected sectors.
Parallel Device Erasure
The BM29F040 is a fully self timed device. This makes it feasible to Erase or Program many devices
in parallel.
Program Command Sequence
(Address/Data)
Embedded Programming Flow Chart
Start
First Write cycle
5555H/ AAH
2AAAH/ 55H
5555H/ A0H
Write Program Command Sequence
(see Fig. 3a)
Second Write cycle
Data poll Device
Third Write cycle
Fourth Write cycle
No
Verify Byte
?
Program Add./Program
Data
Yes
Byte Write
Completed
Figure: 3A
Figure: 3B
Note: See Data Polling Algorithm in Figure 10 and 11.
- 14 -
BRIGHT
Microelectronics
Inc.
Preliminary BM29F040
Embedded Erase Algorithm
Start
Write Program Command Sequence
(see below)
Data poll Device
No
Data = FFH
?
Yes
Erasure
Completed
Figure 3. Embedded Programming Algorithm
Note: See Data Polling Algorithm in Figure 5
Chip Erase Command Sequence
(Address/Data)
Individual Sector/Multiple Sector Erase
Command Sequence (Address/Data)
First Write cycle
5555H/ AAH
2AAAH/ 55H
5555H/ 80H
5555H/ AAH
2AAAH/ 55H
First Write cycle
5555H/ AAH
2AAAH/ 55H
5555H/ 80H
5555H/ AAH
2AAAH/ 55H
5555H/ 10H
Second Write cycle
Third Write cycle
Second Write cycle
Third Write cycle
Fourth Write cycle
Fifth Write cycle
Sixth Write cycle
Fourth Write cycle
Fifth Write cycle
Sixth Write cycle
Sector Address/ 30H
Sector Address/ 30H
Sector Address/ 30H
Additional
Sector erase
commands are
optional
Figure 4. Automated Erase Flow Chart and Sequence
A Winbond Company
Publication Release Date: June 1999
Revision A1
- 15 -
BRIGHT
Microelectronics
Inc.
Preliminary BM29F040
Data Polling Algorithm
Toggle Bit Algorithm
Start
Start
Yes
No
7
DQ = Data
6
DQ = Toggle
?
?
No
Yes
No
No
DQ 5=1
DQ5=1
?
?
Yes
Yes
Note 2
DQ 6 = Toggle
Yes
DQ 7= Data
?
Note 1
No
?
No
Yes
Pass
Pass
Fail
Fail
Note: DQ7 is rechecked even if DQ5 = "1" because DQ7 may
change simultaneously with DQ5.
Note: DQ6 is rechecked even if DQ5 = "1" because DQ6 may
stop toggling at the same time as DQ5 is changed to "1".
Figure 5. Data Polling and Toggle Bit Algorithm
Absolute Maximum Ratings:
Operating Ranges:
Commercial (C) Devices
Storage Temperature
-65°C to +125°C
Temperature Range
0°C to +70°C
Operating Temperature (Note 1)
Vcc supply voltage during 4.5V to 5.5V or
During Read
-55°C to +125°C
all operations
4.75V to 5.25V
During Program/Erase
-55°C to +125°C
Industrial (I) Devices
Temperature Range
Temperature under Bias
(With Power Applied)
-55°C to +125°C
-40°C to +85°C
Voltages with Respect to GND.
All pins except A9 (Note 2, 3)
Vcc (Note 2)
Vcc supply voltage during
all operations
4.5V to 5.5V
-2V to +7V
-2V to +7V
-2V to +14V
A9 (Note 3)
Output short circuit current (Note 4)
200 mA
Notes :
1. The datasheet defines the operation at specific temperature ranges.
2. Minimum DC voltage on input / output pins is -0.5V. During voltage transitions, inputs can undershoot to -2 Volts for periods
of up to 20 nS. The maximum DC voltage on these pins is Vcc +0.5V. During transitions, inputs may overshoot to Vcc +2.0V for
periods < 20 nS.
3. Maximum DC voltage on A9 may overshoot to 14.0V for periods < 20 nS.
4. Outputs may be shorted for no more than one second. Only one/output can be shorted at a time.
*Notice: Stresses above those listed under "Absolute Maximum Ratingsz" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect
device reliability.
- 16 -
BRIGHT
Microelectronics
Inc.
Preliminary BM29F040
Maximum Overshoot
Maximum Negative Overshoot
20 nS
20 nS
+0.8 V
-0.5 V
20 nS
-2.0 V
Maximum Negative Overshoot Waveform
Vcc + 2.0 V
Vcc + 0.5 V
2.0 V
20 nS
20 nS
20 nS
Maximum positive Overshoot Waveform
Figure 6. Maximum Overshoot Waveforms
DC Characteristics
PARAMETER
Input Low Level
SYM.
VIL
MIN.
-0.5
2.0
MAX.
0.8
UNIT
TEST CONDITIONS
V
V
V
V
V
Input High Level
VIH
Vcc +0.5
0.45
Output Low Voltage
Output High Voltage
Output High Voltage
Input Load Current
Output Leakage Current
VOL
VOH
lOL = 12 mA Vcc = Vcc Min.
lOH = -2.5 mA Vcc = Vcc Min.
lOHl = -100 mA Vcc = Vcc Min.
Vin = Vcc or GND Vcc = Vcc Max.
2.4
VOH2 Vcc -0.4
lLI
+/- 1.0
+/- 10
mA
mA
lLO
Vout = Vcc or GND Vcc = Vcc
Max.
Output Short Circuit Current
lOS
100
100
mA
Vout = 0.5V, Vcc = Vcc Max.
Vcc Standby Current (CMOS) 4
lSB1
mA
CE = Vcc +/- 0.5V, Vcc = Vcc
Max.
Vcc Standby Current (TTL) 4
Vcc Active Current Read 1, 3
Vcc Active Current Program or 2
lSB2
lCC1
lCC2
1.0
40
60
mA
mA
mA
CE = VIH Vcc = Vcc Max.
CE = VIL, f = 6 MHz, CE = VIH
CE = VIL, CE = VIH
A9 Intelligent Identifier Volatge
A9 Intelligent Identifier Current
VID
lID
11.5
12.5
50
V
A9 = VID
mA
Table 9
Notes:
1. All Currents are in RMS unless otherwise noted. Typical values are Vcc = +5.0V, T = 25° C.
2. These parameters are sampled but not 100% tested.
3. Automatic power saving reduces the Iccr to 1 mA.
4. CMOS inputs are Vcc +0.5V. TTL inputs are either VIL or VIH.
A Winbond Company
Publication Release Date: June 1999
Revision A1
- 17 -
BRIGHT
Microelectronics
Inc.
Preliminary BM29F040
Capacitance:
TA = 25° C, f = 1 MHZ (2)
PARAMETER
Input Capacitance
Output Capacitance
SYMBOL
Cin
CONDITIONTION
Vin = 0V
TYPICAL
MAX.
8
UNIT
pF
6
Cout
Vout = 0V
10
12
pF
AC Testing Input/Output Waveform
AC Testing Load Circuit
2.7K
R
L
2.4
2.0
0.8
2.0
0.8
Test
Points
Input
0.45
Output
Device Under
Test
AC test inputs are driven at Voh ( 2.4V VTTL) for a
logic "1" and Vol ( 0.4V VTTL) for a logic "0". Input
timing measurement begins at Vih ( 2.0V VTTL) for an
input "1" and Vil ( 0.8V VTTL) fir an input "0".
Output timing measurement ends at 2.0V for an output
"1" and 0.8V for an output "0". Input Rise and fall times
(10% to 90%) <10 nS.
R
C
L
L
6.2K
C
= 100 pF
L
L
C
includes Jig Capacitance
The diodes are 1N3064 or
wequivalent.
Figure 7. A.C.Testing Load and Waveforms
- 18 -
BRIGHT
Microelectronics
Inc.
Preliminary BM29F040
AC Characteristics - Read Only Operations (1)
SYMBOL (4)
DESCRIPTION
-75 -90
-120
-150
UNITS
JEDEC
Standard
tRC
tAVAV
tAVQV
tELQV
Read Cycle Time
Address to Output Delay
70
70
70
90
90
90
120
120
120
150
150
150
nS
nS
nS
tACC
tCE
(2)
(3)
low to Output Delay
low to Output Delay
low to Output LOW Z
high to Output HIGH Z
low to Output LOW Z
high to Output HIGH Z
CE
OE
CE
CE
OE
OE
tGLQV
tELQX
tEHQZ
tGLQX
tGHQZ
tAXQX
tOE
tLZ
30
0
35
0
50
0
55
0
nS
nS
nS
nS
nS
nS
tHZ
20
0
20
0
30
0
35
0
tOLZ
tDF
(3)
(1)
20
0
20
0
30
0
35
0
tOH
Output Hold from Address,
or
, whichever is first
CE
OE
Table 11
Notes:
1. See A.C. Input/Output Reference Waveforms for timing measurements.
2. may be delayed up to tCE-tOE after the falling edge of without impact on tCE.
OE
3. Sampled, not 100% tested.
4. See A.C. Input/Output Reference Waveforms and A.C. Testing Load Circuits for testing characteristics.
CE
Vcc Power-
up
Device &
Outputs
Enabled
Vcc Power-
Standby
Data Valid
Standby
Address Select.
down
t AVAV
Vih
Addresses
Address Valid
Vil
Vih
Vil
CE (E)
OE (G)
WE (W)
t EHQZ
Vih
Vil
t GHQZ
t
GLQV
Vih
ELQV
t
Vil
AVQV
t
AXQX
t
Vih
t
GLQX
High Z
High Z
DATA (D/Q)
Vil
Valid Output
ELQX
t
5.0 V
VCC
GND
Figure 8. A.C.Waveforms for Read Operations
A Winbond Company
Publication Release Date: June 1999
Revision A1
- 19 -
BRIGHT
Microelectronics
Inc.
Preliminary BM29F040
AC CHARACTERISTICS - for WE Controlled Write Operation
SYMBOL
DESCRIPTION
-75
-90
-120
-150 UNITS
JEDEC
Standard
tWC
tCS
tAVAV
tELWL
tAVWL
tDVWH
tWLWH
tWHEH
tWLAX
tWLWH
tWHWL
Write Cycle Time
Setup
(4)
70
0
90
0
120
0
150
0
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
CE
tAS
Address Setup Time
Data Setup Time
Data Hold Time
0
0
0
0
tDS
30
0
45
0
50
0
55
0
tDH
tCH
Hold Time
0
0
0
0
CE
tAH
Address Hold Time
Write Pulase Width
45
35
20
0
45
45
20
0
50
50
20
0
50
50
25
0
tWP
tWPH
tOES
tOEH
Pulse Width High
WE
Output Enable Setup Time
Output Enable
Hold Time
Read (4)
0
0
0
0
Toggle and Data
Polling
10
10
10
10
tGHWL
tWHWH1
tWHWH2
tGHWL
Read Recover Time Before Write
0
16
1.5
30
50
4
0
16
1.5
30
50
4
0
16
1.5
30
50
4
0
16
1.5
30
50
4
nS
mS
sec
sec
mS
mS
mS
mS
mS
tWHWH1 Programming Operation
tWHWH2 Erase Operation (min.) (1)
typ
max
(4)
tVCS
tVLHT
tWPP1
tWPP2
tCESP
Vcc Setup Time
Voltage Transition Time
Write Pulse Width
Write Pulse Width
(2, 4)
(2)
100
10
4
100
10
4
100
10
4
100
10
4
(2)
(3, 4)
Setup Time to
CE
WE
Active
tOESP
4
4
4
4
mS
Table 12
Notes:
1. The Erase operation does not need programming time.
2. These timings are for Sector Protect/Unprotect operation.
3. This timing is only for sector Unprotect.
4. Not 100% tested.
- 20 -
BRIGHT
Microelectronics
Inc.
Preliminary BM29F040
Switching Waveforms
Data Polling
Vih
Addresses (A)
PA
PA
5555H
tWC
Vil
AH
t
RC
t
tAS
Vih
Vil
CE (E)
tGHWL
Vih
Vil
OE (G)
tWPH
CS
t
WHWH1
t
Vih
Vil
WE (W)
DF
t
tWP
tOH
DS
t
t OE
Vih
Vil
DH
t
HIGH Z
DATA (D/Q)
DQ7
PD
A0H
DOUT
CE
t
5.0 V
VCC
GND
Figure 9. A.C.Waveforms for Program Operations ( WE Controlled Writes)
Notes:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at the byte address.
3. DQ7 is the output of the complement of the data written tot he device.
4. DOUT is the output of the data written to the device.
5. Figure indicates the last two bus cycles of four bus cycle sequence.
A Winbond Company
- 21 -
Publication Release Date: June 1999
Revision A1
BRIGHT
Microelectronics
Inc.
Preliminary BM29F040
AC CHARACTERISTICS - for CE Controlled Write Operation
SYMBOL
DESCRIPTION
-75
-90
-120 -150 UNITS
JEDEC
Standard
tWC
tAVAV
tWLEL
Write Cycle Time (Note 4)
70
0
90
0
120
0
150
0
nS
nS
tWS
WE Setup time
Address Setup time
Data Setup time
Data Hold time
tAVEL
tDVEH
tEHDX
tEHWH
tAS
tDS
tDH
tWH
0
30
0
0
45
0
0
50
0
0
50
0
nS
nS
nS
nS
0
0
0
0
WE Hold time
tWLAX
tELEH
tAH
tCP
Address Hold time
45
35
45
45
50
50
50
50
nS
nS
Pulse Width
CE
CE
tEHEL
tCPH
20
20
20
25
nS
Pulse Width High
tOES
tOEH
Output Enable Setup time
0
0
0
0
0
0
0
0
nS
nS
nS
Output Enable Read (Note 4)
Hold time
Toggle and Data
Polling
10
10
10
10
tGHEL
tGHEL
Read Recover time before Write
Programming Operation
Erase Operation (1)
0
0
0
0
nS
uS
tWHWH1 tWHWH1
tWHWH2 tWHWH2
16
1.5
30
50
16
1.5
30
50
16
1.5
30
50
16
1.5
30
50
typ
sec
sec
max
tVCS
Vcc Setup time (Note 4)
Table 13
mS
Notes:
1. The Erase operation does not need programming time.
2. These timings are for Sector Protect/Unprotect operation.
3. This timing is only for sector Unprotect.
3. Not 100% tested.
- 22 -
BRIGHT
Microelectronics
Inc.
Preliminary BM29F040
Switching Waveforms
Data Polling
Vih
Addresses (A)
PA
5555H
t WC
PA
Vil
t
AH
t RC
t
AS
Vih
WE (W)
Vil
tGHEL
Vih
OE (G)
CE (E)
Vil
t
CPH
t
WHWH1
tWS
Vih
t
DF
Vil
t CP
tDS
tOH
t OE
DH
t
Vih
Vil
HIGH Z
A0H
PD
DQ7
DATA (D/Q)
DOUT
CE
t
5.0 V
GND
Vcc
Figure 10.A.C.Waveforms for Program Operations (
Controlled Writes)
CE
Notes:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at the byte address.
3. DQ7 is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
Switching Waveforms
t
AS
Vih
Addresses (A)
2AAAH
SA
5555H
2AAAH
tAH
5555H
5555H
Vil
Vih
CE (E)
Vil
tGHWL
Vih
OE (G)
Vil
t
CS
t
WP
Vih
WE (W)
Vil
WPH
t
tDS
AAH
tDH
Vih
DATA (D/Q)
Vil
HIGH Z
55H
AAH
80H
55H
30H for sector erase
10H for chip erase
tVCS
5.0 V
Vcc
GND
Figure 11. A.C. Waveforms for Chip/Sector Erase Operations
Note: SA is the sector address for Sector erase or 5555H for Chip Erase.
A Winbond Company
- 23 -
Publication Release Date: June 1999
Revision A1
BRIGHT
Microelectronics
Inc.
Preliminary BM29F040
Switching Waveforms
t DF
t CH
Vih
CE (E)
Vil
t OE
Vih
OE (G)
t OEH
Vil
t
CE
Vih
t
WE (W)
Vil
OH
Vih
High Z
DATA (D/Q)
Data Out
Data In
Data Out
Vil
t
WHWH1 or 2
Figure 12. AC Waveforms for Data Polling during Embedded Algorithm operations
Vih
Vil
CE (E)
OE (G)
Vih
Vil
OEH
t
Vih
WE (W)
Vil
Vih
Data In
DQ6
Vil
OH
OH
t
t
Figure 13. AC Waveforms for Toggle Bit during Embedded Algorithm operations Operating
- 24 -
BRIGHT
Microelectronics
Inc.
Preliminary BM29F040
ORDERING INFORMATION
PART NO.
ACCESS
TIME
POWER
SUPPLY CURRENT
MAX. (mA)
PACKAGE CYCLING
(Min)
TEMPERATURE
RANGE
(nS)
29F040-90NC
29F040-12NC
29F040-90AC
29F040-12AC
29F040-90TC
29F040-12TC
29F040-90NI
29F040-12NI
29F040-90AI
29F040-12AI
29F040-90TI
29F040-12TI
90
120
90
60
60
60
60
60
60
60
60
60
60
60
60
32 PDIP
32 PDIP
32 PLCC
32 PLCC
32 TSOP
32 TSOP
32 PDIP
32 PDIP
32 PLCC
32 PLCC
32 TSOP
32 TSOP
10,000
10,000
10,000
10,000
10,000
10,000
10,000
10,000
10,000
10,000
10,000
10,000
0°C - 70°C
0°C - 70°C
0°C - 70°C
0°C - 70°C
120
90
0°C - 70°C
0°C - 70°C
120
90
-40°C - 85°C
-40°C - 85°C
-40°C - 85°C
-40°C - 85°C
-40°C - 85°C
-40°C - 85°C
120
90
120
90
120
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.
3. Typical cycling is 100,000 program and erase cycles.
A Winbond Company
Publication Release Date: June 1999
Revision A1
- 25 -
BRIGHT
Microelectronics
Inc.
Preliminary BM29F040
APPENDIX A
Compatibility to AMD's AMD29F040B
The device is fully functional compatible to the AMD29F040B except during the command addresses
subset mode. In the AMD device, Commands do not require a unique address pattern for bits A15,
A14, A13, A12 or A11 (eg.X555H or X2AAH instead of 5555H and 2AAAH). That is, the BM29F040
requires specifically A14,A13,A12 and A11 to be forced during the command sequence in addition to
A10 through A0. Note specifically that the BM29F040 does not require address A15 along with A18,
A17 and A16 to be forced during the command sequence.
AMD's reduced address requirement makes their device slightly easier to inadvertently create a
Command and cause some program error or malfunction. The advantage of reducing the address is
to simplify the hardware interface in systems where control signals are limited in number. The
29F040B reduces the interface requirement by 4 signals -- from 15 to 11 address control pins.
However if the full Command address is supplied (i.e. 2AAAH and 5555H) by the host system, there
will be no incompatibility using either device.
- 26 -
BRIGHT
Microelectronics
Inc.
Preliminary BM29F040
PACKAGE DIMENSIONS
32-pin P-DIP
Dimension in inches
Dimension in mm
Symbol
Min. Nom. Max. Min. Nom. Max.
5.33
0.210
A
A1
A
B
B
c
D
E
E1
e1
0.010
0.25
0.150 0.155 0.160 3.81
3.94
0.46
1.27
0.25
4.06
0.56
1.37
0.36
2
0.016 0.018
0.41
1.22
0.022
0.054
0.050
0.048
0.008
1
0.010 0.014 0.20
1.650 1.660
D
17
32
41.91 42.16
15.49
13.84 13.97 14.10
0.610
0.555
0.110
15.24
0.590 0.600
0.545 0.550
0.090 0.100
14.99
2.29
3.05
0
2.54
3.30
2.79
E1
0.120
0
0.140
15
0.130
3.56
15
L
a
17.02
0.630 0.650 0.670 16.00 16.51
0.085
eA
S
2.16
16
1
Notes:
E
S
1.Dimensions D Max. & S include mold flash or
tie bar burrs.
c
2.Dimension E1 does not include interlead flash.
2
A
A
L
A1
Base Plane
3.Dimensions D & E1 include mold mismatch and
.
are determined at the mold parting line.
4.Dimension B1 does not include dambar
protrusion/intrusion.
5.Controlling dimension: Inches
6.General appearance spec. should be based on
Seating Plane
B
e1
eA
a
B1
final visual inspection spec.
32-pin PLCC
Dimension in Inches
Dimension in mm
Symbol
Min. Nom. Max. Min. Nom. Max.
H E
E
0.140
3.56
A
A
A
b
b
c
D
E
e
G
G
H
H
L
y
0.020
0.105
0.026
0.016
0.008
0.547
0.447
0.044
0.490
0.390
0.585
0.485
0.075
0.50
2.67
1
4
30
1
32
0.110
0.028
0.018
0.010
0.550
0.450
0.050
0.51
0.115
0.032
0.022
0.014
0.553
0.453
0.056
0.530
0.430
0.595
0.495
0.095
0.004
2.80
0.71
0.46
0.25
13.97
11.43
1.27
12.9
2.93
0.81
2
1
0.66
0.41
0.56
5
29
0.20
0.35
13.89
11.35
1.12
14.05
11.51
1.42
12.45
9.91
13.46
10.92
15.11
12.57
2.41
D
D
G
0.410
0.590
0.49
10.41
14.99
12.45
2.29
E
D
E
D
H D
14.86
12.32
1.91
0.090
0.10
°
0
°
0
°
10
°
10
q
21
13
Notes:
1. Dimensions D & E do not include interlead flash.
2. Dimension b1 does not include dambar protrusion/intrusion.
3. Controlling dimension: Inches
14
c
20
4. General appearance spec. should be based on final
visual inspection sepc.
L
A2
A
q
e
1
b
A
b 1
Seating Plane
y
E
G
A Winbond Company
Publication Release Date: June 1999
Revision A1
- 27 -
BRIGHT
Microelectronics
Inc.
Preliminary BM29F040
Package Dimensions, continued
32-pin TSOP
H D
D
Dimension in Inches
Dimension in mm
Symbol
Max.
Min.
__
Nom.
__
Max.
Min.
__
Nom.
__
A
1.20
0.15
1.05
0.047
0.006
c
__
__
0.002
0.037
A 1
0.05
0.95
0.041
0.009
1.00
0.20
0.15
A
b
2
0.039
M
e
0.007 0.008
0.17
0.12
0.23
0.17
E
c
D
E
0.005 0.006
0.720 0.724
0.007
0.728
0.10(0.004)
18.30 18.40 18.50
b
0.311 0.315
0.780 0.787
7.90
8.00
8.10
0.319
19.80
__
20.00
0.795
__
20.20
__
HD
e
__
0.020
0.50
0.50
0.016 0.020
0.40
__
0.60
__
L
0.024
__
__
L
0.031
0.80
__
1
A
__
0.10
5
0.000
0.004
5
0.00
1
Y
A2
0
1
3
3
0
L
1
A
Y
L1
Note:
Controlling dimension: Millimeters
- 28 -
BRIGHT
Microelectronics
Inc.
Preliminary BM29F040
VERSION HISTORY
VERSION
DATE
Jun. 1999
PAGE
DESCRIPTION
A1
-
Initial Issued
Winbond Electronics (H.K.) Ltd.
Winbond Electronics North America Corp.
Headquarters
Rm. 803, World Trade Square, Tower II, Winbond Memory Lab.
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5796096
123 Hoi Bun Rd., Kwun Tong,
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006
TEL: 408-9436666
FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
A Winbond Company
Publication Release Date: June 1999
Revision A1
- 29 -
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