BD9775FV_11_技术文档

Large Current External FET Switching Regulator Controllers

High Efficiency

Step-down Switching Regulator Controller

No.11028EAT17

BD9775FV

●Description

BD9775FV is Switching Controller with synchronous rectification (BD9775FV is 1channel synchronous rectification) and

wide input range. It can contribute to ecological design (lower power consumption) for most of electronic equipments.

●Features

1) 2channel Step-Down DC/DC FET driver

2) Synchronous rectification for channel 2

3) Able to synchronize to an external clock signal

4) Over Current Protection (OCP) by monitoring VDS of P channel FET

5) Short Circuit Protection (SCP) by delay time and latch method

6) Under Voltage Lock Out (UVLO)

7) Thermal Shut Down (TSD)

8) Package: SSOP-B28

●Applications

Car navigation system, Car Audio, Display, Flat TV

●Absolute maximum ratings (Ta=25℃)

Parameter

Symbol

Ratings

Unit

Supply Voltage (VCC to GND)

VREF to GND Voltage

VCC

Vref

36

V

7

VREGA to GND Voltage

VREGB to VCC Voltage

OUT1, OUT2H to VCC Voltage

OUT2L to GND Voltage

Power Dissipation

Vrega

Vregb

Vouth

Voutl

Pd

7

V

7

V

7

V

640^(*1)

-40 to +85

-55 to +125

+125

mW

℃

Operating Temperature Range

Storage Temperature Range

Junction Temperature

Topr

Tstg

Tjmax

(*1) Without heat sink, reduce to 6.4mW when Ta=25℃ or above

Pd is 850mW mounted on 70x70x1.6mm, and reduce to 8.5mW/℃ above 25℃.

●Recommended operating conditions (Ta=-25 to +75℃)

Ratings

Parameter

Symbol

Unit

Min.

6.0

30

Typ.

-

Max.

30.0

300

56

Supply Voltage

VCC

fosc

RT

V

Oscillating Frequency

Timing Resistance

Timing Capacitance

100

27

kHz

kΩ

pF

10

CT

100

470

4700

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Technical Note

BD9775FV

●Electrical characteristics (Ta=25℃, VCC=13.2V, fosc=100kHz, CTL1=3V, CTL2=3V)

Limits

Parameter

Symbol

Unit

Condition

Min.

Typ.

Max.

【Whole Device】

Stand-by Current

Iccst

Icc

－

5

7

µA

CTL1,CTL2=0V

Circuit Current

2.5

4.2

mA

FB1,FB2=0V

【Reference Voltage】

VREF Output Voltage

Vref

DVli

DVlo

Ios

2.97

－

3.00

－

3.03

10

V

Io=-1mA

Line Regulation

Load Regulation

mV

mA

Vcc=7 to 18V,Io=-1mA

Io=-0.1mA to -2mA

－

10

Short Output Current

-60

-22

-5

【Internal Voltage Regulator】

VREGA Output Voltage

Vrega

Vregb

4.5

5.0

5.5

V

Switching with COUT=5000pF

VREGB to GND Voltage

VREGB Output Voltage

VCC-5.5 VCC-5.0 VCC-4.5

VREGB Dropout Voltage

【Oscillator】

Vdregb

－

1.8

2.2

Oscillating Frequency

fosc

90

100

110

2

kHz

%

RT=27kΩ,CT=470pF

Frequency Tolerance

Dfosc

－

Vcc=7 to 18V

【Synchronized Frequency】

Synchronized Frequency

fosc2

Vthfin

IFIN

－

1.2

-1

120

1.4

－

1.6

1

kHz

V

FIN=120kHz

VFIN=1.4V

FIN Threshold Voltage

FIN Input Current

【Error Amplifier】

Threshold Voltage

µA

Vthea

Ibias

Av

0.98

-1

1.00

－

1.02

1

V

INV Input Bias Current

Voltage Gain

µA

dB

－

70

2.0

2.4

－

DC

Band Width

Bw

－

MHz Av=0dB

Maximum Output Voltage

Minimum Output Voltage

Output Sink Current

Vfbh

Vfbl

Isink

2.2

－

2.6

0.1

5.2

V

INV=0.5V

INV=1.5V

0.5

2

mA

FB1,2 Terminal

Isource1

Isource2

-170

-200

-110

-130

-70

-85

µA

FB1 Terminal

FB2 Terminal

Output Source Current

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Technical Note

BD9775FV

Limits

Typ.

Parameter

Symbol

Unit

Condition

Min.

Max.

【PWM Comparator】

Threshold Voltage at 0%

Vth0

Vth100

Idtc

0.88

1.88

-1

0.98

1.98

－

1.08

2.08

1

V

FB Voltage

Threshold Voltage at 100%

DTC Input Bias Current

【FET Driver】

µA

Sink Current

Isink

20

36

58

mA

VDS=0.4V

Source Current

ON Resistance

Isource

-510

-320

-180

RonN

RonP

7.0

0.7

11.0

1.4

17.8

2.2

Ω

OUT1,2H,2L : L

OUT1,2H,2L : H

Rise Time

Fall Time

Tr

Tf

－

20

100

45

－

nsec Switching with COUT=5000pF

Driver’s Duty Cycle of

Synchronous Rectification

RSYNC=30KΩ,

50% of main driver’s duty cycle

ΔDuty

Vsync

42

48

%

SYNC Terminal Voltage

1.45

1.55

1.65

V

Rsync=30KΩ,FB=1.5V

【Over Current Protection (OCP)】

RCL=21kΩ, the output turn off

after detected 8 cycle

VS Threshold Voltage

VS Input Current

Vths

V

VCC-0.24 VCC-0.21 VCC-0.18

IVSH

IVSL

-1

－

1

µA

VS1,VS2=PBU

VS1,VS2=0V

CL Input Current

【Stand-by】

Icl

9

10

11

µA

Threshold Voltage

Vctl

Ictl

1.0

6

1.5

15

2.0

30

V

CL Input Current

µA

CTL1,CTL2=3V

【Short Circuit Protection (SCP)】

Timer Start Voltage

Vtime

0.6

1.92

－

0.7

2.00

10

0.8

2.08

100

-1.5

V

INV Voltage

SCP Voltage

SCP=1.0V

Threshold Voltage

Stand-by Voltage

Source current

Vthscp

Vstscp

Isoscp

mV

µA

-4.0

-2.5

【Under Voltage Lock Out (UVLO)】

Threshold Voltage

Vuvlo

DVuvlo

5.6

5.7

0.1

5.8

V

Vcc sweep down

Hysteresis Voltage Range

0.05

0.15

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Technical Note

BD9775FV

●Pin Description

●Pin No. / Pin Name

Pin Pin

No. Name

Description

Error amplifier output pin(Channel 1)

1

2

3

28

27

26

FB1

VS1

CL1

1

2

FB1

INV1

RT

CT

Fin

PVCC1

OUT1

INV1 Error amplifier negative input pin(Channel 1)

4

5

25

24

Oscillator frequency adjustment pin

connected resistor

3

RT

VREGB

Oscillator frequency adjustment pin

connected capacitor

6

7

23

22

GND

OUT2H

PVCC2

CL2

4

CT

VREF

5

FIN

Oscillator synchronization pulse signal input pin

8

9

21

20

DTC1

DTC2

INV2

6

GND Low-noise ground

VS2

10

11

12

19

18

SCP

7

VREF Reference voltage output pin

FB 2

VREGA

OUT2L

Maximum duty and soft start adjustment pin

(Channel 1)

8

DTC1

CTL1

CTL2

VCC

17

16

Maximum duty and soft start adjustment pin

(Channel 2)

13

14

PGND

SYNC

9

DTC2

15

10

11

12

13

14

15

16

INV2 Error amplifier negative input pin(Channel 2)

Fig.1 Pin Description

FB2

Error amplifier output pin(Channel 2)

CTL1 Enable/stand-by control input(Channel 1)

CTL2 Enable/stand-by control input(Channel 2)

VCC Main power supply pin

●Block Diagram

SYNC Synchronous rectification timing adjustable pin

Power ground

(connected low-side gate driver and digital ground)

PGND

Low-side ( synchronous rectifier ) gate driver

output pin(Channel 2)

17 OUT2L

18 VREGA Connected capacitor for internal regulator

Delay time of short circuit protection adjustment

pin connected capacitor

19

20

21

SCP

VS2

CL2

Over current detection voltage monitor pin

(connected FET drain, Channel 2)

Over current detection voltage adjustment pin

connected capacitor and resistor(Channel 2)

High-side gate driver power supply input

(Channel 2)

22 PVCC2

23 OUT2H High-side gate driver output pin(Channel 2)

24 VREGB Connected capacitor for internal regulator

Fig.2 Block Diagram

25

OUT1 High-side gate driver output pin(Channel 1)

High-side gate driver power supply input

26 PVCC1

(Channel 1)

Over current detection voltage adjustment pin

connected capacitor and resistor(Channel 1)

27

28

CL1

VS1

Over current detection voltage monitor pin

(connected FET drain, Channel 1)

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Technical Note

BD9775FV

●Function Explanation

1. DC/DC Converter

・Reference Voltage

Stable voltage of compensated temperature, is generated from the power supply voltage (VCC). The reference voltage

is 3.0V, the accuracy is ±1%. Place a capacitor with low ESR (several decades mΩ) between VREF and GND.

・Internal Regulator A (VREGA)

5V is generated the power supply voltage. The voltage is for the driver of the synchronous rectification’s MOSFET.

Place a capacitor with low ESR (several decades mΩ) between VREGA and PGND.

・Internal regulator B (VREGB)

(VCC-5V) is generated from the power supply voltage. The voltage is for the driver of the main MOSFET switch.

Place a capacitor with low ESR (several decades mΩ) between VREGB and PVCC.

・Oscillator

Placing a resistor and a capacitor to RT and CT, respectively, generates two triangle waves for both cannels, and each

wave is opposite phase. The waves are input to the PWM comparators for CH1 and CH2. Also, the oscillating

frequency can be slightly adjusted (less than 20%) by putting external clock pulse into Fin pin, which is higher frequency

than the fixed one.

・Error Amplifier

It amplifies the difference, between the establish output voltage and the actual output one detected at INV. And amplified

voltage comes out from FB. The comparing voltage is 1.0V and the accuracy is ±2%. The phase can be

compensated externally by placing a resistor and a capacitor between INV and FB.

・PWM Comparator

It converts the output voltage from error amplifier into PWM waveform, then output to MOSFET driver.

・MOSFET Driver

The main drivers (OUT1, OUT2H) are for P-channel MOSFETs, and the driver (OUT2L) for synchronous rectification is

for N-channel MOSFET. The values of output voltage are clamp to VREGB, VREGA, respectively. All drivers’ output

configurations are push-pull type. In addition, the output current capability is 36mA for the sink current and 320mA

(Vds=0.4V) for the source current.

2. Channel Control

Each output can be individually turned on or off with CTL1 and CTL2. When the CTL is “H” (more than 1.5V), it becomes

turned on.

3. Protection

・Over Current Protection(OCP)

When detected over current (detecting drop voltage of the main MOSFET’s ON resistance), the MOSFET switch

becomes turned off, and the energy on DTC pin is discharged. After discharged, the output restarts automatically.

The level of the OCP detection threshold can be set by the resistance, which is connected between VCC and CL.

・Short Circuit Protection(SCP)

When either output goes down and the voltage on INV pin gets lower than 0.7V, a capacitor placed on SCP is started to

charge.

When the SCP pin becomes more than 2.0V, the main MOSFET switches of both outputs are turned off; then, the

outputs are latched. While they are latched, the IC can be reset by restarting VCC or CTL, or discharging SCP.

・Under Voltage Lock Out(UVLO)

Due to avoiding malfunctions when the IC is started up or the power supply voltage is rapidly disconnected, the main

MOSFET switches become off and DTC is discharged when the supply voltage is less than 5.7V. Also, when the

output is latched because of SCP function, the latch becomes reset. Due to preventing malfunctions in the case the

power supply voltage fluctuate at near UVLO threshold, there is 0.1V hysteresis between the detection and reset

voltage of UVLO threshold.

・Thermal Shut Down(TSD)

Due to preventing breakdown of the IC by heating up, the main MOSFET switches become off and DTC pin is

discharged by detecting over temperature of the chip. Due to preventing malfunctions in the case temperature fluctuate

at near TSD threshold, there is hysteresis between TSD on and off.

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Technical Note

BD9775FV

●Setting Up Information

1)Simultaneously OFF Duty of MOSFETs for Synchronous Rectification

The simultaneously OFF duty of both main MOSFET switch and synchronous rectification MOSFET is determined by

resistance (Rsync) between SYNC and GND. See Fig.3. In Synchronous Rectification, insert RFB2-GND (RFB2-GND≒3

×Rsync) between FB2 and GND, because it is possible to reduce overshoot(see Fig.3). RFB2-GND decides following

formula.

40

T=-40℃

35

T= 25℃

30

T=105℃

25

t

20

t1

t2

15

10

5

OUT2H

OUT2L

0

20

40

60

80

100

Rsync (kΩ)

Fig.3

・Resistance at FB2-GND setup condition

Threshold Voltage at100%

Vsync

< 3xRsync(MIN)

R_FB2-GND

<

-Output Source Current at FB2

3×Rsync(MAX)

2.08

< 3xRsync(MIN)

<

R_FB2-GND

0.4908

+80.7x10^-6

Rsync(MAX)

※Rsync(MAX)…MAX dispersion range at Rsync

Rsync(MIN)…MIN dispersion range at Rsync

FB2

SYNC

Rsync

R_FB2-GND

Short SYNC to VREF if the synchronous rectification function is not needed.

VREF

SYNC

Without Synchronous Rectification(Don’t insert R_FB2-GND

)

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Technical Note

BD9775FV

2)Oscillator Synchronization by External Pulse Signal

At the operation the oscillator is externally synchronized, input the synchronization signal into Fin in addition to connect a

resistor and a capacitor at RT and CT, respectively. Input the external clock pulse on Fin, which is higher frequency than

the fixed one. However, the frequency variation should be less than 20%. Also, the duty cycle of the pulse should be set

from 10% to 90%.

Fin

： Fixed with RT and CT

CT

： Synchronized

Fig.4 CT Waveform during Synchronized with External Pulse

Short Fin to GND if the function of external synchronization is not needed.

Fin

Fig.5 Without Synchronization Signal

3)Setting the Over Current Threshold Level

The OCP detection level (Iocp) is determined by the ON resistance (R_ON) of the main MOSFET switch and the resistance

(Rcl) which is placed between CL and VCC.

Rcl

Iocp

=

×10^-5[A] (typ.)

R_ON

To prevent a malfunction caused by noise, place a capacitor (Ccl) parallel to Rcl.

If OCP function is not needed, short VS to VCC, and short CL to GND.

VCC

Rcl

CL

Ccl

VCC

VS

To Main MOSFET Drain

With OCP

Without OCP

Fig.6 CL, VS Pin Connection

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Technical Note

BD9775FV

4)Setting the Time for Short Circuit Protection

The time (tscp) from output short to latch activation is determined by the capacitor, Cscp, connected SCP pin.

tscp=7.96×10⁵×Cscp

[sec]

(typ.)

Short SCP to GND if SCP function is not being used.

SCP

Fig.7 Without SCP

5)Single Channel Operation

This device can be used as a single output. The connection is as follows;

DTC, FB, CTL, CL

VS, PVCC

INV

Short to GND

Short to VCC

Short to VREF

DTC

FB

CTL

CL

VCC

VS

PVCC

VREF

INV

Fig.8 Single Channel Operation

6)Setting the Oscillating Frequency

The oscillating frequency can be set by selecting the timing resistor (RRT) and the timing capacitor (CCT).

1000

100

10

1000

CCT=100pF

RRT=5.1kΩ

CCT=470pF

100

RRT=27kΩ

RRT=100kΩ

CCT=1000pF

10

100

1000

10000

10

100

1000

Timing Resistance (kΩ)

Timing Capacitance(pF)

Fig.9 Oscillating Frequency vs. Timing Capacitance (CCT)

Fig.10 Oscillating Frequency vs. Timing Capacitance (RRT)

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Technical Note

BD9775FV

●Timing Chart

・Output ON/OFF, Minimum Input(UVLO)

VCC

6.0V

UVLO is inactivated

at 5.8V

UVLO is activated at 5.7V

CTL1

DTC1

1.0V

Vout1

CTL2

DTC2

Vout2

1.0V

Stand-by

Soft start

Fig.11

・Over Current Protection, Short Circuit Protection, Thermal Shut Down

CTL1,2

Activate SCP

2.0V

Reset the latch by restarting CTL

SCP

DTC1,2

0.7×fixed output voltage

Activate TSD

Inactivate TSD

1.0V

Vout1,2

Half short of output

OCP detection level

Iout1,2

Inactivate half-short

OCP is activated by detecting 8 consecutive cycles

Fig.12

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Technical Note

BD9775FV

●I/O Equivalent Circuit

FB1(1)

FB2(11)

RT(3)

VREF

VREGA VCC

VCC

VREF

VREGA

VREF

FB1

RT

INV1(2),INV2(10)

CT(4)

FIN(5)

VREF

VCC

VREG

VREF

A

INV1,2

FIN

CTL1(12),CTL2(13)

DTC1(8),DTC2(9)

SYNC(15)

VREGA

VREF

VCC

VREF

VREGA

VCC

DTC1,2

CTL1,2

SYNC

SCP(19)

VREF

OUT2L(17),VREGA(18)

VCC

VREF(7)

VCC

VREGA

OUT2L

VREF

SCP

PVCC1(26),PVCC2(22)

OUT1(25),OUT2H(23),VREGB(24)

VS1(28),VS2(20),CL1(27),CL2(21)

VCC

PVCC1,2

OUT1,2H

VREGB

CL1,2

VS1,2

Fig.13

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2011.05 - Rev.A

Technical Note

BD9775FV

●Notes for use

1) Absolute maximum ratings

Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may

result in IC deterioration or damage. Assumptions should not be made regarding the state of the IC (short mode or open

mode) when such damage is suffered. A physical safety measure such as a fuse should be implemented when use of

the IC in a special mode where the absolute maximum ratings may be exceeded is anticipated.

2) GND potential

Ensure a minimum GND pin potential in all operating conditions. In addition, ensure that no pins other than the GND pin

carry a voltage lower than or equal to the GND pin, including during actual transient phenomena.

3) Thermal design

Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating

conditions.

4) Inter-pin shorts and mounting errors

Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result

in damage to the IC. Shorts between output pins or between output pins and the power supply and GND pin caused by

the presence of a foreign object may result in damage to the IC.

5) Operation in a strong electromagnetic field

Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to

malfunction.

6) Thermal shutdown circuit (TSD circuit)

This IC incorporates a built-in thermal shutdown circuit (TSD circuit). The TSD circuit is designed only to shut the IC off

to prevent runaway thermal operation. Do not continue to use the IC after operating this circuit or use the IC in an

environment where the operation of the thermal shutdown circuit is assumed.

7) Testing on application boards

When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to

stress. Always discharge capacitors after each process or step. Ground the IC during assembly steps as an antistatic

measure, and use similar caution when transporting or storing the IC. Always turn the IC's power supply off before

connecting it to or removing it from a jig or fixture during the inspection process.

8) Common impedance

Power supply and ground wiring should reflect consideration of the need to lower common impedance and minimize

ripple as much as possible (by making wiring as short and thick as possible or rejecting ripple by incorporating

inductance and capacitance).

9) Applications with modes that reverse VCC and pin potentials may cause damage to internal IC circuits.

For example, such damage might occur when VCC is shorted with the GND pin while an external capacitor is charged.

It is recommended to insert a diode for preventing back current flow in series with VCC or bypass diodes between VCC

and each pin.

Bypass diode

Countercurrent

prevention diode

Vcc

Fig.14

10) Timing resistor and capacitor

Timing resistor (capacitor) connected between RT (CT) and GND, has to be placed near RT (CT) terminal 3pin (4pin).

And pattern has to be short enough.

11) The Dead time input voltage has to be set more than 1.1V.

Also, the resistance between DTC and VREF is used more than 30kΩ to work OCP function reliably.

12) The energy on DTC1(8pin)and DTC2(9pin)is discharged when CTL1(12pin)and CTL2(13pin)are OFF, respectively, or

VCC(14pin)is OFF (UVLO activation). However, it is considerable to occur overshoot when CTL and VCC are turned

on with remaining more than 1V on the DTC.

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Technical Note

BD9775FV

13) If Gate capacitance of P-channel MOSFET or resistance placed on

Gate is large, and the time from beginning of Gate switching to the end of Drain’s (tsw), is long, it may not start up due to

the OCP malfunction. To avoid it, select MOSFET or adjust resistance as tsw becomes less than 270nsec.

tsw

GATE

DRAIN

Fig.15

14) IC pin input

This monolithic IC contains P+ isolation and PCB layers between adjacent elements in order to keep them isolated.

P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety of

parasitic elements. For example, when a resistor and transistor are connected to pins as shown in following chart,

○the P/N junction functions as a parasitic diode when GND > (Pin A) for the resistor or GND > (Pin B) for the

transistor (NPN).

○Similarly, when GND > (Pin B) for the transistor (NPN), the parasitic diode described above combines with the N

layer of other adjacent elements to operate as a parasitic NPN transistor.

The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable result

of the IC's architecture. The operation of parasitic elements can cause interference with circuit operation as well as IC

malfunction and damage. For these reasons, it is necessary to use caution so that the IC is not used in a way that will

trigger the operation of parasitic elements, such as by the application of voltages lower than the GND (PCB) voltage to

input and output pins.

Resistor

Transistor (NPN)

(PINA)

(PINB)

B

E

C

(PINB)

(PINA)

C

E

B

P

P⁺

N

P

N

GND

Parasitic element

GND

P substrate

GND

Parasitic element

Parasitic element or transistor

Fig.16

Parasitic element or transistor

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Technical Note

BD9775FV

●Thermal Derating Curve

1.0

0.85

0.64

②

①

0.8

0.6

0.4

0.2

0.0

①With no heat sink

②Copper laminate area 70 mm×70mm

0

25

50

75

100

125

150

Ambient Temperature: Ta(

)

℃

Fig.17

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Technical Note

BD9775FV

●Ordering part number

B

D

9

7

5

F

V

-

E

2

Part No.

Package

FV: SSOP-B28

Packaging and forming specification

E2: Embossed tape and reel

SSOP-B28

10 0.2

(MAX 10.35 include BURR)

Tape

Embossed carrier tape

2000pcs

28

15

Quantity

E2

Direction

of feed

The direction is the 1pin of product is at the upper left when you hold

reel on the left hand and you pull out the tape on the right hand

(

)

1

14

0.15 0.1

0.1

0.65

0.22 0.1

Direction of feed

1pin

Reel

(Unit : mm)

Order quantity needs to be multiple of the minimum quantity.

∗

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Notice

N o t e s

No copying or reproduction of this document, in part or in whole, is permitted without the

consent of ROHM Co.,Ltd.

The content speciﬁed herein is subject to change for improvement without notice.

The content speciﬁed herein is for the purpose of introducing ROHM's products (hereinafter

"Products"). If you wish to use any such Product, please be sure to refer to the speciﬁcations,

which can be obtained from ROHM upon request.

Examples of application circuits, circuit constants and any other information contained herein

illustrate the standard usage and operations of the Products. The peripheral conditions must

be taken into account when designing circuits for mass production.

Great care was taken in ensuring the accuracy of the information speciﬁed in this document.

However, should you incur any damage arising from any inaccuracy or misprint of such

information, ROHM shall bear no responsibility for such damage.

The technical information speciﬁed herein is intended only to show the typical functions of and

examples of application circuits for the Products. ROHM does not grant you, explicitly or

implicitly, any license to use or exercise intellectual property or other rights held by ROHM and

other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the

use of such technical information.

The Products speciﬁed in this document are intended to be used with general-use electronic

equipment or devices (such as audio visual equipment, ofﬁce-automation equipment, commu-

nication devices, electronic appliances and amusement devices).

The Products speciﬁed in this document are not designed to be radiation tolerant.

While ROHM always makes efforts to enhance the quality and reliability of its Products, a

Product may fail or malfunction for a variety of reasons.

Please be sure to implement in your equipment using the Products safety measures to guard

against the possibility of physical injury, ﬁre or any other damage caused in the event of the

failure of any Product, such as derating, redundancy, ﬁre control and fail-safe designs. ROHM

shall bear no responsibility whatsoever for your use of any Product outside of the prescribed

scope or not in accordance with the instruction manual.

The Products are not designed or manufactured to be used with any equipment, device or

system which requires an extremely high level of reliability the failure or malfunction of which

may result in a direct threat to human life or create a risk of human injury (such as a medical

instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-

controller or other safety device). ROHM shall bear no responsibility in any way for use of any

of the Products for the above special purposes. If a Product is intended to be used for any

such special purpose, please contact a ROHM sales representative before purchasing.

If you intend to export or ship overseas any Product or technology speciﬁed herein that may

be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to

obtain a license or permit under the Law.

Thank you for your accessing to ROHM product informations.

More detail product informations and catalogs are available, please contact us.

ROHM Customer Support System

http://www.rohm.com/contact/

www.rohm.com

R1120

A


型号：	BD9775FV_11
厂家：	ROHM
描述：	High Efficiency Step-down Switching Regulator Controller 高效率降压型开关稳压器控制器稳压器开关控制器
文件：	总15页 (文件大小：417K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BD9775FV_11 [ROHM]

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