BD9738KN-E2_技术文档

TECHNICAL NOTE

For Digital Still Cameras

FET Built-in Type System Switching

Regulator ICs

BD9734KN, BD9738KN, BD9739KN, BD9740KN

zDescription

These 7-channel switching regulators include built-in FETs and are designed for use in digital still cameras. They feature

built-in power FETs and soft start functionality, reducing the number of external components.

zFeatures

1) Wide supply voltage range: 1.5 V to 11 V (BD9738KN)

1.5 V to 10 V (BD9739KN, BD9740KN)

2) High-precision reference voltage: ± 1%

3) Built-in circuit to shut off output during an overload (timer-latch type)

4) Capable of oscillating frequency externally.

5) Built-in thermal shutdown circuit

6) Standby mode current: 0 µA

7) Built-in positive and negative regulators for CCD use (BD9734KN, BD9738KN)

8) Built-in load switch circuit

9) Step-up/step-down switchable

10) Support for an inversion system that can output negative voltage (BD9739KN, BD9740KN)

11) Support for constant-current LED drive for use in backlights (BD9734KN, BD9738KN, BD9739KN)

12) Includes synchronous rectification-compatible channel

zApplications

Digital still cameras, portable DVD players, digital video cameras

zProduct line-up

Parameter

Input voltage

Reference voltage

precision

BD9734KN

2.5 V to 8 V

BD9738KN

1.5 V to 11 V

BD9739KN

1.5 V to 10 V

BD9740KN

1.5 V to 10 V

1 V ± 1%

Operating

frequency range

Step-up

100 k to 1.2 MHz 100 k to 1.2 MHz 100 k to 1.2 MHz 100 k to 1.2 MHz

3CH

1CH

3CH

1CH

3CH

2CH

1CH

Step-down

Step-up/step-down

switchable

3CH

1CH

3CH

Inversion

—

4CH

—

4CH

1CH

3CH

1CH

Built-in FET

Synchronous

rectification

4CH

3CH

2CH

Load switching

2CH

3CH

—

Operating

temperature range

Package

-20°C to +85°C

QFN84U

-20°C to +85°C

QFN84U

-20°C to +85°C

QFN64U

-20°C to +85°C

QFN48U

Apr. 2005

zAbsolute maximum ratings

Range

BD9739KN

Parameter

Symbol

Unit

BD9734KN

-0.3 to +8.5

-0.3 to +15

-0.3 to +8.5

-0.3 to +20

-0.3 to +17

-0.3 to +20

-12 to +0.3

-0.3 to +12

BD9738KN

-0.3 to +12

-0.3 to +15

-0.3 to +20

-12 to +0.3

-0.3 to +12

BD9740KN

-0.3 to +12

-0.3 to +15

-0.3 to +12

-0.3 to +20

—

Maximum supply

voltage

VBAT, VCC, PVCC

PVCCH, PVCCL

DRAIN*H, DRAIN*L

OUT1B

-0.3 to +12

-0.3 to +15

-0.3 to +12

-0.3 to +20

-0.3 to +17

—

V

OUT2B

VIN+

VIN-

—

SWOUT1, 4, PGIN1,

PG2, 3

-0.3 to +12

SWIN^*

-0.3 to +20

QFN64U

550 ^*1-2

—

V

mW

Power dissipation Pd

QFN84U

QFN48U

500 ^*1-3

760 ^*2-3

610 ^*1-1

1200 ^*2-1

1000 ^*2-2

Operating

temperature

range

Storage

temperature

range

Topr

-25 to +85

°C

Tstg

-55 to +125

+125

Junction

Tjmax

temperature

*1: IC without heat sink operation. Reduced 6.1 mW/°C (1-1), 5.5 mW/°C (1-2), or 5.0 mW/°C (1-3) when Ta ≥ 25°C.

*2: When mounted on a PCB (70 mm ×70 mm ×1.6 mm [thickness], glass epoxy).

Reduced 12.0 mW/°C (2-1), 10.0 mW/°C (2-2), or 7.6 mW/°C (2-3) when Ta ≥ 25°C.

zRecommended Operating Ranges

Range

Parameter

Symbol

Unit

BD9734KN

2.5 to 8

BD9738KN

1.5 to 10

4.0 to 14

BD9739KN

1.5 to 10

4.0 to 14

BD9740KN

1.5 to 10

2.8 to 10

4.0 to 14

Supply voltage

VBAT

V

VCC, PVCC

PVCCL, PVCCH

2.5 to 8

4.0 to 14

Range

Typ.

Parameter

Symbol

fOSC

Unit

Conditions

Min.

0.1

Max.

[Oscillator]

Oscillating frequency

[Driver block]

—

1.2

MHz

8

10

(BD9734KN)

DRAIN pin input voltage

VDRAIN

IOFET1

IOFET2

—

V

N-channel FET output current

(step-down)

N-channel FET output current

(step-up)

700

300

mA

LED channel output current

Driver output current

Driver peak current

Startup NPN TR sink current

[Positive/negative regulators]

VIN+ pin input voltage

VIN- pin input voltage

Positive voltage REG output

current

IOLED

IOUT

IPEAK

—

40

30

200

500

mA

External FET drive circuit

INPNSINK

VVIN1

VVIN2

—

-10

—

18

—

V

IOREG1

IOREG2

—

50

mA

Negative voltage REG output

current

[SW circuit ]

SWOUT1 pin sink current

PGOUT1 pin source current

PG23 pin sink current

ISWOUT1

IPGOUT1

IPG23

—

10

100

1

mA

1

(BD9734KN, BD9738KN)

(BD9739KN)

SWOUT4 pin source current

ISWOUT4

50

SWOUT6 pin source current

SWOUT7 pin source current

ISWOUT6

ISWOUT7

2/16

zElectrical Characteristics (Unless otherwise specified, Ta = 25°C, VBAT = 3 V, VCC = 5 V, RT = 11 kohm, CT = 180 pF, STB1 to

STB7 = 3 V)

Parameter

[Reference voltage, reference voltage for inversion]

Range

Typ.

Symbol

Unit

Conditions

Min.

Max.

Output voltage

Line regulation

Load regulation

Output current when shorted

[Internal regulator]

VREF2

DVLI

DVLO

IOS

0.99

—

1.0

4.0

1.0

1

1.01

12.5

7.5

V

mV

mA

VCC = 3.0 V to 9.5 V

IREF = 10 µA to 100 µA

VREF = 0 V

0.2

—

Output voltage REGA

[Under voltage lockout circuit]

Detection threshold voltage 1

Hysteresis width 1

Detection threshold voltage 2

Hysteresis width 2

VREGA

2.4

2.5

2.6

V

IREG = 1 mA

VSTD1

∆VST1

VSTD2

∆VST2

VSTD3

∆VST3

3.45

—

2.3

—

3.6

300

2.4

200

2.0

50

3.75

—

2.5

—

V

mV

V

mV

V

PVCCL monitor

VCC monitor

VREGA monitor

Detection threshold voltage 3

Hysteresis width 3

mV

[Startup circuit block]

Oscillating frequency

fSTART

VST1

ISS1

50

2.5

1.5

1.1

120

—

220

—

kHz

V

(BD9734KN)

VBAT pin monitor

VSS1 = 0 V

Operation start VBAT voltage

Soft start charge current

[Short protection circuit ]

Timer threshold voltage

2.2

3.3

µA

VTC

2.1

0.5

2

2.2

1.0

4

2.3

1.5

6

V

FB pin monitor

VSCP = 0.1 V

(BD9740KN)

SCP pin source current

ISCP

µA

0.45

0.9

—

0.50

1.0

22

0.55

1.1

170

SCP pin detection voltage

VTSC

VSSC

V

(BD9740KN)

SCP pin standby voltage

[Triangular waveform oscillator]

Oscillating frequency

Frequency stability

mV

fOSC1

Df

450

—

500

0.3

550

2

kHz

%

RT = 11 kΩ, CT = 180 pF

VCC = 3.0 V to 9.5 V

RT pin voltage

VRT

0.78

1.00

1.22

V

[Soft start 23 block] (BD9738KN, BD9739KN)

Soft start charge current

[Error amp]

ISS23

5

10

15

VSS23 = 0 V

µA

Low level output voltage

High level output voltage

Output sink current

Output source current

DTC pin upper resistance

DTC pin lower resistance

NON pin input range

Non-inverted pin reference

voltage

VOL

VOH

IOI

—

VREGA-0.3

36

1.3

—

V

INV = 2 V

INV = 0 V

FB = 1.7 V, VINV = 1.1 V

FB = 1.7 V, VINV = 0.9 V

(BD9740KN)

72

30

95

—

µA

kΩ

V

IOO

36

20

65

-0.3

—

RDTCU

RDTCD

IRES

40

125

1.5

(BD9740KN)

VNON7

—

0.2

—

V

[PWM comparator]

VT0

VT100

DMAX1

—

77

1.49

1.95

85

—

93

V

%

0% duty

100% duty

VINV = 0.9 V, VSCP = 0 V

Input threshold voltage

MAX DUTY

VINV = 0.9 V,

VSCP, UDSEL = 0 V

MAX DUTY (step-up operation)

DMAX2

77

85

93

%

This IC is not designed to be radiation-resistant.

3/16

(Unless otherwise specified, Ta = 25°C, VBAT = 3 V, VCC= 5 V, RT = 11 kohm, CT = 180 pF, STB1 to STB7 = 3 V)

Range

Parameter

[Output circuit]

Symbol

Unit

Conditions

Min.

Typ.

Max.

VCC

-1.6

—

VCC

-0.8

0.8

High level output voltage

Low level output voltage

VSATH

VSATL

—

V

IO = 30 mA

1.6

IO = -30 mA

PVCCH = 5 V

(IO = 200 mA)

(BD9740KN)

PVCCL = 5 V

(IO = 200 mA)

(BD9740KN)

PVCCL = 5 V

(IO = 50 mA)

High-side N-channel FET on

resistance

—

270

300

270

300

0.7

500

1.4

RONH

mΩ

Low-side N-channel FET on

resistance

RONL

mΩ

CH7 N-channel FET on

resistance

RONL7

Ω

[Step-up/step-down selector ]

UDSEL pin

control voltage

Step-down

Step-up

VUDDO

VUDUP

VCC × 0.7

0

—

VCC

VCC × 0.3

V

[POWERGOOD ] (POWERGOOD1) (BD9734KN, BD9738KN)

POWERGOOD1 detection

voltage

Detection voltage low

→ high

VTHPG1

∆VTHPG1

VSAT

0.63

0.7

0.77

300

—

V

mV

V

Hysteresis width

100

VPG1IN

-0.3

—

200

VPG1IN

-0.1

0

Output voltage

Leak current

Discharge resistance

IO = 80 mA, VPG1IN = 5 V

STB1 = 0 V

PG1

ILEAK

RDIS

5

330

µA

Ω

82

165

[POWERGOOD] (POWERGOOD23) (BD9734KN)

POWERGOOD23 detection

voltage

Hysteresis width

Detection voltage low

→ high

VTHPG23

0.72

100

1.8

0.8

200

2.0

200

0.1

0.88

300

2.2

V

mV

V

∆VTHPG23

VTHDE

Detection voltage low

→ high

DELAY pin detection voltage

Hysteresis width

∆VTHDE

VSAT

100

—

300

0.3

mV

V

IO = 100 µA,

VINV3 = 1.1 V

Output voltage

PG23

Leak current

Output voltage

ILEAK

VSATD

—

0

0.1

5

0.3

µA

V

STB23 = 0 V

IO = 100 µA, INV3 = 0 V

DELAY

[Positive/negative regulators] (BD9734KN, BD9738KN)

Soft start charge current

ISS2

VTHON

VTHOFF

1.0

2.0

-0.3

2.0

—

3.0

11

0.3

µA

V

VSS2 = 0 V

REG_ON pin

ON

OFF

control voltage

Control pin

pull-down resistance

RCONT

250

400

700

kΩ

REG1

(VIN+ = 16 V, R1A = 700 kΩ, R1B = 50 kΩ)

VREF

-0.05

—

VREF

+0.05

—

Feedback voltage 1

VNF1

VREF

V

Output voltage1

VO1

IMAX1

ISCP1

∆V1

15

50

80

10

V

IO = 10 mA

Max. output current 1

Output short current 1

I/O differential voltage 1

Load stability 1

mA

mV

VO = 0 V

—

160

50

VIN+ = 14 V, IO = 10 mA

IO = 0.1 mA to 10 mA

f = 120 Hz,

∆VOL1

Ripple rejection 1

RR1

—

40

—

dB

VRR = -20 dBV, IO = 1 mA

Discharge resistance 1

RDIS1

103

207

414

Ω

REG2

(VIN- = -8.5 V, R2A = 100 kΩ, R2B = 50 kΩ)

Feedback voltage 2

Output voltage 2

Max. output current 2

I/O differential voltage 2

Load stability 2

VNF2

VO2

IMAX2

∆V2

-0.05

—

0

-7.5

80

50

10

0.05

—

100

50

V

mA

mV

IO = 10 mA

VIN- = -6.5 V, IO = 10 mA

IO = 0.1 mA to 10 mA

f = 120 Hz,

∆VOL2

Ripple rejection 2

RR2

—

50

—

dB

VRR = -20 dBV, IO = 1 mA

Discharge resistance 2

RDIS2

55

110

220

Ω

This IC is not designed to be radiation-resistant.

4/16

(Unless otherwise specified, Ta = 25°C, VBAT = 3 V, VCC = 5 V, RT = 11 kohm, CT = 180 pF, STB1 to STB7 = 3 V)

Range

Parameter

Symbol

Unit

Conditions

Min.

Typ.

Max.

[Power on switching block] (BD9734KN, BD9738KN, BD9739KN)

Output voltage

Leak current

SWOUT4 Output voltage

Leak current

VSAT

ILEAK

VSAT

ILEAK

—

0.1

0

0.1

0.3

5

0.3

5

V

µA

V

IO = 1 mA

SWOUT1

STB = 0 V

IO = 100 µA

STB = 0 V

IO = 20 mA

VSWIN = 5 V

STB = 0 V

IO = 10 mA

VSWIN = 10 V

STB = 0 V

—

0

VSWIN6

-0.1

µA

VSWIN6

-0.3

—

VSWIN7

-0.3

—

SWOUT

4, 6

Output voltage

Leak current

VSAT

ILEAK

VSAT

ILEAK

—

5

V

µA

V

0

VSWIN7

-0.1

SWOUT7 Output voltage

—

5

Leak current

0

µA

[Soft start block] (BD9740KN)

VCC = PVCC = 5 V

PVCCH = 5.0 V

STB 0→3 V

Soft start time of CH4

TSS1

1.8

3.6

6.0

msec

VCC = PVCC = 5 V,

STB = 3 V

INV4 = 0→1.2 V

VCC = PVCC = 5 V

PVCCH = 5.0 V

Soft start time of CH2, 3

TSS2

VPG4

1.8

3.6

6.0

msec

V

CH2, CH3 soft start

INV4 threshold voltage at start

0.72

0.80

0.88

[STB1 to STB7]

ON

STB pin control voltage

OFF

STB pin pull-down resistance

[Circuit current]

VSTBH

VSTBL

RSTB

2.0

-0.3

250

—

400

11

0.3

700

V

kΩ

STB

Standby current 1

(VBAT pin sink current)

Standby current 2

(VCC, PVCC pin sink current)

Circuit current at startup

(VBAT pin sink current)

Circuit current 1

(VBAT pin sink current)

Circuit current 2

ISTB1

ISTB2

IST

—

5

µA

STB1 to STB7 = 0 V

5

CT = 1.7 V

VCC = 0 V

30

100

5

100

300

15

mA

µA

ICC1

ICC2

CT = 1.7 V

INV = 2.5 V

mA

(VCC, PVCC pin sink current)

This IC is not designed to be radiation-resistant.

zPVCCH and PVCCL input voltages

PVCCH

• Synchronous rectification channels with built-in FETs include N-channel FETs for

both the high-side and low-side. The driver block's power source is supplied to the

PVCCL pin for the low-side and the PVCCH pin for the high-side. (For the

BD9740KN, both sides are supplied to the PVCCH pin.)

PVCCL

In order to turn the FET on, a potential of at least 4 V must be supplied to the PVCCL

pin, and a potential of at least (DRAINH pin voltage + 4 V) must be supplied to the

PVCCH pin.

DRAINH

DRAINL

Note:

Vo

• The breakdown voltage for the PVCCL and PVCCH pins is 15 V. For applications

whose architecture allows the possibility of voltages exceeding 15 V, add a zener

diode or other component to provide overvoltage protection.

PGND

• Shorting the DRAINH pin with the ground while a charge remains in the output

capacitor may cause unexpected current flow, resulting in damage to the IC. Add an

external protective diode for applications where this possibility exists.

Fig. 1 Synchronous Rectification

Channel with Built-In FET

5/16

zBlock Diagram and Application Circuit (1) BD9734KN

Connect a capacitor to prevent oscillation to

the VREGA pin. (See page 10.)

Connect

a capacitor to prevent

For more information

about setting the SCP pin,

see page 11.

oscillation to the VREF pin. (See

page 10.)

Apply the PVCCH pin

voltage with an external

charge pump. (See page 5.)

Connect a capacitor for

setting the soft start

time. (See page 11.)

For more information about

POWERGOOD, see page 11.

For more information about

the CCD REG, see page 12.

Connect a resistor if you

wish to reduce the maximum

duty. (See page 12.)

Connect a resistor for

setting the output

voltage. (See page 12.)

Set the operating

frequency with the

RT and CT pins.

(See page 11.)

Set whether CH2, CH4, and

CH5 will be used as step-up or

step-down. (See page 10.)

This pin is used as the

on/off control pin.

(See page 10.)

The soft start times for

CH2 to CH7 are fixed

internally. (See page 12.)

Fig. 2 BD9734KN Application Circuit

6/16

zBlock Diagram and Application Circuit (2) BD9738KN

Connect a capacitor to prevent

to the VREF pin. (See page 10.)

For more information

about setting the SCP pin,

See page 11.

Connect a capacitor to prevent to the

VREGA pin. (See page 10.)

Apply the PVCCH pin

voltage with an external

charge pump. (See page 5.)

Connect a

capacitor for

setting the soft

start time. (See

pages 11& 12.)

For more information about

the CCD REG, see page 12.

Connect a resistor if you

wish to reduce maximum

duty. (See page 12.)

Connect a resistor for

setting the output

voltage. (See page 12.)

Set whether CH2, CH4, and

CH5 will be used as step-up or

step-down. (see page 10).

This pin is used as the

on/off control pin.

(See page 10.)

The soft start times for

CH2 to CH7 are fixed

internally. (See page 12.)

Set the operating

frequency with the RT and

CT pins. (See page 11.)

Fig. 3 BD9738KN Application Circuit

7/16

zBlock Diagram and Application Circuit (3) BD9739KN

Connect a capacitor to prevent

oscillation to the VREF pin. (See

page 10.)

For more information about

setting the SCP pin, see page 11.

Connect a capacitor to prevent

oscillation to the VREGA pin.

(See page 10.)

Apply the PVCCH pin

voltage with an external

charge pump. (See page 5.)

Connect a

Connect

a

for

capacitor for

capacitor

setting the soft

start time. (See

pages 11& 12.)

page 11.)

Connect a

capacitor for soft

start at DTC pin.

(See page 12 )

Connect a resistor

for setting the

output voltage.

(See page 12.)

Set the operating

frequency with the

RT and CT pins.

The soft start times for

CH4, 6, 7 are fixed

internally. (See page 12.)

Set whether CH1 and CH5

This pin is used as the on/off

control pin. (See page 10.)

will be used as step-up,

step-down or inversion.

(See page 10.)

(See page 11.)

Fig. 4 BD9739KN Application Circuit

8/16

zBlock Diagram and Application Circuit (4) BD9740KN

Connect

a

capacitor to prevent

For more information

about setting the SCP pin,

see page 11.

Connect a capacitor to prevent oscillation to

the VREGA pin. (See page 10.)

oscillation to the VREF pin. (See

page 10.)

Connect a

capacitor for

setting the soft

start time. (See

page 11.)

The soft start times for

CH2 to CH4 are fixed

internally. (See page 12.)

Apply the PVCCH pin voltage

with an external charge pump.

(See page 5.)

Connect a

capacitor for soft

start at DTC pin.

(See page 12.)

Connect a resistor

for setting the

output voltage.

(See page 12.)

Set the operating

frequency with the RT and

CT pins. (See page 11.)

This pin is used as the

on/off control pin.

(See page 10.)

Set whether CH1, CH2, and

CH3 will be used as step-up or

step-down. (See page 10.)

Fig. 5 BD9740KN Application Circuit

9/16

zBD9734KN Pin No.

Pin No.

83

84

Pin name

Pin No.

3

8, 9, 10, 11, 19, 20

6, 7, 12, 13, 17, 18

Pin name

OUT1B

DRAIN1, 2, 3H

DRAIN1, 2, 3L

MAIN4

SUB4

VREF

DTC 5, 6

Pin No.

36,57

44

43

42

Pin name

SS1, 2

RT

CT

SCP

SYNC_DTC

UDSEL2, 4, 5

MODE

Pin No.

63

2

67, 81

1

21

Pin name

VINMINUS

PG1IN

SWIN6, 7

PG1OUT

PG23

VBAT1

VBAT2

VCC

39

70

80

79

PVCC

PVCCH

PVCCL

73

71

38

45

78, 77, 76

29

59

60

OUTPLUS

NFPLUS

4, 5, 14, 15, 16, 72 PGND1, 23, 4

64, 65

34, 33, 30, 51,

54, 55, 50

35, 32, 31, 52, 53, 56

48, 49

STB 1, 23, 4, 5,

6, 7

DELAY

REG_ON

VINPLUS

46

GND

FB1 to FB7

22, 23, 24, 25, 26, 27

62

OUTMINUS

40

69, 68

75

VREGA

OUT5,6

OUT7B

INV1 to INV6

INV7I, V

41

28

58

61

NFMINUS

SWOUT 1, 4, 6, 7

37, 74, 66, 82

47

NON7

zBD9738KN Pin No.

Pin No.

83

84

Pin name

Pin No.

Pin name

OUT1B

DRAIN1, 2, 3H

DRAIN1, 2, 3L

MAIN4

SUB4

VREF

DTC 5, 6

Pin No.

47

36, 57

44

43

42

Pin name

NON7

SS1, 2

RT

CT

SCP

SYNC_DTC

UDSEL2, 4, 5

MODE

Pin No.

58

63

2

67, 81

1

59

60

Pin name

VINPLUS

VINMINUS

PG1IN

SWIN6, 7

PG1OUT

VBAT1

VBAT2

VCC

3

8, 9, 10, 11, 19, 20

6, 7, 12, 13, 17, 18

73

39

70

80

79

PVCC

PVCCH

PVCCL

71

38

64, 65

45

OUTPLUS

NFPLUS

4, 5, 14, 15, 16, 72 PGND1, 23, 4

78, 77, 76

29

46

40

69, 68

75

GND

34, 33, 30, 51,

54, 55, 50

35, 32, 31, 52, 53, 56

48, 49

62

OUTMINUS

NFMINUS

SWOUT1, 4, 6, 7

N.C

FB1 to FB7

VREGA

OUT5,6

OUT7B

22, 23, 24, 25, 26, 27 STB1, 23, 4, 5, 6, 7

61

37, 74, 66, 82

21

INV1 to INV6

INV7I, V

41

28

SS23

REG_ON

zBD9739KN Pin No.

Pin No.

Pin name

VBAT

VCC

PVCC

PVCCH

PVCCL

Pin No.

60

4, 5, 12, 13

6, 7, 10, 11

Pin name

OUT1B

DRAIN2, 3H

DRAIN2, 3L

OUT1M

OUT1S

VREF

DTC5

Pin No.

44, 36

28

25

34

33

32

Pin name

NON5, 7

SS1

SS23

RT

61

29

54

14

59

55

56

35

43

CT

SCP

8, 9, 57

42

30

51, 52, 53

58

PGND23, PGND

GND

1, 64

UDSEL1, 5

STB 1, 23, 4, 5, 6, 7

SWIN4, 6, 7

SWOUT1, 4, 6, 7

VREGA

OUT4,5,6

OUT7B

26, 24, 21, 47, 46, 41, 39

27, 23, 22, 48, 45, 40

37, 38

FB1 to FB7

INV1 to INV6

INV7I, INV7V

15, 16, 17, 18, 19, 20

50, 2, 62

31, 49, 3, 63

zBD9740KN Pin No.

Pin No.

Pin name

VBAT

VCC

Pin No.

44

43

Pin name

MAIN2

SUB2

Pin No.

30, 37

17

Pin name

NON6, NON7

SS1

4

21

46

PVCC

5

OUT1B

23

RT

10

42

6, 7

31

22

PVCCH

PGND

PGND4

GND

VREGA

OUT1,3,5,6,7

9

8

20

DRAIN4H

DRAIN4L

VREF

DTC5 to DTC7

FB1 to FB7

INV1 to 5, 7

24

25

1

2

CT

SCP

UDSEL12

UDSEL3

STB1, 234, 56, 7

3, 38, 39

16, 18, 27, 28, 32, 35, 36

15, 19, 26, 29, 33, 34

11, 12, 13, 14

40, 41, 45, 47, 48

zExplanation of block diagram and how to set peripheral IC components

1. Voltage reference (VREF)

VREF is the reference voltage source of 1.0V output voltage.

Connect a capacitor to prevent oscillation. Set the capacitance from 1.0 µF to 10 µF.

2. REGA

REGA and REGD are regulators with output voltages of 2.5 V. REGA is used as the power supply for the IC's internal blocks.

Connect a capacitor to prevent oscillation. Set the capacitance from 4.7 µ to 10 µF.

3. UDSEL

Put VCC to the UDSEL pin ,step-down mode is enable, and put 0V or open step-up mode is enable.

When using the startup circuit, set the pin to step-up mode.

Because the pin uses COMS inverter input, you must connect the pin to either GND or VCC to prevent undefined input.

4. On/off logic

The voltage applied to the STB pins can be controlled whether each channel is on or off.

CH1, CH4, and CH5 can be controlled independently, while CH2 and CH3 can be controlled simultaneously.

Applying a voltage of over 2 V turns on the corresponding channel(s), while leaving the pin open or applying 0 V turns off the

corresponding channel(s).

Turning off all channels causes the IC to be a standby state.

Each pin is connected to GND by 400 kΩ pull-down resistor.

10/16

5. Setting the short protection detection time

The detection time can be set with the capacitance connected to the SCP pin.

When the detection time is reached, the latch circuit operates, turning off output for all channels.

To reset the latch circuit, turn all STB pins off and then back on.

Detection time (sec) = CSCP × VTSC / ISCP

(CSCP: capacitance; VTSC: SCP pin detection voltage, ISCP: SCP pin source current)

*Set the capacitance connected to the SCP pin from 0.001 µF to 2.2 µF.

6. Setting the oscillating frequency

The oscillating frequency can be set with the resistance value connected to the RT pin and the capacitance value connected

to the CT pin.

Oscillating frequency = VRT / (CT × RT)

(Unit: Hz)

*Set the resistance connected to the RT pin from 4.7 kΩ to 30 kΩ (BD9730KV/BD9731KV), or from 10 kΩ to 30 kΩ

(BD9733KN).

*Set the capacitance connected to the CT pin from 100 pF to 10,000 pF.

(VRT: RT pin voltage; CT: OSC timing capacitance; RT: OSC timing resistance)

1000

100pF

180pF

11k

20kΩ

30kΩ

330pF

100

10

1000

RT pin RESISTANCE[kΩ]

CT pin CAPACITANCE [pF]

Fig. 6 Oscillating Frequency Versus RT Pin Resistance

Fig. 7 Oscillating Frequency Versus CT Pin Capacitance

7. POWERGOOD (BD9734KN)

(1) POWERGOOD1

POWERGOOD1 is a switch circuit with a built-in N-channel FET. The MODE pin and REGON pin provide on/off

control.

Setting the MODE pin to high turns the FET on.

Setting the REGON pin to low while the MODE pin is high causes CCDREG output to be discharged.

Setting the MODE pin to low turns the FET off and discharges PG1OUT.

(2) POWERGOOD23

This switch circuit is synchronized to CH3 output and includes a delay function. When the INV3 pin reaches a

voltage of approximately 0.8 V, the capacitor connected to the DELAY pin begins to charge. Once the pin reaches

approximately 2.0 V, the PG4 pin turns on.

*Set the capacitance and resistance connected to the DELAY pin from 100 pF to 1 µF and from 100 kΩ to 400 kΩ.

*The resistor should be connected to VREGA.

8. Startup channel soft-start operation

The startup channel's soft start can be controlled with the capacitance connected to the SS1 pin.

Times can be determined with the following equation:

Startup time (sec) = (VSS / ISS) × CSS

(VSS = SS pin voltage [= 0.7 V], ISS = soft start charge current [= approximately 2.0 µA]; CSS = capacitor capacitance)

Example: When CSS = 0.01 µF, startup time = 0.7 / (2.0 ×10-6) × (0.01 × 10-6) = 3.5 ms

*Set the capacitance connected to the SS1 pin from 0.001 µF to 2.2 µF.

STBY1

(Startup block repeat

oscillation prohibited)

Approximately 1.0

Approximately 0.7

V

VCC output voltage waveform

V

(Startup block Main)

VCC

Approximately

0.5

V

SS1

OSC

FB

VREGA

VCC

VREF=1.0

V

VREGA

SS pin voltage

waveform

OUT1B

Startup OSC

(approximately 100 kHz)

DRAIN1L

Fig. 8 Startup Channel Startup Waveform (Reference Data)

Fig. 9 Timing Chart

11/16

9. SWOUT1 pin (BD9734KN/BD9738KN/BD9739KN)

To prevent current from VOUT1 to the feedback resistor during standby operation, connect the ground side of CH1's

feedback resistor to SWOUT1.

10. Soft start operation depending on SS pins (BD9738KN, BD9739KN)

Soft start operation for CH2 and CH3 can be controlled by the capacitance connected to the SS23 pins.

Times can be determined with the following equation:

VREGA

Approximately

VREGA

Startup time (sec) = (VSS / ISS) × CSS23

(VSS: SS pin voltage [= 1.0 V]; ISS: soft start charge current [= approximately 10 µA]; CSS:

capacitance)

R1

30 kΩ

RA

DTC

*Startup of CH2 begins when CH3 output reaches approximately 70%.

*Set the capacitance connected to each SS23 pin from 0.005 µF to 1.0 µF.

RB

Approximately

R2

93 kΩ

BD9734KN

11. Setting MAX DUTY

Fig. 10 DTC External Setting

Circuit (BD9734KN)

The DTC voltage is determined by the internal R1 and R2 resistance values. The DTC voltage

can be changed by connecting resistance values that are from 1 to 2 digits smaller than the

internal R1 (30 kΩ) and R2 (93 kΩ) resistors to the RA and RB pins.

*The resistors connected to the RA and RB pins should be at least 5 kΩ.Avoid shorting the VREGA and DTC pins.

*When VCC falls to 2.8 V or below, a protection circuit will operate to limit MAX DUTY in order to prevent the IC from

malfunctioning when VREGA (the internal circuit power supply) drops.

12. Soft start operation triggered by the DTC pin

Soft start operation can be set by connecting a capacitor to the DTC pin.

Setting the STBY pin to high will cause the capacitor connected to the DTC pin to be charged by the internal pull-up resistor.

Startup will begin when this voltage reaches the minimum voltage of the CT pin's triangular waveform.

*Set the capacitance connected to each DTC pin to 10 µF or less.

13. Internal soft start operation

Soft start times are set internally for CH2 to CH7 (BD9734KN); CH4 to CH7 (BD9738KN); CH4, CH6, and CH7

(BD9739KN); and CH2 to CH4 (BD9740KN).

BD9734KN

BD9738KN

BD9739KN

BD9740KN

CH2: 1.5 ms, CH3 to CH7: 0.5 ms

CH4 to CH7: 3.0 ms

CH4, 6, 7: 2.7 ms

CH2 to CH4: 3.6 ms (Soft start operation of CH2 and CH3 is delayed until CH4 reaches approximately

80%.)

14. Configuring the CCD REG (BD9734KN, BD9738KN)

(1) Setting the output voltage

Set the output voltage for the positive-side REG with the resistance between the OUT+ pin and the NF+ pin, and

between the NF+ pin and the ground.

The reference voltage is 1 V. Set the output voltage for the negative-side REG with the resistance between the OUT

pin and the NF- pin, and between the NF- pin and the OUT- pin. The reference voltage is 0 V.

(2) Setting the soft start

The positive-side REG soft start can be controlled with the capacitance CSS of the capacitor connected to the SS2 pin.

Startup time (sec) = (VSS / ISS) × CSS

(VSS = SS2 pin voltage [= 1.0 V]; ISS = soft start charge current [= approximately 2.0 µA])

The negative-side REG starts up at the same time as the positive-side REG.

*Set the capacitance connected to the SS2 pin from 0.001 µF to 2.2 µF.

(3) Output capacitors

Connect a capacitor for stopping oscillation to each regulator.

*Set the capacitance from 1.0 µF to 22 µF.

15. Setting the error amp feedback resistance

(1) Feedback resistance order (BD9734KN, BD9738KN, BD9739KN, BD9740KN)

Error amp differential input is formed by a PNP transistor, with the base current of this input flowing into the lower

voltage divider resistor. In the worst case, this current may reach 0.2 µA. For this reason, when the resistance of the

lower resistor is increased, the base current may cause an error in the output voltage. For example, resistance values

of 40 kΩ, 20 kΩ, and 10 kΩ result in errors of 1%, 0.5%, and 0.25%, respectively. Refer to these values when setting

the resistance value.

12/16

(2) Setting the inverted channel (BD9739KN, BD9740KN)

For the BD9739KN, connect the CH5 error amp reference voltage (INV5) to the ground.

For the BD9740KN, the CH6 error amp reference voltage is grounded internally.

*It is recommended to use a 10 kΩ resistor between VREF and CH5 output. Use a resistance value from 5 kΩ to

20 kΩ.

zI/O Equivalent Circuit Diagrams

INV2 to INV6, INV7 V

(error amp inverted input)

INV1

DTC5 to DTC7

(dead time control)

(error amp inverted input)

VREGA

VCC

DTC5

DTC6

DTC7

VCC

INV2 to INV6,

INV7V

INV1

RT (triangular waveform timing

resistor connection)

SS1 (startup channel soft start

capacitor connection pin)

INV7I (error amp inverted input)

NON7 (error amp non-inverted input)

VREGA

VCC

VBAT

VCC

INV7I

RT

SS1

VREF

NON7

CT (triangular waveform timing

capacitance connection)

SCP (timer latch time setting

capacitor connection pin)

VREGA (REGA output)

VREGA

VCC

VREGA

VCC

VREGA

VCC

SCP

CT

VREF (reference voltage output)

VCC

DELAY (POWERGOOD

time constant setting pin)

UDSEL (step-up/step-down select input)

VCC

UDSEL1 to

UDSEL 5

DELAY

VREF

13/16

7CH (power transistor drain output)

STBY1 to STBY7 (CH1 to CH7 on/off control)

REGON (CCD REG control input)

MODE (CCD sequence control pin)

VCC

OUT7B

STBY1 to

STBY7

VCC

REGON

MODE

PGND4

Fig. 11 I/O Equivalent Circuit Diagrams (1)

SYNC_DTC (synchronous

rectification delay time setting pin)

SWIN (load switch input pin)

SWOUT (load switch output pin)

FB (error amp output)

VCC

SWIN4, 6, 7

SWOUT4, 6, 7

VCC VREGA

SYNC_DT

FB1 to FB7

MAIN4 (CH4 main output)

SUB4 (CH4 sub output)

OUT5 (power transistor connection)

DRAIN1, 2, 3H

(power MOS drain for CH1, CH2, and CH3)

DRAIN1, 2, 3L

PG1IN (POWERGOOD 1 input)

PG1OUT (POWERGOOD

switch 1 output)

(power MOS drain for CH1, CH2, and CH3)

PGND1, 23 (output step ground)

VCC

PG1OUT

PG1IN

DRAIN1,2,3

PVCCH

PVCC

DRAIN1,2,

VCC

MAIN4

SUB4

OUT5

PGND1,2

OUT6 (power transistor connection)

PVCC (power supply input)

PGND4 (power ground)

VCC

VBAT2 (battery input [driver block])

OUT1B (CH1 power transistor collector output)

PGND4

VCC

VBAT2

OUT1B

SWOUT1, 4 (load switch output pin)

PG23 (POWERGOOD switch 23 output)

PVCC

VCC

SWOUT1, 4

PG23

OUT6

VCC

NFMINUS

PGND4

(CCD REG feedback pin - side)

OUTMINUS

(CCD REG output pin - side)

VINMINUS

VINPLUS

(CCD REG input pin + side)

OUTPLUS

(CCD REG output pin + side)

NFPLUS

(CCD REG feedback pin + side)

SS2 (soft start capacitor

connection pin)

(CCD REG input pin - side)

VCC

VREGA

VCC

NFMINUS

VCC

VINPLUS

SS2

OUTMINUS

VCC

OUTPLU

NFPLUS

VINMINUS

Fig. 12 I/O Equivalent Circuit Diagrams (2)

14/16

zPrecautions

1) Absolute maximum ratings

Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in IC damage.

Assumptions should not be made regarding the state of the IC (short mode or open mode) when such damage is suffered. A physical

safety measure such as a fuse should be implemented when use of the IC in a special mode where the absolute maximum ratings may

be exceeded is anticipated.

2) Connecting the power supply connector backward

Connecting the power supply connector backwards may result in damage to the IC. Insert external diodes between the power supply and

the IC's power supply pins as well as the motor coil to protect against damage from backward connections.

3) Power supply lines

Regenerated current may flow as a result of the motor's back electromotive force. Insert capacitors between the power supply and ground

pins to serve as a route for regenerated current.

4) GND potential

Ensure a minimum GND pin potential in all operating conditions.

5) Thermal design

Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.

6) Inter-pin shorts and mounting errors

Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in damage to the

IC. Shorts between output pins or between output pins and the power supply and GND pin caused by the presence of a foreign object

may result in damage to the IC.

7) Operation in a strong electromagnetic field

Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction.

8) ASO

When using the IC, set the output transistor so that it does not exceed absolute maximum ratings or ASO.

9) Thermal shutdown circuit (TSD circuit)

The IC incorporates a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed only to shut

the IC off to prevent runaway thermal operation. It is not designed to protect the IC or guarantee its operation. Do not continue to use the

IC after operating this circuit or use the IC in an environment where the operation of this circuit is assumed.

10) Capacitors connected between output and ground pins

When a large capacitor is connected between the output and ground pins and for some reason the VCC falls to 0 V or becomes shorted

with the ground pin, the current stored in the capacitor may flow to the output pin, resulting in damage to the IC. Set capacitors connected

between the output and ground pins to values that fall within the recommended range.

11) Testing on application boards

When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always

discharge capacitors after each process or step. Ground the IC during assembly steps as an antistatic measure, and use similar caution

when transporting or storing the IC. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during

the inspection process.

12) IC pin input

This monolithic IC contains P+ isolation and PCB layers between adjacent elements in order to keep them isolated. P/N junctions are

formed at the intersection of these P layers with the N layers of other elements to create a variety of parasitic elements.

For example, when a resistor and transistor are connected to pins as shown in Fig. 13,

{the P/N junction functions as a parasitic diode when GND > (Pin A) for the resistor or GND > (Pin B) for the transistor (NPN).

{Similarly, when GND > (Pin B) for the transistor (NPN), the parasitic diode described above combines with the N layer of other

adjacent elements to operate as a parasitic NPN transistor.

The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable result of the IC's

architecture. The operation of parasitic elements can cause interference with circuit operation as well as IC malfunction and damage. For

these reasons, it is necessary to use caution so that the IC is not used in a way that will trigger the operation of parasitic elements, such

as by the application of voltages lower than the GND (PCB) voltage to input pins.

13) Ground wiring patterns

Power supply and ground wiring should reflect consideration of the need to lower common impedance and minimize ripple as much as

possible (by making wiring as short and thick as possible or rejecting ripple by incorporating inductance and capacitance).

14) STB pin voltage

Set the STB pin voltage to 0.3 V or lower when setting channels to a standby state, or to 2.0 V or higher when setting channels to an

operational state. Do not fix the STB pin voltage to values higher than 0.3 V and lower than 2.0 V or lengthen transition times. Doing so

may cause the IC to malfunction or result in damage.

15) Use a common supply voltage for both the driver block and the main block.

The IC is not compatible with applications requiring the driver block to be used while applying user-selected voltages.

16) Setting the MAX DUTY

MAX DUTY limitations may not operate when using the IC at high frequencies. When using the IC in such applications, allow for sufficient

margins when setting external components.

Transistor (NPN)

B

C

Resistor

(Pin B)

(Pin A)

E

C

E

B

GND

N

P^＋

P

N

GND

Other Adjacent

Elements

N

Parasitic

elements

N

(Pin A)

PCB

Parasitic elements

PCB

Parasitic elements

GND

Parasitic elements

GND

Fig. 13 Example of Simple Bipolar IC Architecture

15/16

zSelecting a Model Name When Ordering

B

D

9

7

3

4

K

N

―

E

2

Taping type

E2 = Reel-wound embossed taping

ROHM model

name

Package type

KN = UQFN

Part number

9734, 9738

9739, 9740

UQFN64

UQFN48

7.2 ± 0.1

7.0 ± 0.1

8.2± 0.1

8.0± 0.1

+0.1

-0.3

0.6

(0

(1.1)

(1.4)

48

33

36

25

49

64

32

17

4

−

37

24

(0

.35)

.55)

3-(0

.45)

.20)

(0

48

13

1

16

0.4

0.20± 0.05

(0.20)

1

12

0.20 ± 0.05

0.05

M

0.4

0.05

(0.6₋⁺₀⁰_.^.₃¹

)

0.05

(Unit:mm)

UQFN84

10.2 ± 0.1

10.0 ± 0.1

Embossed carrier tape(with dry pack)

Tape

(1.1)

63

43

2500pcs

E2

Quantity

64

42

22

Direction

of feed

4

(The direction is the 1pin of product is at the upper left when you hold

reel on the left hand and you pull out the tape on the right hand)

−

(0.4)

84

1

(0.20)

21

0.4

0.20± 0.05

0.05

M

(0.6₋⁺₀⁰_.^.₃¹

)

0.05

Direction of feed

1pin

Reel

(Unit:mm)

※When you order , please order in times the amount of package quantity.

The contents described herein are correct as of October, 2005

The contents described herein are subject to change without notice. For updates of the latest information, please contact and confirm with ROHM CO.,LTD.

Any part of this application note must not be duplicated or copied without our permission.

Application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. Please pay careful attention to the peripheral conditions when designing circuits and deciding

upon circuit constants in the set.

Any data, including, but not limited to application circuit diagrams and information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. ROHM CO.,LTD. disclaims any

warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such

infringement, or arising from or connected with or related to the use of such devices.

Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, implied right or license to practice or commercially exploit any intellectual property rights or other

proprietary rights owned or controlled by ROHM CO., LTD. is granted to any such buyer.

The products described herein utilize silicon as the main material.

The products described herein are not designed to be X ray proof.

Published by

Application Engineering Group

Catalog NO.05N343Be '05.10 ROHM C 2000 TSU

Appendix

Notes

No technical content pages of this document may be reproduced in any form or transmitted by any

means without prior permission of ROHM CO.,LTD.

The contents described herein are subject to change without notice. The specifications for the

product described in this document are for reference only. Upon actual use, therefore, please request

that specifications to be separately delivered.

Application circuit diagrams and circuit constants contained herein are shown as examples of standard

use and operation. Please pay careful attention to the peripheral conditions when designing circuits

and deciding upon circuit constants in the set.

Any data, including, but not limited to application circuit diagrams information, described herein

are intended only as illustrations of such devices and not as the specifications for such devices. ROHM

CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any

third party's intellectual property rights or other proprietary rights, and further, assumes no liability of

whatsoever nature in the event of any such infringement, or arising from or connected with or related

to the use of such devices.

Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or

otherwise dispose of the same, no express or implied right or license to practice or commercially

exploit any intellectual property rights or other proprietary rights owned or controlled by

ROHM CO., LTD. is granted to any such buyer.

Products listed in this document are no antiradiation design.

The products listed in this document are designed to be used with ordinary electronic equipment or devices

(such as audio visual equipment, office-automation equipment, communications devices, electrical

appliances and electronic toys).

Should you intend to use these products with equipment or devices which require an extremely high level

of reliability and the malfunction of which would directly endanger human life (such as medical

instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers

and other safety devices), please be sure to consult with our sales representative in advance.

It is our top priority to supply products with the utmost quality and reliability. However, there is always a chance

of failure due to unexpected factors. Therefore, please take into account the derating characteristics and allow

for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in

order to prevent possible accidents that may result in bodily harm or fire caused by component failure. ROHM

cannot be held responsible for any damages arising from the use of the products under conditions out of the

range of the specifications or due to non-compliance with the NOTES specified in this catalog.

Thank you for your accessing to ROHM product informations.

More detail product informations and catalogs are available, please contact your nearest sales office.

THE AMERICAS / EUROPE / ASIA / JAPAN

ROHM Customer Support System

Contact us : webmaster@ rohm.co.jp

www.rohm.com

TEL : +81-75-311-2121

FAX : +81-75-315-0172

21 Saiin Mizosaki-cho, Ukyo-ku, Kyoto 615-8585, Japan

Appendix1-Rev2.0


型号：	BD9738KN-E2
厂家：	ROHM
描述：	Switching Regulator, 1200kHz Switching Freq-Max, LEAD FREE, QFN-84 开关
文件：	总17页 (文件大小：878K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BD9738KN-E2 [ROHM]

相关型号：

BD9739KN

BD9739KN-E2

BD9739KN_10

BD9740KN

BD9740KN-E2

BD9745EKN

BD9749MWV

BD975

BD9755FV

BD9755FV-E2

BD9756AMWV

BD9757MWV