BD8105FV-E2 [ROHM]
LED Indicator Driver; LED指示灯驱动器
| 型号： | BD8105FV-E2 |
| 厂家： | 
ROHM |
| 描述： | LED Indicator Driver |
| 文件： | 总13页 (文件大小：342K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Power Management ICs for Automotive Body Control
LED
Indicator Driver
No.11039ECT01
BD8105FV
●Description
The BD8105FV is a serial parallel control LED driver with 35V input voltage rating.
Responding to the 3-line serial data, it turns the 12ch open drain output on/off.
Due to its compact size, it is optimal for small spaces.
●Features
1) Open Drain Output
2) 3-line Serial Control + Enable Signal
3) Internal Temperature Protection Circuit (TSD)
4) Cascade Connection Compatible
5) SSOP-B20W
6) Internal 12 ch Power Transistor
Applications
These ICs can be used with car and consumer electronic.
●Absolute Maximum Ratings (Ta=25℃)
Parameter
Symbol
VCC
Ratings
7
Unit
V
Power Supply Voltage
Output Voltage(Pin No : 4～9, 11～16) VDmax
35
V
Input Voltage(Pin No : 1, 2, 3, 17, 18)
Power Dissipation
VIN
Pd
-0.3～VCC
1187*
-40～+105
-55～+150
50
V
mW
℃
Operating Temperature Range
Storage Temperature Range
Drive Current (DC)
Topr
Tstg
℃
IomaxD
IomaxP
Tjmax
mA
mA
℃
Drive Current(Pulse)
150**
Junction Temperature
150
*
**
Pd decreased at 9.50mW/℃for temperatures above Ta=25℃,mounted on 70×70×1.6mm Glass-epoxy PCB.
Do not however exceed Pd. Time to impress≦200msec
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© 2011 ROHM Co., Ltd. All rights reserved.
2011.05 - Rev.C
1/12
Technical Note
BD8105FV
●Operational Conditions (Ta=-40~105℃)
Ratings
Typ.
Parameter
Symbol
Unit
Min.
4.5
Max.
5.5
Power Supply Voltage
Drive Current
Vcc
Io
5
V
-
20
40
mA
* This product is not designed for protection against radioactive rays.
●Electrical Characteristics (Unless specified, Ta=-40~105℃ Vcc=4.5～5.5V)
Limits
Parameter
Symbol
Unit
Conditions
Min.
Typ.
Max.
【Output D0～D11】(Pin No : 4～9, 11～16)
ON Resistor
RON
-
-
6
0
12
5
Ω
ID=20mA
Output leakage current
IDL
µA
VD=34V
【Logic input】(Pin No : 1, 2, 3, 17, 18)
Upper limit threshold voltage
Vcc
×0.8
VTH
VTL
FCLK
IIN
-
-
-
V
V
Vcc
×0.2
Bottom limit threshold voltage
Serial clock frequency
Input Current
-
-
-
1
100
5
MHz
µA
µA
20
-
50
0
VIN=5V
VIN=0V
Input leakage Current
IINL
【WHOLE】
Serial Data Input,
VCC=5V,CLK=500KHz,
SEROUT=OPEN
RST_B=OPEN,
SEROUT=OPEN
Circuit Current
ICC
-
-
0.3
0
5
mA
µA
Static Current
ISTN
50
【SER OUT】(Pin No. : 20)
Output Voltage high
VOH
VOL
4.6
-
4.8
0.2
-
V
V
VCC=5V, ISO=-5mA
VCC=5V, ISO=5mA
Output voltage Low
0.4
* This product is not designed for protection against radioactive rays.
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© 2011 ROHM Co., Ltd. All rights reserved.
2011.05 - Rev.C
2/12
Technical Note
BD8105FV
●Electrical Characteristic Diagrams (Unless otherwise specified Ta=25℃)
10
9
8
7
6
5
4
3
2
1
0
230
225
220
215
210
205
250
200
150
100
50
5.5V
5.0V
105℃
25℃
25℃
105℃
4.5V
-40℃
-40℃
0
-40
-15
10
35
60
85
4.5
4.7
4.9
5.1
5.3
5.5
0
1
2
3
4
5
SUPPLYVOLTAGE：Vcc[V]
SUPPLY VOLTAGE：Vcc[V]
AMBIENT TEMPERATURE ： Ta[℃]
Fig.1 Circuit current 1
Fig.2 Circuit current 2
Fig.3 Dxx on resistance 1
(at IDD=20mA)
6.0
5.8
5.6
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
8
7
6
5
4
3
2
1
0
4.5V
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
-40℃
4.5V
5V
5V
5.5V
5.5V
25℃
105℃
-40
-15
10
35
60
85
4.5
4.7
4.9
5.1
5.3
5.5
10
20
30
40
50
SUPPLY VOLTAGE： Vcc[V]
INPUT CURRENT： ID[mA]
AMBIENT TEMPERATURE ： Ta[℃]
Fig.4 Dxx on resistance 2
(at IDD=20mA)
Fig.5 Dxx on resistance
Fig.6 SEROUT high side voltage 1
(at ISO=-5mA)
6.0
5.5
5.0
4.5
4.0
3.5
3.0
0.35
0.35
5.5V
105℃
25℃
0.30
0.25
0.20
0.15
0.10
0.05
0.00
0.30
4.5V
0.25
5V
0.20
4.5V
5.5V
5V
0.15
-40℃
0.10
0.05
0.00
-40
-15
10
35
60
85
-40
-15
10
35
60
85
4.5
4.7
4.9
5.1
5.3
5.5
AMBIENT TEMPERATURE ： Ta[℃]
SUPPLY VOLTAGE ： Vcc[V]
AMBIENT TEMPERATURE ： Ta[℃]
Fig.7 SEROUT high side voltage 2
(at ISO=-5mA)
Fig.8 SEROUT low side voltage 1
(at ISO=5mA)
Fig.9 SEROUT low side voltage 2
(at ISO=5mA)
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© 2011 ROHM Co., Ltd. All rights reserved.
2011.05 - Rev.C
3/12
Technical Note
BD8105FV
●Block Diagram
SDWN
4 D11
5 D10
3
TSD
D9
D8
D7
6
7
8
<11:0>
9 D6
SERIN
Driver
17
1
D5
D4
D3
D2
D1
D0
11
12
LATCH
CLK
Serial
I/F
13
14
<11:0>
18
2
<11:0> <11:0>
RST_B
15
16
VCC
SEROUT
20
SEROUT
19
10
GND
Fig.10
●Pin Setup Diagram
●Terminal Number・Terminal Name
BD8105FV(SSOP-B20W)
Pin
Terminal
Name
Function
Number
Latch Signal Input Terminal
(H: Latches Data)
1
2
3
LATCH
RST_B
SDWN
1
20
19
18
17
16
15
14
13
12
11
SEROUT
VCC
CLK
SERIN
D0
LATCH
Reset Reversal Input Terminal
(L: FF Data 0)
2
RST_B
Shutdown Input Terminal
(H: Output Off)
3
SDWN
4
D11
D10
D9
Drain Output Terminal 11
4
D11
5
Drain Output Terminal 10
Drain Output Terminal 9
Drain Output Terminal 8
Drain Output Terminal 7
Drain Output Terminal 6
Ground Terminal
5
D10
6
6
D9
D1
7
D8
7
D8
D2
8
D7
9
D6
8
D7
D3
10
11
12
13
14
15
16
17
18
19
20
GND
D5
9
D4
D6
Drain Output Terminal 5
Drain Output Terminal 4
Drain Output Terminal 3
Drain Output Terminal 2
Drain Output Terminal 1
Drain Output Terminal 0
Serial Data Input Terminal
Clock Input Terminal
10
D5
GND
D4
D3
D2
Fig.11
D1
D0
SERIN
CLK
VCC
Supply Voltage Input Terminal
SEROUT Serial Data Output Terminal
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© 2011 ROHM Co., Ltd. All rights reserved.
2011.05 - Rev.C
4/12
Technical Note
BD8105FV
●Block Operation
1)Serial I/F
The I/F is a 3-line serial (LATCH, CLK, SERIN) style.
12-bit output ON/OFF can be set-up. This is composed of shift register. + 12-bit register.
2)Driver
It is a 12-bit open drain output.
3)TSD (Thermal Shut Down)
To prevent heat damage and overheating, when the chip temperature goes over approximately 175℃, the output turns
off. When the temperature goes back down, normal operation resumes. However, the intended use of the temperature
protection circuit is to protect the IC, so please construct thermal design with the junction temperature Tjmax under
150℃.
●Application Circuit
VCC
10uF
10uF
↓IF
Rres
VBAT
VF
VCC
D0
D1
D2
D3
D4
D5
D6
SDWN
LATCH
RST_B
CLK
Micro-
computer
SERIN
SEROUT
GND
D7
D8
D9
D10
D11
VCC
10uF
VCC
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
SDWN
LATCH
RST_B
CLK
SERIN
SEROUT
GND
VBAT - VF
IF=
Rres + RON
Fig.12
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© 2011 ROHM Co., Ltd. All rights reserved.
2011.05 - Rev.C
5/12
Technical Note
BD8105FV
●Serial Communication
The serial I/F is composed of a shift register which changes the CLK and SERIN serial signals to parallel signals, and a
register to remember those signals with a LATCH signal. The registers are reset by applying a voltage under VCC×0.2 to
the RST_B terminal or opening it, and D11~D0 become open. To prevent erroneous LED lighting, please apply voltage
under VCC×0.2 to RST_B or make it open during start-up.
CLK
12bit
12bit
Shift
Driver
Register
SERIN
LATCH
Register
Fig.13
1)Serial Communication Timing
The 12-bit serial data input from SERIN is taken into the shift register by the rise edge of the CLK signal, and is recorded
in the register by the rise edge of the LATCH signal. The recorded data is valid until the next rise edge of the LATCH
signal.
2)Serial Communication Data
The serial data input configuration of SERIN terminal is shown below:
First →
→Last
d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
Data
Data
Terminal Output
Name
Status
d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
1
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
* represents “Don’t care”.
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2011.05 - Rev.C
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Technical Note
BD8105FV
3)Enable Signal
By applying voltage at least VCC×0.8 or more to the SDWN terminal, D0 (16 pin)~D11 (4 pin) become open forcibly.
At this time, the temperature protection circuit (TSD) stops. D11～D0 become PWM operation by inputting PWM to
SDWN(3 pin).
4)SEROUT
A cascade connection can be made (connecting at least 2 or more IC’s in serial).
Serial signal input from SERIN is transferred into receiver IC by the fall edge of the CLK signal.
Since this functionality gives enough margins for the setup time prior to the rise edge of the CLK signal on the receiver
IC (using the exact same CLK signal of sender IC), the application reliability can be improved as cascade connection
functionality.
LATCH
d5
d3
d10 d9 d8
d7 d6
d4
d2 d1
d0
d11
SERIN
CLK
1
2
3
4
5
6
7
8
9
10 11 12 13
SEROUT
D11
Fig.14
●Cascade Connection
By using (at least) 2 ICs, each IC’s D11~D0, at (at least) 24ch, can be controlled by the 24-bit SERIN signal. The serial data
input to the sender IC can be transferred to the receiver IC by inputting 12CLK to the CLK terminal.
Send side IC
Receive side IC
LATCH
d17
d15
9
d5
d3
d22 d21 d20 d19 d18
d16
8
d14 d13 d12
d10 d9 d8
d11
d7 d6
d4
d2 d1 d0
d23
1
SERIN
CLK
2
3
4
5
6
7
10 11 12 13
14
15 16
17 18 19 20
21 22 23 24
Fig.15
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© 2011 ROHM Co., Ltd. All rights reserved.
2011.05 - Rev.C
7/12
Technical Note
BD8105FV
●INPUT SIGNAL’S TIMING CHART
TCK
50%
CLK
TCKL
TCKH
TSESTTSEHD
50%
SERIN
TLADZ
TSEW
TLAH
50%
LATCH
Fig.16
●INPUT SIGNAL’S TIMING RULE(Ta=-40～105℃ Vcc=4.5～5.5V)
Parameter
Symbol
TCK
Min
1000
480
480
980
150
150
480
250
Unit
CLK period
ns
ns
ns
ns
ns
ns
ns
ns
CLK high pulse width
TCKH
TCKL
CLK low pulse width
SERIN high and low pulse width
SERIN setup time prior to CLK rise
SERIN hold time after CLK fall
LATCH high pulse time
TSEW
TSEST
TSEHD
TLAH
Last CLK rise to LATCH rise
TLADZ
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2011.05 - Rev.C
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Technical Note
BD8105FV
●OUTPUT SIGNAL’S DELAY CHART
SDWN
50%
TDSNL
TDSNH
OUTPUT
(D11～D0)
50%
LATCH
50%
TDLAH
OUTPUT
50%
(D11～D0)
50%
CLK
TDSOH
TDSOL
50%
SEROUT
Fig.17
●OUTPUT SIGNAL’S DELAY TIME(Ta=-40～105℃ Vcc=4.5～5.5V)
Parameter
Symbol
TDSNH
TDSNL
TDLAH
TDSOH
TDSOL
Max
300
300
300
350
350
Unit
ns
SDWN Switching Time(L→H)
SDWN Switching Time(H→L)
ns
LATCH Switching Delay Time
ns
SEROUT Propagation Delay Time(L→H)
SEROUT Propagation Delay Time (H→L)
ns
ns
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2011.05 - Rev.C
9/12
Technical Note
BD8105FV
●INPUT/OUTPUT EQUIVALENT CIRCUIT(PIN NAME)
4PIN(D11),5PIN(D10)
1PIN(LATCH)
2PIN(RST_B)
3PIN(SDWN)
17PIN(SERIN)
18PIN(CLK)
6PIN(D9),7PIN(D8)
8PIN(D7),9PIN(D6)
11PIN(D5),12PIN(D4)
13PIN(D3),14PIN(D2)
15PIN(D1),16PIN(D0)
20PIN(SEROUT)
VCC
VCC
VCC
100k
(TYP)
Fig.18
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2011.05 - Rev.C
10/12
Technical Note
BD8105FV
●Notes for use
(1) Absolute maximum ratings
Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may
result in IC damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such
damage is suffered. A physical safety measure such as a fuse should be implemented when use of the IC in a special
mode where the absolute maximum ratings may be exceeded is anticipated.
(2) Reverse connection of a power supply connector
If the connector of power is wrong connected, it may result in IC breakage. In order to prevent the breakage from the
wrong connection, the diode should be connected between external power and the power terminal of IC as protection
solution.
(3) GND potential
Ensure a minimum GND pin potential in all operating conditions.
(4) Setting of heat
Use a setting of heat that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.
(5) Pin short and mistake fitting
Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in
damage to the IC. Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating
temperature range may result in IC damage.
(6) Actions in strong magnetic field
Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to
malfunction.
(7) Thermal shutdown circuit(TSD)
This IC built-in a Thermal shutdown circuit (TSD circuit). If Chip temperature becomes 175℃(TYP.), make the output an
Open state. Eventually, warmly clearing the circuit is decided by the condition of whether the heat excesses over the
assigned limit, resulting the cutoff of the circuit of IC, and not by the purpose of preventing and ensuring the IC. Therefore,
the warm switch-off should not be applied in the premise of continuous employing and operation after the circuit is
switched on.
(8) Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress.
Always discharge capacitors after each process or step. Ground the IC during assembly steps as an antistatic measure,
and use similar caution when transporting or storing the IC. Always turn the IC's power supply off before connecting it to or
removing it from a jig or fixture during the inspection process
(9) IC terminal input
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.
P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety of
parasitic elements. For example, when a resistor and transistor are connected to pins. (See the chart below.)
the P/N junction functions as a parasitic diode when
GND > (Pin A) for the resistor or GND > (Pin B) for the transistor (NPN).
Similarly, when GND > (Pin B) for the transistor (NPN), the parasitic diode described above combines with the N layer
of other adjacent elements to operate as a parasitic NPN transistor.
The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable result
of the IC's architecture. The operation of parasitic elements can cause interference with circuit operation as well as IC
malfunction and damage. For these reasons, it is necessary to use caution so that the IC is not used in a way that will
trigger the operation of parasitic elements, such as by the application of voltages lower than the GND (PCB) voltage to
input pins.
Resistor
Transistor (NPN)
(Pin B)
B
E
(Pin A)
C
E
C
(Pin B)
B
GND
GND
N
P
P
P+
P+
P+
Parasitic
elements
P+
N
N
N
P
N
N
N
(Pin A)
P substrate
GND
Parasitic elements
GND
Parasitic
elements
Parasitic elements
(10) Ground wiring patterns
GND
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns,
placing a single ground point at the application's reference point so that the pattern wiring resistance and voltage
variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the
GND wiring patterns of any external components.
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2011.05 - Rev.C
11/12
Technical Note
BD8105FV
●Ordering part number
B
D
8
1
0
5
F
V
-
E
2
Part No.
Part No.
Package
FV: SSOP-B20W
Packaging and forming specification
E2: Embossed tape and reel
SSOP-B20W
<Tape and Reel information>
6.5 0.2
Tape
Embossed carrier tape
2000pcs
20
11
Quantity
E2
Direction
of feed
The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand
(
)
1
10
0.15 0.1
0.1
0.65
Direction of feed
1pin
0.22 0.1
Reel
Order quantity needs to be multiple of the minimum quantity.
(Unit : mm)
∗
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2011.05 - Rev.C
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Notice
N o t e s
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, office-automation equipment, commu-
nication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
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R1120
A
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